[Bug target/83862] powerpc: ICE in signbit testcase

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

Michael Meissner  changed:

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution|--- |FIXED

--- Comment #6 from Michael Meissner  ---
Fixed in trunk, back ported to GCC 6 and GCC 7 branches.

[Bug target/83862] powerpc: ICE in signbit testcase

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

--- Comment #5 from Michael Meissner  ---
Author: meissner
Date: Thu Jan 25 17:36:47 2018
New Revision: 257060

URL: https://gcc.gnu.org/viewcvs?rev=257060=gcc=rev
Log:
[gcc]
2018-01-25  Michael Meissner  

Back port from trunk
2018-01-22  Michael Meissner  

PR target/83862
* config/rs6000/rs6000-protos.h (rs6000_split_signbit): Delete,
no longer used.
* config/rs6000/rs6000.c (rs6000_split_signbit): Likewise.
* config/rs6000/rs6000.md (signbit2): Change code for IEEE
128-bit to produce an UNSPEC move to get the double word with the
signbit and then a shift directly to do signbit.
(signbit2_dm): Replace old IEEE 128-bit signbit
implementation with a new version that just does either a direct
move or a regular move.  Move memory interface to separate insns.
Move insns so they are next to the expander.
(signbit2_dm_mem_be): New combiner insns to combine load
with signbit move.  Split big and little endian case.
(signbit2_dm_mem_le): Likewise.
(signbit2_dm_ext): Delete, no longer used.
(signbit2_dm2): Likewise.

[gcc/testsuite]
2018-01-25  Michael Meissner  

Back port from trunk
2018-01-22  Michael Meissner  

PR target/83862
* gcc.target/powerpc/pr83862.c: New test.


Added:
branches/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/pr83862.c
Modified:
branches/gcc-7-branch/gcc/ChangeLog
branches/gcc-7-branch/gcc/config/rs6000/rs6000-protos.h
branches/gcc-7-branch/gcc/config/rs6000/rs6000.c
branches/gcc-7-branch/gcc/config/rs6000/rs6000.md
branches/gcc-7-branch/gcc/testsuite/ChangeLog

[Bug target/83862] powerpc: ICE in signbit testcase

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

--- Comment #4 from Michael Meissner  ---
GCC 6 backport applied, GCC 7 backport waiting for GCC 7.3 to ship, before
applying the patch.

[Bug target/83862] powerpc: ICE in signbit testcase

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

--- Comment #3 from Michael Meissner  ---
Author: meissner
Date: Tue Jan 23 15:07:00 2018
New Revision: 256987

URL: https://gcc.gnu.org/viewcvs?rev=256987=gcc=rev
Log:
[gcc]
2018-01-23  Michael Meissner  

Back port from trunk
2018-01-22  Michael Meissner  

PR target/83862
* config/rs6000/rs6000-protos.h (rs6000_split_signbit): Delete,
no longer used.
* config/rs6000/rs6000.c (rs6000_split_signbit): Likewise.
* config/rs6000/rs6000.md (signbit2): Change code for IEEE
128-bit to produce an UNSPEC move to get the double word with the
signbit and then a shift directly to do signbit.
(signbit2_dm): Replace old IEEE 128-bit signbit
implementation with a new version that just does either a direct
move or a regular move.  Move memory interface to separate insns.
Move insns so they are next to the expander.
(signbit2_dm_mem_be): New combiner insns to combine load
with signbit move.  Split big and little endian case.
(signbit2_dm_mem_le): Likewise.
(signbit2_dm_ext): Delete, no longer used.
(signbit2_dm2): Likewise.

[gcc/testsuite]
2018-01-23  Michael Meissner  

Back port from trunk
2018-01-22  Michael Meissner  

PR target/83862
* gcc.target/powerpc/pr83862.c: New test.


Added:
branches/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/pr83862.c
Modified:
branches/gcc-6-branch/gcc/ChangeLog
branches/gcc-6-branch/gcc/config/rs6000/rs6000-protos.h
branches/gcc-6-branch/gcc/config/rs6000/rs6000.c
branches/gcc-6-branch/gcc/config/rs6000/rs6000.md
branches/gcc-6-branch/gcc/testsuite/ChangeLog

[Bug target/83862] powerpc: ICE in signbit testcase

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

--- Comment #2 from Michael Meissner  ---
Author: meissner
Date: Mon Jan 22 19:36:18 2018
New Revision: 256959

URL: https://gcc.gnu.org/viewcvs?rev=256959=gcc=rev
Log:
[gcc]
2018-01-22  Michael Meissner  

PR target/83862
* config/rs6000/rs6000-protos.h (rs6000_split_signbit): Delete,
no longer used.
* config/rs6000/rs6000.c (rs6000_split_signbit): Likewise.
* config/rs6000/rs6000.md (signbit2): Change code for IEEE
128-bit to produce an UNSPEC move to get the double word with the
signbit and then a shift directly to do signbit.
(signbit2_dm): Replace old IEEE 128-bit signbit
implementation with a new version that just does either a direct
move or a regular move.  Move memory interface to separate insns.
Move insns so they are next to the expander.
(signbit2_dm_mem_be): New combiner insns to combine load
with signbit move.  Split big and little endian case.
(signbit2_dm_mem_le): Likewise.
(signbit2_dm_ext): Delete, no longer used.
(signbit2_dm2): Likewise.

[gcc/testsuite]
2018-01-22  Michael Meissner  

PR target/83862
* gcc.target/powerpc/pr83862.c: New test.


Added:
trunk/gcc/testsuite/gcc.target/powerpc/pr83862.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/rs6000/rs6000-protos.h
trunk/gcc/config/rs6000/rs6000.c
trunk/gcc/config/rs6000/rs6000.md
trunk/gcc/testsuite/ChangeLog

[Bug target/83862] powerpc: ICE in signbit testcase

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

Michael Meissner  changed:

   What|Removed |Added

 Status|UNCONFIRMED |ASSIGNED
   Last reconfirmed||2018-01-16
   Assignee|unassigned at gcc dot gnu.org  |meissner at gcc dot 
gnu.org
 Ever confirmed|0   |1

--- Comment #1 from Michael Meissner  ---
The issue is signbit for 128-bit floating point types wants to optimize signbit
coming from memory to load the high 64-bit value directly into the GPR, and
then do an unsigned shift left of 63 bits to isolate the sign bit.

However, if the floating point value is IEEE 128-bit, the system is little
endian, and the address is indexed (register+register), the optimization will
fail because the compiler will generate an address of the form:

(set (reg:DF )
 (mem:DF (plus:DI (plus:DI (reg:DI )
   (reg:DI ))
  (const_int 8

For little endian systems, we would need a temporary register to put the sum of
the base + index registers, and then we can do a load +8.

[Bug target/83862] powerpc: ICE in signbit testcase

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

Richard Biener  changed:

   What|Removed |Added

   Target Milestone|8.0 |---

[Bug target/83862] powerpc: ICE in signbit testcase

[wschmidt at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862

Bill Schmidt  changed:

   What|Removed |Added

 Target||powerpc*-*-*
   Target Milestone|--- |8.0