https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96366
Bug ID: 96366 Summary: [AArch64] ICE due to lack of support for VNx2SI sub instruction Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: bule1 at huawei dot com CC: richard.sandiford at arm dot com Target Milestone: --- Created attachment 48950 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48950&action=edit preprocessed source code for recurent the problem Hi, The test case bb-slp-20.c in the gcc testsuit will cause an ICE in the expand pass because the gcc lack of a pattern for subtraction of the VNx2SI mode. The preprocessed file is attached and the problem will be triggered when compiled with -march=armv8.5-a+sve -msve-vector-bits=256 -O3 -fno-tree-forwprop options. By tracing the debug infomation, it is found that the error is due to a vectorized subtraction gimple with VNx2SI mode cannot find its pattern during the expand pass. I tried to extend the mode of this pattern from SVE_FULL_I to SVE_I as following, after which the problem is solved. diff -Nurp a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md --- a/gcc/config/aarch64/aarch64-sve.md 2020-07-29 15:54:39.360000000 +0800 +++ b/gcc/config/aarch64/aarch64-sve.md 2020-07-29 14:37:21.932000000 +0800 @@ -3644,10 +3644,10 @@ ;; ------------------------------------------------------------------------- (define_insn "sub<mode>3" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w") - (minus:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "aarch64_sve_arith_operand" "w, vsa, vsa") - (match_operand:SVE_FULL_I 2 "register_operand" "w, 0, w")))] + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") + (minus:SVE_I + (match_operand:SVE_I 1 "aarch64_sve_arith_operand" "w, vsa, vsa") + (match_operand:SVE_I 2 "register_operand" "w, 0, w")))] "TARGET_SVE" "@ sub\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype> I noticed that this mode iterator was changed from SVE_I to SVE_FULL_I in Nov 2019 by richard to support partial SVE vectors. However, in the following patch the addition pattern is supported by changing SVE_FULL_I to SVE_I but not the subtraction pattern. Is there any specific reason why this pattern is not supported? Thanks.