[Bug target/98470] ICE: "error: insn does not satisfy its constraints" with hard FP on xtensa
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98470
--- Comment #4 from jcmvbkbc at gcc dot gnu.org ---
I've noticed that this forward-propagation of the literal load followed by not
calling the secondary reload function happens when the first literal load
instruction has the following in its expression list:
(expr_list:REG_EQUIV (mem/u/c:SF (symbol_ref/u:SI ("*.LC0") [flags 0x2]) [0 S4
A32])
and it doesn't happen for instructions that have the following:
(expr_list:REG_EQUIV (const_double:SF 0.0 [0x0.0p+0])
This expression is present in this instruction up to the ce2 pass where it's
lost. Compiling with -fno-if-conversion preserves the expression and results in
the correct output.
[Bug target/98470] ICE: "error: insn does not satisfy its constraints" with hard FP on xtensa
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98470 --- Comment #3 from jcmvbkbc at gcc dot gnu.org --- (In reply to rsand...@gcc.gnu.org from comment #2) > What code should GCC generate if it wants to move the given > MEM into an FP register? The two main options are: > > (1) reload the literal address into a temporary register. > This can be done by using "define_memory_constraint" > instead of "define_constraint" to define "U". I've tried that, it doesn't change anything for me. I've also tried doing this change to the "T" constraint and to both of them. Nothing. > (2) load into a general-purpose register and then move the > general-purpose register to an FP register. This can > be done using the TARGET_SECONDARY_RELOAD hook. There's already TARGET_SECONDARY_RELOAD hook for xtensa which seems to do exactly this. But it's not called from the reload and later passes for literal loads into FPU registers.
[Bug target/98470] ICE: "error: insn does not satisfy its constraints" with hard FP on xtensa
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98470 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Comment #2 from rsandifo at gcc dot gnu.org --- What code should GCC generate if it wants to move the given MEM into an FP register? The two main options are: (1) reload the literal address into a temporary register. This can be done by using "define_memory_constraint" instead of "define_constraint" to define "U". (2) load into a general-purpose register and then move the general-purpose register to an FP register. This can be done using the TARGET_SECONDARY_RELOAD hook.
[Bug target/98470] ICE: "error: insn does not satisfy its constraints" with hard FP on xtensa
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98470
--- Comment #1 from jcmvbkbc at gcc dot gnu.org ---
It happens at the reload pass when reload transforms the following RTL that
comes to it from the IRA pass:
(insn 20 163 164 30 (set (reg:SF 162 [ iftmp.0_87 ])
(mem/u/c:SF (symbol_ref/u:SI ("*.LC0") [flags 0x2]) [0 S4 A32]))
"float-ice.c":11:17 45 {movsf_internal}
(expr_list:REG_EQUIV (mem/u/c:SF (symbol_ref/u:SI ("*.LC0") [flags 0x2])
[0 S4 A32])
(nil)))
...
(insn 538 168 169 32 (set (reg:SF 71 [ iftmp.0_87 ])
(reg:SF 162 [ iftmp.0_87 ])) "float-ice.c":11:17 45 {movsf_internal}
(nil))
to the following RTL:
(insn 538 168 169 32 (set (reg:SF 19 f0 [orig:71 iftmp.0_87 ] [71])
(mem/u/c:SF (symbol_ref/u:SI ("*.LC0") [flags 0x2]) [0 S4 A32]))
"float-ice.c":11:17 45 {movsf_internal}
(nil))
which tries to load a literal into a hardware FP register. There's no opcode
for it in the xtensa ISA, there's no constraint that would match it in the
movsf_internal and the predicate in this instruction definition evaluates to
false on such input, but the substitution happens anyway.
