[Bug target/99842] MMA test case ICEs using -O3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842 Peter Bergner changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED|RESOLVED --- Comment #7 from Peter Bergner --- Fixed everywhere.
[Bug target/99842] MMA test case ICEs using -O3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842 --- Comment #6 from CVS Commits --- The releases/gcc-10 branch has been updated by Peter Bergner : https://gcc.gnu.org/g:206d49a23735168769065716c4b211328dbf1b76 commit r10-9929-g206d49a23735168769065716c4b211328dbf1b76 Author: Peter Bergner Date: Sun May 30 22:45:55 2021 -0500 rs6000: MMA test case ICEs using -O3 [PR99842] The mma_assemble_input_operand predicate does not accept reg+reg indexed addresses which can lead to ICEs. The lxv and lxvp instructions have indexed forms (lxvx and lxvpx), so the simple solution is to just allow indexed addresses in the predicate. 2021-05-30 Peter Bergner gcc/ PR target/99842 * config/rs6000/predicates.md(mma_assemble_input_operand): Allow indexed form addresses. gcc/testsuite/ PR target/99842 * g++.target/powerpc/pr99842.C: New. (cherry picked from commit df4e0359dad239854af0ea9eacb8e7e3719557d0)
[Bug target/99842] MMA test case ICEs using -O3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842 --- Comment #5 from CVS Commits --- The releases/gcc-11 branch has been updated by Peter Bergner : https://gcc.gnu.org/g:aaa8419bcf2ec491c0fd41a526f5817da0cf3ed4 commit r11-8608-gaaa8419bcf2ec491c0fd41a526f5817da0cf3ed4 Author: Peter Bergner Date: Sun May 30 22:45:55 2021 -0500 rs6000: MMA test case ICEs using -O3 [PR99842] The mma_assemble_input_operand predicate does not accept reg+reg indexed addresses which can lead to ICEs. The lxv and lxvp instructions have indexed forms (lxvx and lxvpx), so the simple solution is to just allow indexed addresses in the predicate. 2021-05-30 Peter Bergner gcc/ PR target/99842 * config/rs6000/predicates.md(mma_assemble_input_operand): Allow indexed form addresses. gcc/testsuite/ PR target/99842 * g++.target/powerpc/pr99842.C: New. (cherry picked from commit df4e0359dad239854af0ea9eacb8e7e3719557d0)
[Bug target/99842] MMA test case ICEs using -O3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842 --- Comment #4 from CVS Commits --- The master branch has been updated by Peter Bergner : https://gcc.gnu.org/g:df4e0359dad239854af0ea9eacb8e7e3719557d0 commit r12-1127-gdf4e0359dad239854af0ea9eacb8e7e3719557d0 Author: Peter Bergner Date: Sun May 30 22:45:55 2021 -0500 rs6000: MMA test case ICEs using -O3 [PR99842] The mma_assemble_input_operand predicate does not accept reg+reg indexed addresses which can lead to ICEs. The lxv and lxvp instructions have indexed forms (lxvx and lxvpx), so the simple solution is to just allow indexed addresses in the predicate. 2021-05-30 Peter Bergner gcc/ PR target/99842 * config/rs6000/predicates.md(mma_assemble_input_operand): Allow indexed form addresses. gcc/testsuite/ PR target/99842 * g++.target/powerpc/pr99842.C: New.
[Bug target/99842] MMA test case ICEs using -O3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842 Peter Bergner changed: What|Removed |Added Known to fail||12.0 URL|https://gcc.gnu.org/piperma |https://gcc.gnu.org/piperma |il/gcc-patches/2021-March/5 |il/gcc-patches/2021-May/571 |67496.html |012.html --- Comment #3 from Peter Bergner --- Updated patch submitted.
[Bug target/99842] MMA test case ICEs using -O3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842 Jakub Jelinek changed: What|Removed |Added Target Milestone|11.0|11.2 --- Comment #2 from Jakub Jelinek --- GCC 11.1 has been released, retargeting bugs to GCC 11.2.
[Bug target/99842] MMA test case ICEs using -O3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842 Peter Bergner changed: What|Removed |Added Target||powerpc64le-linux Ever confirmed|0 |1 Known to fail||11.0 Assignee|unassigned at gcc dot gnu.org |bergner at gcc dot gnu.org Last reconfirmed||2021-03-30 Status|UNCONFIRMED |ASSIGNED Target Milestone|--- |11.0 --- Comment #1 from Peter Bergner --- Mine. The problem is that the mma_assemble_input_operand predicate is rejecting valid reg+reg indexed addresses in the MEMs in the above rtl. The predicate is calling quad_address_p() which accepts reg+offset addresses (with constrained offset values), but doesn't allow reg+reg addresses, which are valid. Replacing the MEM_P() && quad_address_p() test with a call to memory_operand() fixes the ICE, since it calls down to rs6000_legitimate_address_p(), which calls quad_address_p() to validate reg+offset addresses, but also allows reg+reg addresses. I'll submit a patch with that fix.
