https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108430
Bug ID: 108430 Summary: [13 Regression] Wrong code with -msve-vector-bits=512 since r13-707-g68e0063397 Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: acoplan at gcc dot gnu.org Target Milestone: --- For the following testcase: static long d; static int i = 37; static unsigned long a[22]; static unsigned short c[22]; static unsigned g[80]; static unsigned short *h = c; static unsigned long *j = a; int main() { for (long m = 0; m < 8; ++m) d = 1; for (unsigned char p = 0; p < 17; p += (d ? i : 0) - 35) { long t = h[p] ? i : j[p]; g[p] = t; } if (g[0]) __builtin_abort (); } we appear to miscompile it with -O3 -march=armv8.2-a+sve -msve-vector-bits=512 since r13-707-g68e0063397ba820e71adc220b2da0581dce29ffa : commit 68e0063397ba820e71adc220b2da0581dce29ffa (HEAD, refs/bisect/bad) Author: Richard Biener <rguent...@suse.de> Date: Mon Apr 11 12:36:53 2022 Force the selection operand of a GIMPLE COND_EXPR to be a register