[Bug tree-optimization/113602] ICE: in vn_reference_maybe_forwprop_address, at tree-ssa-sccvn.cc:1426 with invalid _BitInt() register asm with -O2 -fno-tree-loop-optimize

2024-01-26 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113602

--- Comment #3 from GCC Commits  ---
The master branch has been updated by Richard Biener :

https://gcc.gnu.org/g:f9b143d239db775318a29e9ff63f232b9501a22a

commit r14-8450-gf9b143d239db775318a29e9ff63f232b9501a22a
Author: Richard Biener 
Date:   Fri Jan 26 09:29:22 2024 +0100

tree-optimization/113602 - datarefs of non-addressables

We can end up creating ADDR_EXPRs of non-addressable entities during
for example vectorization.  The following plugs this in data-ref
analysis when that would create such invalid ADDR_EXPR as part of
analyzing the ref structure.

PR tree-optimization/113602
* tree-data-ref.cc (dr_analyze_innermost): Fail when
the base object isn't addressable.

* gcc.dg/pr113602.c: New testcase.

[Bug tree-optimization/113602] ICE: in vn_reference_maybe_forwprop_address, at tree-ssa-sccvn.cc:1426 with invalid _BitInt() register asm with -O2 -fno-tree-loop-optimize

2024-01-26 Thread rguenth at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113602

Richard Biener  changed:

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Richard Biener  ---
Fixed.

[Bug tree-optimization/113602] ICE: in vn_reference_maybe_forwprop_address, at tree-ssa-sccvn.cc:1426 with invalid _BitInt() register asm with -O2 -fno-tree-loop-optimize

2024-01-26 Thread rguenth at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113602

Richard Biener  changed:

   What|Removed |Added

 Status|NEW |ASSIGNED
   Assignee|unassigned at gcc dot gnu.org  |rguenth at gcc dot 
gnu.org

--- Comment #2 from Richard Biener  ---
(gdb) p tem.last ()
$2 = (vn_reference_op_struct &) @0x7fffc820: {opcode = VAR_DECL, 
  clique = 0, base = 0, reverse = 0, align = 0, off = {coeffs = {-1}}, 
  type = , op0 = , 
  op1 = , op2 = }
(gdb) p debug_vn_reference_ops (tem)
{array_ref<_4,0,1>,view_convert_expr,r}
(gdb) p debug_generic_expr (addr)
_CONVERT_EXPR(r)[_4]

We're valueizing

MEM  [(_BitInt(503) *)vectp.5_18]

trying to forward the vectp.5_18 def

vectp.5_18 = _CONVERT_EXPR(r)[_4];

but we're not anticipating this shape of a non-invariant ADDR_EXPR.  We
do wrap all VAR_DECLs but DECL_HARD_REGISTER inside a MEM_REF but then
a DECL_HARD_REGISTER shouldn't be addressable so the IL is actually
invalid, generated by vectorization (but not diagnosed by IL checking).

I'm not sure to what extent we should try to paper over this though ...

The following works for me:

diff --git a/gcc/tree-data-ref.cc b/gcc/tree-data-ref.cc
index ae55bf6aa48..f37734b5340 100644
--- a/gcc/tree-data-ref.cc
+++ b/gcc/tree-data-ref.cc
@@ -1182,7 +1182,12 @@ dr_analyze_innermost (innermost_loop_behavior *drb, tree
ref,
   base = TREE_OPERAND (base, 0);
 }
   else
-base = build_fold_addr_expr (base);
+{
+  if (may_be_nonaddressable_p (base))
+   return opt_result::failure_at (stmt,
+  "failed: base not addressable.\n");
+  base = build_fold_addr_expr (base);
+}

   if (in_loop)
 {

[Bug tree-optimization/113602] ICE: in vn_reference_maybe_forwprop_address, at tree-ssa-sccvn.cc:1426 with invalid _BitInt() register asm with -O2 -fno-tree-loop-optimize

2024-01-25 Thread pinskia at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113602

Andrew Pinski  changed:

   What|Removed |Added

 Status|UNCONFIRMED |NEW
 Ever confirmed|0   |1
   Last reconfirmed||2024-01-25

--- Comment #1 from Andrew Pinski  ---
Confirmed.