[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413 --- Comment #1 from Anatoly aries.nah at gmail dot com 2011-09-15 08:44:57 UTC --- Created attachment 25289 -- http://gcc.gnu.org/bugzilla/attachment.cgi?id=25289 C++ source code
[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413 --- Comment #2 from Anatoly aries.nah at gmail dot com 2011-09-15 09:05:03 UTC --- Forgot to mention: Intel(R) Core(TM) i5 CPU 760 @ 2.80GHz LGA1156 And there's no such bug in GCC 4.3.4
[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413 Uros Bizjak ubizjak at gmail dot com changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution||INVALID --- Comment #3 from Uros Bizjak ubizjak at gmail dot com 2011-09-15 13:29:23 UTC --- (In reply to comment #0) After compilation an attached code with -O2 and -ftree-vectorize flags, it doesn't work properly. Assembler code shows that G++ tries to replace the following code V.uint128.uint64_lower = (V.uint128.uint64_lower 1); V.bitmap.b63 = V.bitmap.b64; V.uint128.uint64_upper = (V.uint128.uint64_upper 1); with SSE instructions: 400a10: movdqa 0x103d8(%rip),%xmm0# 410df0 V 400a17: and$0x1,%edi 400a1b: psrlq $0x1,%xmm0 400a20: movdqa %xmm0,0x103c8(%rip)# 410df0 V But psrlq shifts 64 bit value, it's necessary to use psrldq here You are wrong. The code above describes shift of two 64bit elements, each by one, so psrlq [1] is correct. [1] http://www.rz.uni-karlsruhe.de/rz/docs/VTune/reference/vc259.htm
[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413 Anatoly aries.nah at gmail dot com changed: What|Removed |Added Status|RESOLVED|UNCONFIRMED Resolution|INVALID | --- Comment #4 from Anatoly aries.nah at gmail dot com 2011-09-15 13:42:05 UTC --- It's not serious. Yes, I'm not an expert in SSE instructions (and in ASM at all), and it seems you're right about shifting. But, the bug is a real. GCC losts lower bit of upper quadword during shifting by psrlq. Try to compile my code and check it out. We have V.bitmap.b63 = V.bitmap.b64; to shift a lower bit of the upper quadword but GCC has decided not to do this.
[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413 --- Comment #5 from Uros Bizjak ubizjak at gmail dot com 2011-09-15 14:17:34 UTC --- (In reply to comment #4) We have V.bitmap.b63 = V.bitmap.b64; to shift a lower bit of the upper quadword but GCC has decided not to do this. Ah, I didn't see the purpose of this assignment. I will investigate this a bit more.
