[gcc r14-9538] LoongArch: Fix C23 (...) functions returning large aggregates [PR114175]
https://gcc.gnu.org/g:c1fd4589c2bf9fd8409d51b94df219cb75107762 commit r14-9538-gc1fd4589c2bf9fd8409d51b94df219cb75107762 Author: Xi Ruoyao Date: Mon Mar 18 17:18:34 2024 +0800 LoongArch: Fix C23 (...) functions returning large aggregates [PR114175] We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and there is nothing to advance, but that is not the case for (...) functions returning by hidden reference which have one such artificial argument. This is causing gcc.dg/c23-stdarg-6.c and gcc.dg/c23-stdarg-8.c to fail. Fix the issue by checking if arg.type is NULL, as r14-9503 explains. gcc/ChangeLog: PR target/114175 * config/loongarch/loongarch.cc (loongarch_setup_incoming_varargs): Only skip loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL. Diff: --- gcc/config/loongarch/loongarch.cc | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 70e31bb831c..5344f2a6987 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -767,7 +767,13 @@ loongarch_setup_incoming_varargs (cumulative_args_t cum, argument. Advance a local copy of CUM past the last "real" named argument, to find out how many registers are left over. */ local_cum = *get_cumulative_args (cum); - if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))) + + /* For a C23 variadic function w/o any named argument, and w/o an + artifical argument for large return value, skip advancing args. + There is such an artifical argument iff. arg.type is non-NULL + (PR 114175). */ + if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) + || arg.type != NULL_TREE) loongarch_function_arg_advance (pack_cumulative_args (_cum), arg); /* Found out how many registers we need to save. */
[gcc r14-9539] arc: Fix up arc_setup_incoming_varargs [PR114175]
https://gcc.gnu.org/g:1f257714674cd8fd69db7367aecdd09b672d1db7 commit r14-9539-g1f257714674cd8fd69db7367aecdd09b672d1db7 Author: Jakub Jelinek Date: Tue Mar 19 09:49:59 2024 +0100 arc: Fix up arc_setup_incoming_varargs [PR114175] Like for x86-64, alpha or rs6000, arc seems to be affected too. 2024-03-19 Jakub Jelinek PR target/114175 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL. Diff: --- gcc/config/arc/arc.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc index 179f11f7077..686de0ff2d5 100644 --- a/gcc/config/arc/arc.cc +++ b/gcc/config/arc/arc.cc @@ -2352,7 +2352,8 @@ arc_setup_incoming_varargs (cumulative_args_t args_so_far, /* We must treat `__builtin_va_alist' as an anonymous arg. */ next_cum = *get_cumulative_args (args_so_far); - if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))) + if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) + || arg.type != NULL_TREE) arc_function_arg_advance (pack_cumulative_args (_cum), arg); first_anon_arg = next_cum;
[gcc r14-9536] alpha: Fix alpha_setup_incoming_varargs [PR114175]
https://gcc.gnu.org/g:a185d8aeeed7a25a01505565aa61ccf8a876c6ff
commit r14-9536-ga185d8aeeed7a25a01505565aa61ccf8a876c6ff
Author: Jakub Jelinek
Date: Tue Mar 19 09:14:11 2024 +0100
alpha: Fix alpha_setup_incoming_varargs [PR114175]
Like in the r14-9503 change on x86-64, I think Alpha also needs to
function_arg_advance after the hidden return pointer argument if
any.
At least, the following patch changes the assembly of s1-s6 functions
on the https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647956.html
c23-stdarg-9.c testcase, and eyeballing the assembly for int f8 (...)
the ... args are passed in 16..21 registers and then on the stack,
while for struct S s8 (...) have hidden return pointer passed in 16
register and ... args in 17..21 registers and then on the stack, and
seems without this patch the incoming varargs setup does the wrong thing
(but I can't test on alpha easily).
Many targets seem to be unaffected, e.g. aarch64, arm, s390*, so I'm not
trying to change all targets together because such a change clearly isn't
needed e.g. for targets which use special register for the hidden return
pointer.
2024-03-19 Jakub Jelinek
PR target/114175
* config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
if arg.type is NULL.
Diff:
---
gcc/config/alpha/alpha.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc
index 98df142fb06..1126cea1f7b 100644
--- a/gcc/config/alpha/alpha.cc
+++ b/gcc/config/alpha/alpha.cc
@@ -6090,7 +6090,8 @@ alpha_setup_incoming_varargs (cumulative_args_t pcum,
{
CUMULATIVE_ARGS cum = *get_cumulative_args (pcum);
- if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)))
+ if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
+ || arg.type != NULL_TREE)
/* Skip the current argument. */
targetm.calls.function_arg_advance (pack_cumulative_args (), arg);
[gcc r14-9537] arm: [MVE intrinsics] Fix support for loads [PR target/114323]
https://gcc.gnu.org/g:167ec6df7fd8deb67759acd5dbe72c1982a55873
commit r14-9537-g167ec6df7fd8deb67759acd5dbe72c1982a55873
Author: Christophe Lyon
Date: Fri Mar 15 19:55:43 2024 +
arm: [MVE intrinsics] Fix support for loads [PR target/114323]
The testcase in this PR shows that we would load from an uninitialized
location, because the vld1 instrinsics are reported as "const". This
is because function_instance::reads_global_state_p() does not take
CP_READ_MEMORY into account. Fixing this gives vld1 the "pure"
attribute instead, and solves the problem.
2024-03-15 Christophe Lyon
PR target/114323
gcc/
* config/arm/arm-mve-builtins.cc
(function_instance::reads_global_state_p): Take CP_READ_MEMORY
into account.
gcc/testsuite/
* gcc.target/arm/mve/pr114323.c: New.
Diff:
---
gcc/config/arm/arm-mve-builtins.cc | 2 +-
gcc/testsuite/gcc.target/arm/mve/pr114323.c | 22 ++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm-mve-builtins.cc
b/gcc/config/arm/arm-mve-builtins.cc
index c533d0e93ae..7e8217666fe 100644
--- a/gcc/config/arm/arm-mve-builtins.cc
+++ b/gcc/config/arm/arm-mve-builtins.cc
@@ -657,7 +657,7 @@ function_instance::reads_global_state_p () const
if (flags & CP_READ_FPCR)
return true;
- return false;
+ return flags & CP_READ_MEMORY;
}
/* Return true if calls to the function could modify some form of
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr114323.c
b/gcc/testsuite/gcc.target/arm/mve/pr114323.c
new file mode 100644
index 000..bd9127b886a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr114323.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+
+#include
+
+__attribute__((noipa))
+uint32x4_t foo (void) {
+ uint32x4_t V0 = vld1q_u32(((const uint32_t[4]){1, 2, 3, 4}));
+ return V0;
+}
+
+int main(void)
+{
+ uint32_t buf[4];
+ vst1q_u32 (buf, foo());
+
+ for (int i = 0; i < 4; i++)
+if (buf[i] != i+1)
+ __builtin_abort ();
+}
[gcc r14-9533] tree-optimization/114375 - disallow SLP discovery of permuted mask loads
https://gcc.gnu.org/g:94c3508c5a14d1948fe3bffa9e16c6f3d9c2836a
commit r14-9533-g94c3508c5a14d1948fe3bffa9e16c6f3d9c2836a
Author: Richard Biener
Date: Mon Mar 18 12:39:03 2024 +0100
tree-optimization/114375 - disallow SLP discovery of permuted mask loads
We cannot currently handle permutations of mask loads in code generation
or permute optimization. But we simply drop any permutation on the
floor, so the following instead rejects the SLP build rather than
producing wrong-code. I've also made sure to reject them in
vectorizable_load for completeness.
PR tree-optimization/114375
* tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
load permutation for masked loads but reject it when any
such is necessary.
* tree-vect-stmts.cc (vectorizable_load): Reject masked
VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
supported.
* gcc.dg/vect/vect-pr114375.c: New testcase.
Diff:
---
gcc/testsuite/gcc.dg/vect/vect-pr114375.c | 44 +++
gcc/tree-vect-slp.cc | 39 ---
gcc/tree-vect-stmts.cc| 8 ++
3 files changed, 81 insertions(+), 10 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-pr114375.c
b/gcc/testsuite/gcc.dg/vect/vect-pr114375.c
new file mode 100644
index 000..1e1cb0123d0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/vect-pr114375.c
@@ -0,0 +1,44 @@
+/* { dg-additional-options "-mavx2" { target avx2_runtime } } */
+
+#include "tree-vect.h"
+
+int a[512];
+int b[512];
+int c[512];
+
+void __attribute__((noipa))
+foo(int * __restrict p)
+{
+ for (int i = 0; i < 64; ++i)
+{
+ int tem = 2, tem2 = 2;
+ if (a[4*i + 1])
+tem = p[4*i];
+ if (a[4*i])
+tem2 = p[4*i + 2];
+ b[2*i] = tem2;
+ b[2*i+1] = tem;
+ if (a[4*i + 2])
+tem = p[4*i + 1];
+ if (a[4*i + 3])
+tem2 = p[4*i + 3];
+ c[2*i] = tem2;
+ c[2*i+1] = tem;
+}
+}
+int main()
+{
+ check_vect ();
+
+ for (int i = 0; i < 512; ++i)
+a[i] = (i >> 1) & 1;
+
+ foo (a);
+
+ if (c[0] != 1 || c[1] != 0 || c[2] != 1 || c[3] != 0
+ || b[0] != 2 || b[1] != 2 || b[2] != 2 || b[3] != 2)
+abort ();
+
+ return 0;
+}
+
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 527b06c9f9c..23f9593191a 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -1921,12 +1921,7 @@ vect_build_slp_tree_2 (vec_info *vinfo, slp_tree node,
if (STMT_VINFO_DATA_REF (stmt_info)
&& DR_IS_READ (STMT_VINFO_DATA_REF (stmt_info)))
{
- if (gcall *stmt = dyn_cast (stmt_info->stmt))
- gcc_assert (gimple_call_internal_p (stmt, IFN_MASK_LOAD)
- || gimple_call_internal_p (stmt, IFN_GATHER_LOAD)
- || gimple_call_internal_p (stmt, IFN_MASK_GATHER_LOAD)
- || gimple_call_internal_p (stmt, IFN_MASK_LEN_GATHER_LOAD));
- else if (STMT_VINFO_GATHER_SCATTER_P (stmt_info))
+ if (STMT_VINFO_GATHER_SCATTER_P (stmt_info))
gcc_assert (DR_IS_READ (STMT_VINFO_DATA_REF (stmt_info)));
else
{
@@ -1943,19 +1938,43 @@ vect_build_slp_tree_2 (vec_info *vinfo, slp_tree node,
load_permutation.create (group_size);
stmt_vec_info first_stmt_info
= DR_GROUP_FIRST_ELEMENT (SLP_TREE_SCALAR_STMTS (node)[0]);
+ bool any_permute = false;
FOR_EACH_VEC_ELT (SLP_TREE_SCALAR_STMTS (node), j, load_info)
{
int load_place;
if (STMT_VINFO_GROUPED_ACCESS (stmt_info))
load_place = vect_get_place_in_interleaving_chain
- (load_info, first_stmt_info);
+ (load_info, first_stmt_info);
else
load_place = 0;
gcc_assert (load_place != -1);
- load_permutation.safe_push (load_place);
+ any_permute |= load_place != j;
+ load_permutation.quick_push (load_place);
+ }
+
+ if (gcall *stmt = dyn_cast (stmt_info->stmt))
+ {
+ gcc_assert (gimple_call_internal_p (stmt, IFN_MASK_LOAD)
+ || gimple_call_internal_p (stmt, IFN_GATHER_LOAD)
+ || gimple_call_internal_p (stmt, IFN_MASK_GATHER_LOAD)
+ || gimple_call_internal_p (stmt,
+IFN_MASK_LEN_GATHER_LOAD));
+ load_permutation.release ();
+ /* We cannot handle permuted masked loads, see PR114375. */
+ if (any_permute
+ || (STMT_VINFO_GROUPED_ACCESS (stmt_info)
+ && DR_GROUP_SIZE (first_stmt_info) != group_size)
+ || STMT_VINFO_STRIDED_P (stmt_info))
+ {
+ matches[0] = false;
+ return NULL;
+ }
+
[gcc r14-9534] openmp: Make c_omp_check_loop_binding_exprs diagnostics translatable [PR114364]
https://gcc.gnu.org/g:8959ab63f1881a8a4b1921b946d4ea3986bf1063
commit r14-9534-g8959ab63f1881a8a4b1921b946d4ea3986bf1063
Author: Jakub Jelinek
Date: Tue Mar 19 09:10:26 2024 +0100
openmp: Make c_omp_check_loop_binding_exprs diagnostics translatable
[PR114364]
c_omp_check_loop_binding_exprs with check_loop_binding_expr was composing
diagnostics from a format string with %s that provided additional words
(but not
keywords). That is a big no no for translations, both because the
translator
can't choose a different word order and because the %s part wasn't
translated
at all (would need to use _("...") to get translated), so this patch
rewrites it
such that the whole messages are in the format strings.
2024-03-19 Jakub Jelinek
PR c/114364
* c-omp.cc (enum check_loop_binding_expr_ctx): New type.
(check_loop_binding_expr): Remove context argument, add ctx
argument with check_loop_binding_expr_ctx type at the end. Don't
create diagnostic message from multiple pieces.
(c_omp_check_loop_binding_exprs): Adjust callers.
Diff:
---
gcc/c-family/c-omp.cc | 51 +++
1 file changed, 39 insertions(+), 12 deletions(-)
diff --git a/gcc/c-family/c-omp.cc b/gcc/c-family/c-omp.cc
index 5117022e330..c0e02aa422f 100644
--- a/gcc/c-family/c-omp.cc
+++ b/gcc/c-family/c-omp.cc
@@ -1793,22 +1793,46 @@ check_loop_binding_expr_r (tree *tp, int *walk_subtrees
ATTRIBUTE_UNUSED,
#define LOCATION_OR(loc1, loc2) \
((loc1) != UNKNOWN_LOCATION ? (loc1) : (loc2))
+enum check_loop_binding_expr_ctx {
+ CHECK_LOOP_BINDING_EXPR_CTX_LOOP_VAR,
+ CHECK_LOOP_BINDING_EXPR_CTX_IN_INIT,
+ CHECK_LOOP_BINDING_EXPR_CTX_END_TEST,
+ CHECK_LOOP_BINDING_EXPR_CTX_INCR
+};
+
/* Check a single expression EXPR for references to variables bound in
intervening code in BODY. Return true if ok, otherwise give an error
referencing CONTEXT and return false. Use LOC for the error message
if EXPR doesn't have one. */
static bool
-check_loop_binding_expr (tree expr, tree body, const char *context,
-location_t loc)
+check_loop_binding_expr (tree expr, tree body, location_t loc,
+check_loop_binding_expr_ctx ctx)
{
tree bad = walk_tree (, check_loop_binding_expr_r, (void *), NULL);
if (bad)
{
location_t eloc = EXPR_LOCATION (expr);
- error_at (LOCATION_OR (eloc, loc),
- "variable %qD used %s is bound "
- "in intervening code", bad, context);
+ eloc = LOCATION_OR (eloc, loc);
+ switch (ctx)
+ {
+ case CHECK_LOOP_BINDING_EXPR_CTX_LOOP_VAR:
+ error_at (eloc, "variable %qD used as loop variable is bound "
+ "in intervening code", bad);
+ break;
+ case CHECK_LOOP_BINDING_EXPR_CTX_IN_INIT:
+ error_at (eloc, "variable %qD used in initializer is bound "
+ "in intervening code", bad);
+ break;
+ case CHECK_LOOP_BINDING_EXPR_CTX_END_TEST:
+ error_at (eloc, "variable %qD used in end test is bound "
+ "in intervening code", bad);
+ break;
+ case CHECK_LOOP_BINDING_EXPR_CTX_INCR:
+ error_at (eloc, "variable %qD used in increment expression is bound "
+ "in intervening code", bad);
+ break;
+ }
return false;
}
return true;
@@ -1839,13 +1863,15 @@ c_omp_check_loop_binding_exprs (tree stmt, vec
*orig_inits)
e = TREE_OPERAND (init, 1);
eloc = LOCATION_OR (EXPR_LOCATION (init), loc);
- if (!check_loop_binding_expr (decl, body, "as loop variable", eloc))
+ if (!check_loop_binding_expr (decl, body, eloc,
+ CHECK_LOOP_BINDING_EXPR_CTX_LOOP_VAR))
ok = false;
- if (!check_loop_binding_expr (e, body, "in initializer", eloc))
+ if (!check_loop_binding_expr (e, body, eloc,
+ CHECK_LOOP_BINDING_EXPR_CTX_IN_INIT))
ok = false;
if (orig_init
- && !check_loop_binding_expr (orig_init, body,
- "in initializer", eloc))
+ && !check_loop_binding_expr (orig_init, body, eloc,
+ CHECK_LOOP_BINDING_EXPR_CTX_IN_INIT))
ok = false;
/* INCR and/or COND may be null if this is a template with a
@@ -1859,7 +1885,8 @@ c_omp_check_loop_binding_exprs (tree stmt, vec
*orig_inits)
e = TREE_OPERAND (cond, 0);
else
e = cond;
- if (!check_loop_binding_expr (e, body, "in end test", eloc))
+ if (!check_loop_binding_expr (e, body, eloc,
+ CHECK_LOOP_BINDING_EXPR_CTX_END_TEST))
ok = false;
}
@@ -1870,8 +1897,8 @@ c_omp_check_loop_binding_exprs (tree stmt, vec
*orig_inits)
[gcc r14-9535] rs6000: Fix up setup_incoming_varargs [PR114175]
https://gcc.gnu.org/g:8f85b46337f90c3126b9cefd72ffd29eb9a4ebf3
commit r14-9535-g8f85b46337f90c3126b9cefd72ffd29eb9a4ebf3
Author: Jakub Jelinek
Date: Tue Mar 19 09:13:32 2024 +0100
rs6000: Fix up setup_incoming_varargs [PR114175]
The c23-stdarg-8.c test (as well as the new test below added to cover even
more cases) FAIL on powerpc64le-linux and presumably other powerpc* targets
as well.
Like in the r14-9503-g218d174961 change on x86-64 we need to advance
next_cum after the hidden return pointer argument even in case where
there are no user arguments before ... in C23.
The following patch does that.
There is another TYPE_NO_NAMED_ARGS_STDARG_P use later on:
if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
&& targetm.calls.must_pass_in_stack (arg))
first_reg_offset += rs6000_arg_size (TYPE_MODE (arg.type),
arg.type);
but I believe it was added there in r13-3549-g4fe34cdc unnecessarily,
when there is no hidden return pointer argument, arg.type is NULL and
must_pass_in_stack_var_size as well as must_pass_in_stack_var_size_or_pad
return false in that case, and for the TYPE_NO_NAMED_ARGS_STDARG_P
case with hidden return pointer argument that argument should have pointer
type and it is the first argument, so must_pass_in_stack shouldn't be true
for it either.
2024-03-19 Jakub Jelinek
PR target/114175
* config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P
functions
if arg.type is NULL.
* gcc.dg/c23-stdarg-9.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-call.cc| 3 +-
gcc/testsuite/gcc.dg/c23-stdarg-9.c | 284
2 files changed, 286 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc
index 8c590903c86..1f8f93a2ee7 100644
--- a/gcc/config/rs6000/rs6000-call.cc
+++ b/gcc/config/rs6000/rs6000-call.cc
@@ -2253,7 +2253,8 @@ setup_incoming_varargs (cumulative_args_t cum,
/* Skip the last named argument. */
next_cum = *get_cumulative_args (cum);
- if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)))
+ if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
+ || arg.type != NULL_TREE)
rs6000_function_arg_advance_1 (_cum, arg.mode, arg.type, arg.named,
0);
diff --git a/gcc/testsuite/gcc.dg/c23-stdarg-9.c
b/gcc/testsuite/gcc.dg/c23-stdarg-9.c
new file mode 100644
index 000..e2839e7e2cd
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/c23-stdarg-9.c
@@ -0,0 +1,284 @@
+/* Test C23 variadic functions with no named parameters, or last named
+ parameter with a declaration not allowed in C17. Execution tests. */
+/* { dg-do run } */
+/* { dg-options "-O2 -std=c23 -pedantic-errors" } */
+
+#include
+
+struct S { int a[1024]; };
+
+int
+f1 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+int
+f2 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+int
+f3 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+int
+f4 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+int
+f5 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+int
+f6 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+int
+f7 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+int
+f8 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ r += va_arg (ap, int);
+ va_end (ap);
+ return r;
+}
+
+struct S
+s1 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start (ap);
+ r += va_arg (ap, int);
+ va_end (ap);
+ struct S s = {};
+ s.a[0] = r;
+ return s;
+}
+
+struct S
+s2 (...)
+{
+ int r = 0;
+ va_list ap;
+ va_start
[gcc r14-9542] libstdc++: Sync the atomic_link_flags implementation with GCC.
https://gcc.gnu.org/g:71a44faa8a4f76d68356c66c6054e6c242df820f
commit r14-9542-g71a44faa8a4f76d68356c66c6054e6c242df820f
Author: Iain Sandoe
Date: Mon Mar 18 09:57:33 2024 +
libstdc++: Sync the atomic_link_flags implementation with GCC.
For Darwin, in order to allow uninstalled testing, we need to provide
a '-B' option pointing to each path containing an uninstalled library
that we are using (these get appended to the embedded runpaths).
This updates the version of the atomic_link_flags proc in the libstdc++
testsuite to do the same as the one in the GCC testsuite.
libstdc++-v3/ChangeLog:
* testsuite/lib/dg-options.exp (atomic_link_flags): Emit a -B
option for the path to the uninstalled libatomic.
Signed-off-by: Iain Sandoe
Diff:
---
libstdc++-v3/testsuite/lib/dg-options.exp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libstdc++-v3/testsuite/lib/dg-options.exp
b/libstdc++-v3/testsuite/lib/dg-options.exp
index bc387d17ed7..00ca678a53a 100644
--- a/libstdc++-v3/testsuite/lib/dg-options.exp
+++ b/libstdc++-v3/testsuite/lib/dg-options.exp
@@ -314,7 +314,7 @@ proc atomic_link_flags { paths } {
if { [file exists "${gccpath}/libatomic/.libs/libatomic.a"]
|| [file exists
"${gccpath}/libatomic/.libs/libatomic.${shlib_ext}"] } {
append flags " -B${gccpath}/libatomic/ "
- append flags " -L${gccpath}/libatomic/.libs"
+ append flags " -B${gccpath}/libatomic/.libs"
append ld_library_path ":${gccpath}/libatomic/.libs"
}
} else {
[gcc r12-10284] testsuite/i386: Correct pr111822.C dg-do options [PR111822]
https://gcc.gnu.org/g:f6ed0466d40de496b14225fae44acf618dac1fd2
commit r12-10284-gf6ed0466d40de496b14225fae44acf618dac1fd2
Author: Uros Bizjak
Date: Tue Mar 19 16:57:50 2024 +0100
testsuite/i386: Correct pr111822.C dg-do options [PR111822]
PR target/111822
gcc/testsuite/ChangeLog:
* g++.target/i386/pr111822.C (dg-do): Compile only for ia32 targets.
(dg-options): Add -march=x86-64.
Diff:
---
gcc/testsuite/g++.target/i386/pr111822.C | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/g++.target/i386/pr111822.C
b/gcc/testsuite/g++.target/i386/pr111822.C
index d405387b23c..0829c91f270 100644
--- a/gcc/testsuite/g++.target/i386/pr111822.C
+++ b/gcc/testsuite/g++.target/i386/pr111822.C
@@ -1,6 +1,6 @@
/* PR target/111822 */
-/* { dg-do compile } */
-/* { dg-options "-O2 -flive-range-shrinkage -fno-dce -fnon-call-exceptions" }
*/
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2 -flive-range-shrinkage -fno-dce -fnon-call-exceptions
-march=x86-64" } */
typedef union {
int *pNativeClosure;
[gcc r14-9550] libstdc++: Suppress deprecation messages from [PR101228]
https://gcc.gnu.org/g:c608b57f77a47179899666940c3b8b6a2e5435b2 commit r14-9550-gc608b57f77a47179899666940c3b8b6a2e5435b2 Author: Jonathan Wakely Date: Thu Feb 29 17:13:49 2024 + libstdc++: Suppress deprecation messages from [PR101228] libstdc++-v3/ChangeLog: PR libstdc++/101228 * include/pstl/parallel_backend_tbb.h (TBB_SUPPRESS_DEPRECATED_MESSAGES): Define before including then undef afterwards. Diff: --- libstdc++-v3/include/pstl/parallel_backend_tbb.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/libstdc++-v3/include/pstl/parallel_backend_tbb.h b/libstdc++-v3/include/pstl/parallel_backend_tbb.h index 3ff55237bff..96e4b709fbe 100644 --- a/libstdc++-v3/include/pstl/parallel_backend_tbb.h +++ b/libstdc++-v3/include/pstl/parallel_backend_tbb.h @@ -15,6 +15,11 @@ #include "parallel_backend_utils.h" +#ifndef TBB_SUPPRESS_DEPRECATED_MESSAGES +# define TBB_SUPPRESS_DEPRECATED_MESSAGES 1 +# define _GLIBCXX_UNDEF_SUPPRESS +#endif + // Bring in minimal required subset of Intel TBB #include #include @@ -25,6 +30,11 @@ #include #include +#ifdef _GLIBCXX_UNDEF_SUPPRESS +# undef TBB_SUPPRESS_DEPRECATED_MESSAGES +# undef _GLIBCXX_UNDEF_SUPPRESS +#endif + #if TBB_INTERFACE_VERSION < 1 #error Intel(R) Threading Building Blocks 2018 is required; older versions are not supported. #endif
[gcc r14-9551] libstdc++: Fix infinite loop in std::binomial_distribution [PR114359]
https://gcc.gnu.org/g:07e03761a7fc1626a6a74ed957e117f56981558c
commit r14-9551-g07e03761a7fc1626a6a74ed957e117f56981558c
Author: Jonathan Wakely
Date: Mon Mar 18 13:22:17 2024 +
libstdc++: Fix infinite loop in std::binomial_distribution [PR114359]
The multiplication (4 * _M_t * __1p) can wraparound to zero if _M_t is
unsigned and 4 * _M_t wraps to zero. The third operand has type double,
so do the second multiplication first, so that we aren't multiplying
integers.
libstdc++-v3/ChangeLog:
PR libstdc++/114359
* include/bits/random.tcc (binomial_distribution::param_type):
Ensure arithmetic is done as type double.
* testsuite/26_numerics/random/binomial_distribution/114359.cc: New
test.
Diff:
---
libstdc++-v3/include/bits/random.tcc | 2 +-
.../26_numerics/random/binomial_distribution/114359.cc | 12
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/libstdc++-v3/include/bits/random.tcc
b/libstdc++-v3/include/bits/random.tcc
index ade416390b3..8216883c448 100644
--- a/libstdc++-v3/include/bits/random.tcc
+++ b/libstdc++-v3/include/bits/random.tcc
@@ -1503,7 +1503,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
// sqrt(pi / 2)
const double __spi_2 = 1.2533141373155002512078826424055226L;
_M_s1 = std::sqrt(__np * __1p) * (1 + _M_d1 / (4 * __np));
- _M_s2 = std::sqrt(__np * __1p) * (1 + _M_d2 / (4 * _M_t * __1p));
+ _M_s2 = std::sqrt(__np * __1p) * (1 + _M_d2 / (4 * (_M_t * __1p)));
_M_c = 2 * _M_d1 / __np;
_M_a1 = std::exp(_M_c) * _M_s1 * __spi_2;
const double __a12 = _M_a1 + _M_s2 * __spi_2;
diff --git
a/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/114359.cc
b/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/114359.cc
new file mode 100644
index 000..c1e4c380bf9
--- /dev/null
+++ b/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/114359.cc
@@ -0,0 +1,12 @@
+// { dg-do run { target c++11 } }
+
+// Bug 114359 - std::binomial_distribution hangs in infinite loop
+
+#include
+
+int main()
+{
+ std::default_random_engine g{};
+ std::binomial_distribution b(1U << 30);
+ b(g); // hangs forever
+}
[gcc r13-8466] i386: Unify {general, timode}_scalar_chain::convert_op [PR111822]
https://gcc.gnu.org/g:1a6d04fce7d78b9e5201333be0c0877390f81bc3
commit r13-8466-g1a6d04fce7d78b9e5201333be0c0877390f81bc3
Author: Uros Bizjak
Date: Tue Mar 19 16:56:11 2024 +0100
i386: Unify {general,timode}_scalar_chain::convert_op [PR111822]
Recent PR111822 fix implemented REG_EH_REGION note copying to a STV
converted
preload instruction in general_scalar_chain::convert_op. However, the same
issue remains in timode_scalar_chain::convert_op. Instead of copying the
newly introduced code to timode_scalar_chain::convert_op, the patch unifies
both functions to a common function.
PR target/111822
gcc/ChangeLog:
* config/i386/i386-features.cc (smode_convert_cst): New function
to handle SImode, DImode and TImode immediates.
(scalar_chain::convert_op): Unify from
general_scalar_chain::convert_op and
timode_scalar_chain::convert_op.
(general_scalar_chain::convert_op): Remove.
(timode_scalar_chain::convert_op): Remove.
* config/i386/i386-features.h (class scalar_chain):
Redeclare convert_op as protected class member.
(class general_calar_chain): Remove convert_op.
(class timode_scalar_chain): Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/pr111822.C (dg-do): Compile only for ia32 targets.
(dg-options): Add -march=x86-64.
Diff:
---
gcc/config/i386/i386-features.cc | 119 ++-
gcc/config/i386/i386-features.h | 4 +-
gcc/testsuite/g++.target/i386/pr111822.C | 4 +-
3 files changed, 39 insertions(+), 88 deletions(-)
diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc
index ed3055b43f8..34c320d7eae 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -896,14 +896,35 @@ scalar_chain::convert_reg (rtx_insn *insn, rtx dst, rtx
src)
REGNO (src), REGNO (dst), INSN_UID (insn));
}
+/* Helper function to convert immediate constant X to vmode. */
+static rtx
+smode_convert_cst (rtx x, enum machine_mode vmode)
+{
+ /* Prefer all ones vector in case of -1. */
+ if (constm1_operand (x, GET_MODE (x)))
+return CONSTM1_RTX (vmode);
+
+ unsigned n = GET_MODE_NUNITS (vmode);
+ rtx *v = XALLOCAVEC (rtx, n);
+ v[0] = x;
+ for (unsigned i = 1; i < n; ++i)
+v[i] = const0_rtx;
+ return gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (n, v));
+}
+
/* Convert operand OP in INSN. We should handle
memory operands and uninitialized registers.
All other register uses are converted during
registers conversion. */
void
-general_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
+scalar_chain::convert_op (rtx *op, rtx_insn *insn)
{
+ rtx tmp;
+
+ if (GET_MODE (*op) == V1TImode)
+return;
+
*op = copy_rtx_if_shared (*op);
if (GET_CODE (*op) == NOT)
@@ -913,20 +934,21 @@ general_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
}
else if (MEM_P (*op))
{
- rtx_insn* eh_insn, *movabs = NULL;
- rtx tmp = gen_reg_rtx (GET_MODE (*op));
+ rtx_insn *movabs = NULL;
/* Emit MOVABS to load from a 64-bit absolute address to a GPR. */
if (!memory_operand (*op, GET_MODE (*op)))
{
- rtx tmp2 = gen_reg_rtx (GET_MODE (*op));
- movabs = emit_insn_before (gen_rtx_SET (tmp2, *op), insn);
+ tmp = gen_reg_rtx (GET_MODE (*op));
+ movabs = emit_insn_before (gen_rtx_SET (tmp, *op), insn);
- *op = tmp2;
+ *op = tmp;
}
- eh_insn
- = emit_insn_before (gen_rtx_SET (gen_rtx_SUBREG (vmode, tmp, 0),
+ tmp = gen_rtx_SUBREG (vmode, gen_reg_rtx (GET_MODE (*op)), 0);
+
+ rtx_insn *eh_insn
+ = emit_insn_before (gen_rtx_SET (copy_rtx (tmp),
gen_gpr_to_xmm_move_src (vmode, *op)),
insn);
@@ -943,33 +965,17 @@ general_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
}
}
- *op = gen_rtx_SUBREG (vmode, tmp, 0);
+ *op = tmp;
if (dump_file)
fprintf (dump_file, " Preloading operand for insn %d into r%d\n",
INSN_UID (insn), REGNO (tmp));
}
else if (REG_P (*op))
+*op = gen_rtx_SUBREG (vmode, *op, 0);
+ else if (CONST_SCALAR_INT_P (*op))
{
- *op = gen_rtx_SUBREG (vmode, *op, 0);
-}
- else if (CONST_INT_P (*op))
-{
- rtx vec_cst;
- rtx tmp = gen_rtx_SUBREG (vmode, gen_reg_rtx (smode), 0);
-
- /* Prefer all ones vector in case of -1. */
- if (constm1_operand (*op, GET_MODE (*op)))
- vec_cst = CONSTM1_RTX (vmode);
- else
- {
- unsigned n = GET_MODE_NUNITS (vmode);
- rtx *v = XALLOCAVEC (rtx, n);
- v[0] = *op;
- for (unsigned i = 1; i < n; ++i)
- v[i] = const0_rtx;
- vec_cst = gen_rtx_CONST_VECTOR (vmode,
[gcc r14-9543] testsuite, Darwin: Use the IOKit framework in framework-1.c [PR114049].
https://gcc.gnu.org/g:4adb1a5839e7a3310a127c1776f1f95d7edaa6ff
commit r14-9543-g4adb1a5839e7a3310a127c1776f1f95d7edaa6ff
Author: Iain Sandoe
Date: Mon Mar 18 10:06:44 2024 +
testsuite, Darwin: Use the IOKit framework in framework-1.c [PR114049].
The intent of the test is to show that we find a framework that
is installed in /System/Library/Frameworks when the user has added
a '-F' option. The trick is to choose some header that is present
for all the Darwin versions we support and that does not contain any
content we cannot parse. We had been using the Kernel framework for
this, but recent SDK versions have revealed that this is not suitable.
Replacing with a use of IOKit.
PR target/114049
gcc/testsuite/ChangeLog:
* gcc.dg/framework-1.c: Use an IOKit header instead of a
Kernel one.
Signed-off-by: Iain Sandoe
Diff:
---
gcc/testsuite/gcc.dg/framework-1.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/framework-1.c
b/gcc/testsuite/gcc.dg/framework-1.c
index de4adc39868..fdec129a8fb 100644
--- a/gcc/testsuite/gcc.dg/framework-1.c
+++ b/gcc/testsuite/gcc.dg/framework-1.c
@@ -1,4 +1,10 @@
/* { dg-do compile { target *-*-darwin* } } */
/* { dg-options "-F." } */
-#include
+/* The intent of the test is to show that we find a framework that
+ is installed in /System/Library/Frameworks when the user has added
+ a '-F' option. The trick is to choose some header that is present
+ for all the Darwin versions we support and that does not contain any
+ content we cannot parse. */
+
+#include
[gcc r14-9544] analyzer: fixes to __atomic_{exchange, load, store} [PR114286]
https://gcc.gnu.org/g:c7a774edbf802d79b95871ede5b80f6e9adf8e88
commit r14-9544-gc7a774edbf802d79b95871ede5b80f6e9adf8e88
Author: David Malcolm
Date: Tue Mar 19 09:06:45 2024 -0400
analyzer: fixes to __atomic_{exchange,load,store} [PR114286]
In r14-1497-gef768035ae8090 I added some support to the analyzer for
__atomic_ builtins (enough to fix false positives I was seeing in
my integration tests).
Unfortunately I messed up the implementation of
__atomic_{exchange,load,store}, leading to ICEs seen in
PR analyzer/114286.
Fixed thusly, fixing the ICEs. Given that we're in stage 4, the patch
doesn't add support for any of the various __atomic_compare_exchange
builtins, so that these continue to fall back to the analyzer's
"anything could happen" handling of unknown functions.
Signed-off-by: David Malcolm
gcc/analyzer/ChangeLog:
PR analyzer/114286
* kf.cc (class kf_atomic_exchange): Reimplement based on signature
seen in gimple, rather than user-facing signature.
(class kf_atomic_load): Likewise.
(class kf_atomic_store): New.
(register_atomic_builtins): Register kf_atomic_store.
gcc/testsuite/ChangeLog:
PR analyzer/114286
* c-c++-common/analyzer/atomic-builtins-pr114286.c: New test.
Signed-off-by: David Malcolm
Diff:
---
gcc/analyzer/kf.cc | 135 -
.../analyzer/atomic-builtins-pr114286.c| 48
2 files changed, 150 insertions(+), 33 deletions(-)
diff --git a/gcc/analyzer/kf.cc b/gcc/analyzer/kf.cc
index ed48ffbcba2..d197ccbd0f0 100644
--- a/gcc/analyzer/kf.cc
+++ b/gcc/analyzer/kf.cc
@@ -116,39 +116,54 @@ kf_alloca::impl_call_pre (const call_details ) const
cd.maybe_set_lhs (ptr_sval);
}
-/* Handler for:
- void __atomic_exchange (type *ptr, type *val, type *ret, int memorder). */
+/* Handler for __atomic_exchange.
+ Although the user-facing documentation specifies it as having this
+ signature:
+ void __atomic_exchange (type *ptr, type *val, type *ret, int memorder)
+
+ by the time the C/C++ frontends have acted on it, any calls that
+ can't be mapped to a _N variation end up with this signature:
+
+ void
+ __atomic_exchange (size_t sz, void *ptr, void *val, void *ret,
+ int memorder)
+
+ as seen in the gimple seen by the analyzer, and as specified
+ in sync-builtins.def. */
class kf_atomic_exchange : public internal_known_function
{
public:
/* This is effectively:
- *RET = *PTR;
- *PTR = *VAL;
+ tmpA = *PTR;
+ tmpB = *VAL;
+ *PTR = tmpB;
+ *RET = tmpA;
*/
void impl_call_pre (const call_details ) const final override
{
-const svalue *ptr_ptr_sval = cd.get_arg_svalue (0);
-tree ptr_ptr_tree = cd.get_arg_tree (0);
-const svalue *val_ptr_sval = cd.get_arg_svalue (1);
-tree val_ptr_tree = cd.get_arg_tree (1);
-const svalue *ret_ptr_sval = cd.get_arg_svalue (2);
-tree ret_ptr_tree = cd.get_arg_tree (2);
+const svalue *num_bytes_sval = cd.get_arg_svalue (0);
+const svalue *ptr_sval = cd.get_arg_svalue (1);
+tree ptr_tree = cd.get_arg_tree (1);
+const svalue *val_sval = cd.get_arg_svalue (2);
+tree val_tree = cd.get_arg_tree (2);
+const svalue *ret_sval = cd.get_arg_svalue (3);
+tree ret_tree = cd.get_arg_tree (3);
/* Ignore the memorder param. */
region_model *model = cd.get_model ();
region_model_context *ctxt = cd.get_ctxt ();
-const region *val_region
- = model->deref_rvalue (val_ptr_sval, val_ptr_tree, ctxt);
-const svalue *star_val_sval = model->get_store_value (val_region, ctxt);
-const region *ptr_region
- = model->deref_rvalue (ptr_ptr_sval, ptr_ptr_tree, ctxt);
-const svalue *star_ptr_sval = model->get_store_value (ptr_region, ctxt);
-const region *ret_region
- = model->deref_rvalue (ret_ptr_sval, ret_ptr_tree, ctxt);
-model->set_value (ptr_region, star_val_sval, ctxt);
-model->set_value (ret_region, star_ptr_sval, ctxt);
+const region *ptr_reg = model->deref_rvalue (ptr_sval, ptr_tree, ctxt);
+const region *val_reg = model->deref_rvalue (val_sval, val_tree, ctxt);
+const region *ret_reg = model->deref_rvalue (ret_sval, ret_tree, ctxt);
+
+const svalue *tmp_a_sval
+ = model->read_bytes (ptr_reg, ptr_tree, num_bytes_sval, ctxt);
+const svalue *tmp_b_sval
+ = model->read_bytes (val_reg, val_tree, num_bytes_sval, ctxt);
+model->write_bytes (ptr_reg, num_bytes_sval, tmp_b_sval, ctxt);
+model->write_bytes (ret_reg, num_bytes_sval, tmp_a_sval, ctxt);
}
};
@@ -265,32 +280,85 @@ private:
enum tree_code m_op;
};
-/* Handler for:
- void __atomic_load (type *ptr, type *ret, int memorder). */
+/* Handler for __atomic_load.
+ Although the user-facing documentation specifies it as
[gcc r14-9545] libstdc++: Begin lifetime of storage in std::vector [PR114367]
https://gcc.gnu.org/g:16afbd9c9c4282d56062cef95e6eccfdcf3efe03
commit r14-9545-g16afbd9c9c4282d56062cef95e6eccfdcf3efe03
Author: Jonathan Wakely
Date: Mon Mar 18 13:00:17 2024 +
libstdc++: Begin lifetime of storage in std::vector [PR114367]
This doesn't cause a problem with GCC, but Clang correctly diagnoses a
bug in the code. The objects in the allocated storage need to begin
their lifetime before we start using them.
This change uses the allocator's construct function instead of using
std::construct_at directly, in order to support fancy pointers.
libstdc++-v3/ChangeLog:
PR libstdc++/114367
* include/bits/stl_bvector.h (_M_allocate): Use allocator's
construct function to begin lifetime of words.
Diff:
---
libstdc++-v3/include/bits/stl_bvector.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/libstdc++-v3/include/bits/stl_bvector.h
b/libstdc++-v3/include/bits/stl_bvector.h
index 2c8b892b07a..a3343d95b36 100644
--- a/libstdc++-v3/include/bits/stl_bvector.h
+++ b/libstdc++-v3/include/bits/stl_bvector.h
@@ -674,13 +674,13 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER
_M_allocate(size_t __n)
{
_Bit_pointer __p = _Bit_alloc_traits::allocate(_M_impl, _S_nword(__n));
-#if __cpp_lib_is_constant_evaluated
+#if __cpp_lib_is_constant_evaluated && __cpp_constexpr_dynamic_alloc
if (std::is_constant_evaluated())
- {
- __n = _S_nword(__n);
- for (size_t __i = 0; __i < __n; ++__i)
- __p[__i] = 0ul;
- }
+ {
+ __n = _S_nword(__n);
+ for (size_t __i = 0; __i < __n; ++__i)
+ std::construct_at(std::to_address(__p) + __i);
+ }
#endif
return __p;
}
[gcc r14-9546] libstdc++: Fix typos in MemoryChecker assertion messages in PSTL tests
https://gcc.gnu.org/g:f5118546a8d0a99edb34fd672e7847370a1adae1
commit r14-9546-gf5118546a8d0a99edb34fd672e7847370a1adae1
Author: Jonathan Wakely
Date: Mon Mar 18 12:55:36 2024 +
libstdc++: Fix typos in MemoryChecker assertion messages in PSTL tests
This has been reported upstream.
libstdc++-v3/ChangeLog:
* testsuite/util/pstl/test_utils.h: Fix typos in comments.
Diff:
---
libstdc++-v3/testsuite/util/pstl/test_utils.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/libstdc++-v3/testsuite/util/pstl/test_utils.h
b/libstdc++-v3/testsuite/util/pstl/test_utils.h
index e35084eabb2..55b510098a0 100644
--- a/libstdc++-v3/testsuite/util/pstl/test_utils.h
+++ b/libstdc++-v3/testsuite/util/pstl/test_utils.h
@@ -252,7 +252,7 @@ struct MemoryChecker {
MemoryChecker(MemoryChecker&& other) : _value(other.value()) {
// check for EXPECT_TRUE(state() != alive_state, ...) has not been
done since
// compiler can optimize out the move ctor call that results in false
positive failure
-EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker(MemoryChecker&&): attemp to construct an object from non-existing
object");
+EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker(MemoryChecker&&): attempt to construct an object from
non-existing object");
// set constructed state and increment counter for living object
inc_alive_objects();
_state = alive_state;
@@ -260,15 +260,15 @@ struct MemoryChecker {
MemoryChecker(const MemoryChecker& other) : _value(other.value()) {
// check for EXPECT_TRUE(state() != alive_state, ...) has not been
done since
// compiler can optimize out the copy ctor call that results in false
positive failure
-EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker(const MemoryChecker&): attemp to construct an object from
non-existing object");
+EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker(const MemoryChecker&): attempt to construct an object from
non-existing object");
// set constructed state and increment counter for living object
inc_alive_objects();
_state = alive_state;
}
MemoryChecker& operator=(MemoryChecker&& other) {
// check if we do not assign over uninitialized memory
-EXPECT_TRUE(state() == alive_state, "wrong effect from
MemoryChecker::operator=(MemoryChecker&& other): attemp to assign to
non-existing object");
-EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker::operator=(MemoryChecker&& other): attemp to assign from
non-existing object");
+EXPECT_TRUE(state() == alive_state, "wrong effect from
MemoryChecker::operator=(MemoryChecker&& other): attempt to assign to
non-existing object");
+EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker::operator=(MemoryChecker&& other): attempt to assign from
non-existing object");
// just assign new value, counter is the same, state is the same
_value = other.value();
@@ -276,8 +276,8 @@ struct MemoryChecker {
}
MemoryChecker& operator=(const MemoryChecker& other) {
// check if we do not assign over uninitialized memory
-EXPECT_TRUE(state() == alive_state, "wrong effect from
MemoryChecker::operator=(const MemoryChecker& other): attemp to assign to
non-existing object");
-EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker::operator=(const MemoryChecker& other): attemp to assign from
non-existing object");
+EXPECT_TRUE(state() == alive_state, "wrong effect from
MemoryChecker::operator=(const MemoryChecker& other): attempt to assign to
non-existing object");
+EXPECT_TRUE(other.state() == alive_state, "wrong effect from
MemoryChecker::operator=(const MemoryChecker& other): attempt to assign from
non-existing object");
// just assign new value, counter is the same, state is the same
_value = other.value();
@@ -285,7 +285,7 @@ struct MemoryChecker {
}
~MemoryChecker() {
// check if we do not double destruct the object
-EXPECT_TRUE(state() == alive_state, "wrong effect from
~MemoryChecker(): attemp to destroy non-existing object");
+EXPECT_TRUE(state() == alive_state, "wrong effect from
~MemoryChecker(): attempt to destroy non-existing object");
// set destructed state and decrement counter for living object
static_cast(_state) = dead_state;
dec_alive_objects();
[gcc r14-9553] RISC-V: Update test expectancies with recent scheduler change
https://gcc.gnu.org/g:bc91e3870e9c984c180b478a3449a9a2e56cd107
commit r14-9553-gbc91e3870e9c984c180b478a3449a9a2e56cd107
Author: Edwin Lu
Date: Tue Mar 12 14:31:40 2024 -0700
RISC-V: Update test expectancies with recent scheduler change
Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Disable
scheduling
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: Update test expectancies
* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
* gcc.target/riscv/rvv/base/vcreate.c: Disable scheduling and update
test expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Disable
scheduling
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Update test
expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
Signed-off-by: Edwin Lu
Diff:
---
.../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c| 1 +
.../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c| 1 +
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 12 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c| 6 --
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c | 1 +
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c | 1 +
.../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c | 12 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c | 6 +++---
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 4 ++--
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 4 ++--
23 files changed, 75 insertions(+), 69 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index bd7ce23f6b8..b23acebc916 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param
riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling
-fdump-tree-vect-details" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 61619a0c879..ef719ee8445 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* {
[gcc r14-9552] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
https://gcc.gnu.org/g:60586710b0646efdbbd77a7f53b93fb5edb87a61 commit r14-9552-g60586710b0646efdbbd77a7f53b93fb5edb87a61 Author: Edwin Lu Date: Mon Mar 18 11:43:41 2024 -0700 RISC-V: Fix C23 (...) functions returning large aggregates [PR114175] We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and there is nothing to advance, but that is not the case for (...) functions returning by hidden reference which have one such artificial argument. This causes gcc.dg/c23-stdarg-[68].c to fail Fix the issue by checking if arg.type is NULL as r14-9503-g218d1749612 explains Tested on linux rv64gcv. gcc/ChangeLog: PR target/114175 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions if arg.type is NULL Diff: --- gcc/config/riscv/riscv.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 45015addd1f..02a927f96b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5395,7 +5395,8 @@ riscv_setup_incoming_varargs (cumulative_args_t cum, argument. Advance a local copy of CUM past the last "real" named argument, to find out how many registers are left over. */ local_cum = *get_cumulative_args (cum); - if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))) + if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)) + || arg.type != NULL_TREE) riscv_function_arg_advance (pack_cumulative_args (_cum), arg); /* Found out how many registers we need to save. */
[gcc r14-9547] libstdc++: Fix Python scripts to output the correct filename
https://gcc.gnu.org/g:ef2efc53fd89920a864fa076cabe03873b7f1bdc
commit r14-9547-gef2efc53fd89920a864fa076cabe03873b7f1bdc
Author: Jonathan Wakely
Date: Tue Mar 19 12:43:29 2024 +
libstdc++: Fix Python scripts to output the correct filename
These scripts both print "generated by $file, do not edit" header but
one of them prints the wrong filename. Use the built-in __file__
attribute to ensure it's correct.
contrib/ChangeLog:
* unicode/gen_libstdcxx_unicode_data.py: Fix header of generated
file to name the correct script.
libstdc++-v3/ChangeLog:
* include/bits/text_encoding-data.h: Regenerate.
* include/bits/unicode-data.h: Regenerate.
* scripts/gen_text_encoding_data.py: Fix header of generated
file to name the correct script.
Diff:
---
contrib/unicode/gen_libstdcxx_unicode_data.py | 6 --
libstdc++-v3/include/bits/text_encoding-data.h | 3 ++-
libstdc++-v3/include/bits/unicode-data.h | 2 +-
libstdc++-v3/scripts/gen_text_encoding_data.py | 5 -
4 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/contrib/unicode/gen_libstdcxx_unicode_data.py
b/contrib/unicode/gen_libstdcxx_unicode_data.py
index 2341a442f6a..da2f6ee66bf 100755
--- a/contrib/unicode/gen_libstdcxx_unicode_data.py
+++ b/contrib/unicode/gen_libstdcxx_unicode_data.py
@@ -29,9 +29,11 @@
import sys
import re
import math
+import os
-print("""// Generated by contrib/unicode/gen_std_format_width.py, do not edit.
-
+self = os.path.basename(__file__)
+print("// Generated by contrib/unicode/{}, do not edit.".format(self))
+print("""
// Copyright The GNU Toolchain Authors.
//
// This file is part of the GNU ISO C++ Library. This library is free
diff --git a/libstdc++-v3/include/bits/text_encoding-data.h
b/libstdc++-v3/include/bits/text_encoding-data.h
index 81bd94e6c3a..d6c34f895f5 100644
--- a/libstdc++-v3/include/bits/text_encoding-data.h
+++ b/libstdc++-v3/include/bits/text_encoding-data.h
@@ -1,4 +1,5 @@
-// Generated by gen_text_encoding_data.py, do not edit.
+// Generated by scripts/gen_text_encoding_data.py, do not edit.
+
// Copyright The GNU Toolchain Authors.
//
diff --git a/libstdc++-v3/include/bits/unicode-data.h
b/libstdc++-v3/include/bits/unicode-data.h
index 69b8f2926c3..e39a6c45f6c 100644
--- a/libstdc++-v3/include/bits/unicode-data.h
+++ b/libstdc++-v3/include/bits/unicode-data.h
@@ -1,4 +1,4 @@
-// Generated by contrib/unicode/gen_std_format_width.py, do not edit.
+// Generated by contrib/unicode/gen_libstdcxx_unicode_data.py, do not edit.
// Copyright The GNU Toolchain Authors.
//
diff --git a/libstdc++-v3/scripts/gen_text_encoding_data.py
b/libstdc++-v3/scripts/gen_text_encoding_data.py
index 13792b5f5e7..e11b26e69fc 100755
--- a/libstdc++-v3/scripts/gen_text_encoding_data.py
+++ b/libstdc++-v3/scripts/gen_text_encoding_data.py
@@ -26,12 +26,15 @@
import sys
import csv
+import os
if len(sys.argv) != 2:
print("Usage: %s " % sys.argv[0], file=sys.stderr)
sys.exit(1)
-print("""// Generated by gen_text_encoding_data.py, do not edit.
+self = os.path.basename(__file__)
+print("// Generated by scripts/{}, do not edit.".format(self))
+print("""
// Copyright The GNU Toolchain Authors.
//
[gcc r14-9548] libstdc++: Update docs on build process and generated files
https://gcc.gnu.org/g:d1b8c2237d7c6a2d52ea5a852a9a11ad426496f3 commit r14-9548-gd1b8c2237d7c6a2d52ea5a852a9a11ad426496f3 Author: Jonathan Wakely Date: Tue Mar 19 12:58:27 2024 + libstdc++: Update docs on build process and generated files There are several more sub-directories below 'src' now, with lots more conveience libraries. Document them all as of GCC 14. Also document how to regenerate the generated headers under include/bits and how to update the tzdata.zi file. libstdc++-v3/ChangeLog: * doc/xml/manual/build_hacking.xml: Document generated files. Update list of convenience libraries and sub-directories under the src directory. * doc/html/*: Regenerate. Diff: --- libstdc++-v3/doc/html/index.html | 2 +- libstdc++-v3/doc/html/manual/appendix.html | 2 +- libstdc++-v3/doc/html/manual/appendix_porting.html | 119 +-- libstdc++-v3/doc/html/manual/index.html| 2 +- libstdc++-v3/doc/xml/manual/build_hacking.xml | 164 +++-- 5 files changed, 262 insertions(+), 27 deletions(-) diff --git a/libstdc++-v3/doc/html/index.html b/libstdc++-v3/doc/html/index.html index f9288e471f4..395908f17a1 100644 --- a/libstdc++-v3/doc/html/index.html +++ b/libstdc++-v3/doc/html/index.html @@ -135,7 +135,7 @@ Contributor ChecklistReadingAssignmentGetting SourcesSubmitting PatchesDirectory Layout and Source ConventionsCoding StyleBad IdentifiersBy ExampleDesign NotesB. Porting and Maintenance -Configure and Build HackingPrerequisitesOverviewGeneral ProcessWhat Comes from WhereConfigureStoring Information in non-AC files (like configure.host)Coding and Commenting ConventionsThe acinclude.m4 layoutGLIBCXX_ENABLE, the --enable makerShared Library VersioningMakeWriting and Generating DocumentationIntroductionGenerating DocumentationDoxygenPrerequisitesGenerating the Doxygen FilesDebugging GenerationMarkupDocbookPrerequisitesGenerati ng the DocBook FilesDebugging GenerationEditing and ValidationFile Organization and BasicsMarkup By ExamplePorting to New Hardware or Operating SystemsOperating SystemCPUCharacter TypesThread SafetyNumeric LimitsLibtoolTestingTest OrganizationDirectory LayoutNaming ConventionsRunning the TestsuiteBasicVariationsPermutationsWriting a new test caseExamples of Test DirectivesDirectives Specific to Libstdc++ TestsTest Harness and UtilitiesDejaGnu Harness DetailsUtilitiesSpecial Topics +Configure and Build HackingPrerequisitesOverviewGeneral ProcessWhat Comes from WhereConfigureStoring Information in non-AC files (like configure.host)Coding and Commenting ConventionsThe acinclude.m4 layoutGLIBCXX_ENABLE, the --enable makerShared Library VersioningMakeGenerated filesWriting and Generating Documentation< a href="manual/documentation_hacking.html#doc.intro">IntroductionGenerating DocumentationDoxygenPrerequisitesGenerating the Doxygen FilesDebugging GenerationMarkupDocbookP rerequisitesGenerating the DocBook FilesDebugging GenerationEditing and ValidationFile Organization and BasicsMarkup By ExamplePorting to New Hardware or Operating SystemsOperating SystemCPU< span class="section">Character TypesThread SafetyNumeric LimitsLibtoolTestingTest OrganizationDirectory LayoutNaming ConventionsRunning the TestsuiteBasicVariationsPermutationsWriting a new test caseExamples of Test DirectivesDirectives Specific to Libstdc++ TestsTest Harness and UtilitiesDejaGnu Harness DetailsUtilitiesSpecial Topics Qualifying Exception Safety Guarantees Overview diff --git a/libstdc++-v3/doc/html/manual/appendix.html b/libstdc++-v3/doc/html/manual/appendix.html index 03746f90269..affd5839f43 100644 --- a/libstdc++-v3/doc/html/manual/appendix.html +++ b/libstdc++-v3/doc/html/manual/appendix.html @@ -9,7 +9,7 @@ Contributor ChecklistReadingAssignmentGetting SourcesSubmitting PatchesDirectory Layout and Source ConventionsCoding StyleBad IdentifiersBy ExampleDesign NotesB. Porting and Maintenance -Configure and Build HackingPrerequisitesOverviewGeneral ProcessWhat Comes from WhereConfigureStoring Information in non-AC files (like configure.host)Coding and Commenting ConventionsThe acinclude.m4 layoutGLIBCXX_ENABLE, the --enable makerShared Library VersioningMakeWriting and Generating DocumentationIntroductionGenerating DocumentationDoxygenPrerequisitesGenerating the Doxygen FilesDebugging GenerationMarkupDocbookPrerequisitesGenerating the DocBook FilesDebugging GenerationEditing and ValidationFile Organization and BasicsMarkup By ExamplePorting to New Hardware or Operating SystemsOperating SystemCPUCharacter TypesThread SafetyNumeric LimitsLibtoolTestingTest OrganizationDirectory LayoutNaming ConventionsRunning the TestsuiteBasicVariationsPermutationsWriting a new test caseExamples of Test DirectivesDirectives Specific to
[gcc r14-9549] libstdc++: Regenerate in maintainer mode
https://gcc.gnu.org/g:90788dd722346560d410fe9a5c2d543811027336
commit r14-9549-g90788dd722346560d410fe9a5c2d543811027336
Author: Jonathan Wakely
Date: Fri Mar 1 11:20:51 2024 +
libstdc++: Regenerate in maintainer mode
This is a generated header but regenerating it requires the manual step
of running 'make -C include update-version' in the libstdc++ build dir.
Make it regenerate automatically when --enable-maintainer-mode is used.
libstdc++-v3/ChangeLog:
* include/Makefile.am [MAINTAINER_MODE]: Add target to
automatically update .
* include/Makefile.in: Regenerate.
gcc/ChangeLog:
* doc/install.texi (Prerequisites): Document use of autogen for
libstdc++.
Diff:
---
gcc/doc/install.texi | 2 ++
libstdc++-v3/include/Makefile.am | 6 ++
libstdc++-v3/include/Makefile.in | 4
3 files changed, 12 insertions(+)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index e3650e0c4f4..014ca25aa62 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -545,6 +545,8 @@ Necessary to run @samp{make check} for @file{fixinc}.
Necessary to regenerate the top level @file{Makefile.in} file from
@file{Makefile.tpl} and @file{Makefile.def}.
+Necessary to regenerate the @file{bits/version.h} header for libstdc++.
+
@item Flex version 2.5.4 (or later)
Necessary when modifying @file{*.l} files.
diff --git a/libstdc++-v3/include/Makefile.am b/libstdc++-v3/include/Makefile.am
index 64152351ed0..cb902de36ae 100644
--- a/libstdc++-v3/include/Makefile.am
+++ b/libstdc++-v3/include/Makefile.am
@@ -1480,6 +1480,12 @@ update-version:
cd ${bits_srcdir} && \
autogen version.def
+if MAINTAINER_MODE
+# Regenerate it automatically in maintainer mode.
+${bits_srcdir}/version.h: ${bits_srcdir}/version.def ${bits_srcdir}/version.tpl
+ $(MAKE) update-version
+endif
+
# The real deal.
install-data-local: install-headers
install-headers:
diff --git a/libstdc++-v3/include/Makefile.in b/libstdc++-v3/include/Makefile.in
index 5a965c8e03b..9357087acb4 100644
--- a/libstdc++-v3/include/Makefile.in
+++ b/libstdc++-v3/include/Makefile.in
@@ -1954,6 +1954,10 @@ update-version:
cd ${bits_srcdir} && \
autogen version.def
+# Regenerate it automatically in maintainer mode.
+@MAINTAINER_MODE_TRUE@${bits_srcdir}/version.h: ${bits_srcdir}/version.def
${bits_srcdir}/version.tpl
+@MAINTAINER_MODE_TRUE@ $(MAKE) update-version
+
# The real deal.
install-data-local: install-headers
install-headers:
[gcc r14-9554] diagnostics: fix corrupt json/SARIF on stderr [PR114348]
https://gcc.gnu.org/g:0bf99b1b7eda2f4c34b9f56b895980ea1c261765
commit r14-9554-g0bf99b1b7eda2f4c34b9f56b895980ea1c261765
Author: David Malcolm
Date: Tue Mar 19 13:57:35 2024 -0400
diagnostics: fix corrupt json/SARIF on stderr [PR114348]
Various values of -fdiagnostics-format= request machine-readable output
on stderr, using JSON, but in various places we use fnotice to write
free-form text to stderr, such as "compilation terminated", leading to
corrupt JSON.
Fix by having fnotice skip the output for such cases.
gcc/ChangeLog:
PR middle-end/114348
* diagnostic-format-json.cc
(json_stderr_output_format::machine_readable_stderr_p): New.
(json_file_output_format::machine_readable_stderr_p): New.
* diagnostic-format-sarif.cc
(sarif_stream_output_format::machine_readable_stderr_p): New.
(sarif_file_output_format::machine_readable_stderr_p): New.
* diagnostic.cc (diagnostic_context::action_after_output): Move
"fnotice" to before "finish" call, so that we still have the
diagnostic_context.
(fnotice): Bail out if the user requested one of the
machine-readable diagnostic output formats on stderr.
* diagnostic.h
(diagnostic_output_format::machine_readable_stderr_p): New pure
virtual function.
(diagnostic_text_output_format::machine_readable_stderr_p): New.
(diagnostic_context::get_output_format): New accessor.
Signed-off-by: David Malcolm
Diff:
---
gcc/diagnostic-format-json.cc | 8
gcc/diagnostic-format-sarif.cc | 8
gcc/diagnostic.cc | 12 +++-
gcc/diagnostic.h | 10 ++
4 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/gcc/diagnostic-format-json.cc b/gcc/diagnostic-format-json.cc
index 51e016b6463..0782ae831eb 100644
--- a/gcc/diagnostic-format-json.cc
+++ b/gcc/diagnostic-format-json.cc
@@ -314,6 +314,10 @@ public:
{
flush_to_file (stderr);
}
+ bool machine_readable_stderr_p () const final override
+ {
+return true;
+ }
};
class json_file_output_format : public json_output_format
@@ -345,6 +349,10 @@ public:
fclose (outf);
free (filename);
}
+ bool machine_readable_stderr_p () const final override
+ {
+return false;
+ }
private:
char *m_base_file_name;
diff --git a/gcc/diagnostic-format-sarif.cc b/gcc/diagnostic-format-sarif.cc
index 307b2f56c28..97c5943cd33 100644
--- a/gcc/diagnostic-format-sarif.cc
+++ b/gcc/diagnostic-format-sarif.cc
@@ -1750,6 +1750,10 @@ public:
{
m_builder.flush_to_file (m_stream);
}
+ bool machine_readable_stderr_p () const final override
+ {
+return m_stream == stderr;
+ }
private:
FILE *m_stream;
};
@@ -1782,6 +1786,10 @@ public:
fclose (outf);
free (filename);
}
+ bool machine_readable_stderr_p () const final override
+ {
+return false;
+ }
private:
char *m_base_file_name;
diff --git a/gcc/diagnostic.cc b/gcc/diagnostic.cc
index 1d143fa7498..8e4621f8031 100644
--- a/gcc/diagnostic.cc
+++ b/gcc/diagnostic.cc
@@ -802,8 +802,8 @@ diagnostic_context::action_after_output (diagnostic_t
diag_kind)
case DK_FATAL:
if (m_abort_on_error)
real_abort ();
- finish ();
fnotice (stderr, "compilation terminated.\n");
+ finish ();
exit (FATAL_EXIT_CODE);
default:
@@ -2264,6 +2264,16 @@ diagnostic_context::emit_diagram (const
diagnostic_diagram )
void
fnotice (FILE *file, const char *cmsgid, ...)
{
+ /* If the user requested one of the machine-readable diagnostic output
+ formats on stderr (e.g. -fdiagnostics-format=sarif-stderr), then
+ emitting free-form text on stderr will lead to corrupt output.
+ Skip the message for such cases. */
+ if (file == stderr && global_dc)
+if (const diagnostic_output_format *output_format
+ = global_dc->get_output_format ())
+ if (output_format->machine_readable_stderr_p ())
+ return;
+
va_list ap;
va_start (ap, cmsgid);
diff --git a/gcc/diagnostic.h b/gcc/diagnostic.h
index 0a7c7e02b37..065ac784e25 100644
--- a/gcc/diagnostic.h
+++ b/gcc/diagnostic.h
@@ -210,6 +210,7 @@ public:
virtual void on_end_diagnostic (const diagnostic_info &,
diagnostic_t orig_diag_kind) = 0;
virtual void on_diagram (const diagnostic_diagram ) = 0;
+ virtual bool machine_readable_stderr_p () const = 0;
protected:
diagnostic_output_format (diagnostic_context )
@@ -238,6 +239,10 @@ public:
void on_end_diagnostic (const diagnostic_info &,
diagnostic_t orig_diag_kind) override;
void on_diagram (const diagnostic_diagram ) override;
+ bool machine_readable_stderr_p () const final override
+ {
+return false;
+ }
};
/* A stack of sets of classifications: each entry in the stack is
@@
[gcc r13-8467] Fortran: error recovery in frontend optimization [PR103715]
https://gcc.gnu.org/g:9623e5dd70b0d8334ebe093459721d0d447ce4f2
commit r13-8467-g9623e5dd70b0d8334ebe093459721d0d447ce4f2
Author: Harald Anlauf
Date: Mon Mar 18 19:36:59 2024 +0100
Fortran: error recovery in frontend optimization [PR103715]
gcc/fortran/ChangeLog:
PR fortran/103715
* frontend-passes.cc (check_externals_expr): Prevent invalid read
in case of mismatch of external subroutine with function.
gcc/testsuite/ChangeLog:
PR fortran/103715
* gfortran.dg/pr103715.f90: New test.
(cherry picked from commit 3be2b8f475f22c531d6cef1b041c0573b3ea5133)
Diff:
---
gcc/fortran/frontend-passes.cc | 3 +++
gcc/testsuite/gfortran.dg/pr103715.f90 | 12
2 files changed, 15 insertions(+)
diff --git a/gcc/fortran/frontend-passes.cc b/gcc/fortran/frontend-passes.cc
index 85ebca56a69..349d26ec29a 100644
--- a/gcc/fortran/frontend-passes.cc
+++ b/gcc/fortran/frontend-passes.cc
@@ -5807,6 +5807,9 @@ check_externals_expr (gfc_expr **ep, int *walk_subtrees
ATTRIBUTE_UNUSED,
if (e->expr_type != EXPR_FUNCTION)
return 0;
+ if (e->symtree && e->symtree->n.sym->attr.subroutine)
+return 0;
+
sym = e->value.function.esym;
if (sym == NULL)
return 0;
diff --git a/gcc/testsuite/gfortran.dg/pr103715.f90
b/gcc/testsuite/gfortran.dg/pr103715.f90
new file mode 100644
index 000..72c5a31fb21
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr103715.f90
@@ -0,0 +1,12 @@
+! { dg-do compile }
+! PR fortran/103715 - ICE in gfc_find_gsymbol
+!
+! valgrind did report an invalid read in check_externals_procedure
+
+program p
+ select type (y => g()) ! { dg-error "Selector shall be polymorphic" }
+ end select
+ call g()
+end
+
+! { dg-prune-output "already being used as a FUNCTION" }
[gcc r13-8468] Fortran: fix IS_CONTIGUOUS for polymorphic dummy arguments [PR114001]
https://gcc.gnu.org/g:5b928badac560ad48e0e9fc480096ff396d9d9c6
commit r13-8468-g5b928badac560ad48e0e9fc480096ff396d9d9c6
Author: Harald Anlauf
Date: Tue Mar 12 22:58:39 2024 +0100
Fortran: fix IS_CONTIGUOUS for polymorphic dummy arguments [PR114001]
gcc/fortran/ChangeLog:
PR fortran/114001
* expr.cc (gfc_is_simply_contiguous): Adjust logic so that CLASS
symbols are also handled.
gcc/testsuite/ChangeLog:
PR fortran/114001
* gfortran.dg/is_contiguous_4.f90: New test.
(cherry picked from commit 11caf47b599568c6c6f5a12cf8e21f50778176d3)
Diff:
---
gcc/fortran/expr.cc | 19 ---
gcc/testsuite/gfortran.dg/is_contiguous_4.f90 | 81 +++
2 files changed, 91 insertions(+), 9 deletions(-)
diff --git a/gcc/fortran/expr.cc b/gcc/fortran/expr.cc
index 9fdbe7a84c5..8b9c93940c8 100644
--- a/gcc/fortran/expr.cc
+++ b/gcc/fortran/expr.cc
@@ -5994,15 +5994,16 @@ gfc_is_simply_contiguous (gfc_expr *expr, bool strict,
bool permit_element)
}
sym = expr->symtree->n.sym;
- if (expr->ts.type != BT_CLASS
- && ((part_ref
- && !part_ref->u.c.component->attr.contiguous
- && part_ref->u.c.component->attr.pointer)
- || (!part_ref
- && !sym->attr.contiguous
- && (sym->attr.pointer
- || (sym->as && sym->as->type == AS_ASSUMED_RANK)
- || (sym->as && sym->as->type == AS_ASSUMED_SHAPE)
+ if ((part_ref
+ && part_ref->u.c.component
+ && !part_ref->u.c.component->attr.contiguous
+ && IS_POINTER (part_ref->u.c.component))
+ || (!part_ref
+ && expr->ts.type != BT_CLASS
+ && !sym->attr.contiguous
+ && (sym->attr.pointer
+ || (sym->as && sym->as->type == AS_ASSUMED_RANK)
+ || (sym->as && sym->as->type == AS_ASSUMED_SHAPE
return false;
if (!ar || ar->type == AR_FULL)
diff --git a/gcc/testsuite/gfortran.dg/is_contiguous_4.f90
b/gcc/testsuite/gfortran.dg/is_contiguous_4.f90
new file mode 100644
index 000..cb066f8836b
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/is_contiguous_4.f90
@@ -0,0 +1,81 @@
+! { dg-do run }
+! PR fortran/114001 - IS_CONTIGUOUS and polymorphic dummy
+
+program main
+ implicit none
+ integer :: i, cnt = 0
+ logical :: expect
+ integer, target :: m(10) = [(i,i=1,size(m))]
+ integer, pointer :: p(:)
+ type t
+ integer :: j
+ end type t
+ type(t), pointer :: tt(:), tp(:) ! Type pointer
+ class(t), pointer :: ct(:), cp(:) ! Class pointer
+
+ p => m(1:3)
+ expect = is_contiguous (p)
+ print *, "is_contiguous (p)=", expect
+ if (.not. expect) stop 91
+ call sub_star (p, expect)
+ p => m(1::3)
+ expect = is_contiguous (p)
+ print *, "is_contiguous (p)=", expect
+ if (expect) stop 92
+ call sub_star (p, expect)
+
+ allocate (tt(10))
+ tt(:)% j = m
+ tp => tt(4:6)
+ expect = is_contiguous (tp)
+ if (.not. expect) stop 96
+ print *, "is_contiguous (tp)=", expect
+ call sub_t (tp, expect)
+ tp => tt(4::3)
+ expect = is_contiguous (tp)
+ if (expect) stop 97
+ print *, "is_contiguous (tp)=", expect
+ call sub_t (tp, expect)
+
+ allocate (ct(10))
+ ct(:)% j = m
+ cp => ct(7:9)
+ expect = is_contiguous (cp)
+ print *, "is_contiguous (cp)=", expect
+ if (.not. expect) stop 98
+ call sub_t (cp, expect)
+ cp => ct(4::3)
+ expect = is_contiguous (cp)
+ print *, "is_contiguous (cp)=", expect
+ if (expect) stop 99
+ call sub_t (cp, expect)
+
+contains
+
+ subroutine sub_star (x, expect)
+class(*), intent(in) :: x(:)
+logical, intent(in) :: expect
+cnt = cnt + 10
+if (is_contiguous (x) .neqv. expect) then
+ print *, "sub_star(1): is_contiguous (x)=", is_contiguous (x), expect
+ stop (cnt + 1)
+end if
+select type (x)
+type is (integer)
+ if (is_contiguous (x) .neqv. expect) then
+ print *, "sub_star(2): is_contiguous (x)=", is_contiguous (x), expect
+ stop (cnt + 2)
+ end if
+end select
+ end
+
+ subroutine sub_t (x, expect)
+class(t), intent(in) :: x(:)
+logical, intent(in) :: expect
+cnt = cnt + 10
+if (is_contiguous (x) .neqv. expect) then
+ print *, "sub_t: is_contiguous (x)=", is_contiguous (x), expect
+ stop (cnt + 3)
+end if
+ end
+end
[gcc r14-9558] testsuite: fix target for linkage-1.C
https://gcc.gnu.org/g:7a6261332de58fd47283d694d8cd61ea7cdb324c
commit r14-9558-g7a6261332de58fd47283d694d8cd61ea7cdb324c
Author: Marek Polacek
Date: Tue Mar 19 17:15:38 2024 -0400
testsuite: fix target for linkage-1.C
This test fails in C++11 due to:
linkage-1.C:3:8: error: 'f' function uses 'auto' type specifier without
trailing return type
3 | inline auto f() {
|^~~~
linkage-1.C:3:8: note: deduced return type only available with '-std=c++14'
or '-std=gnu++14'
Compile it in C++14 thus.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/linkage-1.C: Use target c++14.
Diff:
---
gcc/testsuite/g++.dg/cpp2a/linkage-1.C | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/g++.dg/cpp2a/linkage-1.C
b/gcc/testsuite/g++.dg/cpp2a/linkage-1.C
index 888ed6fa5b5..2b83ffe55b7 100644
--- a/gcc/testsuite/g++.dg/cpp2a/linkage-1.C
+++ b/gcc/testsuite/g++.dg/cpp2a/linkage-1.C
@@ -1,4 +1,4 @@
-// { dg-do compile { target c++11 } }
+// { dg-do compile { target c++14 } }
inline auto f() {
struct A {};
[gcc(refs/users/meissner/heads/work163)] Revert all changes
https://gcc.gnu.org/g:acd5a60cccacc1b769f3afa835546368761cf431
commit acd5a60cccacc1b769f3afa835546368761cf431
Author: Michael Meissner
Date: Tue Mar 19 17:28:40 2024 -0400
Revert all changes
Diff:
---
gcc/config.gcc | 4 +-
gcc/config/rs6000/aix71.h | 1 -
gcc/config/rs6000/aix72.h | 1 -
gcc/config/rs6000/aix73.h | 1 -
gcc/config/rs6000/driver-rs6000.cc | 2 -
gcc/config/rs6000/power10.md| 145 ++--
gcc/config/rs6000/rs6000-c.cc | 2 -
gcc/config/rs6000/rs6000-cpus.def | 5 --
gcc/config/rs6000/rs6000-opts.h | 3 +-
gcc/config/rs6000/rs6000-string.cc | 1 -
gcc/config/rs6000/rs6000-tables.opt | 3 -
gcc/config/rs6000/rs6000.cc | 30 ++--
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 -
gcc/doc/invoke.texi | 2 +-
16 files changed, 85 insertions(+), 121 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6f31c789102..f8036b6476e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5568,7 +5568,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x |
future \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 570ddcc451d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 242ca94bd06..fe59f8319b4 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 2bd6b4bb3c4..1318b0b3662 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 07852fa50cf..f4900724b98 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -441,7 +441,6 @@ struct asm_name {
static const struct asm_name asm_names[] = {
#if defined (_AIX)
- { "future", "-mfuture" },
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
@@ -471,7 +470,6 @@ static const struct asm_name asm_names[] = {
#else
{ "cell","-mcell" },
- { "future", "-mfuture },
{ "power3", "-mppc64" },
{ "power4", "-mpower4" },
{ "power5", "-mpower5" },
diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 1ec1bef0726..90312643858 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,5 +1,4 @@
-;; Scheduling description for the IBM POWER10 and POWER11 processors as well as
-;; potential future processors.
+;; Scheduling description for the IBM POWER10 and POWER11 processors.
;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -98,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
(define_insn_reservation "power10-fused-load" 4
(and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
- (eq_attr "cpu"
[gcc(refs/users/meissner/heads/work163)] Add -mcpu=future support.
https://gcc.gnu.org/g:e6477b55b225b6e0d6e996a56385e6130ff6875f
commit e6477b55b225b6e0d6e996a56385e6130ff6875f
Author: Michael Meissner
Date: Tue Mar 19 17:38:23 2024 -0400
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfuture to the assembler if the user uses -mcpu=future.
2024-03-18 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
15 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index f8036b6476e..6f31c789102 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5568,7 +5568,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work163)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:04201e61597afb4d35694447fce09b6d45a511da commit 04201e61597afb4d35694447fce09b6d45a511da Author: Michael Meissner Date: Tue Mar 19 17:40:19 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-03-18 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 90312643858..1ec1bef0726 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM POWER10 and POWER11 processors. +;; Scheduling description for the IBM POWER10 and POWER11 processors as well as +;; potential future processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update
[gcc r14-9555] analyzer: fix ICE due to corrupt MEM_REFs [PR113505]
https://gcc.gnu.org/g:c87f1f3d660f4103c91c72a4d3e1d19ff2858671
commit r14-9555-gc87f1f3d660f4103c91c72a4d3e1d19ff2858671
Author: Jakub Jelinek
Date: Tue Mar 19 16:06:13 2024 -0400
analyzer: fix ICE due to corrupt MEM_REFs [PR113505]
gcc/analyzer/ChangeLog
PR analyzer/113505
* region-model.cc (get_tree_for_byte_offset,
region_model::get_representative_path_var_1,
test_mem_ref, test_POINTER_PLUS_EXPR_then_MEM_REF): Use
char __attribute__((may_alias)) * as type of MEM_REF second
argument.
gcc/testsuite/ChangeLog
PR analyzer/113505
* gcc.dg/analyzer/pr113505.c: New test.
Signed-off-by: David Malcolm
Diff:
---
gcc/analyzer/region-model.cc | 16 ++--
gcc/testsuite/gcc.dg/analyzer/pr113505.c | 24
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc
index f079d1fb37e..8fff5324173 100644
--- a/gcc/analyzer/region-model.cc
+++ b/gcc/analyzer/region-model.cc
@@ -3967,9 +3967,10 @@ static tree
get_tree_for_byte_offset (tree ptr_expr, byte_offset_t byte_offset)
{
gcc_assert (ptr_expr);
+ tree ptype = build_pointer_type_for_mode (char_type_node, ptr_mode, true);
return fold_build2 (MEM_REF,
char_type_node,
- ptr_expr, wide_int_to_tree (size_type_node, byte_offset));
+ ptr_expr, wide_int_to_tree (ptype, byte_offset));
}
/* Simulate a series of reads of REG until we find a 0 byte
@@ -5360,9 +5361,10 @@ region_model::get_representative_path_var_1 (const
region *reg,
tree addr_parent = build1 (ADDR_EXPR,
build_pointer_type (reg->get_type ()),
parent_pv.m_tree);
- return path_var (build2 (MEM_REF,
-reg->get_type (),
-addr_parent, offset_pv.m_tree),
+ tree ptype = build_pointer_type_for_mode (char_type_node, ptr_mode,
+ true);
+ return path_var (build2 (MEM_REF, reg->get_type (), addr_parent,
+fold_convert (ptype, offset_pv.m_tree)),
parent_pv.m_stack_depth);
}
@@ -9024,7 +9026,8 @@ test_mem_ref ()
tree int_17 = build_int_cst (integer_type_node, 17);
tree addr_of_x = build1 (ADDR_EXPR, int_star, x);
- tree offset_0 = build_int_cst (integer_type_node, 0);
+ tree ptype = build_pointer_type_for_mode (char_type_node, ptr_mode, true);
+ tree offset_0 = build_int_cst (ptype, 0);
tree star_p = build2 (MEM_REF, integer_type_node, p, offset_0);
region_model_manager mgr;
@@ -9074,7 +9077,8 @@ test_POINTER_PLUS_EXPR_then_MEM_REF ()
tree a = build_global_decl ("a", int_star);
tree offset_12 = build_int_cst (size_type_node, 12);
tree pointer_plus_expr = build2 (POINTER_PLUS_EXPR, int_star, a, offset_12);
- tree offset_0 = build_int_cst (integer_type_node, 0);
+ tree ptype = build_pointer_type_for_mode (char_type_node, ptr_mode, true);
+ tree offset_0 = build_int_cst (ptype, 0);
tree mem_ref = build2 (MEM_REF, integer_type_node,
pointer_plus_expr, offset_0);
region_model_manager mgr;
diff --git a/gcc/testsuite/gcc.dg/analyzer/pr113505.c
b/gcc/testsuite/gcc.dg/analyzer/pr113505.c
new file mode 100644
index 000..58a2b6cd6f4
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/pr113505.c
@@ -0,0 +1,24 @@
+/* PR analyzer/113505 */
+/* { dg-additional-options "-O -fdump-analyzer" } */
+
+enum E **foo () __attribute__((__const__));
+char a[2];
+void bar (char *);
+
+void
+baz (void)
+{
+ char *s, *l;
+ for (;;)
+{
+ bar (a);
+ s = a;
+ while (foo ()[*s])
+ s++;
+ l = s;
+ *l++ = '\0';
+ while (foo ()[*l])
+ l++;
+ bar (s);
+}
+}
[gcc r14-9559] ipa: Fix C++ member ptr indirect inlining (PR 114254, PR 108802)
https://gcc.gnu.org/g:bf838884fac573b4902a21bb82d9b6f777e32cb9
commit r14-9559-gbf838884fac573b4902a21bb82d9b6f777e32cb9
Author: Martin Jambor
Date: Tue Mar 19 22:33:27 2024 +0100
ipa: Fix C++ member ptr indirect inlining (PR 114254, PR 108802)
Even though we have had code to handle creation of indirect call graph
edges (so that these calls can than be made direct as part of IPA-CP
and inlining and eventually also inlined) for C++ member pointers for
many years, it turns out that it does not work for lambdas and that it
has been severely broken since GCC 10 when the base class has virtual
functions.
Lambdas don't work because the code cannot work with structures
representing member function pointers because they are passed by
reference instead by value and the code was not ready for that.
The presence of virtual methods broke thinks because at some point C++
FE got clever and stopped emitting the check for virtual methods when
the base class does not have any and that in turn made our existing
testcases not test the necessary pattern matching code. The pattern
matcher had a small bug which did not matter before
r10-917-g3b47da42de621c but did afterwards.
This patch changes the pattern matcher to match both of these cases.
gcc/ChangeLog:
2024-03-06 Martin Jambor
PR ipa/108802
PR ipa/114254
* ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
at COMPONENT_REFs directly from a PARM_DECL, also recognize loads
from
a pointer parameter.
(ipa_analyze_indirect_call_uses): Also recognize loads from a
pointer
parameter, also recognize the case when pfn pointer is loaded in its
own BB.
gcc/testsuite/ChangeLog:
2024-03-06 Martin Jambor
PR ipa/108802
PR ipa/114254
* g++.dg/ipa/iinline-4.C: New test.
* g++.dg/ipa/pr108802.C: Likewise.
Diff:
---
gcc/ipa-prop.cc | 110 +--
gcc/testsuite/g++.dg/ipa/iinline-4.C | 61 +++
gcc/testsuite/g++.dg/ipa/pr108802.C | 14 +
3 files changed, 154 insertions(+), 31 deletions(-)
diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc
index e22c4f78405..e8e4918d5a8 100644
--- a/gcc/ipa-prop.cc
+++ b/gcc/ipa-prop.cc
@@ -2500,7 +2500,9 @@ static tree
ipa_get_stmt_member_ptr_load_param (gimple *stmt, bool use_delta,
HOST_WIDE_INT *offset_p)
{
- tree rhs, rec, ref_field, ref_offset, fld, ptr_field, delta_field;
+ tree rhs, fld, ptr_field, delta_field;
+ tree ref_field = NULL_TREE;
+ tree ref_offset = NULL_TREE;
if (!gimple_assign_single_p (stmt))
return NULL_TREE;
@@ -2511,35 +2513,53 @@ ipa_get_stmt_member_ptr_load_param (gimple *stmt, bool
use_delta,
ref_field = TREE_OPERAND (rhs, 1);
rhs = TREE_OPERAND (rhs, 0);
}
- else
-ref_field = NULL_TREE;
- if (TREE_CODE (rhs) != MEM_REF)
-return NULL_TREE;
- rec = TREE_OPERAND (rhs, 0);
- if (TREE_CODE (rec) != ADDR_EXPR)
-return NULL_TREE;
- rec = TREE_OPERAND (rec, 0);
- if (TREE_CODE (rec) != PARM_DECL
- || !type_like_member_ptr_p (TREE_TYPE (rec), _field, _field))
+
+ if (TREE_CODE (rhs) == MEM_REF)
+{
+ ref_offset = TREE_OPERAND (rhs, 1);
+ if (ref_field && integer_nonzerop (ref_offset))
+ return NULL_TREE;
+}
+ else if (!ref_field)
return NULL_TREE;
- ref_offset = TREE_OPERAND (rhs, 1);
+
+ if (TREE_CODE (rhs) == MEM_REF
+ && TREE_CODE (TREE_OPERAND (rhs, 0)) == SSA_NAME
+ && SSA_NAME_IS_DEFAULT_DEF (TREE_OPERAND (rhs, 0)))
+{
+ rhs = TREE_OPERAND (rhs, 0);
+ if (TREE_CODE (SSA_NAME_VAR (rhs)) != PARM_DECL
+ || !type_like_member_ptr_p (TREE_TYPE (TREE_TYPE (rhs)), _field,
+ _field))
+ return NULL_TREE;
+}
+ else
+{
+ if (TREE_CODE (rhs) == MEM_REF
+ && TREE_CODE (TREE_OPERAND (rhs, 0)) == ADDR_EXPR)
+ rhs = TREE_OPERAND (TREE_OPERAND (rhs, 0), 0);
+ if (TREE_CODE (rhs) != PARM_DECL
+ || !type_like_member_ptr_p (TREE_TYPE (rhs), _field,
+ _field))
+ return NULL_TREE;
+}
if (use_delta)
fld = delta_field;
else
fld = ptr_field;
- if (offset_p)
-*offset_p = int_bit_position (fld);
if (ref_field)
{
- if (integer_nonzerop (ref_offset))
+ if (ref_field != fld)
return NULL_TREE;
- return ref_field == fld ? rec : NULL_TREE;
}
- else
-return tree_int_cst_equal (byte_position (fld), ref_offset) ? rec
- : NULL_TREE;
+ else if (!tree_int_cst_equal (byte_position (fld), ref_offset))
+return NULL_TREE;
+
+ if (offset_p)
+*offset_p = int_bit_position (fld);
+ return rhs;
}
/* Returns true iff T is an SSA_NAME defined by
[gcc r14-9561] diagnostics: Fix behavior of permerror options after diagnostic pop [PR111918]
https://gcc.gnu.org/g:44ba7bcb752a40ec7490dea53d3a472ce633371d
commit r14-9561-g44ba7bcb752a40ec7490dea53d3a472ce633371d
Author: Lewis Hyatt
Date: Wed Nov 8 16:13:14 2023 -0500
diagnostics: Fix behavior of permerror options after diagnostic pop
[PR111918]
When a diagnostic pragma changes the classification of a given diagnostic,
the global options flags (such as warn_narrowing, etc.) may get changed too.
Specifically, if a warning was not enabled initially and was later enabled
by a pragma, then the corresponding global flag will change from false to
true when the pragma is processed. That change is permanent and is not
undone by a subsequent `#pragma GCC diagnostic pop'; the warning flag needs
to remain enabled since a diagnostic could be generated later on for a
source location prior to the pop.
So in order to support popping to the initial classification, given that the
global options flags no longer reflect that state, the diagnostic_context
object itself remembers the way things were before it changed anything. The
current implementation works fine for diagnostics that are always errors or
always warnings, but it doesn't do the right thing for diagnostics that
could be either, such as -Wnarrowing. The classification of that diagnostic
(or any permerror diagnostic) depends on the state of -fpermissive; for the
particular case of -Wnarrowing it also matters whether a compile-time or
run-time narrowing is being diagnosed.
The problem is that the current implementation insists on recording whether
an enabled diagnostic should be a DK_WARNING or a DK_ERROR, and then, after
popping to the initial state, it overrides it always to that type only. Fix
that up by adding a new internal diagnostic type DK_ANY. This just indicates
that the diagnostic is enabled without mandating exactly what type of
diagnostic it should be. Then the diagnostic can be emitted with whatever
type the frontend asks for.
Incidentally, while making this change, I noticed that classify_diagnostic()
spends some time computing a return value (the old classification kind) that
is not used anywhere. The computed value seems to have some problems, mainly
that it does not take into account `#pragma GCC diagnostic pop' at all, and
so the returned value doesn't seem like it could make sense in many
contexts. Given it would also not be desirable to leak the new internal-only
DK_ANY type to outside callers, I think it would make sense in a subsequent
cleanup patch to remove the return value altogether.
gcc/ChangeLog:
PR c++/111918
* diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
* diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
Make use of DK_ANY to indicate a diagnostic was initially enabled.
(diagnostic_context::diagnostic_enabled): Do not change the type of
a diagnostic if the saved classification is type DK_ANY.
gcc/testsuite/ChangeLog:
PR c++/111918
* g++.dg/cpp0x/Wnarrowing21a.C: New test.
* g++.dg/cpp0x/Wnarrowing21b.C: New test.
* g++.dg/cpp0x/Wnarrowing21c.C: New test.
* g++.dg/cpp0x/Wnarrowing21d.C: New test.
Diff:
---
gcc/diagnostic-core.h | 5 -
gcc/diagnostic.cc | 13 ++---
gcc/testsuite/g++.dg/cpp0x/Wnarrowing21a.C | 14 ++
gcc/testsuite/g++.dg/cpp0x/Wnarrowing21b.C | 9 +
gcc/testsuite/g++.dg/cpp0x/Wnarrowing21c.C | 9 +
gcc/testsuite/g++.dg/cpp0x/Wnarrowing21d.C | 9 +
6 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/gcc/diagnostic-core.h b/gcc/diagnostic-core.h
index f5e1e500dc3..8071cc1f69b 100644
--- a/gcc/diagnostic-core.h
+++ b/gcc/diagnostic-core.h
@@ -33,7 +33,10 @@ typedef enum
DK_LAST_DIAGNOSTIC_KIND,
/* This is used for tagging pragma pops in the diagnostic
classification history chain. */
- DK_POP
+ DK_POP,
+ /* This is used internally to note that a diagnostic is enabled
+ without mandating any specific type. */
+ DK_ANY,
} diagnostic_t;
/* RAII-style class for grouping related diagnostics. */
diff --git a/gcc/diagnostic.cc b/gcc/diagnostic.cc
index 8e4621f8031..6ffd6236146 100644
--- a/gcc/diagnostic.cc
+++ b/gcc/diagnostic.cc
@@ -1136,8 +1136,7 @@ classify_diagnostic (const diagnostic_context *context,
if (old_kind == DK_UNSPECIFIED)
{
old_kind = !context->option_enabled_p (option_index)
- ? DK_IGNORED : (context->warning_as_error_requested_p ()
- ? DK_ERROR : DK_WARNING);
+ ? DK_IGNORED : DK_ANY;
m_classify_diagnostic[option_index] = old_kind;
}
@@ -1472,7 +1471,15 @@ diagnostic_context::diagnostic_enabled (diagnostic_info
*diagnostic)
[gcc(refs/users/meissner/heads/work163-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:87a4b55f5f3d3cf1fc77626ef56e9396d53f15c2 commit 87a4b55f5f3d3cf1fc77626ef56e9396d53f15c2 Author: Michael Meissner Date: Mon Mar 18 15:55:27 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-03-18 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..c6226335975 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work163-vpair, baseline + +2024-03-18 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index f37c7e5ef94..e5f8c9811d3 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work163 branch +work163-vpair branch
[gcc(refs/users/meissner/heads/work163-vpair)] Merge commit 'refs/users/meissner/heads/work163-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:614f37d2b0a5da702c04190a386874f8e0220583 commit 614f37d2b0a5da702c04190a386874f8e0220583 Merge: 87a4b55f5f3 5b4f20d93e6 Author: Michael Meissner Date: Wed Mar 20 00:17:23 2024 -0400 Merge commit 'refs/users/meissner/heads/work163-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work163-vpair Diff:
[gcc/meissner/heads/work163-vpair] (5 commits) Merge commit 'refs/users/meissner/heads/work163-vpair' of g
The branch 'meissner/heads/work163-vpair' was updated to point to: 614f37d2b0a... Merge commit 'refs/users/meissner/heads/work163-vpair' of g It previously pointed to: 5b4f20d93e6... Merge commit 'refs/users/meissner/heads/work163-vpair' of g Diff: Summary of changes (added commits): --- 614f37d... Merge commit 'refs/users/meissner/heads/work163-vpair' of g 87a4b55... Add ChangeLog.vpair and update REVISION. 04201e6... Add -mcpu=future tuning support. (*) e6477b5... Add -mcpu=future support. (*) acd5a60... Revert all changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work163-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work163-test)] Merge commit 'refs/users/meissner/heads/work163-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:c18733b88678d32b25064d233870e8e6e3e0a9e4 commit c18733b88678d32b25064d233870e8e6e3e0a9e4 Merge: 12f6a9e9fae fd35cfe58c0 Author: Michael Meissner Date: Wed Mar 20 00:14:02 2024 -0400 Merge commit 'refs/users/meissner/heads/work163-test' of git+ssh://gcc.gnu.org/git/gcc into me/work163-test Diff:
[gcc/meissner/heads/work163-dmf] (12 commits) Merge commit 'refs/users/meissner/heads/work163-dmf' of git
The branch 'meissner/heads/work163-dmf' was updated to point to: dc65989f104... Merge commit 'refs/users/meissner/heads/work163-dmf' of git It previously pointed to: 672c4b0e0de... Update ChangeLog.* Diff: Summary of changes (added commits): --- dc65989... Merge commit 'refs/users/meissner/heads/work163-dmf' of git a5fd8dd... Update ChangeLog.* da66991... PowerPC: Add support for 1,024 bit DMR registers. aa0c252... Add dense math test for new instruction names. f4c6cc2... PowerPC: Switch to dense math names for all MMA operations. 64bb9c0... Add support for dense math registers. 98e71fc... Add wD constraint. 88cc50b... Use vector pair load/store for memcpy with -mcpu=future 0024baa... Add ChangeLog.dmf and update REVISION. 04201e6... Add -mcpu=future tuning support. (*) e6477b5... Add -mcpu=future support. (*) acd5a60... Revert all changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work163-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work163-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:0024baaccb3953f143e8cc7fb6adc913bd5f9166 commit 0024baaccb3953f143e8cc7fb6adc913bd5f9166 Author: Michael Meissner Date: Mon Mar 18 15:54:31 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-03-18 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..1599736218a --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work163-dmf, baseline + +2024-03-18 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index f37c7e5ef94..1116969d5bd 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work163 branch +work163-dmf branch
[gcc(refs/users/meissner/heads/work163-ajit)] Add ChangeLog.ajit and update REVISION.
https://gcc.gnu.org/g:42b44e48d28d2b64fbdc3a7fdf589c7ddedb8d0c commit 42b44e48d28d2b64fbdc3a7fdf589c7ddedb8d0c Author: Michael Meissner Date: Mon Mar 18 15:56:21 2024 -0400 Add ChangeLog.ajit and update REVISION. 2024-03-18 Michael Meissner gcc/ * ChangeLog.ajit: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.ajit | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.ajit b/gcc/ChangeLog.ajit new file mode 100644 index 000..01cf332c638 --- /dev/null +++ b/gcc/ChangeLog.ajit @@ -0,0 +1,6 @@ + Branch work163-ajit, baseline + +2024-03-18 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index f37c7e5ef94..cb3f7c4e90b 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work163 branch +work163-ajit branch
[gcc/meissner/heads/work163-ajit] (5 commits) Merge commit 'refs/users/meissner/heads/work163-ajit' of gi
The branch 'meissner/heads/work163-ajit' was updated to point to: c53cc37c0d6... Merge commit 'refs/users/meissner/heads/work163-ajit' of gi It previously pointed to: c2c87b83e7e... Merge commit 'refs/users/meissner/heads/work163-ajit' of gi Diff: Summary of changes (added commits): --- c53cc37... Merge commit 'refs/users/meissner/heads/work163-ajit' of gi 42b44e4... Add ChangeLog.ajit and update REVISION. 04201e6... Add -mcpu=future tuning support. (*) e6477b5... Add -mcpu=future support. (*) acd5a60... Revert all changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work163-ajit' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work163-ajit)] Merge commit 'refs/users/meissner/heads/work163-ajit' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:c53cc37c0d6cb8ecc70ded7307b2221569e831ae commit c53cc37c0d6cb8ecc70ded7307b2221569e831ae Merge: 42b44e48d28 c2c87b83e7e Author: Michael Meissner Date: Wed Mar 20 00:04:34 2024 -0400 Merge commit 'refs/users/meissner/heads/work163-ajit' of git+ssh://gcc.gnu.org/git/gcc into me/work163-ajit Diff:
[gcc r13-8471] libstdc++: Fix N3344 behavior on _Safe_iterator::_M_can_advance
https://gcc.gnu.org/g:51e2f7a22e82a7cb2d321b82613b477b58ee4c60
commit r13-8471-g51e2f7a22e82a7cb2d321b82613b477b58ee4c60
Author: François Dumont
Date: Sun Mar 17 19:06:55 2024 +0100
libstdc++: Fix N3344 behavior on _Safe_iterator::_M_can_advance
We shall be able to advance from a 0 offset a value-initialized iterator.
libstdc++-v3/ChangeLog:
* include/debug/safe_iterator.tcc
(_Safe_iterator<>::_M_can_advance):
Accept 0 offset advance on value-initialized iterator.
* testsuite/23_containers/vector/debug/n3644.cc: New test case.
(cherry picked from commit dda96a9d942d73a587e174dd5efe061208a195af)
Diff:
---
libstdc++-v3/include/debug/safe_iterator.tcc | 3 +++
.../testsuite/23_containers/vector/debug/n3644.cc| 16
2 files changed, 19 insertions(+)
diff --git a/libstdc++-v3/include/debug/safe_iterator.tcc
b/libstdc++-v3/include/debug/safe_iterator.tcc
index 2640fc8a473..4e213c4a0f6 100644
--- a/libstdc++-v3/include/debug/safe_iterator.tcc
+++ b/libstdc++-v3/include/debug/safe_iterator.tcc
@@ -86,6 +86,9 @@ namespace __gnu_debug
_Safe_iterator<_Iterator, _Sequence, _Category>::
_M_can_advance(difference_type __n, bool __strict) const
{
+ if (this->_M_value_initialized() && __n == 0)
+ return true;
+
if (this->_M_singular())
return false;
diff --git a/libstdc++-v3/testsuite/23_containers/vector/debug/n3644.cc
b/libstdc++-v3/testsuite/23_containers/vector/debug/n3644.cc
new file mode 100644
index 000..052c52f26b7
--- /dev/null
+++ b/libstdc++-v3/testsuite/23_containers/vector/debug/n3644.cc
@@ -0,0 +1,16 @@
+// { dg-do run { target c++11 } }
+// { dg-require-debug-mode "" }
+
+#include
+#include
+
+#include
+
+int main()
+{
+ std::vector::iterator it{};
+ auto cpy = it;
+ std::advance(it, 0);
+ VERIFY( it == cpy );
+ return 0;
+}
[gcc r13-8470] libstdc++: Fix _Safe_local_iterator<>::_M_valid_range
https://gcc.gnu.org/g:86183487993315214091d593334893a883954f17
commit r13-8470-g86183487993315214091d593334893a883954f17
Author: François Dumont
Date: Sun Mar 17 17:30:58 2024 +0100
libstdc++: Fix _Safe_local_iterator<>::_M_valid_range
Unordered container local_iterator range shall not contain any singular
iterator unless both iterators are both value-initialized.
libstdc++-v3/ChangeLog:
* include/debug/safe_local_iterator.tcc
(_Safe_local_iterator::_M_valid_range): Add _M_value_initialized and
_M_singular checks.
* testsuite/23_containers/unordered_set/debug/114316.cc: New test
case.
(cherry picked from commit 5f6e0853c30fec72d977afaa6f7a5633a8d910be)
Diff:
---
libstdc++-v3/include/debug/safe_local_iterator.tcc | 8 ++-
.../23_containers/unordered_set/debug/114316.cc| 28 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/libstdc++-v3/include/debug/safe_local_iterator.tcc
b/libstdc++-v3/include/debug/safe_local_iterator.tcc
index 6fba344f16a..2444f41bb85 100644
--- a/libstdc++-v3/include/debug/safe_local_iterator.tcc
+++ b/libstdc++-v3/include/debug/safe_local_iterator.tcc
@@ -78,7 +78,13 @@ namespace __gnu_debug
_M_valid_range(const _Safe_local_iterator& __rhs,
std::pair& __dist) const
{
- if (!_M_can_compare(__rhs))
+ if (_M_value_initialized() && __rhs._M_value_initialized())
+ {
+ __dist = { 0, __dp_exact };
+ return true;
+ }
+
+ if (_M_singular() || __rhs._M_singular() || !_M_can_compare(__rhs))
return false;
if (bucket() != __rhs.bucket())
diff --git a/libstdc++-v3/testsuite/23_containers/unordered_set/debug/114316.cc
b/libstdc++-v3/testsuite/23_containers/unordered_set/debug/114316.cc
new file mode 100644
index 000..41b649a9cbd
--- /dev/null
+++ b/libstdc++-v3/testsuite/23_containers/unordered_set/debug/114316.cc
@@ -0,0 +1,28 @@
+// { dg-do run { target c++11 } }
+// { dg-require-debug-mode "" }
+
+// PR libstdc++/114316
+
+#include
+#include
+
+#include
+
+void test01()
+{
+ std::unordered_set::iterator it{};
+ VERIFY( std::find(it, it, 0) == it );
+}
+
+void test02()
+{
+ std::unordered_set::local_iterator it{};
+ VERIFY( std::find(it, it, 0) == it );
+}
+
+int main()
+{
+ test01();
+ test02();
+ return 0;
+}
[gcc(refs/users/meissner/heads/work163-dmf)] Add support for dense math registers.
https://gcc.gnu.org/g:64bb9c0b57b3fa6ba03793dedf2fb83ef8cba837 commit 64bb9c0b57b3fa6ba03793dedf2fb83ef8cba837 Author: Michael Meissner Date: Tue Mar 19 00:58:25 2024 -0400 Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as an optional feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped with the VSX registers 0..31, but logically the accumulator registers were separate from the FPR registers. In ISA 3.1, it was anticipated that in future systems, the accumulator registers may no overlap with the FPR registers. This patch adds the support for dense math registers as separate registers. This particular patch does not change the MMA support to use the accumulators within the dense math registers. This patch just adds the basic support for having separate DMRs. The next patch will switch the MMA support to use the accumulators if -mcpu=future is used. For testing purposes, I added an undocumented option '-mdense-math' to enable or disable the dense math support. This patch adds a new constraint (wD). If MMA is selected but dense math is not selected (i.e. -mcpu=power10), the wD constraint will allow access to accumulators that overlap with VSX registers 0..31. If both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint will only allow dense math registers. This patch modifies the existing %A output modifier. If MMA is selected but dense math is not selected, then %A output modifier converts the VSX register number to the accumulator number, by dividing it by 4. If both MMA and dense math are selected, then %A will map the separate DMR registers into 0..7. The intention is that user code using extended asm can be modified to run on both MMA without dense math and MMA with dense math: 1) If possible, don't use extended asm, but instead use the MMA built-in functions; 2) If you do need to write extended asm, change the d constraints targetting accumulators should now use wD; 3) Only use the built-in zero, assemble and disassemble functions create move data between vector quad types and dense math accumulators. I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the extended asm code. The reason is these instructions assume there is a 1-to-1 correspondence between 4 adjacent FPR registers and an accumulator that overlaps with those instructions. With accumulators now being separate registers, there no longer is a 1-to-1 correspondence. It is possible that the mangling for DMRs and the GDB register numbers may produce other changes in the future. 2024-03-19 Michael Meissner * config/rs6000/mma.md (movxo): Add comments about dense math registers. (movxo_nodm): Rename from movxo and restrict the usage to machines without dense math registers. (movxo_dm): New insn for movxo support for machines with dense math registers. (mma_): Restrict usage to machines without dense math registers. (mma_xxsetaccz): Make a define_expand, and add support for dense math registers. (mma_xxsetaccz_nodm): Rename from mma_xxsetaccz, and restrict to machines without dense math registers. (mma_dmsetaccz): New insn. * config/rs6000/predicates.md (dmr_operand): New predicate. (accumulator_operand): Add support for dense math registers. * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do not de-prime accumulator when disassembling a vector quad. * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE. (enum rs6000_reload_reg_type): Add RELOAD_REG_DMR. (LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD constraint. (reload_reg_map): Likewise. (rs6000_reg_names): Likewise. (alt_reg_names): Likewise. (rs6000_hard_regno_nregs_internal): Likewise. (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_secondary_reload_memory): Add support for DMR registers. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. (print_operand): Make %A handle both FPRs and DMRs. (rs6000_dmr_register_move_cost): New helper function. (rs6000_register_move_cost): Add support for DMR
[gcc(refs/users/meissner/heads/work163-dmf)] PowerPC: Add support for 1, 024 bit DMR registers.
https://gcc.gnu.org/g:da66991ee0b5fa2cef008a77861e761f9ae57014
commit da66991ee0b5fa2cef008a77861e761f9ae57014
Author: Michael Meissner
Date: Tue Mar 19 01:08:10 2024 -0400
PowerPC: Add support for 1,024 bit DMR registers.
This patch is a prelimianry patch to add the full 1,024 bit dense math
register
(DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of
the
DMR register.
This patch only adds the new 1,024 bit register support. It does not add
support for any instructions that need 1,024 bit registers instead of 512
bit
registers.
I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers. The 'wD' constraint added in previous patches is used for these
registers. I added support to do load and store of DMRs via the VSX
registers,
since there are no load/store dense math instructions. I added the new
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs. At
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed
internally.
The patches have been tested on both little and big endian systems. Can I
check
it into the master branch?
2024-03-19 Michael Meissner
gcc/
* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
support.
(rs6000_init_builtins): Add support for __dmr keyword.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add
support
for TDOmode.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (TDOmode): New mode.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
support for TDOmode.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup
reload
hooks for DMR mode.
(reg_offset_addressing_ok_p): Add support for TDOmode.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_mangle_type): Add mangling for __dmr type.
(rs6000_dmr_register_move_cost): Add support for TDOmode.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
(enum rs6000_builtin_type_index): Add DMR type nodes.
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.
gcc/testsuite/
* gcc.target/powerpc/dm-1024bit.c: New test.
Diff:
---
gcc/config/rs6000/mma.md | 154 ++
gcc/config/rs6000/rs6000-builtin.cc | 17 +++
gcc/config/rs6000/rs6000-call.cc | 10 +-
gcc/config/rs6000/rs6000-modes.def| 4 +
gcc/config/rs6000/rs6000.cc | 101 -
gcc/config/rs6000/rs6000.h| 6 +-
gcc/testsuite/gcc.target/powerpc/dm-1024bit.c | 63 +++
7 files changed, 321 insertions(+), 34 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index f3870eac51a..4f9c59046ea 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -91,6 +91,11 @@
UNSPEC_MMA_XVI8GER4SPP
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
+ UNSPEC_DM_INSERT512_UPPER
+ UNSPEC_DM_INSERT512_LOWER
+ UNSPEC_DM_EXTRACT512
+ UNSPEC_DMR_RELOAD_FROM_MEMORY
+ UNSPEC_DMR_RELOAD_TO_MEMORY
])
(define_c_enum "unspecv"
@@ -770,3 +775,152 @@
}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
+
+;; TDOmode (__dmr keyword for 1,024 bit registers).
+(define_expand "movtdo"
+ [(set (match_operand:TDO 0 "nonimmediate_operand")
+ (match_operand:TDO 1 "input_operand"))]
+ "TARGET_MMA_DENSE_MATH"
+{
+ rs6000_emit_move (operands[0], operands[1], TDOmode);
+ DONE;
+})
+
+(define_insn_and_split "*movtdo"
+ [(set (match_operand:TDO 0
[gcc(refs/users/meissner/heads/work163-dmf)] Update ChangeLog.*
https://gcc.gnu.org/g:a5fd8dd42b3e82d6cebf8554312be8d04c9c1a91 commit a5fd8dd42b3e82d6cebf8554312be8d04c9c1a91 Author: Michael Meissner Date: Tue Mar 19 01:11:52 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 308 +- 1 file changed, 307 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index 1599736218a..5a28e3e994b 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,6 +1,312 @@ + Branch work163-dmf, patch #106 + +PowerPC: Add support for 1,024 bit DMR registers. + +This patch is a prelimianry patch to add the full 1,024 bit dense math register +(DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of the +DMR register. + +This patch only adds the new 1,024 bit register support. It does not add +support for any instructions that need 1,024 bit registers instead of 512 bit +registers. + +I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit +registers. The 'wD' constraint added in previous patches is used for these +registers. I added support to do load and store of DMRs via the VSX registers, +since there are no load/store dense math instructions. I added the new keyword +'__dmr' to create 1,024 bit types that can be loaded into DMRs. At present, I +don't have aliases for __dmr512 and __dmr1024 that we've discussed internally. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +2024-03-19 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec. + (UNSPEC_DM_INSERT512_LOWER): Likewise. + (UNSPEC_DM_EXTRACT512): Likewise. + (UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise. + (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise. + (movtdo): New define_expand and define_insn_and_split to implement 1,024 + bit DMR registers. + (movtdo_insert512_upper): New insn. + (movtdo_insert512_lower): Likewise. + (movtdo_extract512): Likewise. + (reload_dmr_from_memory): Likewise. + (reload_dmr_to_memory): Likewise. + * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR + support. + (rs6000_init_builtins): Add support for __dmr keyword. + * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support + for TDOmode. + (rs6000_function_arg): Likewise. + * config/rs6000/rs6000-modes.def (TDOmode): New mode. + * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add + support for TDOmode. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_hard_regno_mode_ok): Likewise. + (rs6000_modes_tieable_p): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload + hooks for DMR mode. + (reg_offset_addressing_ok_p): Add support for TDOmode. + (rs6000_emit_move): Likewise. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_secondary_reload_class): Likewise. + (rs6000_mangle_type): Add mangling for __dmr type. + (rs6000_dmr_register_move_cost): Add support for TDOmode. + (rs6000_split_multireg_move): Likewise. + (rs6000_invalid_conversion): Likewise. + * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode. + (enum rs6000_builtin_type_index): Add DMR type nodes. + (dmr_type_node): Likewise. + (ptr_dmr_type_node): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/dm-1024bit.c: New test. + + Branch work163-dmf, patch #105 + +Add dense math test for new instruction names. + +2024-03-19 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/dm-double-test.c: New test. + * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New + target test. + + Branch work163-dmf, patch #104 + +PowerPC: Switch to dense math names for all MMA operations. + +This patch changes the assembler instruction names for MMA instructions from +the original name used in power10 to the new name when used with the dense math +system. I.e. xvf64gerpp becomes dmxvf64gerpp. The assembler will emit the +same bits for either spelling. + +For the non-prefixed MMA instructions, we add a 'dm' prefix in front of the +instruction. However, the prefixed instructions have a 'pm' prefix, and we add +the 'dm' prefix afterwards. To prevent having two sets of parallel int +attributes, we remove the "pm" prefix from the instruction string in the +attributes, and add it later, both in the insn name and in the output template. + +2024-03-19 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (vvi4i4i8): Change the instruction to not
[gcc(refs/users/meissner/heads/work163-dmf)] Add dense math test for new instruction names.
https://gcc.gnu.org/g:aa0c25296782e59c906d6e2f7e9f5d0f6e1556f3
commit aa0c25296782e59c906d6e2f7e9f5d0f6e1556f3
Author: Michael Meissner
Date: Tue Mar 19 01:02:48 2024 -0400
Add dense math test for new instruction names.
2024-03-19 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/dm-double-test.c: New test.
* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
target test.
Diff:
---
gcc/testsuite/gcc.target/powerpc/dm-double-test.c | 194 ++
gcc/testsuite/lib/target-supports.exp | 23 +++
2 files changed, 217 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
new file mode 100644
index 000..66c19779585
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
@@ -0,0 +1,194 @@
+/* Test derived from mma-double-1.c, modified for dense math. */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_dense_math_ok } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+#include
+#include
+#include
+
+typedef unsigned char vec_t __attribute__ ((vector_size (16)));
+typedef double v4sf_t __attribute__ ((vector_size (16)));
+#define SAVE_ACC(ACC, ldc, J) \
+ __builtin_mma_disassemble_acc (result, ACC); \
+ rowC = (v4sf_t *) [0*ldc+J]; \
+ rowC[0] += result[0]; \
+ rowC = (v4sf_t *) [1*ldc+J]; \
+ rowC[0] += result[1]; \
+ rowC = (v4sf_t *) [2*ldc+J]; \
+ rowC[0] += result[2]; \
+ rowC = (v4sf_t *) [3*ldc+J]; \
+ rowC[0] += result[3];
+
+void
+DM (int m, int n, int k, double *A, double *B, double *C)
+{
+ __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;
+ v4sf_t result[4];
+ v4sf_t *rowC;
+ for (int l = 0; l < n; l += 4)
+{
+ double *CO;
+ double *AO;
+ AO = A;
+ CO = C;
+ C += m * 4;
+ for (int j = 0; j < m; j += 16)
+ {
+ double *BO = B;
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ unsigned long i;
+
+ for (i = 0; i < k; i++)
+ {
+ vec_t *rowA = (vec_t *) & AO[i * 16];
+ __vector_pair rowB;
+ vec_t *rb = (vec_t *) & BO[i * 4];
+ __builtin_mma_assemble_pair (, rb[1], rb[0]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[0]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[1]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[2]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[3]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[4]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[5]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[6]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[7]);
+ }
+ SAVE_ACC (, m, 0);
+ SAVE_ACC (, m, 4);
+ SAVE_ACC (, m, 2);
+ SAVE_ACC (, m, 6);
+ SAVE_ACC (, m, 8);
+ SAVE_ACC (, m, 12);
+ SAVE_ACC (, m, 10);
+ SAVE_ACC (, m, 14);
+ AO += k * 16;
+ BO += k * 4;
+ CO += 16;
+ }
+ B += k * 4;
+}
+}
+
+void
+init (double *matrix, int row, int column)
+{
+ for (int j = 0; j < column; j++)
+{
+ for (int i = 0; i < row; i++)
+ {
+ matrix[j * row + i] = (i * 16 + 2 + j) / 0.123;
+ }
+}
+}
+
+void
+init0 (double *matrix, double *matrix1, int row, int column)
+{
+ for (int j = 0; j < column; j++)
+for (int i = 0; i < row; i++)
+ matrix[j * row + i] = matrix1[j * row + i] = 0;
+}
+
+
+void
+print (const char *name, const double *matrix, int row, int column)
+{
+ printf ("Matrix %s has %d rows and %d columns:\n", name, row, column);
+ for (int i = 0; i < row; i++)
+{
+ for (int j = 0; j < column; j++)
+ {
+ printf ("%f ", matrix[j * row + i]);
+ }
+ printf ("\n");
+}
+ printf ("\n");
+}
+
+int
+main (int argc, char *argv[])
+{
+ int rowsA, colsB, common;
+ int i, j, k;
+ int ret = 0;
+
+ for (int t = 16; t <= 128; t += 16)
+{
+ for (int t1 = 4; t1 <= 16; t1 += 4)
+ {
+ rowsA = t;
+ colsB = t1;
+ common = 1;
+ /* printf ("Running test for rows = %d,cols = %d\n", t, t1); */
+ double A[rowsA * common];
+ double B[common * colsB];
+ double C[rowsA * colsB];
+ double D[rowsA * colsB];
+
+
+ init (A, rowsA, common);
+ init (B, common, colsB);
+ init0 (C, D, rowsA, colsB);
+ DM (rowsA, colsB, common, A, B, C);
+
+ for (i = 0; i < colsB; i++)
+ {
+ for (j = 0; j < rowsA; j++)
+ {
+ D[i *
[gcc(refs/users/meissner/heads/work163-dmf)] PowerPC: Switch to dense math names for all MMA operations.
https://gcc.gnu.org/g:f4c6cc290f3742ddafeedd15712ebbf6c57e922e commit f4c6cc290f3742ddafeedd15712ebbf6c57e922e Author: Michael Meissner Date: Tue Mar 19 01:01:25 2024 -0400 PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruction names for MMA instructions from the original name used in power10 to the new name when used with the dense math system. I.e. xvf64gerpp becomes dmxvf64gerpp. The assembler will emit the same bits for either spelling. For the non-prefixed MMA instructions, we add a 'dm' prefix in front of the instruction. However, the prefixed instructions have a 'pm' prefix, and we add the 'dm' prefix afterwards. To prevent having two sets of parallel int attributes, we remove the "pm" prefix from the instruction string in the attributes, and add it later, both in the insn name and in the output template. 2024-03-19 Michael Meissner gcc/ * config/rs6000/mma.md (vvi4i4i8): Change the instruction to not have a "pm" prefix. (avvi4i4i8): Likewise. (vvi4i4i2): Likewise. (avvi4i4i2): Likewise. (vvi4i4): Likewise. (avvi4i4): Likewise. (pvi4i2): Likewise. (apvi4i2): Likewise. (vvi4i4i4): Likewise. (avvi4i4i4): Likewise. (mma_xxsetaccz): Add support for running on DMF systems, generating the dense math instruction and using the dense math accumulators. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_pm): Add support for running on DMF systems, generating the dense math instruction and using the dense math accumulators. Rename the insn with a 'pm' prefix and add either 'pm' or 'pmdm' prefixes based on whether we have the original MMA specification or if we have dense math support. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. Diff: --- gcc/config/rs6000/mma.md | 161 +++ 1 file changed, 107 insertions(+), 54 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 2ce613b46cc..f3870eac51a 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -224,44 +224,47 @@ (UNSPEC_MMA_XVF64GERNP "xvf64gernp") (UNSPEC_MMA_XVF64GERNN "xvf64gernn")]) -(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")]) +;; The "pm" prefix is not in these expansions, so that we can generate +;; pmdmxvi4ger8 on systems with dense math registers and xvi4ger8 on systems +;; without dense math registers. +(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "xvi4ger8")]) -(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")]) +(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "xvi4ger8pp")]) -(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2"pmxvi16ger2") -(UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s") -(UNSPEC_MMA_PMXVF16GER2"pmxvf16ger2") -(UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")]) +(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2"xvi16ger2") +(UNSPEC_MMA_PMXVI16GER2S "xvi16ger2s") +(UNSPEC_MMA_PMXVF16GER2"xvf16ger2") +(UNSPEC_MMA_PMXVBF16GER2 "xvbf16ger2")]) -(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp") -(UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp") -(UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp") -(UNSPEC_MMA_PMXVF16GER2PN "pmxvf16ger2pn") -(UNSPEC_MMA_PMXVF16GER2NP "pmxvf16ger2np") -(UNSPEC_MMA_PMXVF16GER2NN "pmxvf16ger2nn") -(UNSPEC_MMA_PMXVBF16GER2PP "pmxvbf16ger2pp") -(UNSPEC_MMA_PMXVBF16GER2PN "pmxvbf16ger2pn") -(UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np") -(UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")]) +(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "xvi16ger2pp") +(UNSPEC_MMA_PMXVI16GER2SPP "xvi16ger2spp") +(UNSPEC_MMA_PMXVF16GER2PP "xvf16ger2pp") +
[gcc(refs/users/meissner/heads/work163-dmf)] Add wD constraint.
https://gcc.gnu.org/g:98e71fc431df3b382531fcd3d3a87628c07f8f97
commit 98e71fc431df3b382531fcd3d3a87628c07f8f97
Author: Michael Meissner
Date: Tue Mar 19 00:51:39 2024 -0400
Add wD constraint.
This patch adds a new constraint ('wD') that matches the accumulator
registers
that overlap with VSX registers 0..31 on power10. Future patches will add
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.
2024-03-19 Michael Meissner
* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_disassemble_acc): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
"TARGET_MMA"
" %A0"
@@ -515,7 +513,7 @@
;; UNSPEC_VOLATILE.
(define_insn "mma_xxsetaccz"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD")
(unspec_volatile:XO [(const_int 0)]
UNSPECV_MMA_XXSETACCZ))]
"TARGET_MMA"
@@ -523,7 +521,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +530,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +540,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +549,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +559,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +572,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +586,7 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +599,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO
[gcc(refs/users/meissner/heads/work163-dmf)] Use vector pair load/store for memcpy with -mcpu=future
https://gcc.gnu.org/g:88cc50bad1cb1e15e719ebf000b87d9532fd29bd commit 88cc50bad1cb1e15e719ebf000b87d9532fd29bd Author: Michael Meissner Date: Mon Mar 18 22:58:56 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC did not enable using the load vector pair and store vector pair instructions when optimizing things like memory copy. This patch enables using those instructions if -mcpu=future is used. 2024-03-18 Michael Meissner gcc/ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using load vector pair and store vector pair instructions for memory copy operations. (POWERPC_MASKS): Make the bit for enabling using load vector pair and store vector pair operations set and reset when the PowerPC processor is changed. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 47365534af8..4ddba142e44 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -90,6 +90,7 @@ | OPTION_MASK_POWER11) #define ISA_FUTURE_MASKS_SERVER(ISA_POWER11_MASKS_SERVER \ +| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\ | OPTION_MASK_FUTURE) /* Flags that need to be turned off if -mno-vsx. */ @@ -121,6 +122,7 @@ /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC\ +| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \
[gcc(refs/users/meissner/heads/work163-dmf)] Merge commit 'refs/users/meissner/heads/work163-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:dc65989f104026665d03a44dad3d7d1e6aa26e9d commit dc65989f104026665d03a44dad3d7d1e6aa26e9d Merge: a5fd8dd42b3 672c4b0e0de Author: Michael Meissner Date: Wed Mar 20 00:07:40 2024 -0400 Merge commit 'refs/users/meissner/heads/work163-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work163-dmf Diff:
[gcc r14-9562] LoongArch: Remove unused/useless definitions.
https://gcc.gnu.org/g:0529f98b7b1b0eadb009a7aa3161462897e53745
commit r14-9562-g0529f98b7b1b0eadb009a7aa3161462897e53745
Author: Chenghui Pan
Date: Fri Mar 15 09:30:25 2024 +0800
LoongArch: Remove unused/useless definitions.
This patch removes some unnecessary definitions of target hook functions
according to the documentation of GCC.
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h
(loongarch_cfun_has_cprestore_slot_p): Delete.
(loongarch_adjust_insn_length): Delete.
(current_section_name): Delete.
(loongarch_split_symbol_type): Delete.
* config/loongarch/loongarch.cc
(loongarch_case_values_threshold): Delete.
(loongarch_spill_class): Delete.
(TARGET_OPTAB_SUPPORTED_P): Delete.
(TARGET_CASE_VALUES_THRESHOLD): Delete.
(TARGET_SPILL_CLASS): Delete.
Diff:
---
gcc/config/loongarch/loongarch-protos.h | 5 -
gcc/config/loongarch/loongarch.cc | 26 --
2 files changed, 31 deletions(-)
diff --git a/gcc/config/loongarch/loongarch-protos.h
b/gcc/config/loongarch/loongarch-protos.h
index 1fdfda9af01..871544f760c 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -93,7 +93,6 @@ extern void loongarch_split_lsx_copy_d (rtx, rtx, rtx, rtx
(*)(rtx, rtx, rtx));
extern void loongarch_split_lsx_insert_d (rtx, rtx, rtx, rtx);
extern void loongarch_split_lsx_fill_d (rtx, rtx);
extern const char *loongarch_output_move (rtx, rtx);
-extern bool loongarch_cfun_has_cprestore_slot_p (void);
#ifdef RTX_CODE
extern void loongarch_expand_scc (rtx *);
extern bool loongarch_expand_vec_cmp (rtx *);
@@ -135,7 +134,6 @@ extern int loongarch_class_max_nregs (enum reg_class,
machine_mode);
extern machine_mode loongarch_hard_regno_caller_save_mode (unsigned int,
unsigned int,
machine_mode);
-extern int loongarch_adjust_insn_length (rtx_insn *, int);
extern const char *loongarch_output_conditional_branch (rtx_insn *, rtx *,
const char *,
const char *);
@@ -157,7 +155,6 @@ extern bool loongarch_global_symbol_noweak_p (const_rtx);
extern bool loongarch_weak_symbol_p (const_rtx);
extern bool loongarch_symbol_binds_local_p (const_rtx);
-extern const char *current_section_name (void);
extern unsigned int current_section_flags (void);
extern bool loongarch_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
extern bool loongarch_check_zero_div_p (void);
@@ -198,8 +195,6 @@ extern bool loongarch_epilogue_uses (unsigned int);
extern bool loongarch_load_store_bonding_p (rtx *, machine_mode, bool);
extern bool loongarch_split_symbol_type (enum loongarch_symbol_type);
-typedef rtx (*mulsidi3_gen_fn) (rtx, rtx, rtx);
-
extern void loongarch_register_frame_header_opt (void);
extern void loongarch_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
extern void loongarch_expand_vec_cond_mask_expr (machine_mode, machine_mode,
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 5344f2a6987..570e9aebad1 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10816,23 +10816,6 @@ loongarch_expand_vec_cmp (rtx operands[])
return true;
}
-/* Implement TARGET_CASE_VALUES_THRESHOLD. */
-
-unsigned int
-loongarch_case_values_threshold (void)
-{
- return default_case_values_threshold ();
-}
-
-/* Implement TARGET_SPILL_CLASS. */
-
-static reg_class_t
-loongarch_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
- machine_mode mode ATTRIBUTE_UNUSED)
-{
- return NO_REGS;
-}
-
/* Implement TARGET_PROMOTE_FUNCTION_MODE. */
/* This function is equivalent to default_promote_function_mode_always_promote
@@ -11287,9 +11270,6 @@ loongarch_asm_code_end (void)
#undef TARGET_FUNCTION_ARG_BOUNDARY
#define TARGET_FUNCTION_ARG_BOUNDARY loongarch_function_arg_boundary
-#undef TARGET_OPTAB_SUPPORTED_P
-#define TARGET_OPTAB_SUPPORTED_P loongarch_optab_supported_p
-
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P loongarch_vector_mode_supported_p
@@ -11359,18 +11339,12 @@ loongarch_asm_code_end (void)
#undef TARGET_SCHED_REASSOCIATION_WIDTH
#define TARGET_SCHED_REASSOCIATION_WIDTH loongarch_sched_reassociation_width
-#undef TARGET_CASE_VALUES_THRESHOLD
-#define TARGET_CASE_VALUES_THRESHOLD loongarch_case_values_threshold
-
#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV loongarch_atomic_assign_expand_fenv
#undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
#define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
-#undef TARGET_SPILL_CLASS
-#define TARGET_SPILL_CLASS
[gcc r14-9563] LoongArch: Change loongarch_expand_vec_cmp()'s return type from bool to void.
https://gcc.gnu.org/g:1938d9d2bb8ecf84d2aa3c3ef2fb78ec19433057
commit r14-9563-g1938d9d2bb8ecf84d2aa3c3ef2fb78ec19433057
Author: Chenghui Pan
Date: Fri Mar 15 09:30:26 2024 +0800
LoongArch: Change loongarch_expand_vec_cmp()'s return type from bool to
void.
This function is always return true at the end of function implementation,
so the return value is useless.
gcc/ChangeLog:
* config/loongarch/lasx.md (vec_cmp): Remove
checking
of loongarch_expand_vec_cmp()'s return value.
(vec_cmpu): Ditto.
* config/loongarch/lsx.md (vec_cmp): Ditto.
(vec_cmpu): Ditto.
* config/loongarch/loongarch-protos.h
(loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s
return
type from bool to void.
* config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
Diff:
---
gcc/config/loongarch/lasx.md| 6 ++
gcc/config/loongarch/loongarch-protos.h | 2 +-
gcc/config/loongarch/loongarch.cc | 3 +--
gcc/config/loongarch/lsx.md | 6 ++
4 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 3f25c0c1756..2fa5e46c8e8 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -1378,8 +1378,7 @@
(match_operand:LASX 3 "register_operand")]))]
"ISA_HAS_LASX"
{
- bool ok = loongarch_expand_vec_cmp (operands);
- gcc_assert (ok);
+ loongarch_expand_vec_cmp (operands);
DONE;
})
@@ -1390,8 +1389,7 @@
(match_operand:ILASX 3 "register_operand")]))]
"ISA_HAS_LASX"
{
- bool ok = loongarch_expand_vec_cmp (operands);
- gcc_assert (ok);
+ loongarch_expand_vec_cmp (operands);
DONE;
})
diff --git a/gcc/config/loongarch/loongarch-protos.h
b/gcc/config/loongarch/loongarch-protos.h
index 871544f760c..e3ed2b912a5 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -95,7 +95,7 @@ extern void loongarch_split_lsx_fill_d (rtx, rtx);
extern const char *loongarch_output_move (rtx, rtx);
#ifdef RTX_CODE
extern void loongarch_expand_scc (rtx *);
-extern bool loongarch_expand_vec_cmp (rtx *);
+extern void loongarch_expand_vec_cmp (rtx *);
extern void loongarch_expand_conditional_branch (rtx *);
extern void loongarch_expand_conditional_move (rtx *);
extern void loongarch_expand_conditional_trap (rtx);
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 570e9aebad1..f11cf149bbf 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10807,13 +10807,12 @@ loongarch_expand_vec_cond_mask_expr (machine_mode
mode, machine_mode vimode,
}
/* Expand integer vector comparison */
-bool
+void
loongarch_expand_vec_cmp (rtx operands[])
{
rtx_code code = GET_CODE (operands[1]);
loongarch_expand_lsx_cmp (operands[0], code, operands[2], operands[3]);
- return true;
}
/* Implement TARGET_PROMOTE_FUNCTION_MODE. */
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index b9b94b9079c..87d3e7c5d9f 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -518,8 +518,7 @@
(match_operand:LSX 3 "register_operand")]))]
"ISA_HAS_LSX"
{
- bool ok = loongarch_expand_vec_cmp (operands);
- gcc_assert (ok);
+ loongarch_expand_vec_cmp (operands);
DONE;
})
@@ -530,8 +529,7 @@
(match_operand:ILSX 3 "register_operand")]))]
"ISA_HAS_LSX"
{
- bool ok = loongarch_expand_vec_cmp (operands);
- gcc_assert (ok);
+ loongarch_expand_vec_cmp (operands);
DONE;
})
[gcc r14-9564] LoongArch: Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros.
https://gcc.gnu.org/g:994d8f922b9d88f45775f57a490409ab1c3baf59 commit r14-9564-g994d8f922b9d88f45775f57a490409ab1c3baf59 Author: Chenghui Pan Date: Fri Mar 15 09:30:27 2024 +0800 LoongArch: Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros. These macros are completely same in definition, so we can keep the previous one and eliminate later one. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros. (loongarch_hard_regno_nregs): Ditto. (loongarch_class_max_nregs): Ditto. (loongarch_get_separate_components): Ditto. (loongarch_process_components): Ditto. * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto. (UNITS_PER_HWFPVALUE): Ditto. (UNITS_PER_FPVALUE): Ditto. Diff: --- gcc/config/loongarch/loongarch.cc | 10 +- gcc/config/loongarch/loongarch.h | 7 ++- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index f11cf149bbf..030957db4e7 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -6776,7 +6776,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode) and TRUNC. There's no point allowing sizes smaller than a word, because the FPU has no appropriate load/store instructions. */ if (mclass == MODE_INT) - return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG; + return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FP_REG; } return false; @@ -6819,7 +6819,7 @@ loongarch_hard_regno_nregs (unsigned int regno, machine_mode mode) if (LASX_SUPPORTED_MODE_P (mode)) return 1; - return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; + return (GET_MODE_SIZE (mode) + UNITS_PER_FP_REG - 1) / UNITS_PER_FP_REG; } /* All other registers are word-sized. */ @@ -6854,7 +6854,7 @@ loongarch_class_max_nregs (enum reg_class rclass, machine_mode mode) else if (LSX_SUPPORTED_MODE_P (mode)) size = MIN (size, UNITS_PER_LSX_REG); else - size = MIN (size, UNITS_PER_FPREG); + size = MIN (size, UNITS_PER_FP_REG); } left &= ~reg_class_contents[FP_REGS]; } @@ -8228,7 +8228,7 @@ loongarch_get_separate_components (void) if (IMM12_OPERAND (offset)) bitmap_set_bit (components, regno); - offset -= UNITS_PER_FPREG; + offset -= UNITS_PER_FP_REG; } /* Don't mess with the hard frame pointer. */ @@ -8307,7 +8307,7 @@ loongarch_process_components (sbitmap components, loongarch_save_restore_fn fn) if (bitmap_bit_p (components, regno)) loongarch_save_restore_reg (mode, regno, offset, fn); - offset -= UNITS_PER_FPREG; + offset -= UNITS_PER_FP_REG; } } diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index bf2351f0968..888a633961d 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -138,19 +138,16 @@ along with GCC; see the file COPYING3. If not see /* Width of a LASX vector register in bits. */ #define BITS_PER_LASX_REG (UNITS_PER_LASX_REG * BITS_PER_UNIT) -/* For LARCH, width of a floating point register. */ -#define UNITS_PER_FPREG (TARGET_DOUBLE_FLOAT ? 8 : 4) - /* The largest size of value that can be held in floating-point registers and moved with a single instruction. */ #define UNITS_PER_HWFPVALUE \ - (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FPREG) + (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FP_REG) /* The largest size of value that can be held in floating-point registers. */ #define UNITS_PER_FPVALUE \ (TARGET_SOFT_FLOAT ? 0 \ - : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ + : TARGET_SINGLE_FLOAT ? UNITS_PER_FP_REG \ : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) /* The number of bytes in a double. */
[gcc(refs/users/meissner/heads/work163-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:12f6a9e9fae06b2df732fc02158d4396aa019fe0 commit 12f6a9e9fae06b2df732fc02158d4396aa019fe0 Author: Michael Meissner Date: Mon Mar 18 15:57:16 2024 -0400 Add ChangeLog.test and update REVISION. 2024-03-18 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..07f6729db60 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work163-test, baseline + +2024-03-18 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index f37c7e5ef94..604bf44a62f 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work163 branch +work163-test branch
[gcc/meissner/heads/work163-test] (5 commits) Merge commit 'refs/users/meissner/heads/work163-test' of gi
The branch 'meissner/heads/work163-test' was updated to point to: c18733b8867... Merge commit 'refs/users/meissner/heads/work163-test' of gi It previously pointed to: fd35cfe58c0... Merge commit 'refs/users/meissner/heads/work163-test' of gi Diff: Summary of changes (added commits): --- c18733b... Merge commit 'refs/users/meissner/heads/work163-test' of gi 12f6a9e... Add ChangeLog.test and update REVISION. 04201e6... Add -mcpu=future tuning support. (*) e6477b5... Add -mcpu=future support. (*) acd5a60... Revert all changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work163-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc r14-9557] [PR99829][LRA]: Fixing LRA ICE on arm
https://gcc.gnu.org/g:9c91f8a88b2db50c8faf70786d3cef27b39ac9fc
commit r14-9557-g9c91f8a88b2db50c8faf70786d3cef27b39ac9fc
Author: Vladimir N. Makarov
Date: Tue Mar 19 16:57:11 2024 -0400
[PR99829][LRA]: Fixing LRA ICE on arm
LRA removed insn setting equivalence to memory whose output was
reloaded. This resulted in writing an uninitiated value to the memory
which triggered assert in LRA code checking the final generated code.
This patch fixes the problem. Comment in the patch contains more
details about the problem and its solution.
gcc/ChangeLog:
PR target/99829
* lra-constraints.cc (lra_constraints): Prevent removing insn
with reverse equivalence to memory if the memory was reloaded.
Diff:
---
gcc/lra-constraints.cc | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 0ae81c1ff9c..10e3d4e4097 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -5213,7 +5213,7 @@ lra_constraints (bool first_p)
bool changed_p;
int i, hard_regno, new_insns_num;
unsigned int min_len, new_min_len, uid;
- rtx set, x, reg, dest_reg;
+ rtx set, x, reg, nosubreg_dest;
rtx_insn *original_insn;
basic_block last_bb;
bitmap_iterator bi;
@@ -5377,14 +5377,14 @@ lra_constraints (bool first_p)
{
if ((set = single_set (curr_insn)) != NULL_RTX)
{
- dest_reg = SET_DEST (set);
+ nosubreg_dest = SET_DEST (set);
/* The equivalence pseudo could be set up as SUBREG in a
case when it is a call restore insn in a mode
different from the pseudo mode. */
- if (GET_CODE (dest_reg) == SUBREG)
- dest_reg = SUBREG_REG (dest_reg);
- if ((REG_P (dest_reg)
- && (x = get_equiv (dest_reg)) != dest_reg
+ if (GET_CODE (nosubreg_dest) == SUBREG)
+ nosubreg_dest = SUBREG_REG (nosubreg_dest);
+ if ((REG_P (nosubreg_dest)
+ && (x = get_equiv (nosubreg_dest)) != nosubreg_dest
/* Remove insns which set up a pseudo whose value
cannot be changed. Such insns might be not in
init_insns because we don't update equiv data
@@ -5403,11 +5403,21 @@ lra_constraints (bool first_p)
up the equivalence. */
|| in_list_p (curr_insn,
ira_reg_equiv
-[REGNO (dest_reg)].init_insns)))
+[REGNO (nosubreg_dest)].init_insns)))
|| (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
&& in_list_p (curr_insn,
ira_reg_equiv
- [REGNO (SET_SRC (set))].init_insns)))
+ [REGNO (SET_SRC (set))].init_insns)
+ /* This is a reverse equivalence to memory (see ira.cc)
+in store insn. We can reload all the destination and
+have an output reload which is a store to memory. If
+we just remove the insn, we will have the output
+reload storing an undefined value to the memory.
+Check that we did not reload the memory to prevent a
+wrong code generation. We could implement using the
+equivalence still in such case but doing this is not
+worth the efforts as such case is very rare. */
+ && MEM_P (nosubreg_dest)))
{
/* This is equiv init insn of pseudo which did not get a
hard register -- remove the insn. */
[gcc r14-9540] tree-optimization/114151 - revert PR114074 fix
https://gcc.gnu.org/g:e0e9499aeffdaca88f0f29334384aa5f710a81a4
commit r14-9540-ge0e9499aeffdaca88f0f29334384aa5f710a81a4
Author: Richard Biener
Date: Tue Mar 19 12:24:08 2024 +0100
tree-optimization/114151 - revert PR114074 fix
The following reverts the chrec_fold_multiply fix and only keeps
handling of constant overflow which keeps the original testcase
fixed. A better solution might involve ranger improvements or
tracking of assumptions during SCEV analysis similar to what niter
analysis does.
PR tree-optimization/114151
PR tree-optimization/114269
PR tree-optimization/114322
PR tree-optimization/114074
* tree-chrec.cc (chrec_fold_multiply): Restrict the use of
unsigned arithmetic when actual overflow on constant operands
is observed.
* gcc.dg/pr68317.c: Revert last change.
Diff:
---
gcc/testsuite/gcc.dg/pr68317.c | 4 +--
gcc/tree-chrec.cc | 63 +++---
2 files changed, 30 insertions(+), 37 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/pr68317.c b/gcc/testsuite/gcc.dg/pr68317.c
index 06cd2e1da9c..bd053a7522b 100644
--- a/gcc/testsuite/gcc.dg/pr68317.c
+++ b/gcc/testsuite/gcc.dg/pr68317.c
@@ -12,8 +12,8 @@ foo ()
{
int32_t index = 0;
- for (index; index <= 10; index--) /* { dg-warning "iteration \[0-9\]+ invokes
undefined behavior" } */
+ for (index; index <= 10; index--) // expected warning here
/* Result of the following multiply will overflow
when converted to signed int32_t. */
- bar ((0xcafe + index) * 0xdead);
+ bar ((0xcafe + index) * 0xdead); /* { dg-warning "iteration \[0-9\]+
invokes undefined behavior" } */
}
diff --git a/gcc/tree-chrec.cc b/gcc/tree-chrec.cc
index 1b2ed753551..8b7982a2dbe 100644
--- a/gcc/tree-chrec.cc
+++ b/gcc/tree-chrec.cc
@@ -38,8 +38,6 @@ along with GCC; see the file COPYING3. If not see
#include "gimple.h"
#include "tree-ssa-loop.h"
#include "dumpfile.h"
-#include "value-range.h"
-#include "value-query.h"
#include "tree-scalar-evolution.h"
/* Extended folder for chrecs. */
@@ -475,41 +473,36 @@ chrec_fold_multiply (tree type,
/* When overflow is undefined and CHREC_LEFT/RIGHT do not have the
same sign or CHREC_LEFT is zero then folding the multiply into
-the addition does not have the same behavior on overflow. Use
-unsigned arithmetic in that case. */
- value_range rl, rr;
- if (!ANY_INTEGRAL_TYPE_P (type)
- || TYPE_OVERFLOW_WRAPS (type)
- || integer_zerop (CHREC_LEFT (op0))
- || (TREE_CODE (CHREC_LEFT (op0)) == INTEGER_CST
- && TREE_CODE (CHREC_RIGHT (op0)) == INTEGER_CST
- && (tree_int_cst_sgn (CHREC_LEFT (op0))
- == tree_int_cst_sgn (CHREC_RIGHT (op0
- || (get_range_query (cfun)->range_of_expr (rl, CHREC_LEFT (op0))
- && !rl.undefined_p ()
- && (rl.nonpositive_p () || rl.nonnegative_p ())
- && get_range_query (cfun)->range_of_expr (rr,
- CHREC_RIGHT (op0))
- && !rr.undefined_p ()
- && ((rl.nonpositive_p () && rr.nonpositive_p ())
- || (rl.nonnegative_p () && rr.nonnegative_p ()
- {
- tree left = chrec_fold_multiply (type, CHREC_LEFT (op0), op1);
- tree right = chrec_fold_multiply (type, CHREC_RIGHT (op0), op1);
- return build_polynomial_chrec (CHREC_VARIABLE (op0), left, right);
- }
- else
+the addition does not have the same behavior on overflow.
+Using unsigned arithmetic in that case causes too many performance
+regressions, but catch the constant case where the multiplication
+of the step overflows. */
+ if (INTEGRAL_TYPE_P (type)
+ && TYPE_OVERFLOW_UNDEFINED (type)
+ && !integer_zerop (CHREC_LEFT (op0))
+ && TREE_CODE (op1) == INTEGER_CST
+ && TREE_CODE (CHREC_RIGHT (op0)) == INTEGER_CST)
{
- tree utype = unsigned_type_for (type);
- tree uop1 = chrec_convert_rhs (utype, op1);
- tree uleft0 = chrec_convert_rhs (utype, CHREC_LEFT (op0));
- tree uright0 = chrec_convert_rhs (utype, CHREC_RIGHT (op0));
- tree left = chrec_fold_multiply (utype, uleft0, uop1);
- tree right = chrec_fold_multiply (utype, uright0, uop1);
- tree tem = build_polynomial_chrec (CHREC_VARIABLE (op0),
-left, right);
- return chrec_convert_rhs (type, tem);
+ wi::overflow_type ovf = wi::OVF_NONE;
+ wide_int res
+ = wi::mul (wi::to_wide (CHREC_RIGHT (op0)),
+
[gcc r14-9541] libstdc++, Darwin: Do not use dev/null as the file for executables.
https://gcc.gnu.org/g:e47330d0742c985fd8d5fe7089aa381d34967d61
commit r14-9541-ge47330d0742c985fd8d5fe7089aa381d34967d61
Author: Iain Sandoe
Date: Tue Mar 19 10:40:50 2024 +
libstdc++, Darwin: Do not use dev/null as the file for executables.
Darwin has a separate debug linker, which is invoked when the command
line contains source files and debug is enabled.
Using /dev/null as the executable name does not, therefore, work when
debug is enabled, since the debug linker does not accept /dev/null as
a valid executable name.
The leads to incorrectly UNSUPPORTED testcases because of the unintended
error result from the test compilation.
The solution here is to use a temporary file that is deleted at the
end of the test (which is the mechanism used elsewhere)
libstdc++-v3/ChangeLog:
* testsuite/lib/libstdc++.exp (v3_target_compile): Instead of
/dev/null, use a temporary file for test executables on Darwin.
Signed-off-by: Iain Sandoe
Diff:
---
libstdc++-v3/testsuite/lib/libstdc++.exp | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/libstdc++-v3/testsuite/lib/libstdc++.exp
b/libstdc++-v3/testsuite/lib/libstdc++.exp
index 58804ecab26..7466fb51c58 100644
--- a/libstdc++-v3/testsuite/lib/libstdc++.exp
+++ b/libstdc++-v3/testsuite/lib/libstdc++.exp
@@ -615,11 +615,15 @@ proc v3_target_compile { source dest type options } {
}
}
+# For Windows and Darwin we might want to create a temporary file.
+# Note that it needs deleting.
+set file_to_delete ""
# Small adjustment for Windows hosts.
if { $dest == "/dev/null"
&& [info exists ::env(OS)] && [string match "Windows*" $::env(OS)] } {
if { $type == "executable" } {
set dest "x.exe"
+ set file_to_delete ${dest}
} else {
# Windows uses special file named "nul" as a substitute for
# /dev/null
@@ -627,6 +631,15 @@ proc v3_target_compile { source dest type options } {
}
}
+# Using /dev/null as the executable name does not work on Darwin when
+# debug is enabled, since the debug linker does not accept /dev/null as
+# a valid executable name.
+if { $dest == "/dev/null" && [istarget *-*-darwin*]
+ && $type == "executable" } {
+ set dest dev-null-[pid].exe
+ set file_to_delete ${dest}
+}
+
lappend options "compiler=$cxx_final"
lappend options "timeout=[timeout_value]"
@@ -637,7 +650,12 @@ proc v3_target_compile { source dest type options } {
}
set comp_output [target_compile $source $dest $type $options]
-
+if { $type == "executable" && $file_to_delete != "" } {
+ file delete $file_to_delete
+ if { [istarget *-*-darwin*] && [file exists $file_to_delete.dSYM] } {
+ file delete -force $file_to_delete.dSYM
+ }
+}
return $comp_output
}
