[PATCH, testsuite]: Avoid 'overflow in implicit constant conversion' warning in gcc.target/i386/pr50275.c for x32
Hello! 2012-09-25 Uros Bizjak ubiz...@gmail.com * gcc.target/i386/pr50725.c: Change 'long' to 'long long'. Tested on x86_64-pc-linux-gnu, committed to mainline SVN. Uros. Index: gcc.target/i386/pr50725.c === --- gcc.target/i386/pr50725.c (revision 191688) +++ gcc.target/i386/pr50725.c (working copy) @@ -39,7 +39,7 @@ if (bar (22) != 24 || bar (20) != 128) abort (); #ifdef __x86_64__ - register long r10 __asm__ (r10) = 0xdeadbeefdeadbeefUL; + register long long r10 __asm__ (r10) = 0xdeadbeefdeadbeefULL; asm volatile ( : +r (r10)); #endif if (baz (0, 0, 0, 0, 0, 0, 22) != 24 || baz (0, 0, 0, 0, 0, 0, 20) != 128)
Re: [PATCH] Fix PR C++/50970 -- Function pointer dereferenced twice in if statement on Arm cpu
On 22 September 2012 06:42, rearn...@arm.com wrote:
On 20 Sep 2012, at 08:51, Zhenqiang Chen zhenqiang.c...@linaro.org wrote:
Hi,
PR 50970 is a general c++ front-end issue for targets which define
TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta, although the
reporter had issues only on ARM.
Root cause: It misses a check for side effects when generating pfn and
delta related expressions.
In the failed case, op0 is a function call. pfn0 and delta0 are
expressions based on the return value of op0. Without the check, the
function will be called twice.
The patch is to add the check for op0.
No make check regression on ARM.
Is it OK for trunk?
Thanks!
-Zhenqiang
cp/ChangeLog:
2012-09-20 Zhenqiang Chen zhenqiang.c...@linaro.org
PR c++/50970
* typeck.c (cp_build_binary_op): Check side effects before generating
pfn and delta related expressions.
Ok.
R.
Thanks, committed to trunk.
The bug also happens in FSF 4.7. Can I backport it to 4.7?
Thanks!
-Zhenqiang
diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c
index ad4b090..884f7d0 100644
--- a/gcc/cp/typeck.c
+++ b/gcc/cp/typeck.c
@@ -4159,18 +4159,23 @@ cp_build_binary_op (location_t location,
if (TARGET_PTRMEMFUNC_VBIT_LOCATION
== ptrmemfunc_vbit_in_delta)
{
- tree pfn0 = pfn_from_ptrmemfunc (op0);
- tree delta0 = delta_from_ptrmemfunc (op0);
- tree e1 = cp_build_binary_op (location,
-EQ_EXPR,
- pfn0,
- build_zero_cst (TREE_TYPE (pfn0)),
-complain);
- tree e2 = cp_build_binary_op (location,
-BIT_AND_EXPR,
-delta0,
-integer_one_node,
-complain);
+ tree pfn0, delta0, e1, e2;
+
+ if (TREE_SIDE_EFFECTS (op0))
+op0 = save_expr (op0);
+
+ pfn0 = pfn_from_ptrmemfunc (op0);
+ delta0 = delta_from_ptrmemfunc (op0);
+ e1 = cp_build_binary_op (location,
+ EQ_EXPR,
+ pfn0,
+ build_zero_cst (TREE_TYPE (pfn0)),
+ complain);
+ e2 = cp_build_binary_op (location,
+ BIT_AND_EXPR,
+ delta0,
+ integer_one_node,
+ complain);
if ((complain tf_warning)
c_inhibit_evaluation_warnings == 0
Re: [PATCH] Fix PR54674
On Mon, 24 Sep 2012, William J. Schmidt wrote: In cases where pointers and ints are cast back and forth, SLSR can be tricked into introducing a multiply where one of the operands is of pointer type. Don't do that! Verified that the reduced test case in the PR is fixed with a cross-compile to sh4-unknown-linux-gnu with -Os, which is the only known situation where the replacement looks profitable. (It appears multiply costs are underestimated.) Bootstrapped and tested on powerpc64-unknown-linux-gnu with no new regressions. Ok for trunk? Ok. Btw, a multiply by/of a pointer in GIMPLE is done by casting to an appropriate unsigned type, doing the multiply, and then casting back to the pointer type. Just in case it _is_ profitable to do the transform (the patch seems to try to avoid the situation only?) Thanks, Richard. Thanks, Bill 2012-09-24 Bill Schmidt wschm...@linux.vnet.ibm.com * gimple-ssa-strength-reduction.c (analyze_increments): Don't introduce a multiplication with a pointer operand. Index: gcc/gimple-ssa-strength-reduction.c === --- gcc/gimple-ssa-strength-reduction.c (revision 191665) +++ gcc/gimple-ssa-strength-reduction.c (working copy) @@ -2028,6 +2028,15 @@ analyze_increments (slsr_cand_t first_dep, enum ma incr_vec[i].cost = COST_INFINITE; + /* If we need to add an initializer, make sure we don't introduce + a multiply by a pointer type, which can happen in certain cast + scenarios. */ + else if (!incr_vec[i].initializer + TREE_CODE (first_dep-stride) != INTEGER_CST + POINTER_TYPE_P (TREE_TYPE (first_dep-stride))) + + incr_vec[i].cost = COST_INFINITE; + /* For any other increment, if this is a multiply candidate, we must introduce a temporary T and initialize it with T_0 = stride * increment. When optimizing for speed, walk the -- Richard Biener rguent...@suse.de SUSE / SUSE Labs SUSE LINUX Products GmbH - Nuernberg - AG Nuernberg - HRB 16746 GF: Jeff Hawn, Jennifer Guild, Felix Imend
[PATCH, rtl-optimization]: Fix PR54457, [x32] Fail to combine 64bit index + constant
Hello!
Attached patch fixes the combine deficiency, where combine is not able
to recognize combination of:
Trying 6 - 8:
Failed to match this instruction:
(set (reg:QI 66)
(mem/j:QI (plus:SI (subreg:SI (plus:DI (reg/v:DI 62 [ position ])
(const_int 1 [0x1])) 0)
(symbol_ref:SI (array) [flags 0x40] var_decl
0x719ad260 array)) [0 array S1 A8]))
This should be a valid address, but the RTX is not accepted in
ix86_decompose_address since
we have two displacements here. Combine should simplify this RTX to:
(set (reg:QI 68)
(mem/j:QI (plus:SI (subreg:SI (reg/v:DI 62 [ position ]) 0)
(const:SI (plus:SI (symbol_ref:SI (array) [flags 0x40]
var_decl 0x7f8d1bc41390 array)
(const_int 1 [0x1] [0 array S1 A8]))
as is the case with -m32 (but rejected for 32bit targets in
ix86_address_subreg_operand for unrelated reason).
The solution is, to transform operands of PLUS and MINUS RTX in the
form of (subreg:M (op:N A C) 0) to (op:M (subreg:N (A 0)) C), as is
done for standalone subreg operation in 32bit case. This
transformation generates canonical (plus:M (plus:M (subreg:N (A 0) C1)
C2)) RTXes that can be recognized and further optimized by
simplify_plus_minus.
The effect of the patch on following testcase (-O2 -mx32 -maddres-mode=short):
--cut here--
extern char array[40];
char foo (long long position)
{
return array[position + 1];
}
--cut here--
foo:
- addq$1, %rdi
- movzbl array(%edi), %eax
+ movzbl array+1(%edi), %eax
ret
The patch is effective also for -fpic:
foo:
movlarray@GOTPCREL(%rip), %eax
- addq$1, %rdi
- movzbl (%eax,%edi), %eax
+ movzbl 1(%eax,%edi), %eax
ret
Generated code for vanilla 32bit and 64bit targets is unchanged.
2012-09-25 Uros Bizjak ubiz...@gmail.com
PR rtl-optimization/54457
* combine.c (combine_simplify_rtx) RTX_COMM_ARITH, RTX_BIN_ARIT:
For PLUS and MINUS, convert plus_minus_operand_p operands in
the form of (subreg:M (op:N A C) 0) to (op:M (subreg:N (A 0)) C).
* simplify-rtx.c (plus_minus_operand_p): Make global.
* rtl.h (plus_minus_operand_p): Declare.
testsuite/ChangeLog:
2012-09-25 Uros Bizjak ubiz...@gmail.com
PR rtl-optimization/54457
* gcc.target/i386/pr54457.c: New test.
Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu
{,-m32}, also on x32 target by H.J [1].
OK for mainline?
[1] http://gcc.gnu.org/ml/gcc-testresults/2012-09/msg02448.html
Uros.
Index: combine.c
===
--- combine.c (revision 191681)
+++ combine.c (working copy)
@@ -5314,6 +5314,26 @@ combine_simplify_rtx (rtx x, enum machine_mode op0
break;
case RTX_COMM_ARITH:
case RTX_BIN_ARITH:
+ if ((code == PLUS || code == MINUS)
+ GET_MODE_CLASS (mode) == MODE_INT
+ HWI_COMPUTABLE_MODE_P (mode))
+ {
+ /* Adjust operands in the form of (subreg:M (op:N A C) 0)
+to (op:M (subreg:N (A 0)) C). This transformation
+generates canonical (plus:M (plus:M (subreg:N (A 0) C1) C2))
+RTXes that can be recognized and further optimized by
+simplify_plus_minus. */
+ if (GET_CODE (XEXP (x, 0)) == SUBREG
+ plus_minus_operand_p (SUBREG_REG (XEXP (x, 0
+ SUBST (XEXP (x, 0),
+ force_to_mode (XEXP (x, 0), mode,
+ ~(unsigned HOST_WIDE_INT) 0, 0));
+ if (GET_CODE (XEXP (x, 1)) == SUBREG
+ plus_minus_operand_p (SUBREG_REG (XEXP (x, 1
+ SUBST (XEXP (x, 1),
+ force_to_mode (XEXP (x, 1), mode,
+ ~(unsigned HOST_WIDE_INT) 0, 0));
+ }
temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
break;
case RTX_BITFIELD_OPS:
Index: rtl.h
===
--- rtl.h (revision 191681)
+++ rtl.h (working copy)
@@ -1895,6 +1895,7 @@ extern bool val_signbit_known_set_p (enum machine_
unsigned HOST_WIDE_INT);
extern bool val_signbit_known_clear_p (enum machine_mode,
unsigned HOST_WIDE_INT);
+extern bool plus_minus_operand_p (const_rtx);
/* In reginfo.c */
extern enum machine_mode choose_hard_reg_mode (unsigned int, unsigned int,
Index: simplify-rtx.c
===
--- simplify-rtx.c (revision 191681)
+++ simplify-rtx.c (working copy)
@@ -48,7 +48,6 @@ along with GCC; see the file COPYING3. If not see
HOST_WIDE_INT) low) 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
static rtx neg_const_int (enum machine_mode, const_rtx);
-static bool plus_minus_operand_p (const_rtx);
static bool simplify_plus_minus_op_data_cmp (rtx,
Re: [patch] PR54645 move location_adhoc_data map into GC
On Mon, Sep 24, 2012 at 10:23 PM, Hans-Peter Nilsson h...@bitrange.com wrote: On Fri, 21 Sep 2012, Dehao Chen wrote: This patch moves location_adhoc_data into GC, and also rebuild the hash table when reading in the PCH. After the patch, PCH can work as expected. Bootstrapped and passed gcc regression tests on x8664_linux. If you have a moment to consider improvements for the test-instructions at http://gcc.gnu.org/contribute.html#testing to try and avoid this situation (introducing regressions), that'd be nice; IIUC it wasn't clear enough that the make check must be at the top tree? It seems to say so but maybe that's somehow in a blind spot. OK for trunk? Thanks, Dehao libcpp/ChangeLog: 2012-09-21 Dehao Chen de...@google.com PR middle-end/54645 * include/line-map.h (location_adhoc_data): Move location_adhoc_data into GC. (location_adhoc_data_map): Likewise. (line_maps): Likewise. (rebuild_location_adhoc_htab): New Function. * line-map.c (+rebuild_location_adhoc_htab): new Funcion. (get_combined_adhoc_loc): Move location_adhoc_data into GC. (location_adhoc_data_fini): Likewise. (linemap_init): Likewise. (location_adhoc_data_init): Remove Function. gcc/ChangeLog: 2012-09-21 Dehao Chen de...@google.com PR middle-end/54645 * c-family/c-pch.c (c_common_read_pch): Rebuild the location_adhoc_data map when read in the pch. I can't say anything insightful about this patch other than the nitpick below (i.e. I see nothing wrong with it) but I'd encourage a proper review of it to resolve the PCH regressions. There's no PCH section in MAINTAINERS, but next-of-kin global maintainers CC:ed. IMHO the PCH implementation is awkward and that is enough of a reason to remove PCH in its current form. Richard. I have just a nitpicking remark: please break the overlong lines. I noticed the ones with htab_create calls as my viewer helpfully broke the lines at 80 columns at the last comma. brgds, H-P
Re: [PATCH] rs6000: Fix ne0 patterns (PR51274)
PR target/51274 Also: PR target/53087
RE: [Updated]: [PATCH GCC/ARM] Fix problem that hardreg_cprop opportunities are missed on thumb1
-Original Message-
From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
Sent: Wednesday, September 05, 2012 6:09 AM
To: Bin Cheng
Cc: Ramana Radhakrishnan; 'Eric Botcazou'; gcc-patches@gcc.gnu.org
Subject: Re: Ping: [PATCH GCC/ARM] Fix problem that hardreg_cprop
opportunities are missed on thumb1
Subtraction of zero isn't canonical rtl though. Passes after peephole2
would
be well within their rights to simplify the expression back to a move.
From that point of view, making the passes recognise (plus X 0) and (minus
X 0)
as special cases would be inconsistent.
Rather than make the Thumb 1 CC usage implicit in the rtl stream, and
carry
the current state around in cfun-machine, it seems like it would be
better to
get md_reorg to rewrite the instructions into a form that makes the use of
condition codes explicit.
md_reorg also sounds like a better place in the pipeline than peephole2 to
be
doing this kind of transformation, although I admit I have zero evidence
to
back that up...
Hi Richard,
This is the updated patch according to your suggestions. I removed the
peephole2 patterns and introduced function thumb1_reorg to rewrite
instructions in md_reorg pass.
In addition to missed propagation, this patch also detects following case:
mov r5, r0
str r0, [r4] ---miscellaneous irrelevant instructions
[cmp r0, 0]---saved
bne .Lxxx
Patch tested on arm-none-eabi/cortex-m0, no regressions introduced.
Is it OK?
Thanks.
2012-09-25 Bin Cheng bin.ch...@arm.com
* config/arm/arm.c (thumb1_reorg): New function.
(arm_reorg): Call thumb1_reorg.
(thumb1_final_prescan_insn): Record src operand in thumb1_cc_op0.
* config/arm/arm.md : Remove peephole2 patterns which rewrites move
into subtract of ZERO.
Index: gcc/config/arm/arm.c
===
--- gcc/config/arm/arm.c(revision 191088)
+++ gcc/config/arm/arm.c(working copy)
@@ -13263,6 +13263,62 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT ad
return;
}
+/* Rewrite move insn into subtract of 0 if the condition codes will
+ be useful in next conditional jump insn. */
+
+static void
+thumb1_reorg (void)
+{
+ basic_block bb;
+
+ FOR_EACH_BB (bb)
+{
+ rtx set, dest, src;
+ rtx pat, op0;
+ rtx prev, insn = BB_END (bb);
+
+ while (insn != BB_HEAD (bb) DEBUG_INSN_P (insn))
+ insn = PREV_INSN (insn);
+
+ /* Find the last cbranchsi4_insn in basic block BB. */
+ if (INSN_CODE (insn) != CODE_FOR_cbranchsi4_insn)
+ continue;
+
+ /* Find the first non-note insn before INSN in basic block BB. */
+ gcc_assert (insn != BB_HEAD (bb));
+ prev = PREV_INSN (insn);
+ while (prev != BB_HEAD (bb) (NOTE_P (prev) || DEBUG_INSN_P (prev)))
+ prev = PREV_INSN (prev);
+
+ set = single_set (prev);
+ if (!set)
+ continue;
+
+ dest = SET_DEST (set);
+ src = SET_SRC (set);
+ if (!low_register_operand (dest, SImode)
+ || !low_register_operand (src, SImode))
+ continue;
+
+ pat = PATTERN (insn);
+ op0 = XEXP (XEXP (SET_SRC (pat), 0), 0);
+ /* Rewrite move into subtract of 0 if its operand is compared with ZERO
+in INSN. Don't need to check dest since cprop_hardreg pass propagates
+src into INSN. */
+ if (REGNO (op0) == REGNO (src))
+ {
+ dest = copy_rtx (dest);
+ src = copy_rtx (src);
+ src = gen_rtx_MINUS (SImode, src, const0_rtx);
+ PATTERN (prev) = gen_rtx_SET (VOIDmode, dest, src);
+ INSN_CODE (prev) = -1;
+ /* Set test register in INSN to dest. */
+ XEXP (XEXP (SET_SRC (pat), 0), 0) = copy_rtx (dest);
+ INSN_CODE (insn) = -1;
+ }
+}
+}
+
/* Convert instructions to their cc-clobbering variant if possible, since
that allows us to use smaller encodings. */
@@ -13459,7 +13515,9 @@ arm_reorg (void)
HOST_WIDE_INT address = 0;
Mfix * fix;
- if (TARGET_THUMB2)
+ if (TARGET_THUMB1)
+thumb1_reorg ();
+ else if (TARGET_THUMB2)
thumb2_reorg ();
/* Ensure all insns that must be split have been split at this point.
@@ -21736,6 +21794,12 @@ thumb1_final_prescan_insn (rtx insn)
if (src1 == const0_rtx)
cfun-machine-thumb1_cc_mode = CCmode;
}
+ else if (REG_P (SET_DEST (set)) REG_P (SET_SRC (set)))
+ {
+ /* Record the src register operand instead of dest because
+cprop_hardreg pass propagates src. */
+ cfun-machine-thumb1_cc_op0 = SET_SRC (set);
+ }
}
else if (conds != CONDS_NOCOND)
cfun-machine-thumb1_cc_insn = NULL_RTX;
Index: gcc/config/arm/arm.md
===
--- gcc/config/arm/arm.md (revision 191088)
+++ gcc/config/arm/arm.md (working copy)
@@
Re: PING Re: [PATCH, MIPS] add new peephole for 74k dspr2
Maciej W. Rozycki ma...@codesourcery.com writes: On Mon, 24 Sep 2012, Richard Sandiford wrote: From the context I am assuming none of this matters for the 74K (and presumably the 24KE/34K) and a MULT $0, $0 is indeed faster, but overall isn't it something that should be decided based on instruction costs from DFA schedulers? Is there anything that I've missed here? It doesn't appear to me your (and neither the original) proposal takes instruction cost calculation into consideration. In practice, we only move 0 into HI and LO for MADD- and MSUB-style operations. We deliberately don't use HI and LO as scratch space. I think it's a reasonable default assumption that anything that supports those instructions also has a fast path from MULT to MADD or MULT to MSUB. According to my sources the R4650 has a 4-cycle MULT latency (MAD is 3-4 cycles on that processor). An MTHI/MTLO pair will take 2 cycles; obviously the resulting larger code may adversely affect cache performance in some scenarios. That's not how the 4650 DFA models it though. (define_insn_reservation generic_hilo 1 (eq_attr type mfhi,mflo,mthi,mtlo) imuldiv*3) (define_insn_reservation r4650_imul 4 (and (eq_attr cpu r4650) (eq_attr type imul,imul3,imadd)) imuldiv*4) So if we believed the DFA, MTLO + MTHI would occupy the muldiv unit for 6 rather than 4 cycles. Any attempt to use the DFA would still favour MULT. Richard
[SH] PR 54089 - More rotcr, rotl, rotr
Hello,
This patch does some further improvements to the utilization of rotate
insns on SH. Tested on rev 191657 with
make -k check RUNTESTFLAGS=--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}
and no new failures.
OK?
(BTW, comparing test summaries of rev. 191342 and rev. 191657 shows a
lot of new PCH related failures on my xgcc SH setup)
Cheers,
Oleg
gcc/ChangeLog:
PR target/54089
* config/sh/constraints.md (Jhb): New constraint.
* config/sh/predicates.md (negt_reg_shl31_operand): New
predicate.
* config/sh/sh.md (rotrsi3): New expander.
(rotrsi3_1, *rotrsi3_1, *rotlsi3_1): New insns.
(rotlsi3, rotlhi3): Use const_int_operand predicate instead of
immediate_operand and remove CONST_INT_P checks in expansion
code.
(*rotcr): Cleanup variable usage. Handle preceding nott insn.
Add split with swapped operands.
(*rotcr_neg_t, *movt_msb, *negt_msb): New insns and splits.
testsuite/ChangeLog:
PR target/54089
* gcc.target/sh/pr54089-1.c (test_15, test_16, test_17, test_18,
test_19, test_20, test_21, test_22, test_23): New functions.
* gcc.target/sh/pr54089-4.c: New.
* gcc.target/sh/pr54089-5.c: New.
* gcc.target/sh/pr54089-6.c: New.
* gcc.target/sh/pr54089-7.c: New.
Index: gcc/testsuite/gcc.target/sh/pr54089-4.c
===
--- gcc/testsuite/gcc.target/sh/pr54089-4.c (revision 0)
+++ gcc/testsuite/gcc.target/sh/pr54089-4.c (revision 0)
@@ -0,0 +1,15 @@
+/* Check that the rotcr instruction is generated when shifting the
+ negated T bit on non-SH2A. */
+/* { dg-do compile { target sh*-*-* } } */
+/* { dg-options -O1 } */
+/* { dg-skip-if { sh*-*-* } { -m5* -m2a* } { } } */
+/* { dg-final { scan-assembler-times rotcr 1 } } */
+/* { dg-final { scan-assembler-times tst 1 } } */
+/* { dg-final { scan-assembler-times movt 1 } } */
+
+int
+test_00 (int a, int b)
+{
+ int r = a != b;
+ return r 31;
+}
Index: gcc/testsuite/gcc.target/sh/pr54089-6.c
===
--- gcc/testsuite/gcc.target/sh/pr54089-6.c (revision 0)
+++ gcc/testsuite/gcc.target/sh/pr54089-6.c (revision 0)
@@ -0,0 +1,30 @@
+/* Check that the rotr and rotl instructions are generated. */
+/* { dg-do compile { target sh*-*-* } } */
+/* { dg-options -O1 } */
+/* { dg-skip-if { sh*-*-* } { -m5* } { } } */
+/* { dg-final { scan-assembler-times rotr 2 } } */
+/* { dg-final { scan-assembler-times rotl 2 } } */
+
+int
+test_00 (int a)
+{
+ return (a 1) | ((a 31) 1);
+}
+
+int
+test_01 (int a)
+{
+ return (a 1) | ((unsigned int)a 31);
+}
+
+int
+test_02 (int a)
+{
+ return ((unsigned int)a 1) | (a 31);
+}
+
+int
+test_03 (int a)
+{
+ return ((a 1) 0x7FFF) | (a 31);
+}
Index: gcc/testsuite/gcc.target/sh/pr54089-1.c
===
--- gcc/testsuite/gcc.target/sh/pr54089-1.c (revision 191657)
+++ gcc/testsuite/gcc.target/sh/pr54089-1.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-do compile { target sh*-*-* } } */
/* { dg-options -O1 } */
/* { dg-skip-if { sh*-*-* } { -m5*} { } } */
-/* { dg-final { scan-assembler-times rotcr 15 } } */
+/* { dg-final { scan-assembler-times rotcr 24 } } */
/* { dg-final { scan-assembler-times shll\t 1 } } */
typedef char bool;
@@ -109,3 +109,66 @@
bool r = b 0;
return ((a 1) | (r 31));
}
+
+unsigned int
+test_15 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 1) | (r 31));
+}
+
+unsigned int
+test_16 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 2) | (r 31));
+}
+
+unsigned int
+test_17 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 3) | (r 31));
+}
+
+unsigned int
+test_18 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 4) | (r 31));
+}
+
+unsigned int
+test_19 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 5) | (r 31));
+}
+
+unsigned int
+test_20 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 6) | (r 31));
+}
+
+unsigned int
+test_21 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 7) | (r 31));
+}
+
+unsigned int
+test_22 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 8) | (r 31));
+}
+
+unsigned int
+test_23 (unsigned int a, int b, int c)
+{
+ bool r = b != c;
+ return ((a 31) | (r 31));
+}
Index: gcc/testsuite/gcc.target/sh/pr54089-5.c
===
--- gcc/testsuite/gcc.target/sh/pr54089-5.c (revision 0)
+++ gcc/testsuite/gcc.target/sh/pr54089-5.c (revision 0)
@@ -0,0 +1,14 @@
+/* Check that the movrt rotr instruction sequence is generated when shifting
+ the negated T bit on SH2A. */
+/* { dg-do compile { target sh*-*-* } } */
+/* { dg-options -O1 } */
+/* { dg-skip-if { sh*-*-* } { * }
Re: PING Re: [PATCH, MIPS] add new peephole for 74k dspr2
Richard Sandiford rdsandif...@googlemail.com writes: Maciej W. Rozycki ma...@codesourcery.com writes: On Mon, 24 Sep 2012, Richard Sandiford wrote: From the context I am assuming none of this matters for the 74K (and presumably the 24KE/34K) and a MULT $0, $0 is indeed faster, but overall isn't it something that should be decided based on instruction costs from DFA schedulers? Is there anything that I've missed here? It doesn't appear to me your (and neither the original) proposal takes instruction cost calculation into consideration. In practice, we only move 0 into HI and LO for MADD- and MSUB-style operations. We deliberately don't use HI and LO as scratch space. I think it's a reasonable default assumption that anything that supports those instructions also has a fast path from MULT to MADD or MULT to MSUB. According to my sources the R4650 has a 4-cycle MULT latency (MAD is 3-4 cycles on that processor). An MTHI/MTLO pair will take 2 cycles; obviously the resulting larger code may adversely affect cache performance in some scenarios. That's not how the 4650 DFA models it though. (define_insn_reservation generic_hilo 1 (eq_attr type mfhi,mflo,mthi,mtlo) imuldiv*3) (define_insn_reservation r4650_imul 4 (and (eq_attr cpu r4650) (eq_attr type imul,imul3,imadd)) imuldiv*4) So if we believed the DFA, MTLO + MTHI would occupy the muldiv unit for 6 rather than 4 cycles. Any attempt to use the DFA would still favour MULT. Although I see the 4kp with its 32-cycle MULTs and MADDs is one where MULT $0,$0 would be a really bad choice. Sigh. The amount of effort required for this optimisation is getting a bit ridiculous. Richard
Re: [SH] PR 54089 - More rotcr, rotl, rotr
Oleg Endo oleg.e...@t-online.de wrote:
This patch does some further improvements to the utilization of rotate
insns on SH. Tested on rev 191657 with
make -k check RUNTESTFLAGS=--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}
and no new failures.
OK?
OK.
(BTW, comparing test summaries of rev. 191342 and rev. 191657 shows a
lot of new PCH related failures on my xgcc SH setup)
Looks not only for SH. Even for i686-pc-linux-gnu. See
http://gcc.gnu.org/ml/gcc-testresults/2012-09/msg02508.html
for example.
Regards,
kaz
New German PO file for 'gcc' (version 4.7.2)
Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the German team of translators. The file is available at: http://translationproject.org/latest/gcc/de.po (This file, 'gcc-4.7.2.de.po', has just now been sent to you in a separate email.) All other PO files for your package are available in: http://translationproject.org/latest/gcc/ Please consider including all of these in your next release, whether official or a pretest. Whenever you have a new distribution with a new version number ready, containing a newer POT file, please send the URL of that distribution tarball to the address below. The tarball may be just a pretest or a snapshot, it does not even have to compile. It is just used by the translators when they need some extra translation context. The following HTML page has been updated: http://translationproject.org/domain/gcc.html If any question arises, please contact the translation coordinator. Thank you for all your work, The Translation Project robot, in the name of your translation coordinator. coordina...@translationproject.org
Re: [Patch] catch builtin_bswap16 construct
On 25 September 2012 07:00, Segher Boessenkool
seg...@kernel.crashing.org wrote:
Christophe, it looks like the zero-extend in the unsigned case is not
needed on any target? Assuming the shifts are at least SImode, of
course (I'm too lazy to check, sorry).
It's also present when compiling:
unsigned short swapu16(unsigned short x) {
return __builtin_bswap16(x);
}
so it's not directly caused by my patch I think.
We have to look at the __builtin_bswap16 expansion with an unsigned argument.
Christophe.
[C++ Patch] PR 54526
Hi,
if I understand correctly, in C++11 mode we should simply accept what we
used to accept only with -fpermissive.
Tested x86_64-linux.
Thanks,
Paolo.
//
/cp
2012-09-25 Paolo Carlini paolo.carl...@oracle.com
PR c++/54526
* parser.c (cp_parser_template_id): In C++11 mode simply accept
X::A.
/testsuite
2012-09-25 Paolo Carlini paolo.carl...@oracle.com
PR c++/54526
* g++.dg/cpp0x/parse2.C: New.
* g++.dg/parse/error11.C: Adjust.
* g++.dg/parse/error12.C: Likewise.
Index: cp/parser.c
===
--- cp/parser.c (revision 191695)
+++ cp/parser.c (working copy)
@@ -12479,9 +12479,11 @@ cp_parser_template_id (cp_parser *parser,
return error_mark_node;
}
/* Otherwise, emit an error about the invalid digraph, but continue
-parsing because we got our argument list. */
- if (permerror (next_token-location,
-%::% cannot begin a template-argument list))
+parsing because we got our argument list. In C++11 do not emit
+any error, per 2.5/3. */
+ if (cxx_dialect cxx0x
+ permerror (next_token-location,
+ %::% cannot begin a template-argument list))
{
static bool hint = false;
inform (next_token-location,
Index: testsuite/g++.dg/parse/error11.C
===
--- testsuite/g++.dg/parse/error11.C(revision 191695)
+++ testsuite/g++.dg/parse/error11.C(working copy)
@@ -16,22 +16,22 @@ struct Foo
};
void method(void) {
-typename Foo::B::template Nested::B n; // { dg-error 17:'::' cannot
begin 17-begin }
-// { dg-message 17:':' is an alternate spelling 17-alt { target *-*-* }
19 }
-// { dg-error 39:'::' cannot begin 39-begin { target *-*-* } 19 }
-// { dg-message 39:':' is an alternate spelling 39-alt { target *-*-* }
19 }
+typename Foo::B::template Nested::B n; // { dg-error 17:'::' cannot
begin 17-begin { target c++98 } }
+// { dg-message 17:':' is an alternate spelling 17-alt { target c++98 }
19 }
+// { dg-error 39:'::' cannot begin 39-begin { target c++98 } 19 }
+// { dg-message 39:':' is an alternate spelling 39-alt { target c++98 }
19 }
n.template NestedB::method();
-n.template Nested::B::method(); // { dg-error 22:'::' cannot begin
error }
-// { dg-message 22:':' is an alternate note { target *-*-* } 24 }
+n.template Nested::B::method(); // { dg-error 22:'::' cannot begin
error { target c++98 } }
+// { dg-message 22:':' is an alternate note { target c++98 } 24 }
NestedB::method();
-Nested::B::method(); // { dg-error 11:'::' cannot begin error }
-// { dg-message 11:':' is an alternate note { target *-*-* } 27 }
+Nested::B::method(); // { dg-error 11:'::' cannot begin error {
target c++98 } }
+// { dg-message 11:':' is an alternate note { target c++98 } 27 }
}
};
template int N struct Foo2 {};
-template struct Foo2::B; // { dg-error 21:'::' cannot begin begin }
-// { dg-message 21:':' is an alternate alt { target *-*-* } 33 }
+template struct Foo2::B; // { dg-error 21:'::' cannot begin begin {
target c++98 } }
+// { dg-message 21:':' is an alternate alt { target c++98 } 33 }
// { dg-message 25:type/value mismatch mismatch { target *-*-* } 33 }
// { dg-error 25:expected a constant const { target *-*-* } 33 }
@@ -39,11 +39,11 @@ int value = 0;
void func(void)
{
- Foo::B f; // { dg-error cannot begin begin }
-// { dg-message alternate spelling alt { target *-*-* } 42 }
+ Foo::B f; // { dg-error cannot begin begin { target c++98 } }
+// { dg-message alternate spelling alt { target c++98 } 42 }
f.FooB::method();
- f.Foo::B::method(); // { dg-error 8:cannot begin begin }
-// { dg-message 8:alternate spelling alt { target *-*-* } 45 }
+ f.Foo::B::method(); // { dg-error 8:cannot begin begin { target c++98
} }
+// { dg-message 8:alternate spelling alt { target c++98 } 45 }
// Check cases where we the token sequence is the correct one, but there
// was no digraph or whitespaces in the middle, so we should not emit
@@ -63,9 +63,9 @@ void func(void)
Foo[::value] = 0;
}
-template struct Foo::B; // { dg-error 20:'::' cannot begin begin }
-// { dg-message 20:is an alternate alt { target *-*-* } 66 }
+template struct Foo::B; // { dg-error 20:'::' cannot begin begin {
target c++98 } }
+// { dg-message 20:is an alternate alt { target c++98 } 66 }
// On the first error message, an additional note about the use of
// -fpermissive should be present
-// { dg-message 17:\\(if you use '-fpermissive' G\\+\\+ will accept your
code\\) -fpermissive { target *-*-* } 19 }
+// { dg-message 17:\\(if you use '-fpermissive' G\\+\\+ will accept your
code\\) -fpermissive { target c++98 } 19 }
Index: testsuite/g++.dg/parse/error12.C
===
---
Re: Rewrite lto-symtab to work on symbol table
On Mon, Sep 24, 2012 at 6:10 PM, H.J. Lu hjl.to...@gmail.com wrote:
On Mon, Sep 24, 2012 at 8:50 AM, Martin Jambor mjam...@suse.cz wrote:
Hi,
On Tue, Sep 18, 2012 at 03:35:45PM +0200, Jan Hubicka wrote:
Hi,
this patch reorganize lto-symtab to work across symtab's symbol table
instead
of building its own. This simplifies things a bit and with the previous
changes it is rather straighforward - i.e. replace all uses of
lto_symtab_entry_t by symtab_node.
There are few differences in between the symtab as built by lto-symtab and
our symbol table. In one direction the declarations that are not going to
be
output to final assembly (i.e. are used by debug info and such) are not in
symbol table and consequentely they no longer get merged. I think this is
fine.
Other difference is that symbol table contains some symbols that are not
really
symbols in classical definition - such as inline clones or functions held in
table only for purposes of materialization. I added symtab_real_symbol_p
predicate for this. It would make more sense to exclude those from the
assembler name hash and drop checks I added to lto-symtab.c. I plan to
work on
this incrementally - it is not completely trivial. The symbol can become
non-real in several ways and it will need bit of work to get this
consistent.
Bootstrapped/regtested x86_64-linux, tested by building Mozilla, Qt and
other
stuff with LTO. OK?
Honza
* symtab.c (insert_to_assembler_name_hash): Do not insert
register vars.
(unlink_from_assembler_name_hash): NULL out pointers of unlinked
var.
(symtab_prevail_in_asm_name_hash): New.
(symtab_initialize_asm_name_hash): Break out from ...
(symtab_node_for_asm): ... here.
(dump_symtab_base): Dump LTO file data.
(verify_symtab_base): Register vars are not in symtab.
* cgraph.h (symtab_initialize_asm_name_hash,
symtab_prevail_in_asm_name_hash): New functions.
(symtab_real_symbol_p): New inline.
* lto-symtab.c: Do not include gt-lto-symtab.h.
(lto_symtab_entry_def): Remove.
(lto_symtab_entry_t): Remove.
(lto_symtab_identifiers): Remove.
(lto_symtab_free): Remove.
(lto_symtab_entry_hash): Remove.
(lto_symtab_entry_eq): Remove.
(lto_symtab_entry_marked_p): Remove.
(lto_symtab_maybe_init_hash_table): Remove.
(resolution_guessed_p, set_resolution_guessed): New functions.
(lto_symtab_register_decl): Only set resolution info.
(lto_symtab_get, lto_symtab_get_resolution): Remove.
(lto_symtab_merge): Reorg to work across symtab; do nothing if decls
are same.
(lto_symtab_resolve_replaceable_p): Reorg to work on symtab.
(lto_symtab_resolve_can_prevail_p): Likewise; only real symbols can
prevail.
(lto_symtab_resolve_symbols): Reorg to work on symtab.
(lto_symtab_merge_decls_2): Likewise.
(lto_symtab_merge_decls_1): Likewise; add debug dumps.
(lto_symtab_merge_decls): Likewise; do not merge at ltrans stage.
(lto_symtab_merge_cgraph_nodes_1): Reorg to work on symtab.
(lto_symtab_merge_cgraph_nodes): Likewise; do not merge at ltrans
stage.
(lto_symtab_prevailing_decl): Rewrite to lookup into symtab.
* lto-streaer.h (lto_symtab_free): Remove.
* lto-cgraph.c (add_references): Cleanup.
* varpool.c (varpool_assemble_decl): Skip hard regs.
* lto.c (lto_materialize_function): Update confused comment.
(read_cgraph_and_symbols): Do not free symtab.
Unfortunately, this patch breaks SPEC2006 povray LTO build for me.
I'm getting:
In file included from :168:0:
lighting.cpp: In function 'InitMallocPools':
lighting.cpp:5971:13: error: address taken, but ADDRESSABLE bit not set
static void InitMallocPools(void)
^
PHI argument
Frame.Number_Of_Light_Sources;
for PHI node
_191 = PHI Frame.Number_Of_Light_Sources(100), D.7040(101)
lighting.cpp:5971:13: internal compiler error: verify_ssa failed
I'm currently a bit too busy to try to reduce this, I hope you'll be
able to reproduce the issue yourself easily though. If not, ping me
on IRC.
Thanks,
Many of SPEC CPU 2K/2006 benchmarks failed with LTO:
http://gcc.gnu.org/ml/gcc-regression/2012-09/msg00419.html
http://gcc.gnu.org/ml/gcc-regression/2012-09/msg00392.html
Maybe
Index: lto-symtab.c
===
--- lto-symtab.c(revision 191694)
+++ lto-symtab.c(working copy)
@@ -566,7 +566,7 @@ lto_symtab_merge_decls_1 (symtab_node fi
/* Merge the chain to the single prevailing decl and diagnose
mismatches. */
- lto_symtab_merge_decls_2 (first, diagnosed_p);
+ lto_symtab_merge_decls_2 (prevailing, diagnosed_p);
if (cgraph_dump_file)
{
will fix it.
--
H.J.
[PATCH] Fix up CFLAGS/CXXFLAGS gcc/configure adjustment (PR other/54692)
Hi! On Thu, Sep 13, 2012 at 06:24:14PM +0200, Paolo Bonzini wrote: Il 13/09/2012 17:57, Jakub Jelinek ha scritto: Can we get this change in? The current state is terribly annoying. Yes, please go ahead. Here it is, bootstrapped/regtested on x86_64-linux and i686-linux, additionally tested on --disable-bootstrap tree, both by make cc1 inside of gcc subdir (no -O2) and make all-gcc above it (with -O2). Ok. Seems the sed command was using * at the end, so it happily changed e.g. -Og into just g instead of either keeping -Og in, or removing it altogether. This patches fixes it, now -Ofast, -Og, -Os, -O, -O[0-9]* are removed when followed by whitespace and not otherwise. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2012-09-25 Jakub Jelinek ja...@redhat.com PR other/54692 * configure.ac (CFLAGS, CXXFLAGS): Remove -Ofast or -Og properly. * configure: Regenerated. --- gcc/configure.ac.jj 2012-09-13 18:29:46.0 +0200 +++ gcc/configure.ac2012-09-24 21:47:41.606278259 +0200 @@ -296,8 +296,8 @@ AC_SUBST(OUTPUT_OPTION) # optimizations to be activated explicitly by the toplevel. case $CC in */prev-gcc/xgcc*) ;; - *) CFLAGS=`echo $CFLAGS | sed s/-O[[s0-9]]* *// ` - CXXFLAGS=`echo $CXXFLAGS | sed s/-O[[s0-9]]* *// ` ;; + *) CFLAGS=`echo $CFLAGS | sed -e s/-Ofast[[ ]]// -e s/-O[[gs]][[ ]]// -e s/-O[[0-9]]*[[]]// ` + CXXFLAGS=`echo $CXXFLAGS | sed -e s/-Ofast[[ ]]// -e s/-O[[gs]][[ ]]// -e s/-O[[0-9]]*[[]]// ` ;; esac AC_SUBST(CFLAGS) AC_SUBST(CXXFLAGS) --- gcc/configure.jj2012-09-17 11:13:13.119075354 +0200 +++ gcc/configure 2012-09-24 21:49:02.900837573 +0200 @@ -4863,8 +4863,8 @@ fi # optimizations to be activated explicitly by the toplevel. case $CC in */prev-gcc/xgcc*) ;; - *) CFLAGS=`echo $CFLAGS | sed s/-O[s0-9]* *// ` - CXXFLAGS=`echo $CXXFLAGS | sed s/-O[s0-9]* *// ` ;; + *) CFLAGS=`echo $CFLAGS | sed -e s/-Ofast[ ]// -e s/-O[gs][ ]// -e s/-O[0-9]*[]// ` + CXXFLAGS=`echo $CXXFLAGS | sed -e s/-Ofast[ ]// -e s/-O[gs][ ]// -e s/-O[0-9]*[]// ` ;; esac Jakub
[PATCH] Fix lto-bootstrap issue (one of them)
The following fixes the TREE_ADDRESSABLE issue during LTO bootstrap.
We fail to merge all symbols because 'first' may no longer be 'first'.
Committed as obvious. LTO bootstrap is still broken for me:
/tmp/ccXpATTw.ltrans19.ltrans.o: In function `is_ctor_or_dtor.17240':
ccXpATTw.ltrans19.o:(.text+0x133): undefined reference to `alloca'
ccXpATTw.ltrans19.o:(.text+0x147): undefined reference to `alloca'
/tmp/ccXpATTw.ltrans19.ltrans.o: In function `d_demangle_callback.17277':
ccXpATTw.ltrans19.o:(.text+0x1495): undefined reference to `alloca'
ccXpATTw.ltrans19.o:(.text+0x14b8): undefined reference to `alloca'
collect2: error: ld returned 1 exit status
I'll try updating binutils (but I don't see how alloca calls
should survive!? both of the above is for cp-demangle.c of libiberty).
Richard.
2012-09-25 Richard Guenther rguent...@suse.de
* lto-symtab.c (lto_symtab_merge_decls_1): Properly merge
all of the chain.
Index: gcc/lto-symtab.c
===
--- gcc/lto-symtab.c(revision 191696)
+++ gcc/lto-symtab.c(working copy)
@@ -566,12 +566,12 @@ lto_symtab_merge_decls_1 (symtab_node fi
/* Merge the chain to the single prevailing decl and diagnose
mismatches. */
- lto_symtab_merge_decls_2 (first, diagnosed_p);
+ lto_symtab_merge_decls_2 (prevailing, diagnosed_p);
if (cgraph_dump_file)
{
fprintf (cgraph_dump_file, After resolution:\n);
- for (e = first; e; e = e-symbol.next_sharing_asm_name)
+ for (e = prevailing; e; e = e-symbol.next_sharing_asm_name)
dump_symtab_node (cgraph_dump_file, e);
}
[PATCH] Fix VRP single-bit signed precision handling (PR tree-optimization/54676)
Hi!
This patch fixes two spots where signed 1-bit precision isn't handled
properly in VRP. With that type, build_int_cst (TREE_TYPE (min), 1)
will overflow and thus adding it to something or subtracting leads to
ICEs or bad code. In the first spot min is different from max, which
for 1-bit precision implies either all values, or none (but we don't have
empty ranges and fallback to varying for those anyway).
In the second case we can optimize if the anti range is singleton, then
the corresponding range is singleton too (the other value).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2012-09-25 Jakub Jelinek ja...@redhat.com
PR tree-optimization/54676
* tree-vrp.c (set_and_canonicalize_value_range): Handle
one bit precision properly.
* gcc.dg/pr54676.c: New test.
--- gcc/tree-vrp.c.jj 2012-09-17 11:13:12.0 +0200
+++ gcc/tree-vrp.c 2012-09-24 10:06:10.814376659 +0200
@@ -501,8 +501,19 @@ set_and_canonicalize_value_range (value_
to adjust them. */
if (tree_int_cst_lt (max, min))
{
- tree one = build_int_cst (TREE_TYPE (min), 1);
- tree tmp = int_const_binop (PLUS_EXPR, max, one);
+ tree one, tmp;
+
+ /* For one bit precision if max min, then the swapped
+range covers all values, so for VR_RANGE it is varying and
+for VR_ANTI_RANGE empty range, so drop to varying as well. */
+ if (TYPE_PRECISION (TREE_TYPE (min)) == 1)
+ {
+ set_value_range_to_varying (vr);
+ return;
+ }
+
+ one = build_int_cst (TREE_TYPE (min), 1);
+ tmp = int_const_binop (PLUS_EXPR, max, one);
max = int_const_binop (MINUS_EXPR, min, one);
min = tmp;
@@ -531,6 +542,24 @@ set_and_canonicalize_value_range (value_
set_value_range_to_varying (vr);
return;
}
+ else if (TYPE_PRECISION (TREE_TYPE (min)) == 1
+ !TYPE_UNSIGNED (TREE_TYPE (min))
+ (is_min || is_max))
+ {
+ /* For signed 1-bit precision, one is not in-range and
+thus adding/subtracting it would result in overflows. */
+ if (operand_equal_p (min, max, 0))
+ {
+ min = max = is_min ? vrp_val_max (TREE_TYPE (min))
+: vrp_val_min (TREE_TYPE (min));
+ t = VR_RANGE;
+ }
+ else
+ {
+ set_value_range_to_varying (vr);
+ return;
+ }
+ }
else if (is_min
/* As a special exception preserve non-null ranges. */
!(TYPE_UNSIGNED (TREE_TYPE (min))
--- gcc/testsuite/gcc.dg/pr54676.c.jj 2012-09-24 10:52:48.911691835 +0200
+++ gcc/testsuite/gcc.dg/pr54676.c 2012-09-24 10:52:30.0 +0200
@@ -0,0 +1,23 @@
+/* PR tree-optimization/54676 */
+/* { dg-do compile } */
+/* { dg-options -O -fno-tree-ccp -fno-tree-copy-prop -fno-tree-fre
-ftree-vrp } */
+
+struct S
+{
+ int s:1;
+};
+
+struct S bar (void);
+
+int a;
+
+void
+foo (int x)
+{
+ struct S s = bar ();
+ while (!a)
+{
+ int l = 94967295;
+ a = x || (s.s = l);
+}
+}
Jakub
Re: [PATCH] Fix up CFLAGS/CXXFLAGS gcc/configure adjustment (PR other/54692)
On Tue, Sep 25, 2012 at 1:19 PM, Jakub Jelinek ja...@redhat.com wrote: Hi! On Thu, Sep 13, 2012 at 06:24:14PM +0200, Paolo Bonzini wrote: Il 13/09/2012 17:57, Jakub Jelinek ha scritto: Can we get this change in? The current state is terribly annoying. Yes, please go ahead. Here it is, bootstrapped/regtested on x86_64-linux and i686-linux, additionally tested on --disable-bootstrap tree, both by make cc1 inside of gcc subdir (no -O2) and make all-gcc above it (with -O2). Ok. Seems the sed command was using * at the end, so it happily changed e.g. -Og into just g instead of either keeping -Og in, or removing it altogether. This patches fixes it, now -Ofast, -Og, -Os, -O, -O[0-9]* are removed when followed by whitespace and not otherwise. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Looks good to me. Thanks, Richard. 2012-09-25 Jakub Jelinek ja...@redhat.com PR other/54692 * configure.ac (CFLAGS, CXXFLAGS): Remove -Ofast or -Og properly. * configure: Regenerated. --- gcc/configure.ac.jj 2012-09-13 18:29:46.0 +0200 +++ gcc/configure.ac2012-09-24 21:47:41.606278259 +0200 @@ -296,8 +296,8 @@ AC_SUBST(OUTPUT_OPTION) # optimizations to be activated explicitly by the toplevel. case $CC in */prev-gcc/xgcc*) ;; - *) CFLAGS=`echo $CFLAGS | sed s/-O[[s0-9]]* *// ` - CXXFLAGS=`echo $CXXFLAGS | sed s/-O[[s0-9]]* *// ` ;; + *) CFLAGS=`echo $CFLAGS | sed -e s/-Ofast[[ ]]// -e s/-O[[gs]][[ ]]// -e s/-O[[0-9]]*[[]]// ` + CXXFLAGS=`echo $CXXFLAGS | sed -e s/-Ofast[[ ]]// -e s/-O[[gs]][[ ]]// -e s/-O[[0-9]]*[[]]// ` ;; esac AC_SUBST(CFLAGS) AC_SUBST(CXXFLAGS) --- gcc/configure.jj2012-09-17 11:13:13.119075354 +0200 +++ gcc/configure 2012-09-24 21:49:02.900837573 +0200 @@ -4863,8 +4863,8 @@ fi # optimizations to be activated explicitly by the toplevel. case $CC in */prev-gcc/xgcc*) ;; - *) CFLAGS=`echo $CFLAGS | sed s/-O[s0-9]* *// ` - CXXFLAGS=`echo $CXXFLAGS | sed s/-O[s0-9]* *// ` ;; + *) CFLAGS=`echo $CFLAGS | sed -e s/-Ofast[ ]// -e s/-O[gs][ ]// -e s/-O[0-9]*[]// ` + CXXFLAGS=`echo $CXXFLAGS | sed -e s/-Ofast[ ]// -e s/-O[gs][ ]// -e s/-O[0-9]*[]// ` ;; esac Jakub
Re: [Patch] catch builtin_bswap16 construct
Christophe, it looks like the zero-extend in the unsigned case is not
needed on any target? Assuming the shifts are at least SImode, of
course (I'm too lazy to check, sorry).
It's also present when compiling:
unsigned short swapu16(unsigned short x) {
return __builtin_bswap16(x);
}
so it's not directly caused by my patch I think.
The RTL is (set (reg:HI) (bswap:HI (reg:HI))) which then gets
extended for the SI (or DI) function return. Nothing to see here,
it's a target problem. Your results look good.
Segher
Re: [PATCH] Fix VRP single-bit signed precision handling (PR tree-optimization/54676)
On Tue, Sep 25, 2012 at 1:23 PM, Jakub Jelinek ja...@redhat.com wrote:
Hi!
This patch fixes two spots where signed 1-bit precision isn't handled
properly in VRP. With that type, build_int_cst (TREE_TYPE (min), 1)
will overflow and thus adding it to something or subtracting leads to
ICEs or bad code. In the first spot min is different from max, which
for 1-bit precision implies either all values, or none (but we don't have
empty ranges and fallback to varying for those anyway).
emty ranges are turned into VR_UNDEFINED in intersect_range for example
(but not consistently so I see, not in set_and_canonicalize_value_range
at least).
In the second case we can optimize if the anti range is singleton, then
the corresponding range is singleton too (the other value).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
Ok.
Thanks,
Richard.
2012-09-25 Jakub Jelinek ja...@redhat.com
PR tree-optimization/54676
* tree-vrp.c (set_and_canonicalize_value_range): Handle
one bit precision properly.
* gcc.dg/pr54676.c: New test.
--- gcc/tree-vrp.c.jj 2012-09-17 11:13:12.0 +0200
+++ gcc/tree-vrp.c 2012-09-24 10:06:10.814376659 +0200
@@ -501,8 +501,19 @@ set_and_canonicalize_value_range (value_
to adjust them. */
if (tree_int_cst_lt (max, min))
{
- tree one = build_int_cst (TREE_TYPE (min), 1);
- tree tmp = int_const_binop (PLUS_EXPR, max, one);
+ tree one, tmp;
+
+ /* For one bit precision if max min, then the swapped
+range covers all values, so for VR_RANGE it is varying and
+for VR_ANTI_RANGE empty range, so drop to varying as well. */
+ if (TYPE_PRECISION (TREE_TYPE (min)) == 1)
+ {
+ set_value_range_to_varying (vr);
+ return;
+ }
+
+ one = build_int_cst (TREE_TYPE (min), 1);
+ tmp = int_const_binop (PLUS_EXPR, max, one);
max = int_const_binop (MINUS_EXPR, min, one);
min = tmp;
@@ -531,6 +542,24 @@ set_and_canonicalize_value_range (value_
set_value_range_to_varying (vr);
return;
}
+ else if (TYPE_PRECISION (TREE_TYPE (min)) == 1
+ !TYPE_UNSIGNED (TREE_TYPE (min))
+ (is_min || is_max))
+ {
+ /* For signed 1-bit precision, one is not in-range and
+thus adding/subtracting it would result in overflows. */
+ if (operand_equal_p (min, max, 0))
+ {
+ min = max = is_min ? vrp_val_max (TREE_TYPE (min))
+: vrp_val_min (TREE_TYPE (min));
+ t = VR_RANGE;
+ }
+ else
+ {
+ set_value_range_to_varying (vr);
+ return;
+ }
+ }
else if (is_min
/* As a special exception preserve non-null ranges. */
!(TYPE_UNSIGNED (TREE_TYPE (min))
--- gcc/testsuite/gcc.dg/pr54676.c.jj 2012-09-24 10:52:48.911691835 +0200
+++ gcc/testsuite/gcc.dg/pr54676.c 2012-09-24 10:52:30.0 +0200
@@ -0,0 +1,23 @@
+/* PR tree-optimization/54676 */
+/* { dg-do compile } */
+/* { dg-options -O -fno-tree-ccp -fno-tree-copy-prop -fno-tree-fre
-ftree-vrp } */
+
+struct S
+{
+ int s:1;
+};
+
+struct S bar (void);
+
+int a;
+
+void
+foo (int x)
+{
+ struct S s = bar ();
+ while (!a)
+{
+ int l = 94967295;
+ a = x || (s.s = l);
+}
+}
Jakub
Re: [PATCH] PR c++/54372 - unused attribute inactive on dependant entities
Jason Merrill ja...@redhat.com writes:
On 09/20/2012 10:01 AM, Dodji Seketeli wrote:
This is because in cplus_decl_attributes, save_template_attributes
makes so that the 'unused' attribute is applied to its appertaining
entity only at instantiation time. But then at parsing time
maybe_warn_unused_local_typedefs checks for TREE_USED before warning.
I guess we should propagate TREE_USED when instantiating a typedef.
As we discussed on IRC, this will not really help, as what we want is to
be able to take advantage of the attribute at compile time.
Rather, the patch below makes is_late_template_attribute the unused
attribute be applied directly, as you suggested.
Tested on x86_64-unknown-linux-gnu against trunk.
---
gcc/cp/decl2.c | 5
.../c-c++-common/Wunused-local-typedefs-2.c| 35 ++
2 files changed, 40 insertions(+)
create mode 100644 gcc/testsuite/c-c++-common/Wunused-local-typedefs-2.c
diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c
index 0df4613..a590d17 100644
--- a/gcc/cp/decl2.c
+++ b/gcc/cp/decl2.c
@@ -1104,6 +1104,11 @@ is_late_template_attribute (tree attr, tree decl)
if (is_attribute_p (weak, name))
return true;
+ /* Attribute unused is applied directly, as it appertains to
+ decls. */
+ if (is_attribute_p (unused, name))
+return false;
+
/* If any of the arguments are dependent expressions, we can't evaluate
the attribute until instantiation time. */
for (arg = args; arg; arg = TREE_CHAIN (arg))
diff --git a/gcc/testsuite/c-c++-common/Wunused-local-typedefs-2.c
b/gcc/testsuite/c-c++-common/Wunused-local-typedefs-2.c
new file mode 100644
index 000..77bacd7
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Wunused-local-typedefs-2.c
@@ -0,0 +1,35 @@
+/* Origin PR c++/54372
+{ dg-options -Wunused-local-typedefs }
+{ dg-do compile }
+*/
+
+template typename T
+void f2()
+{
+typedef T t __attribute__((unused));
+}
+
+class S
+{
+template typename T
+void f4()
+{
+ typedef T t __attribute__((unused));
+}
+};
+
+template typename T
+class tS
+{
+void f()
+{
+ typedef T t2 __attribute__((unused));
+}
+
+template typename U
+void f2()
+{
+ typedef T t1 __attribute__((unused));
+ typedef U t2 __attribute__((unused));
+}
+};
--
Dodji
Re: [PR54551] global dead debug pseudo tracking in fast-dce
On Sun, Sep 23, 2012 at 07:59:37AM -0300, Alexandre Oliva wrote:
This patch introduces a global mode of dead_debug tracking for use in
fast DCE. If a debug use reaches the top of a basic block before
finding its death point, the pending and subsequent uses of the pseudo
in debug insns will all be substituted with the same debug temp, and
death points will get the value bound to the debug temp.
Thanks for working on this. The patch generally looks good, just some minor
nits below.
If it turns out to be too expensive to do global dead debug tracking in
every fast DCE, we could limit it to the first one via some new DF flag.
* df-problems.c: Adjust.
I think you should list here what functions you've changed.
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
...
+static bool
+dead_debug_global_replace_temp (struct dead_debug_global *global,
+ df_ref use, unsigned int uregno,
+ bitmap *pto_rescan)
+{
+ if (!global || uregno FIRST_PSEUDO_REGISTER
+ || !global-used
+ || !bitmap_bit_p (global-used, uregno))
+return false;
+
+ gcc_checking_assert (REGNO (*DF_REF_REAL_LOC (use)) == uregno);
+
+ dead_debug_global_entry *entry
+= dead_debug_global_find (global, *DF_REF_REAL_LOC (use));
+ gcc_checking_assert (GET_CODE (entry-reg) == REG
+ REGNO (entry-reg) == uregno);
I think just for safety you should here:
if (GET_MODE (*DF_REF_REAL_LOC (use)) != GET_MODE (entry-reg))
return false;
(the other alternative would be to use mode in the hash function etc.,
but if usually the same pseudo has the same mode everywhere, then the above
should be good enough).
+static void
+dead_debug_promote_uses (struct dead_debug_local *debug)
+{
+ for (struct dead_debug_use *head = debug-head, **headp = debug-head;
+ head; head = *headp)
+{
+ rtx reg = *DF_REF_REAL_LOC (head-use);
+
+ if (GET_CODE (reg) != REG
+ || REGNO (reg) FIRST_PSEUDO_REGISTER)
+ {
+ headp = head-next;
+ continue;
+ }
+
+ if (!debug-global-used)
+ debug-global-used = BITMAP_ALLOC (NULL);
+
+ if (bitmap_set_bit (debug-global-used, REGNO (reg)))
+ dead_debug_global_insert (debug-global, reg,
+ make_debug_expr_from_rtl (reg));
+
+ dead_debug_global_replace_temp (debug-global, head-use, REGNO (reg),
+ debug-to_rescan);
Here you are ignoring the return value from dead_debug_global_replace_temp.
IMHO you should just do what you do a few lines above if it returns false,
something like
if (!dead_debug_global_replace_temp (debug-global, head-use, REGNO (reg),
debug-to_rescan))
{
headp = head-next;
continue;
}
+
+ *headp = head-next;
+ XDELETE (head);
+}
+}
+
/* Reset all debug insns with pending uses. Release the bitmap in it,
unless it is USED. USED must be the same bitmap passed to
dead_debug_init. */
The above comment should be adjusted to dead_debug_local_init.
- rtx reg = NULL;
+ rtx reg = NULL_RTX;
rtx breg;
- rtx dval;
+ rtx dval = NULL_RTX;
rtx bind;
+ bool global;
- if (!debug-used || !bitmap_clear_bit (debug-used, uregno))
+ if (!debug-used)
+return 0;
+
+ global = debug-global debug-global-used
+ bitmap_bit_p (debug-global-used, uregno);
I'd think here formatting should put below debug in = debug-global.
Perhaps put debug-global-used onto its own line too?
+/* Descriptor for hash_table to hash by dead_debug_global_entry's REG
+ and map to DTEMP. */
+
+struct dead_debug_hash_descr
+{
+ /* The hash table contains pointers to entries of this type. */
+ typedef struct dead_debug_global_entry T;
+ /* Hash on the pseudo number. */
+ static inline hashval_t hash (T const *my)
+ {
+return REGNO (my-reg);
+ }
+ /* Entries are identical if they refer to the same pseudo. */
+ static inline bool equal (T const *my, T const *other)
+ {
+return my-reg == other-reg;
+ }
+ /* Release entries when they're removed. */
+ static inline void remove (T *p)
+ {
+XDELETE (p);
+ }
+};
I believe the coding conventions ask to put the inlines outside of the
class body, see e.g. coverage.c.
+
+/* Maintain a global table of pseudos used in debug insns after their
+ deaths in other blocks, and debug temps their deathpoint values are
+ to be bound to. */
+
+struct dead_debug_global
+{
+ /* This hash table that maps pseudos to debug temps. */
+ hash_tabledead_debug_hash_descr htab;
I think all other hash_table uses put a space here before .
BTW, the patch fixes most of the (non-LTO) fails left in the
http://gcc.gnu.org/ml/gcc-patches/2012-09/msg00711.html patch, good job!
Jakub
Re: [PATCH] Fix PR54674
On Tue, 2012-09-25 at 09:14 +0200, Richard Guenther wrote: On Mon, 24 Sep 2012, William J. Schmidt wrote: In cases where pointers and ints are cast back and forth, SLSR can be tricked into introducing a multiply where one of the operands is of pointer type. Don't do that! Verified that the reduced test case in the PR is fixed with a cross-compile to sh4-unknown-linux-gnu with -Os, which is the only known situation where the replacement looks profitable. (It appears multiply costs are underestimated.) Bootstrapped and tested on powerpc64-unknown-linux-gnu with no new regressions. Ok for trunk? Ok. Btw, a multiply by/of a pointer in GIMPLE is done by casting to an appropriate unsigned type, doing the multiply, and then casting back to the pointer type. Just in case it _is_ profitable to do the transform (the patch seems to try to avoid the situation only?) Ok, that's good to know, thanks. There's a general to-do in that area to make the whole casting part better than it is right now, and that should be addressed when I can get back to GCC and work on some of these things. I'll add a comment to that effect. Appreciate the information! Thanks, Bill Thanks, Richard. Thanks, Bill 2012-09-24 Bill Schmidt wschm...@linux.vnet.ibm.com * gimple-ssa-strength-reduction.c (analyze_increments): Don't introduce a multiplication with a pointer operand. Index: gcc/gimple-ssa-strength-reduction.c === --- gcc/gimple-ssa-strength-reduction.c (revision 191665) +++ gcc/gimple-ssa-strength-reduction.c (working copy) @@ -2028,6 +2028,15 @@ analyze_increments (slsr_cand_t first_dep, enum ma incr_vec[i].cost = COST_INFINITE; + /* If we need to add an initializer, make sure we don't introduce +a multiply by a pointer type, which can happen in certain cast +scenarios. */ + else if (!incr_vec[i].initializer + TREE_CODE (first_dep-stride) != INTEGER_CST + POINTER_TYPE_P (TREE_TYPE (first_dep-stride))) + + incr_vec[i].cost = COST_INFINITE; + /* For any other increment, if this is a multiply candidate, we must introduce a temporary T and initialize it with T_0 = stride * increment. When optimizing for speed, walk the
[PATCH] Fix PR54702 and LTO bootstrap (for me)
This fixes PR54702 and LTO bootstrap (well, at least I now survive
stage2 cc1 build). We shouldn't enter builtins into the symtab
asm-name hash, too much code seems to be confused by that (at least
we should at most insert builtins with a set assembler name).
Smells somewhat LTO-ish, but well.
LTO bootstrap running on x86_64-unknown-linux-gnu, regtest pending.
Richard.
2012-09-25 Richard Guenther rguent...@suse.de
PR middle-end/54702
* symtab.c (insert_to_assembler_name_hash): Do not insert builtins.
(verify_symtab_base): Adjust.
(unlink_from_assembler_name_hash): Likewise.
* gcc.dg/lto/pr54702_0.c: New testcase.
* gcc.dg/lto/pr54702_1.c: Likewise.
Index: gcc/symtab.c
===
*** gcc/symtab.c(revision 191700)
--- gcc/symtab.c(working copy)
*** insert_to_assembler_name_hash (symtab_no
*** 106,111
--- 106,113
{
if (symtab_variable_p (node) DECL_HARD_REGISTER (node-symbol.decl))
return;
+ if (symtab_function_p (node) DECL_BUILT_IN (node-symbol.decl))
+ return;
gcc_checking_assert (!node-symbol.previous_sharing_asm_name
!node-symbol.next_sharing_asm_name);
if (assembler_name_hash)
*** insert_to_assembler_name_hash (symtab_no
*** 130,135
--- 132,141
static void
unlink_from_assembler_name_hash (symtab_node node)
{
+ if (symtab_variable_p (node) DECL_HARD_REGISTER (node-symbol.decl))
+ return;
+ if (symtab_function_p (node) DECL_BUILT_IN (node-symbol.decl))
+ return;
if (assembler_name_hash)
{
if (node-symbol.next_sharing_asm_name)
*** verify_symtab_base (symtab_node node)
*** 622,628
hashed_node = hashed_node-symbol.next_sharing_asm_name;
}
if (!hashed_node
!!(symtab_variable_p (node) || DECL_HARD_REGISTER
(node-symbol.decl)))
{
error (node not found in symtab assembler name hash);
error_found = true;
--- 628,635
hashed_node = hashed_node-symbol.next_sharing_asm_name;
}
if (!hashed_node
!!(symtab_variable_p (node) DECL_HARD_REGISTER
(node-symbol.decl))
! !(symtab_function_p (node) DECL_BUILT_IN (node-symbol.decl)))
{
error (node not found in symtab assembler name hash);
error_found = true;
Index: gcc/testsuite/gcc.dg/lto/pr54702_0.c
===
*** gcc/testsuite/gcc.dg/lto/pr54702_0.c(revision 0)
--- gcc/testsuite/gcc.dg/lto/pr54702_0.c(working copy)
***
*** 0
--- 1,10
+ /* { dg-lto-do link } */
+ /* { dg-lto-options { { -O2 -flto -w } } } */
+ /* { dg-extra-ld-options { -r -nostdlib } } */
+
+ #include stdlib.h
+ void* f ()
+ {
+ void* p = malloc (1);
+ return p;
+ }
Index: gcc/testsuite/gcc.dg/lto/pr54702_1.c
===
*** gcc/testsuite/gcc.dg/lto/pr54702_1.c(revision 0)
--- gcc/testsuite/gcc.dg/lto/pr54702_1.c(working copy)
***
*** 0
--- 1,16
+ int *b;
+ void *d;
+ int c;
+ static int *f1 ();
+ void f2 ()
+ {
+ int *a = f1 (0);
+ }
+
+ int *f1 (j)
+ {
+ b = malloc (0);
+ d = *malloc;
+ c = j;
+ }
+
RE: [PATCH, AArch64] Allow symbol+offset even if not being used for memory access
Ok. Having dug a bit deeper I think the main problem is that you're working against yourself by not handling this pattern right from the beginning. You have split the address incorrectly to begin and are now trying to recover after the fact. The following patch seems to do the trick for me, producing (insn 6 5 7 (set (reg:DI 81) (high:DI (const:DI (plus:DI (symbol_ref:DI (arr) [flags 0x80] var_decl 0x7f9bae1105f0 arr) (const_int 12 [0xc]) z.c:8 -1 (nil)) (insn 7 6 8 (set (reg:DI 80) (lo_sum:DI (reg:DI 81) (const:DI (plus:DI (symbol_ref:DI (arr) [flags 0x80] var_decl 0x7f9bae1105f0 arr) (const_int 12 [0xc]) z.c:8 -1 (expr_list:REG_EQUAL (const:DI (plus:DI (symbol_ref:DI (arr) [flags 0x80] var_decl 0x7f9bae1105f0 arr) (const_int 12 [0xc]))) (nil))) right from the .150.expand dump. I'll leave it to you to fully regression test and commit the patch as appropriate. ;-) Thanks so much for this, Richard. I have prepared a new patch heavily based off yours, which really demands its own new email trail, so I shall make a fresh post. Cheers, Ian
Re: [C++ Patch] PR 54526
On 09/25/2012 06:47 AM, Paolo Carlini wrote: if I understand correctly, in C++11 mode we should simply accept what we used to accept only with -fpermissive. Let's also mention -std=c++11 as an alternative to -fpermissive in the note. OK with that change. Jason
Re: [PATCH] rs6000: Fix ne0 patterns (PR51274)
On Tue, Sep 25, 2012 at 12:44 AM, Segher Boessenkool seg...@kernel.crashing.org wrote: The current patterns will never match. Fix that. Also, merge the SI and DI variants of each. Also, remove an unnecessary earlyclobber. And add a pattern for what combine considers the canonical form of one of these patterns. Bootstrapped and regression checked on powerpc64-linux. Also tested all these patterns manually, -m32 and -m64 and -m32 -mpowerpc64, -misel and -mno-isel. Okay to apply? Segher 2012-09-24 Segher Boessenkool seg...@kernel.crashing.org gcc/ PR target/51274 * config/rs6000/rs6000.md (ne0si): Remove unnecessary earlyclobber. Merge with... (ne0di): ... to... (ne0_mode): New. (plus_ne0si): Merge with... (plus_ne0di): ... to... (plus_ne0_mode): New. (compare_plus_ne0si): Merge with... (compare_plus_ne0di)... to... (compare_plus_ne0_mode): New. (compare_plus_ne0_mode_1): New. (plus_ne0si_compare): Merge with... (plus_ne0di_compare)... to... (plus_ne0_mode_compare): New. This is okay, but can you also add a target testcase to check that the correct assembly instructions are generated so that we can try to ensure this does not regress again? Thanks, David
Re: [PATCH] rs6000: Fix ne0 patterns (PR51274)
This is okay, but can you also add a target testcase to check that the correct assembly instructions are generated so that we can try to ensure this does not regress again? This won't regress in this way again, because now the pattern is a single RTL op. But yes, target tests for this kind of thing would be quite useful. However, I'm going to overhaul the whole SCC thing, so I'd rather add tests for everything at once. OTOH, it's a good exercise I suppose... Your choice :-) Segher
[PATCH, AArch64] Handle symbol + offset more effectively
Hi all,
This patch corrects what seemed to be a typo in expand_mov_immediate
in aarch64.c, where we had || instead of an in our original code.
if (offset != const0_rtx
(targetm.cannot_force_const_mem (mode, imm)
|| (can_create_pseudo_p ( // - should have been
At any given time, this code would have treated all input the same
and will have caused all non-zero offsets to have been forced to
temporaries, and made us never run the code in the remainder of the
function.
In terms of measurable impact, this patch provides a better fix to the
problem I was trying to solve with this patch:
http://gcc.gnu.org/ml/gcc-patches/2012-08/msg02072.html
Almost all credit should go to Richard Henderson for this patch.
It is all his, but for a minor change I made to some predicates which
now become relevant when we execute more of the expand_mov_immediate
function.
My testing showed no regressions for bare-metal or linux.
OK for aarch64-branch and aarch64-4.7-branch?
Cheers,
Ian
2012-09-25 Richard Henderson r...@redhat.com
Ian Bolton ian.bol...@arm.com
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Fix a
functional typo and refactor code in switch statement.
* config/aarch64/aarch64.md (add_losym): Handle symbol + offset.
* config/aarch64/predicates.md (aarch64_tls_ie_symref): Match const.
(aarch64_tls_le_symref): Likewise.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2d7eba7..edeee30 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -652,43 +652,57 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
unsigned HOST_WIDE_INT val;
bool subtargets;
rtx subtarget;
- rtx base, offset;
int one_match, zero_match;
gcc_assert (mode == SImode || mode == DImode);
- /* If we have (const (plus symbol offset)), and that expression cannot
- be forced into memory, load the symbol first and add in the offset. */
- split_const (imm, base, offset);
- if (offset != const0_rtx
- (targetm.cannot_force_const_mem (mode, imm)
- || (can_create_pseudo_p (
-{
- base = aarch64_force_temporary (dest, base);
- aarch64_emit_move (dest, aarch64_add_offset (mode, NULL, base, INTVAL
(offset)));
- return;
-}
-
/* Check on what type of symbol it is. */
- if (GET_CODE (base) == SYMBOL_REF || GET_CODE (base) == LABEL_REF)
+ if (GET_CODE (imm) == SYMBOL_REF
+ || GET_CODE (imm) == LABEL_REF
+ || GET_CODE (imm) == CONST)
{
- rtx mem;
- switch (aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR))
+ rtx mem, base, offset;
+ enum aarch64_symbol_type sty;
+
+ /* If we have (const (plus symbol offset)), separate out the offset
+before we start classifying the symbol. */
+ split_const (imm, base, offset);
+
+ sty = aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR);
+ switch (sty)
{
case SYMBOL_FORCE_TO_MEM:
- mem = force_const_mem (mode, imm);
+ if (offset != const0_rtx
+ targetm.cannot_force_const_mem (mode, imm))
+ {
+ gcc_assert(can_create_pseudo_p ());
+ base = aarch64_force_temporary (dest, base);
+ base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
+ aarch64_emit_move (dest, base);
+ return;
+ }
+ mem = force_const_mem (mode, imm);
gcc_assert (mem);
emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
return;
-case SYMBOL_SMALL_TLSGD:
-case SYMBOL_SMALL_TLSDESC:
-case SYMBOL_SMALL_GOTTPREL:
-case SYMBOL_SMALL_TPREL:
+case SYMBOL_SMALL_TLSGD:
+case SYMBOL_SMALL_TLSDESC:
+case SYMBOL_SMALL_GOTTPREL:
case SYMBOL_SMALL_GOT:
+ if (offset != const0_rtx)
+ {
+ gcc_assert(can_create_pseudo_p ());
+ base = aarch64_force_temporary (dest, base);
+ base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
+ aarch64_emit_move (dest, base);
+ return;
+ }
+ /* FALLTHRU */
+
+case SYMBOL_SMALL_TPREL:
case SYMBOL_SMALL_ABSOLUTE:
- aarch64_load_symref_appropriately
- (dest, imm, aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR));
+ aarch64_load_symref_appropriately (dest, imm, sty);
return;
default:
@@ -696,7 +710,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
}
}
- if ((CONST_INT_P (imm) aarch64_move_imm (INTVAL (imm), mode)))
+ if (CONST_INT_P (imm) aarch64_move_imm (INTVAL (imm), mode))
{
emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
return;
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b399ab4..3834558 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2840,7 +2840,7 @@
(lo_sum:DI
[CPP] Add pragmas for emitting diagnostics
This patch adds support for #pragma GCC warning and #pragma GCC error.
These pragmas can be used from preprocessor macros, unlike the existing
#warning and #error directives. Library authors can use these pragmas
to add deprecation warnings to macros they define.
Bootstrapped and tested on x86_64-redhat-linux-gnu, with no apparent
regressions. Okay for trunk?
--
Florian Weimer / Red Hat Product Security Team
gcc/ChangeLog:
2012-09-25 Florian Weimer fwei...@redhat.com
* doc/cpp.texi (Pragmas): Document #pragma GCC warning, #pragma
GCC error.
gcc/testsuite/ChangeLog:
2012-09-25 Florian Weimer fwei...@redhat.com
* c-c++-common/cpp/diagnostic-pragma-1.c: New testcase.
libcpp/ChangeLog:
2012-09-25 Florian Weimer fwei...@redhat.com
* directives.c (do_pragma_warning_or_error): New.
(do_pragma_warning): New.
(do_pragma_error): New.
(_cpp_init_internal_pragmas): Register new pragmas.
Index: gcc/doc/cpp.texi
===
--- gcc/doc/cpp.texi (revision 191700)
+++ gcc/doc/cpp.texi (working copy)
@@ -3634,6 +3634,16 @@
current file to be treated as if it came from a system header.
@xref{System Headers}.
+@item #pragma GCC warning
+@itemx #pragma GCC error
+@code{#pragma GCC warning message} causes the preprocessor to issue
+a warning diagnostic with the text @samp{message}. The message
+contained in the pragma must be a single string literal. Similary,
+@code{#pragma GCC error message} issues an error message. Unlike
+the @samp{#warning} and @samp{#error} directives provided by
+compilers, these pragmas can be embedded in preprocessor macros using
+@samp{_Pragma}.
+
@end ftable
@node Other Directives
Index: gcc/testsuite/c-c++-common/cpp/diagnostic-pragma-1.c
===
--- gcc/testsuite/c-c++-common/cpp/diagnostic-pragma-1.c (revision 0)
+++ gcc/testsuite/c-c++-common/cpp/diagnostic-pragma-1.c (working copy)
@@ -0,0 +1,11 @@
+// { dg-do compile }
+
+#pragma GCC warning warn-a // { dg-warning warn-a }
+#pragma GCC error err-b // { dg-error err-b }
+
+#define CONST1 _Pragma(GCC warning \warn-c\) 1
+#define CONST2 _Pragma(GCC error \err-d\) 2
+
+char a[CONST1]; // { dg-warning warn-c }
+char b[CONST2]; // { dg-error err-d }
+
Index: libcpp/directives.c
===
--- libcpp/directives.c (revision 191700)
+++ libcpp/directives.c (working copy)
@@ -1,7 +1,5 @@
/* CPP Library. (Directive handling.)
- Copyright (C) 1986, 1987, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005,
- 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
+ Copyright (C) 1986-2012 Free Software Foundation, Inc.
Contributed by Per Bothner, 1994-95.
Based on CCCP program by Paul Rubin, June 1986
Adapted to ANSI C, Richard Stallman, Jan 1987
@@ -118,6 +116,9 @@
static void do_pragma_poison (cpp_reader *);
static void do_pragma_system_header (cpp_reader *);
static void do_pragma_dependency (cpp_reader *);
+static void do_pragma_warning_or_error (cpp_reader *, bool error);
+static void do_pragma_warning (cpp_reader *);
+static void do_pragma_error (cpp_reader *);
static void do_linemarker (cpp_reader *);
static const cpp_token *get_token_no_padding (cpp_reader *);
static const cpp_token *get__Pragma_string (cpp_reader *);
@@ -1263,6 +1264,8 @@
register_pragma_internal (pfile, GCC, system_header,
do_pragma_system_header);
register_pragma_internal (pfile, GCC, dependency, do_pragma_dependency);
+ register_pragma_internal (pfile, GCC, warning, do_pragma_warning);
+ register_pragma_internal (pfile, GCC, error, do_pragma_error);
}
/* Return the number of registered pragmas in PE. */
@@ -1634,6 +1637,42 @@
free ((void *) fname);
}
+/* Issue a diagnostic with the message taken from the pragma. If
+ ERROR is true, the diagnostic is a warning, otherwise, it is an
+ error. */
+static void
+do_pragma_warning_or_error (cpp_reader *pfile, bool error)
+{
+ const cpp_token *tok = _cpp_lex_token (pfile);
+ cpp_string str;
+ if (tok-type != CPP_STRING
+ || !cpp_interpret_string_notranslate (pfile, tok-val.str, 1, str,
+ CPP_STRING)
+ || str.len == 0)
+{
+ cpp_error (pfile, CPP_DL_ERROR, invalid #pragma GCC %s directive,
+ error ? error : warning);
+ return;
+}
+ cpp_error (pfile, error ? CPP_DL_ERROR : CPP_DL_WARNING,
+ %s, str.text);
+ free ((void *)str.text);
+}
+
+/* Issue a warning diagnostic. */
+static void
+do_pragma_warning (cpp_reader *pfile)
+{
+ do_pragma_warning_or_error (pfile, false);
+}
+
+/* Issue an error diagnostic. */
+static void
+do_pragma_error (cpp_reader *pfile)
+{
+ do_pragma_warning_or_error (pfile, true);
+}
+
/* Get a token but skip padding. */
static const cpp_token *
get_token_no_padding (cpp_reader *pfile)
Re: [PATCH] Fix PR54702 and LTO bootstrap (for me)
On Tue, 25 Sep 2012, Richard Guenther wrote:
This fixes PR54702 and LTO bootstrap (well, at least I now survive
stage2 cc1 build). We shouldn't enter builtins into the symtab
asm-name hash, too much code seems to be confused by that (at least
we should at most insert builtins with a set assembler name).
Smells somewhat LTO-ish, but well.
And breaks regular build. The following fixes PR54625 and this one
and passes bootstrap regtest.
Committed.
Richard.
2012-09-25 Richard Guenther rguent...@suse.de
PR lto/54625
* lto-symtab.c (lto_symtab_merge_cgraph_nodes_1): Do not merge
cgraph nodes for builtins.
* gcc.dg/lto/pr54702_0.c: New testcase.
* gcc.dg/lto/pr54702_1.c: Likewise.
* gcc.dg/lto/pr54625-1_0.c: Likewise.
* gcc.dg/lto/pr54625-1_1.C: Likewise.
* gcc.dg/lto/pr54625-2_0.c: Likewise.
* gcc.dg/lto/pr54625-2_1.C: Likewise.
Index: gcc/testsuite/gcc.dg/lto/pr54702_0.c
===
*** gcc/testsuite/gcc.dg/lto/pr54702_0.c(revision 0)
--- gcc/testsuite/gcc.dg/lto/pr54702_0.c(working copy)
***
*** 0
--- 1,10
+ /* { dg-lto-do link } */
+ /* { dg-lto-options { { -O2 -flto -w } } } */
+ /* { dg-extra-ld-options { -r -nostdlib } } */
+
+ #include stdlib.h
+ void* f ()
+ {
+ void* p = malloc (1);
+ return p;
+ }
Index: gcc/testsuite/gcc.dg/lto/pr54702_1.c
===
*** gcc/testsuite/gcc.dg/lto/pr54702_1.c(revision 0)
--- gcc/testsuite/gcc.dg/lto/pr54702_1.c(working copy)
***
*** 0
--- 1,16
+ int *b;
+ void *d;
+ int c;
+ static int *f1 ();
+ void f2 ()
+ {
+ int *a = f1 (0);
+ }
+
+ int *f1 (j)
+ {
+ b = malloc (0);
+ d = *malloc;
+ c = j;
+ }
+
Index: gcc/testsuite/gcc.dg/lto/pr54625-1_0.c
===
--- gcc/testsuite/gcc.dg/lto/pr54625-1_0.c (revision 0)
+++ gcc/testsuite/gcc.dg/lto/pr54625-1_0.c (working copy)
@@ -0,0 +1,10 @@
+/* { dg-lto-do link } */
+/* { dg-extra-ld-options { -r -nostdlib } } */
+
+float a;
+double sin ();
+speex_resampler_init_frac ()
+{
+ a = sin (0);
+}
+
Index: gcc/testsuite/gcc.dg/lto/pr54625-1_1.C
===
--- gcc/testsuite/gcc.dg/lto/pr54625-1_1.C (revision 0)
+++ gcc/testsuite/gcc.dg/lto/pr54625-1_1.C (working copy)
@@ -0,0 +1,19 @@
+extern C double sin (double);
+typedef double UnaryFunType (double);
+class A
+{
+public:
+ int hash ();
+ double lookup (UnaryFunType p1)
+{
+ int a = hash ();
+ if (p1)
+ return 0;
+}
+};
+A b;
+void
+math_sin_impl ()
+{
+ b.lookup (sin);
+}
Index: gcc/testsuite/gcc.dg/lto/pr54625-2_0.c
===
--- gcc/testsuite/gcc.dg/lto/pr54625-2_0.c (revision 0)
+++ gcc/testsuite/gcc.dg/lto/pr54625-2_0.c (working copy)
@@ -0,0 +1,9 @@
+/* { dg-lto-do link } */
+/* { dg-extra-ld-options { -r -nostdlib } } */
+
+float a;
+double sin ();
+update_filter ()
+{
+ a = sin (0);
+}
Index: gcc/testsuite/gcc.dg/lto/pr54625-2_1.C
===
--- gcc/testsuite/gcc.dg/lto/pr54625-2_1.C (revision 0)
+++ gcc/testsuite/gcc.dg/lto/pr54625-2_1.C (working copy)
@@ -0,0 +1,24 @@
+extern C double sin (double);
+typedef double (*UnaryFunType) (double);
+class A
+{
+public:
+ int hash ();
+ void lookup (UnaryFunType p1)
+{
+ int a = hash ();
+ p1 (0);
+}
+};
+A b, c;
+void
+math_sin_impl ()
+{
+ b.lookup (sin);
+}
+
+void
+js_math_sqrt ()
+{
+ c.lookup (0);
+}
Index: gcc/lto-symtab.c
===
--- gcc/lto-symtab.c(revision 191700)
+++ gcc/lto-symtab.c(working copy)
@@ -629,7 +629,8 @@ lto_symtab_merge_cgraph_nodes_1 (symtab_
if (!symtab_real_symbol_p (e))
continue;
- if (symtab_function_p (e))
+ if (symtab_function_p (e)
+ !DECL_BUILT_IN (e-symbol.decl))
lto_cgraph_replace_node (cgraph (e), cgraph (prevailing));
if (symtab_variable_p (e))
lto_varpool_replace_node (varpool (e), varpool (prevailing));
Re: [Patch] catch builtin_bswap16 construct
On 25 September 2012 13:32, Segher Boessenkool
seg...@kernel.crashing.org wrote:
Christophe, it looks like the zero-extend in the unsigned case is not
needed on any target? Assuming the shifts are at least SImode, of
course (I'm too lazy to check, sorry).
It's also present when compiling:
unsigned short swapu16(unsigned short x) {
return __builtin_bswap16(x);
}
so it's not directly caused by my patch I think.
The RTL is (set (reg:HI) (bswap:HI (reg:HI))) which then gets
extended for the SI (or DI) function return. Nothing to see here,
it's a target problem. Your results look good.
OK thank for the confirmation.
I guess I just have to wait for approval by the right maintainer now?
[PATCH] Fix PR54704
I am testing the following patch to fix a typo(?) in the hash
function for location ad-hoc data. The current hash function
causes 1000 collisions for each search when building tramp3d.
Bootstrap and regtest running on x86_64-unknown-linux-gnu.
Richard.
2012-09-25 Richard Guenther rguent...@suse.de
PR middle-end/54704
* line-map.c (location_adhoc_data_hash): Fix.
Index: libcpp/line-map.c
===
--- libcpp/line-map.c (revision 191706)
+++ libcpp/line-map.c (working copy)
@@ -58,7 +58,7 @@ location_adhoc_data_hash (const void *l)
{
const struct location_adhoc_data *lb =
(const struct location_adhoc_data *) l;
- return (hashval_t) lb-locus + (size_t) lb-data;
+ return (hashval_t) lb-locus + (size_t) lb-data;
}
/* Compare function for location_adhoc_data hashtable. */
Re: [Patch] catch builtin_bswap16 construct
I guess I just have to wait for approval by the right maintainer now? Right, GCC's bureaucracy is no legend. :-) I've CCed Richard, who approved the __builtin_bswap16 stuff back in April. -- Eric Botcazou
Re: [PATCH] Fix up CFLAGS/CXXFLAGS gcc/configure adjustment (PR other/54692)
Il 25/09/2012 13:19, Jakub Jelinek ha scritto: Hi! On Thu, Sep 13, 2012 at 06:24:14PM +0200, Paolo Bonzini wrote: Il 13/09/2012 17:57, Jakub Jelinek ha scritto: Can we get this change in? The current state is terribly annoying. Yes, please go ahead. Here it is, bootstrapped/regtested on x86_64-linux and i686-linux, additionally tested on --disable-bootstrap tree, both by make cc1 inside of gcc subdir (no -O2) and make all-gcc above it (with -O2). Ok. Seems the sed command was using * at the end, so it happily changed e.g. -Og into just g instead of either keeping -Og in, or removing it altogether. This patches fixes it, now -Ofast, -Og, -Os, -O, -O[0-9]* are removed when followed by whitespace and not otherwise. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? Yes, thanks. Would it make sense to leave -Og in? Paolo
Re: [PATCH] rs6000: Fix ne0 patterns (PR51274)
On Tue, Sep 25, 2012 at 03:40:10PM +0200, Segher Boessenkool wrote: This is okay, but can you also add a target testcase to check that the correct assembly instructions are generated so that we can try to ensure this does not regress again? This won't regress in this way again, because now the pattern is a single RTL op. But yes, target tests for this kind of thing would be quite useful. However, I'm going to overhaul the whole SCC thing, so I'd rather add tests for everything at once. OTOH, it's a good exercise I suppose... Your choice :-) Yes, I had probably fixed that regression 2-3 times while I was rewriting the SCC stuff, but since I never could get any improvements without regressions, I put it on the back burner to get to more stuff. If you want, I can share what I had. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meiss...@linux.vnet.ibm.com fax +1 (978) 399-6899
[Patch,avr,committed] PR54641, PR54701
Applied the following patches: PR64641: http://gcc.gnu.org/viewcvs?view=revisionrevision=191714 PR target/54641 * config/avr/t-avr: Use ALL_COMPILERFLAGS instead of ALL_CFLAGS for sources compiled with COMPILER. PR54701: http://gcc.gnu.org/viewcvs?view=revisionrevision=191701 http://gcc.gnu.org/viewcvs?view=revisionrevision=191716 PR other/54701 * config/avr/avr.c (avr_map_decompose): Use double_int::from_uhwi instead of uhwi_to_double_int. * config/avr/avr-log.c (avr_double_int_pop_digit): Rewrite using double_int::udivmod. Misc: http://gcc.gnu.org/viewcvs?view=revisionrevision=191715 * config/avr/avr.c (avr_set_current_function): Check cfun-machine to be non-NULL.
[ARM] fix for PR49423
Hi Ramana, Here is obvious fix for PR49423, I just added pool range for arm_zero_extendqisi2, arm_zero_extendqisi2_v6, arm_zero_extendhisi2, arm_zero_extendhisi2_v6 patterns. thanks, Dinar. PR49423.patch Description: Binary data
Re: [PATCH] Fix up CFLAGS/CXXFLAGS gcc/configure adjustment (PR other/54692)
On Tue, Sep 25, 2012 at 05:59:28PM +0200, Paolo Bonzini wrote: Il 25/09/2012 13:19, Jakub Jelinek ha scritto: Yes, thanks. Would it make sense to leave -Og in? Maybe once it matures more. E.g. the scheduler isn't currently tweaked for -Og (should either not schedule at all, or only within group of insns with the same location (source loc + block), possibly allowing no location/block insns to be moved around at will). Jakub
Re: Ping: PATCH RFA: Print backtrace on ICE
On 2012-09-20 22:33 , Ian Lance Taylor wrote: gcc/: 2012-09-17 Ian Lance Taylor i...@google.com * diagnostic.c: Include demangle.h and backtrace.h. (bt_stop): New static array. (bt_callback, bt_err_callback): New static functions. (diagnostic_action_after_output): Call backtrace_full for DK_ICE. * Makefile.in (BACKTRACE): New variable. (BACKTRACEINC, LIBBACKTRACE): New variables. (BACKTRACE_H): New variable. (LIBDEPS, LIBS): Add $(LIBBACKTRACE). (INCLUDES): Add $(BACKTRACEINC). (diagnostic.o): Depend upon $(DEMANGLE_H) and $(BACKTRACE_H). ./: 2012-09-17 Ian Lance Taylor i...@google.com * Makefile.def: Make all-gcc depend on all-libbacktrace. * Makefile.in: Rebuild. I wanted a --param to control it, but I agree that it can be added later. This looks OK to me. Thanks! Diego.
RFA: update config-list.mk
A few arm targets were removed from config.gcc, and picochip is only available with --enable-obsolete. This patch brings config-list.mk up-to-date in these respects. 2012-09-24 Joern Rennecke joern.renne...@embecosm.com * contrib-list.mk (LIST): Remove arm-freebsd6, arm-linux, arm-ecos-elf, arm-rtems, arm-elf and arm-wince-pe. Use --enable-obsolete for picochip-elf. Index: contrib/config-list.mk === --- contrib/config-list.mk (revision 191658) +++ contrib/config-list.mk (working copy) @@ -13,9 +13,9 @@ # v850e1-elf is rejected by config.sub LIST = alpha-linux-gnu alpha-freebsd6 alpha-netbsd alpha-openbsd \ alpha64-dec-vms alpha-dec-vms am33_2.0-linux \ - arm-wrs-vxworks arm-freebsd6 arm-netbsdelf arm-linux \ - arm-linux-androideabi arm-uclinux_eabi arm-ecos-elf arm-eabi \ - arm-symbianelf arm-rtems arm-elf arm-wince-pe avr-rtems avr-elf \ + arm-wrs-vxworks arm-netbsdelf \ + arm-linux-androideabi arm-uclinux_eabi arm-eabi \ + arm-symbianelf avr-rtems avr-elf \ bfin-elf bfin-uclinux bfin-linux-uclibc bfin-rtems bfin-openbsd \ c6x-elf c6x-uclinux cr16-elf cris-elf cris-linux crisv32-elf crisv32-linux \ epiphany-elf epiphany-elfOPT-with-stack-offset=16 fido-elf \ @@ -42,7 +42,8 @@ LIST = alpha-linux-gnu alpha-freebsd6 al mipsisa64-elfoabi mipsisa64r2el-elf mipsisa64sr71k-elf mipsisa64sb1-elf \ mipsel-elf mips64-elf mips64vr-elf mips64orion-elf mips-rtems \ mips-wrs-vxworks mipstx39-elf mmix-knuth-mmixware mn10300-elf moxie-elf \ - moxie-uclinux moxie-rtems pdp11-aout picochip-elf powerpc-darwin8 \ + moxie-uclinux moxie-rtems pdp11-aout picochip-elfOPT-enable-obsolete \ + powerpc-darwin8 \ powerpc-darwin7 powerpc64-darwin powerpc-freebsd6 powerpc-netbsd \ powerpc-eabispe powerpc-eabisimaltivec powerpc-eabisim ppc-elf \ powerpc-eabialtivec powerpc-xilinx-eabi powerpc-eabi \
Re: [Patch][AArch64] Implement support for LD{1,2,3,4}/ST{1,2,3,4}.
I've committed this patch to aarch64-branch and backported to aarch64-4.7-branch. /Marcus On 10 Sep 2012, at 15:54, Tejas Belagod tbela...@arm.com wrote: Hi, The attached patch implements register list support, standard patterns for struct vector(strided) load-store support and their associated Advanced SIMD intrinsics. Regression tested on aarch64-none-elf. This patch exposed some bugs for which I will post follow-up patches. OK for aarch64-branch? Thanks, Tejas. ChangeLog: 2012-09-10 Tejas Belagod tejas.bela...@arm.com * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_data): Populate intrinsic table with struct loads and store descriptors. (init_aarch64_simd_builtins): Remove cruft. (aarch64_simd_expand_builtin): Expand the builtins. * config/aarch64/aarch64-modes.def: Define new vector modes for register lists. * config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_move): New. (aarch64_simd_mem_operand_p): New. (aarch64_simd_imm_zero_p): New. (aarch64_output_move_struct): New. (aarch64_simd_disambiguate_copy): New. * config/aarch64/aarch64-simd.md (simd_mode): Add OI, CI and XI to the list. (movmode): Tighten predicates for simd operand. (movmisalignmode): Likewise. (*aarch64_simd_movmode): Tighten predicates and constraints for simd operands. (*aarch64_combinezmode): New. (vec_load_lanesoimode, vec_store_lanesoimode, vec_load_lanescimode, vec_store_lanescimode, vec_load_lanesximode, vec_store_lanesximode, movmode, *aarch64_movmode, aarch64_ld2mode_dreg, aarch64_ld3mode_dreg, aarch64_ld4mode_dreg, aarch64_ldVSTRUCT:nregsVDC:mode, aarch64_ldVSTRUCT:nregsVQ:mode, aarch64_get_dregVSTRUCT:modeVDC:mode, aarch64_get_qregVSTRUCT:modeVQ:mode, aarch64_st2mode_dreg, aarch64_st3mode_dreg, aarch64_st4mode_dreg, aarch64_stVSTRUCT:nregsVDC:mode, aarch64_stVSTRUCT:nregsVQ:mode, aarch64_set_qregVSTRUCT:modeVQ:mode): New expanders and patterns for vector struct loads and stores. * config/aarch64/aarch64.c (aarch64_vect_struct_mode_p): New. (aarch64_vector_mode_p): New. (aarch64_array_mode_supported_p): New. (aarch64_hard_regno_mode_ok): Check that reglists don't go out of range and don't allocate general regs to large int modes. (aarch64_classify_address): Restrict addressing modes of large int modes to same as SIMD addressing modes. (aarch64_print_operand): Print specifiers for register lists. (aarch64_legitimize_reload_address): Treat large int modes simliar to SIMD modes. (aarch64_class_max_nregs): Return the correct max number of register for a particular mode. (aarch64_legitimate_constant_p): Do not allow large int modes immediate values. (aarch64_simd_imm_zero_p): New. (aarch64_simd_mem_operand_p): Check if mem operand has a valid SIMD addressing mode. (aarch64_simd_disambiguate_copy): Copy values that span multiple register with and without overlapping. (aarch64_simd_attr_length_move): Length of instruction sequence depending on the mode. * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_QREG_MODE): New. * config/aarch64/aarch64.md (UNSPEC_VSTRUCTDUMMY, UNSPEC_LD2, UNSPEC_LD3, UNSPEC_LD4, UNSPEC_ST2, UNSPEC_ST3, UNSPEC_ST4): New. * config/aarch64/arm_neon.h: Remove assembler implementation of vector struct loads and stores and add new C implementations. * config/aarch64/constraints.md (Utv): New memory constraint for SIMD memory operands. (Dz): New. * config/aarch64/iterators.md (VDIC, VSTRUCT, DX): New mode iterators. (Vendreg, nregs, VRL2, VRL3, VRL4, VSTRUCT_DREG): New mode attributes. * config/aarch64/predicates.md (aarch64_simd_struct_operand): New. (aarch64_simd_general_operand): New. (aarch64_simd_nonimmediate_operand): New. (aarch64_simd_reg_or_zero): New. (aarch64_simd_imm_zero): New. * testsuite/lib/target-supports.exp (check_effective_target_vect_stridedN): Enable support for strided load and stores for aarch64.vldn-vstn.txt
Re: [Patch][AArch64] Expand binary operations' constant operands for neon intrinsics.
On 10/09/12 16:02, Tejas Belagod wrote: Hi, This patch expands an Advanced SIMD intrinsic's operand into a constant operand only if the predicate allows it. Regression-tested on aarch64-none-elf. OK for aarch64-branch? Thanks, Tejas Belagod ARM. Changelog 2012-09-10 Tejas Belagodtejas.bela...@arm.com gcc/ * config/aarch64/aarch64.c (aarch64_simd_expand_builtin): Expand binary operations' constant operand only if the predicate allows it. Committed to aarch64-branch and aarch64-4.7-branch. /Marcus
Re: [Patch][AArch64] Split a move of Q-reg vectors contained in general regs.
On 10/09/12 16:05, Tejas Belagod wrote: 2012-09-10 Tejas Belagodtejas.bela...@arm.com gcc/ * config/aarch64/aarch64-simd.md (*aarch64_simd_movmode): Split Q-reg vector value move contained in general registers. Committed to aarch64-branch and aarch64-4.7-branch /Marcus
Re: [Patch][AArch64] Tighten predicate for CMP pattern.
On 10/09/12 16:11, Tejas Belagod wrote: 2012-09-10 Tejas Belagodtejas.bela...@arm.com gcc/ * config/aarch64/aarch64-simd.md (aarch64_cmcmpmode): Tighten predicate for operand 2 of the compare pattern to accept register or zero. * config/aarch64/predicates.md (aarch64_simd_reg_or_zero): New. Committed to aarch64-branch and aarch64-4.7-branch. /Marcus
Re: PING Re: [PATCH, MIPS] add new peephole for 74k dspr2
On Tue, 25 Sep 2012, Richard Sandiford wrote: According to my sources the R4650 has a 4-cycle MULT latency (MAD is 3-4 cycles on that processor). An MTHI/MTLO pair will take 2 cycles; obviously the resulting larger code may adversely affect cache performance in some scenarios. That's not how the 4650 DFA models it though. (define_insn_reservation generic_hilo 1 (eq_attr type mfhi,mflo,mthi,mtlo) imuldiv*3) (define_insn_reservation r4650_imul 4 (and (eq_attr cpu r4650) (eq_attr type imul,imul3,imadd)) imuldiv*4) So if we believed the DFA, MTLO + MTHI would occupy the muldiv unit for 6 rather than 4 cycles. Any attempt to use the DFA would still favour MULT. I can't track a reference on R4650 MTHI/MTLO latency; I'd be happy to learn of one, or otherwise I wonder where the delay is coming from. Also a small update: apparently MULT is 3 clocks only on the R4650 where operands are 16 bits (unsure if it is enough if only one is; for a zero by zero multiplication it surely does not matter though). So I think using a MULT here is at least reasonable. Although I see the 4kp with its 32-cycle MULTs and MADDs is one where MULT $0,$0 would be a really bad choice. Sigh. The amount of effort required for this optimisation is getting a bit ridiculous. I have double-checked some documentation, and in fact many MIPS cores, including the current ones, have a configuration option to include either a high-performance or an area-efficient MD unit. Take the M14Kc for example -- its high-performance unit has a one-cycle latency/issue rate for 16-bit multiplication (two-cycle for full 32 bits; here the width of rt is explicitly named) and the area-efficient has a 32-cycle latency/issue rate only regardless of the operand size (obviously iterating over addition one bit at a time). The latency of MTHI/MTLO is 1 across both units. So I think this can't really be selected automatically for all cores, some human-supplied knowledge about the MD unit used is required -- that obviously affects other operations too, e.g. some multiplications involving a constant that may be cheaper to do either directly or with a sequence of additions depending on the MD unit present (unless optimising for size, of course). Maciej
Re: [Patch][AArch64] Move immediate into Advanced SIMD scalar.
On 10/09/12 16:14, Tejas Belagod wrote: 2012-09-10 Tejas Belagodtejas.bela...@arm.com gcc/ * config/aarch64/aarch64-protos.h (aarch64_simd_imm_scalar_p): Declare. * config/aarch64/aarch64.c (aarch64_simd_imm_scalar_p): New. * config/aarch64/aarch64.md (*movdi_aarch64): Add alternative for moving valid scalar immediate into a Advanved SIMD D-register. * config/aarch64/constraints.md (Dd): New. Committed to aarch64-branch and aarch64-4.7-branch. /Marcus
Re: [PATCH] PR c++/54372 - unused attribute inactive on dependant entities
OK. Jason
Re: [Patch][AArch64] Fix vfmaq_lane_f64.
On 10/09/12 16:18, Tejas Belagod wrote: 2012-09-10 Tejas Belagodtejas.bela...@arm.com gcc/ * config/aarch64/arm_neon.h (vfmaq_lane_f64): Fix prototype and assembler template accordingly. Committed to aarch64-branch and aarch64-4.7-branch. /Marcus
Re: [Patch][AArch64] Implement vmovq_n_f64.
On 10/09/12 16:20, Tejas Belagod wrote: 2012-09-10 Tejas Belagodtejas.bela...@arm.com gcc/ * config/aarch64/arm_neon.h (vmovq_n_f64): Add. Committed to aarch64-branch and aarch64-4.7-branch. /Marcus
Re: [Patch][AArch64] Fix Narrowing high shifts.
On 10/09/12 16:22, Tejas Belagod wrote: 2012-09-10 Tejas Belagodtejas.bela...@arm.com gcc/ * config/aarch64/arm_neon.h (vrshrn_high_n_s16, vrshrn_high_n_s32, vrshrn_high_n_s64, vrshrn_high_n_u16, vrshrn_high_n_u32, vrshrn_high_n_u64, vshrn_high_n_s16, vshrn_high_n_s32, vshrn_high_n_s32, vshrn_high_n_s64, vshrn_high_n_u16, vshrn_high_n_u32, vshrn_high_n_u64): Fix template to reference correct operands. Committed to aarch64-branch and aarch64-4.7-branch. /Marcus
Re: [Patch][AArch64] Implement TARGET_SHIFT_TRUNCATION_MASK.
On 10/09/12 16:28, Tejas Belagod wrote: gcc/ * config/aarch64/aarch64.c (aarch64_shift_truncation_mask): Define. (TARGET_SHIFT_TRUNCATION_MASK): Define. * config/aarch64/aarch64.h (SHIFT_COUNT_TRUNCATED): Conditionalize on TARGET_SIMD. Committed to aarch64-branch and aarch64-4.7-branch. /Marcus
[PATCH] rs6000: Add testcase for ne0 stuff
How's this?
Segher
2012-09-25 Segher Boessenkool seg...@kernel.crashing.org
gcc/testsuite/
* gcc.target/powerpc/ppc-ne0-1.c: New.
---
gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c | 33 ++
1 files changed, 33 insertions(+), 0 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
new file mode 100644
index 000..63c4b60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
@@ -0,0 +1,33 @@
+/* PR target/51274 */
+/* { dg-do compile } */
+/* { dg-options -O2 -mno-isel } */
+
+/* { dg-final { scan-assembler-times addic 4 } } */
+/* { dg-final { scan-assembler-times subfe 1 } } */
+/* { dg-final { scan-assembler-times addze 3 } } */
+
+long ne0(long a)
+{
+ return a != 0;
+}
+
+long plus_ne0(long a, long b)
+{
+ return (a != 0) + b;
+}
+
+void dummy(void);
+
+void cmp_plus_ne0(long a, long b)
+{
+ if ((a != 0) + b)
+dummy();
+}
+
+long plus_ne0_cmp(long a, long b)
+{
+ a = (a != 0) + b;
+ if (a)
+dummy();
+ return a;
+}
--
1.7.7.6
Re: [RFA 2/n] Don't lift loads above register using jumps in postreload-gcse.c
On Wednesday 05 September 2012 17:40:23 Steven Bosscher wrote:
On Wed, Sep 5, 2012 at 3:18 PM, Matthew Gretton-Dann
matthew.gretton-d...@linaro.org wrote:
On 5 September 2012 13:45, Richard Earnshaw rearn...@arm.com wrote:
On 05/09/12 13:02, Steven Bosscher wrote:
On Wed, Sep 5, 2012 at 1:42 PM, Matthew Gretton-Dann wrote:
Whilst this fix works for this particular case I am not sure it is the
best fix for the general issue, and so if others have a better idea how
to fix this I would be very happy.
postreload-gcse.c is broken in interesting ways. Look at this gem for
example:
static bool
reg_changed_after_insn_p (rtx x, int cuid)
{
unsigned int regno, end_regno;
regno = REGNO (x);
end_regno = END_HARD_REGNO (x);
do
if (reg_avail_info[regno] cuid)
return true;
while (++regno end_regno);
return false;
}
So the more conservative the fix, the better :-)
I suppose removing the pass is too conservative :-)
The patch looks correct to me. But perhaps the pass should just punt
on blocks not ending in a simple jump in
bb_has_well_behaved_predecessors?
By 'simple jump' you mean any block with at most only EDGE_FALLTHRU on the
edge?
No, I mean using the onlyjump_p predicate.
Again sorry for the delay. Attached is an updated patch using the onlyjump_p
predicate as suggested by Steven.
Tested cross arm-none-linux-gnueabi with QEmu.
OK for trunk?
Thanks,
Matt
gcc/ChangeLog:
2012-09-25 Matthew Gretton-Dann matthew.gretton-d...@arm.com
* postreload-gcse.c (bb_has_well_behaved_predecessors): Don't handle
blocks
that end in a non-simple jump.
--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-d...@linaro.orgdiff --git a/gcc/postreload-gcse.c b/gcc/postreload-gcse.c
index b9e9f25..412c8fc 100644
--- a/gcc/postreload-gcse.c
+++ b/gcc/postreload-gcse.c
@@ -925,6 +925,9 @@ bb_has_well_behaved_predecessors (basic_block bb)
if (JUMP_TABLE_DATA_P (BB_END (pred-src)))
return false;
+
+ if (onlyjump_p (BB_END (pred-src)))
+ return false;
}
return true;
}
Re: [RFA 2/n] Don't lift loads above register using jumps in postreload-gcse.c
On Tue, Sep 25, 2012 at 9:12 PM, Matthew Gretton-Dann matthew.gretton-d...@linaro.org wrote: No, I mean using the onlyjump_p predicate. Again sorry for the delay. Attached is an updated patch using the onlyjump_p predicate as suggested by Steven. + if (onlyjump_p (BB_END (pred-src))) Eh, don't you want (!onlyjump_p (BB_END (pred-src))) ? Note the not. You also have to deal with non-jump BB_END insns. Ciao! Steven
Re: [PATCH] rs6000: Add testcase for ne0 stuff
On Tue, Sep 25, 2012 at 2:28 PM, Segher Boessenkool seg...@kernel.crashing.org wrote: How's this? Segher 2012-09-25 Segher Boessenkool seg...@kernel.crashing.org gcc/testsuite/ * gcc.target/powerpc/ppc-ne0-1.c: New. Okay. Thanks, David
Re: add typedef printers to libstdc++
Magnus == Magnus Fromreide ma...@lysator.liu.se writes:
Magnus How does it display the types of the variables us, s and ss in the
Magnus following code:
It does what you'd expect.
Magnus I would expect it to say std::basic_stringunsigned char,...,
Magnus std::string and std::basic_stringsigned char,..., but I thought a test
Magnus case here couldn't hurt?
Here's an updated patch with the new tests.
Tom
2012-09-25 Tom Tromey tro...@redhat.com
* testsuite/libstdc++-prettyprinters/whatis.cc: New file.
* testsuite/lib/gdb-test.exp (whatis-test): New proc.
(gdb-test): Handle 'whatis' tests.
(gdb_batch_check): New proc.
(gdb_version_check): Rewrite to use gdb_batch_check.
* python/libstdcxx/v6/printers.py: Import gdb.types.
(FilteringTypePrinter): New class.
(add_one_type_printer, register_type_printers): New functions.
(register_libstdcxx_printers): Call register_type_printers.
diff --git a/libstdc++-v3/python/libstdcxx/v6/printers.py
b/libstdc++-v3/python/libstdcxx/v6/printers.py
index 0eac413..5b11cb0 100644
--- a/libstdc++-v3/python/libstdcxx/v6/printers.py
+++ b/libstdc++-v3/python/libstdcxx/v6/printers.py
@@ -26,6 +26,15 @@ try:
except ImportError:
_use_gdb_pp = False
+# Try to install type-printers.
+_use_type_printing = False
+try:
+import gdb.types
+if hasattr(gdb.types, 'TypePrinter'):
+_use_type_printing = True
+except ImportError:
+pass
+
# Starting with the type ORIG, search for the member type NAME. This
# handles searching upward through superclasses. This is needed to
# work around http://sourceware.org/bugzilla/show_bug.cgi?id=13615.
@@ -789,6 +798,97 @@ class Printer(object):
libstdcxx_printer = None
+class FilteringTypePrinter(object):
+def __init__(self, match, name):
+self.match = match
+self.name = name
+self.enabled = True
+
+class _recognizer(object):
+def __init__(self, match, name):
+self.match = match
+self.name = name
+self.type_obj = None
+
+def recognize(self, type_obj):
+if type_obj.tag is None:
+return None
+
+if self.type_obj is None:
+if not self.match in type_obj.tag:
+# Filter didn't match.
+return None
+try:
+self.type_obj = gdb.lookup_type(self.name).strip_typedefs()
+except:
+pass
+if self.type_obj == type_obj:
+return self.name
+return None
+
+def instantiate(self):
+return self._recognizer(self.match, self.name)
+
+def add_one_type_printer(obj, match, name):
+printer = FilteringTypePrinter(match, 'std::' + name)
+gdb.types.register_type_printer(obj, printer)
+
+def register_type_printers(obj):
+global _use_type_printing
+
+if not _use_type_printing:
+return
+
+for pfx in ('', 'w'):
+add_one_type_printer(obj, 'basic_string', pfx + 'string')
+add_one_type_printer(obj, 'basic_ios', pfx + 'ios')
+add_one_type_printer(obj, 'basic_streambuf', pfx + 'streambuf')
+add_one_type_printer(obj, 'basic_istream', pfx + 'istream')
+add_one_type_printer(obj, 'basic_ostream', pfx + 'ostream')
+add_one_type_printer(obj, 'basic_iostream', pfx + 'iostream')
+add_one_type_printer(obj, 'basic_stringbuf', pfx + 'stringbuf')
+add_one_type_printer(obj, 'basic_istringstream',
+ pfx + 'istringstream')
+add_one_type_printer(obj, 'basic_ostringstream',
+ pfx + 'ostringstream')
+add_one_type_printer(obj, 'basic_stringstream',
+ pfx + 'stringstream')
+add_one_type_printer(obj, 'basic_filebuf', pfx + 'filebuf')
+add_one_type_printer(obj, 'basic_ifstream', pfx + 'ifstream')
+add_one_type_printer(obj, 'basic_ofstream', pfx + 'ofstream')
+add_one_type_printer(obj, 'basic_fstream', pfx + 'fstream')
+add_one_type_printer(obj, 'basic_regex', pfx + 'regex')
+add_one_type_printer(obj, 'sub_match', pfx + 'csub_match')
+add_one_type_printer(obj, 'sub_match', pfx + 'ssub_match')
+add_one_type_printer(obj, 'match_results', pfx + 'cmatch')
+add_one_type_printer(obj, 'match_results', pfx + 'smatch')
+add_one_type_printer(obj, 'regex_iterator', pfx + 'cregex_iterator')
+add_one_type_printer(obj, 'regex_iterator', pfx + 'sregex_iterator')
+add_one_type_printer(obj, 'regex_token_iterator',
+ pfx + 'cregex_token_iterator')
+add_one_type_printer(obj, 'regex_token_iterator',
+ pfx + 'sregex_token_iterator')
+
+# Note that we can't have a printer for std::wstreampos, because
+# it shares the same underlying type as std::streampos.
+
[PATCH committed] Fix PR54704
Hi,
This patch (fixed by Richard, I just helped testing) fixes a bug in
the hash function which leads to too many collisions and a 3x compile
time overhead for tramp3d. After applying the patch, the compile time
of tramp3d returns to normal (the same as no block-location patch).
Bootstrapped and passed all gcc regression tests.
As the bug itself is obvious, I'll check in the patch to trunk now.
Thanks,
Dehao
libcpp/ChangeLog:
2012-09-25 Dehao Chen de...@google.com
PR middle-end/54704
* line-map.c (location_adhoc_data_hash): Fix the hash function.
Index: libcpp/line-map.c
===
--- libcpp/line-map.c (revision 191743)
+++ libcpp/line-map.c (working copy)
@@ -58,7 +58,7 @@ location_adhoc_data_hash (const void *l)
{
const struct location_adhoc_data *lb =
(const struct location_adhoc_data *) l;
- return (hashval_t) lb-locus + (size_t) lb-data;
+ return (hashval_t) lb-locus + (size_t) lb-data;
}
/* Compare function for location_adhoc_data hashtable. */
Re: Merge C++ conversion into trunk (4/6 - hash table rewrite)
On 8/15/12, Richard Henderson r...@redhat.com wrote: On 2012-08-15 07:29, Richard Guenther wrote: + typedef typename Element::Element_t Element_t; Can we use something less ugly than Element_t? Such as typedef typename Element::T T; ? Given that this name is scoped anyway... I've been finding the use of T as a typedef confusing. It sort of flies in the face of all existing convention. The C++ standard would use either element_type or value_type. I suggest a rename, but I'm guessing that folks don't want something as verbose as element_type. How about elemtype? Any objections to me changing it to that? -- Lawrence Crowl
Re: [PR54551] global dead debug pseudo tracking in fast-dce
On Sep 25, 2012, Jakub Jelinek ja...@redhat.com wrote: (the other alternative would be to use mode in the hash function etc., but if usually the same pseudo has the same mode everywhere, then the above should be good enough). AFAIK each pseudo is referenced everywhere using the same RTX; if so, it follows that it has the same mode in all uses. I believe the coding conventions ask to put the inlines outside of the class body, see e.g. coverage.c. I wasn't sure about one-liners; hash-table.h itself has inline one-liners, one of which I used as the basis for the descriptor. That said, the braces were not in separate lines. I'm going on a trip tomorrow morning, and I'll only return on Friday evening. I'll have a look at the C++ coding conventions and the other issues you brought up when I return. However, if you'd rather have the fix in before that, I won't mind if you pick it up from where I left. BTW, the patch fixes most of the (non-LTO) fails left in the http://gcc.gnu.org/ml/gcc-patches/2012-09/msg00711.html patch, good job! Cool! Thanks for the good news, and for the review. -- Alexandre Oliva, freedom fighterhttp://FSFLA.org/~lxoliva/ You must be the change you wish to see in the world. -- Gandhi Be Free! -- http://FSFLA.org/ FSF Latin America board member Free Software Evangelist Red Hat Brazil Compiler Engineer
Re: add typedef printers to libstdc++
Hi Tom, On 09/25/2012 10:53 PM, Tom Tromey wrote: Magnus == Magnus Fromreide ma...@lysator.liu.se writes: Magnus How does it display the types of the variables us, s and ss in the Magnus following code: It does what you'd expect. Magnus I would expect it to say std::basic_stringunsigned char,..., Magnus std::string and std::basic_stringsigned char,..., but I thought a test Magnus case here couldn't hurt? Here's an updated patch with the new tests. Jon knows the prettyprinters much better than me, but he is currently traveling. I guess, unless he has something to add over the next couple of days or so, let's go ahead. Thanks! Paolo.
Go patch committed: Better error for switch on non-comparable type
This patch to the Go frontend gives a better error message for a switch
on a non-comparable type. Bootstrapped and ran Go testsuite on
x86_64-unknown-linux-gnu. Committed to mainline and 4.7 branch.
Ian
diff -r 74d2d7d217d8 -r f47f5449a663 go/statements.cc
--- a/go/statements.cc Sat Sep 22 00:17:10 2012 -0700
+++ b/go/statements.cc Mon Sep 24 15:20:45 2012 -0700
@@ -3846,6 +3846,16 @@
return new Constant_switch_statement(this-val_, this-clauses_,
this-break_label_, loc);
+ if (this-val_ != NULL
+ !this-val_-type()-is_comparable()
+ !Type::are_compatible_for_comparison(true, this-val_-type(),
+ Type::make_nil_type(), NULL))
+{
+ error_at(this-val_-location(),
+ cannot switch on value whose type that may not be compared);
+ return Statement::make_error_statement(loc);
+}
+
Block* b = new Block(enclosing, loc);
if (this-clauses_-empty())
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[PATCH] Refactor the code to remove IS_UNKNOWN_LOCATION
IS_UNKNOWN_LOCATION is very misleading. This patch removes this macro
from input.h. For sites when checking LOCUS is intended, we explicit
use LOCATION_LOCUS and compare it to UNKNOWN_LOCATION.
Bootstrapped and passed all gcc regression tests.
Ok for trunk?
Thanks,
Dehao
gcc/ChangeLog:
2012-09-25 Dehao Chen de...@google.com
* gcc/tree.h (tree_constructor): Remove IS_UNKNOWN_LOCATION.
(extern void protected_set_expr_location): Likewise.
(function_args_iter_next): Likewise.
(inlined_function_outer_scope_p): Likewise.
* gcc/input.h (IS_UNKNOWN_LOCATION): Likewise.
* gcc/fold-const.c (expr_location_or): Likewise.
* gcc/lto-cgraph.c (output_node_opt_summary): Likewise.
* gcc/dwarf2out.c (add_src_coords_attributes): Likewise.
* gcc/tree-eh.c (lower_try_finally_dup_block): Likewise.
* gcc/profile.c (branch_prob):
* gcc/cfgexpand.c (expand_gimple_cond): Likewise.
(expand_gimple_basic_block): Likewise.
(construct_exit_block): Likewise.
(gimple_expand_cfg): Likewise.
* gcc/cfgcleanup.c (try_forward_edges): Likewise.
* gcc/tree-ssa-live.c (remove_unused_scope_block_p): Likewise.
(dump_scope_block): Likewise.
* gcc/ipa-prop.c (ipa_write_jump_function): Likewise.
* gcc/rtl.h (extern void rtl_check_failed_flag): Likewise.
* gcc/gimple.h (gimple_set_location): Likewise.
(gimple_has_location): Likewise.
* gcc/cfgrtl.c (unique_locus_on_edge_between_p): Likewise.
(force_nonfallthru_and_redirect): Likewise.
(fixup_reorder_chain): Likewise.
(cfg_layout_merge_blocks): Likewise.
Index: gcc/tree.h
===
--- gcc/tree.h (revision 191746)
+++ gcc/tree.h (working copy)
@@ -1612,7 +1612,8 @@ struct GTY(()) tree_constructor {
#define EXPR_LOCATION(NODE) \
(CAN_HAVE_LOCATION_P ((NODE)) ? (NODE)-exp.locus : UNKNOWN_LOCATION)
#define SET_EXPR_LOCATION(NODE, LOCUS) EXPR_CHECK ((NODE))-exp.locus = (LOCUS)
-#define EXPR_HAS_LOCATION(NODE) (!IS_UNKNOWN_LOCATION (EXPR_LOCATION (NODE)))
+#define EXPR_HAS_LOCATION(NODE) (LOCATION_LOCUS (EXPR_LOCATION (NODE)) \
+ != UNKNOWN_LOCATION)
/* The location to be used in a diagnostic about this expression. Do not
use this macro if the location will be assigned to other expressions. */
#define EXPR_LOC_OR_HERE(NODE) (EXPR_HAS_LOCATION (NODE) ? (NODE)-exp.locus :
input_location)
@@ -1791,7 +1792,8 @@ extern void protected_set_expr_location (tree, loc
OMP_CLAUSE_PRIVATE, \
OMP_CLAUSE_COPYPRIVATE), 0)
#define OMP_CLAUSE_HAS_LOCATION(NODE) \
- (!IS_UNKNOWN_LOCATION ((OMP_CLAUSE_CHECK (NODE))-omp_clause.locus))
+ (LOCATION_LOCUS ((OMP_CLAUSE_CHECK (NODE))-omp_clause.locus)
\
+ != UNKNOWN_LOCATION)
#define OMP_CLAUSE_LOCATION(NODE) (OMP_CLAUSE_CHECK (NODE))-omp_clause.locus
/* True on an OMP_SECTION statement that was the last lexical member.
@@ -5535,7 +5537,7 @@ function_args_iter_next (function_args_iterator *i
static inline bool
inlined_function_outer_scope_p (const_tree block)
{
- return !IS_UNKNOWN_LOCATION (BLOCK_SOURCE_LOCATION (block));
+ return LOCATION_LOCUS (BLOCK_SOURCE_LOCATION (block)) != UNKNOWN_LOCATION;
}
/* Loop over all function arguments of FNTYPE. In each iteration, PTR is set
Index: gcc/input.h
===
--- gcc/input.h (revision 191746)
+++ gcc/input.h (working copy)
@@ -56,9 +56,6 @@ extern location_t input_location;
#define LOCATION_BLOCK(LOC) \
((tree) ((IS_ADHOC_LOC (LOC)) ? get_data_from_adhoc_loc (line_table, (LOC)) \
: NULL))
-#define IS_UNKNOWN_LOCATION(LOC) \
- ((IS_ADHOC_LOC (LOC)) ? get_location_from_adhoc_loc (line_table, LOC) == 0 \
- : (LOC) == 0)
#define input_line LOCATION_LINE (input_location)
#define input_filename LOCATION_FILE (input_location)
Index: gcc/fold-const.c
===
--- gcc/fold-const.c(revision 191746)
+++ gcc/fold-const.c(working copy)
@@ -145,7 +145,7 @@ static location_t
expr_location_or (tree t, location_t loc)
{
location_t tloc = EXPR_LOCATION (t);
- return IS_UNKNOWN_LOCATION (tloc) ? loc : tloc;
+ return tloc == UNKNOWN_LOCATION ? loc : tloc;
}
/* Similar to protected_set_expr_location, but never modify x in place,
Index: gcc/lto-cgraph.c
===
--- gcc/lto-cgraph.c(revision 191746)
+++ gcc/lto-cgraph.c(working copy)
@@ -1412,7 +1412,7 @@ output_node_opt_summary (struct output_block *ob,
mechanism to store function local declarations into summaries. */
gcc_assert (parm);
streamer_write_uhwi (ob, parm_num);
- gcc_assert (IS_UNKNOWN_LOCATION (EXPR_LOCATION (map-new_tree)));
+ gcc_assert
