Fix COMDAT_GROUP dissolving in ipa.c

[Jan Hubicka]

Hi,
this is a problem I noticed in libreoffice.  When disolving COMDAT group,
we should turn WEAKs into normal symbols.

Bootstrapped/regtested x86_64-linux, comited.


* ipa.c (function_and_variable_visibility): Also clear WEAK
flag when disolving COMDAT_GROUP.
Index: ipa.c
===
--- ipa.c   (revision 207870)
+++ ipa.c   (working copy)
@@ -1027,7 +1027,10 @@ function_and_variable_visibility (bool w
for (next = node->same_comdat_group;
 next != node;
 next = next->same_comdat_group)
+   {
  DECL_COMDAT_GROUP (next->decl) = NULL;
+ DECL_WEAK (next->decl) = false;
+   }
  DECL_COMDAT_GROUP (node->decl) = NULL;
  symtab_dissolve_same_comdat_group_list (node);
}

[patch] Shorten Windows path

[Joey Ye]

Max length of path on Windows is 255, which is easy to exceed in a
complicated project. Ultimate solution may be complex but canonizing the
path and skipping the ".."s in path is helpful.

Relative discussion in gcc-patches:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg00582.html

OK to trunk stage 1?

ChangeLog.libcpp:
* files.c (find_file_in_dir): Always try to shorten for DOS.

diff --git a/libcpp/files.c b/libcpp/files.c
index 7e88778..9dcc71f 100644
--- a/libcpp/files.c
+++ b/libcpp/files.c
@@ -386,9 +386,18 @@ find_file_in_dir (cpp_reader *pfile, _cpp_file *file,
bool *invalid_pch)
   hashval_t hv;
   char *copy;
   void **pp;
+  bool do_canonical;
 
+#ifdef HAVE_DOS_BASED_FILE_SYSTEM
+  /* For DOS based file system, we always try to shorten file path
+   * to as it has a shorter constraint on max path length.  */
+  do_canonical = true;
+#else
   /* We try to canonicalize system headers.  */
-  if (CPP_OPTION (pfile, canonical_system_headers) && file->dir->sysp)
+  do_canonical = (CPP_OPTION (pfile, canonical_system_headers)
+  && file->dir->sysp);
+#endif
+  if ( do_canonical )
{
  char * canonical_path = maybe_shorter_path (path);
  if (canonical_path)

max_path_joey-140109-1.patch
Description: Binary data

Re: Fix three issues in ipa-prop

[Jan Hubicka]

Hi,
this is patch I ended up comitting.  THere was one additional problem with
ICE when param_type happens to be VOID pointer.

* ipa-prop.h (ipa_ancestor_jf_data): Update ocmment.
* ipa-prop.c (ipa_set_jf_known_type): Return early when
not devirtualizing.
(ipa_set_ancestor_jf): Set type to NULL hwen it is not preserved;
do more sanity checks.
(detect_type_change): Return true when giving up early.
(compute_complex_assign_jump_func): Fix type parameter of
ipa_set_ancestor_jf.
(compute_complex_ancestor_jump_func): Likewise.
(update_jump_functions_after_inlining): Fix updating of
ancestor function.
* ipa-cp.c (ipa_get_jf_ancestor_result): Be ready for type
to be NULL.
Index: ipa-prop.h
===
--- ipa-prop.h  (revision 207870)
+++ ipa-prop.h  (working copy)
@@ -130,7 +130,9 @@ struct GTY(()) ipa_ancestor_jf_data
 {
   /* Offset of the field representing the ancestor.  */
   HOST_WIDE_INT offset;
-  /* Type of the result.  */
+  /* Type of the result.
+ When TYPE_PRESERVED is false, TYPE is NULL, since it is only
+ relevant for the devirtualization machinery.  */
   tree type;
   /* Number of the caller's formal parameter being passed.  */
   int formal_id;
Index: ipa-prop.c
===
--- ipa-prop.c  (revision 207870)
+++ ipa-prop.c  (working copy)
@@ -393,6 +393,9 @@ ipa_set_jf_known_type (struct ipa_jump_f
 {
   gcc_assert (TREE_CODE (component_type) == RECORD_TYPE
  && TYPE_BINFO (component_type));
+  if (!flag_devirtualize)
+return;
+  gcc_assert (BINFO_VTABLE (TYPE_BINFO (component_type)));
   jfunc->type = IPA_JF_KNOWN_TYPE;
   jfunc->value.known_type.offset = offset,
   jfunc->value.known_type.base_type = base_type;
@@ -477,10 +480,16 @@ ipa_set_ancestor_jf (struct ipa_jump_fun
 tree type, int formal_id, bool agg_preserved,
 bool type_preserved)
 {
+  if (!flag_devirtualize)
+type_preserved = false;
+  gcc_assert (!type_preserved
+ || (TREE_CODE (type) == RECORD_TYPE
+ && TYPE_BINFO (type)
+ && BINFO_VTABLE (TYPE_BINFO (type;
   jfunc->type = IPA_JF_ANCESTOR;
   jfunc->value.ancestor.formal_id = formal_id;
   jfunc->value.ancestor.offset = offset;
-  jfunc->value.ancestor.type = type;
+  jfunc->value.ancestor.type = type_preserved ? type : NULL;
   jfunc->value.ancestor.agg_preserved = agg_preserved;
   jfunc->value.ancestor.type_preserved = type_preserved;
 }
@@ -686,7 +695,7 @@ detect_type_change (tree arg, tree base,
   || TREE_CODE (comp_type) != RECORD_TYPE
   || !TYPE_BINFO (comp_type)
   || !BINFO_VTABLE (TYPE_BINFO (comp_type)))
-return false;
+return true;
 
   /* C++ methods are not allowed to change THIS pointer unless they
  are constructors or destructors.  */
@@ -1103,7 +1112,8 @@ compute_complex_assign_jump_func (struct
   bool type_p = !detect_type_change (op1, base, TREE_TYPE (param_type),
 call, jfunc, offset);
   if (type_p || jfunc->type == IPA_JF_UNKNOWN)
-   ipa_set_ancestor_jf (jfunc, offset, TREE_TYPE (op1), index,
+   ipa_set_ancestor_jf (jfunc, offset,
+type_p ? TREE_TYPE (param_type) : NULL, index,
 parm_ref_data_pass_through_p (&parms_ainfo[index],
   call, ssa), type_p);
 }
@@ -1236,7 +1246,7 @@ compute_complex_ancestor_jump_func (stru
 type_p = !detect_type_change (obj, expr, TREE_TYPE (param_type),
  call, jfunc, offset);
   if (type_p || jfunc->type == IPA_JF_UNKNOWN)
-ipa_set_ancestor_jf (jfunc, offset, TREE_TYPE (obj), index,
+ipa_set_ancestor_jf (jfunc, offset, type_p ? TREE_TYPE (param_type) : 
NULL, index,
 parm_ref_data_pass_through_p (&parms_ainfo[index],
   call, parm), type_p);
 }
@@ -2391,7 +2401,7 @@ update_jump_functions_after_inlining (st
ipa_set_jf_known_type (dst,
   ipa_get_jf_known_type_offset (src),
   ipa_get_jf_known_type_base_type 
(src),
-  ipa_get_jf_known_type_base_type 
(src));
+  ipa_get_jf_known_type_component_type 
(src));
  else
dst->type = IPA_JF_UNKNOWN;
  break;
Index: ipa-cp.c
===
--- ipa-cp.c(revision 207870)
+++ ipa-cp.c(working copy)
@@ -798,7 +798,9 @@ ipa_get_jf_ancestor_result (struct ipa_j
   tree t = TREE_OPERAND (input, 0);
   t = build_ref_for_offset (EXPR_LOCATION (t), t,

Fix ICE when call is optimized out during clone materialization

[Jan Hubicka]

Hi,
this patch fixes ICE while building Qt 5 with LTO.  When call is optimized out
and removed by cgraph_update_edges_for_call_stmt_node, we must also eliminate
inline clones, or the verifier will complain.

Bootstrapped/regtested x86_64-linux, comitted.

2014-02-18  Jan Hubicka  

* cgraph.c (cgraph_update_edges_for_call_stmt_node): Also remove
inline clones when edge disappears.

Index: cgraph.c
===
--- cgraph.c(revision 207870)
+++ cgraph.c(working copy)
@@ -1529,7 +1529,10 @@ cgraph_update_edges_for_call_stmt_node (
 attached to edge is invalid.  */
  count = e->count;
  frequency = e->frequency;
- cgraph_remove_edge (e);
+ if (e->indirect_unknown_callee || e->inline_failed)
+   cgraph_remove_edge (e);
+ else
+   cgraph_remove_node_and_inline_clones (e->callee, NULL);
}
   else if (new_call)
{

cleaning up and c++ifying bitmaps

[Trevor Saunders]

Hi,

 I've been working on c++ifying bitmaps and while there make them a
 little faster.  My current work is in the tbsaunde/bitmap git branch
 please look and give comments :)

 Some interesting differences
 -745 LOC
 averaged over 10 runs with a --enable-checking=release g++ on one
 ~334kloc .i compiled with -)3
 +300k rss (not sure why need to look soon)
 -0.04s

 I think the bitmap API is pretty reasonable at this point, but I'd like
 to do something about the bitmap obstacks, they make things a bit messy
 than they might otherwise be.

thanks!

 Trev

Re: [patch] Fix array overflow in gcc.dg/vect/no-vfa-vect-depend-2.c

[Jakub Jelinek]

On Tue, Feb 18, 2014 at 06:24:17PM -0800, Paul Pluzhnikov wrote:
> Jakub,
> 
> On Mon, Feb 10, 2014 at 12:09 AM, Jakub Jelinek  wrote:
> > On Tue, Feb 04, 2014 at 04:59:14PM -0800, Paul Pluzhnikov wrote:
> >> gcc/testsuite/ChangeLog:
> >>
> >> 2014-02-04  Paul Pluzhnikov  
> >>
> >>   * gcc.dg/vect/no-vfa-vect-depend-2.c (main1): Fix buffer
> >>   overflow.
> >
> > Ok, thanks.
> 
> Sorry, did you vouch for this:
> 
> -  for (i = N - 1; i >= 0; i--)
> +  for (i = N - 2; i >= 0; i--)

This one.

Jakub

Re: [patch] Fix array overflow in gcc.dg/vect/no-vfa-vect-depend-2.c

[Paul Pluzhnikov]

Jakub,

On Mon, Feb 10, 2014 at 12:09 AM, Jakub Jelinek  wrote:
> On Tue, Feb 04, 2014 at 04:59:14PM -0800, Paul Pluzhnikov wrote:
>> gcc/testsuite/ChangeLog:
>>
>> 2014-02-04  Paul Pluzhnikov  
>>
>>   * gcc.dg/vect/no-vfa-vect-depend-2.c (main1): Fix buffer
>>   overflow.
>
> Ok, thanks.

Sorry, did you vouch for this:

-  for (i = N - 1; i >= 0; i--)
+  for (i = N - 2; i >= 0; i--)

or that:

-int ia[N] = {48,45,42,39,36,33,30,27,24,21,18,15,12,9,6,3,0};
+int ia[N + 1] = {48,45,42,39,36,33,30,27,24,21,18,15,12,9,6,3,0};


Thanks,
-- 
Paul Pluzhnikov

[PATCH][committed] two minor fixes in libcilkrts

[Iyer, Balaji V]

Hello Everyone,
This patch will fix two minor issues in libcilkrts. First being that we 
default to ABI 0 and secondly, fix an issue to initialize the stack frame 
correctly. All the changes are in libcilkrts and does not cause any regression 
failures.

Thanks,

Balaji V. Iyer.
diff --git a/libcilkrts/ChangeLog b/libcilkrts/ChangeLog
index c340785..434b974 100644
--- a/libcilkrts/ChangeLog
+++ b/libcilkrts/ChangeLog
@@ -1,3 +1,10 @@
+2014-02-18  Balaji V. Iyer  
+
+   * include/cilk/common.h (__CILKRTS_ABI_VERSION): Set the ABI version
+   to 1 instead of 0.
+   * runtime/cilk-abi-cilk-for.cpp (cilk_for_recursive): Added a fix to
+   initialize stack frame correctly.
+
 2014-02-10  Balaji V. Iyer  
 
PR target/59691
diff --git a/libcilkrts/include/cilk/common.h b/libcilkrts/include/cilk/common.h
index d2c84fa..97dd66e 100644
--- a/libcilkrts/include/cilk/common.h
+++ b/libcilkrts/include/cilk/common.h
@@ -317,13 +317,12 @@ namespace cilk {
 #ifndef __CILKRTS_ABI_VERSION
 #   ifdef IN_CILK_RUNTIME
 #   define __CILKRTS_ABI_VERSION 1
-#   elif __INTEL_COMPILER > 1200
-// Intel compiler version >= 12.1
-#   define __CILKRTS_ABI_VERSION 1
-#   else
-// Compiler does not support ABI version 1
-// (Non-Intel compiler or Intel compiler prior to version 12.1).
+#   elif defined(__INTEL_COMPILER) && (__INTEL_COMPILER <= 1200)
+// Intel compilers prior to version 12.1 support only ABI 0
 #   define __CILKRTS_ABI_VERSION 0
+#   else
+// Non-Intel compiler or Intel compiler after version 12.0.
+#   define __CILKRTS_ABI_VERSION 1
 #   endif
 #endif
 
diff --git a/libcilkrts/runtime/cilk-abi-cilk-for.cpp 
b/libcilkrts/runtime/cilk-abi-cilk-for.cpp
index 4fa6dce..4cd04f5 100644
--- a/libcilkrts/runtime/cilk-abi-cilk-for.cpp
+++ b/libcilkrts/runtime/cilk-abi-cilk-for.cpp
@@ -256,9 +256,19 @@ tail_recurse:
 // argument list of the spawned function, hence the call to
 // capture_spawn_arg_stack_frame().
 __cilkrts_stack_frame *sf;
+#if defined(__GNUC__) && ! defined(__INTEL_COMPILER) && ! defined(__clang__)
+// The current version of gcc initializes the sf structure eagerly.
+// We can take advantage of this fact to avoid calling
+// `capture_spawn_arg_stack_frame` when compiling with gcc.
+// Remove this if the "shrink-wrap" optimization is implemented.
+sf = w->current_stack_frame;
+_Cilk_spawn cilk_for_recursive(low, mid, body, data, grain, w,
+   loop_root_pedigree);
+#else
 _Cilk_spawn cilk_for_recursive(low, mid, body, data, grain,
capture_spawn_arg_stack_frame(sf, w),
loop_root_pedigree);
+#endif
 w = sf->worker;
 low = mid;
 

Re: [PATCH] PR 60203, fix little endian breakage of my PR 60203 fix

[David Edelsohn]

On Tue, Feb 18, 2014 at 5:08 PM, Michael Meissner
 wrote:
> When I made my patches for PR target/60203 (allow use of ISA 2.07 direct move
> instructions for long double and _Decimal128), I was not aware that little
> endian TDmode has the double words in big endian order, but the bytes within
> the double words in little endian order in memory.  This means that normal
> SUBREG's of TDmode is not allowed.  That patch broke the little endian build,
> and this patch fixes it.  In this patch, I don't allow doing direct move of
> TDmode in little endian.
>
> I have done bootstraps and make check on a big endian power7, big endian
> power8, and little endian power8 systems.  The two big endian systems 
> introduce
> no regressions with the patch applied and without the patch.  The little 
> endian
> system now builds, and runs the test suite.  Is this patch ok to apply?
>
> I did not write a test case, as the normal bootstrap on a little endian power8
> system will catch regressions in the future.
>
> 2014-02-18  Michael Meissner  
>
> PR target/60203
> * config/rs6000/rs6000.md (mov_64bit, TF/TDmode moves):
> Split 64-bit moves into 2 patterns.  Do not allow the use of
> direct move for TDmode in little endian, since the decimal value
> has little endian bytes within a word, but the 64-bit pieces are
> ordered in a big endian fashion, and normal subreg's of TDmode are
> not allowed.

Okay.

Thanks, David

Re: [C PATCH] Kill bogus warnings on _Atomics (PR c/60195)

[Joseph S. Myers]

On Tue, 18 Feb 2014, Marek Polacek wrote:

> This PR is about bogus warnings on _Atomics.  E.g., for _Atomic int,
> the warning "right-hand operand of comma has no effect" makes no sense.  One
> problem was that when making COMPOUND_EXPR out of atomic variable, we create
> artificial variable via create_tmp_var, but we shouldn't warn on those.  So
> I've set TREE_NO_WARNING on such variables.
> Another issue is that we warned that a variable is unused, even when it's
> actually used in __atomic_load; mark_exp_read fixed it.
> 
> Also I noticed a typo, so fixed (s/val/old/).
> 
> Regtested/bootstrapped on x86_64-linux, ok for 5.0?  (Or 4.9 instead?)

OK for 4.9.

-- 
Joseph S. Myers
jos...@codesourcery.com

Re: [PATCH] Fix -ftrack-macro-expansion preprocessing of A######A (PR preprocessor/58844)

[Joseph S. Myers]

On Tue, 18 Feb 2014, Jakub Jelinek wrote:

> Hi!
> 
> The following testcase build with -ftrack-macro-expansion=0,
> but don't build otherwise.  The problem seems to be that
> the libcpp for macro redefinition warning/error purposes if it sees
> more than one paste operator adds those extra CPP_PASTE tokens at the end,
> after normal tokens from the macro.  For -ftrack-macro-expansion=0 we were
> using macro_real_token_count (macro) to only use the real tokens for macro
> expansion purposes, but for track_macro_expansion it used macro->count,
> which includes also the extra tokens.
> 
> Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux,
> ok for trunk (and after a while for 4.8)?

OK.

-- 
Joseph S. Myers
jos...@codesourcery.com

Re: [5.0] PR60194 [c-family] add -Wformat-signedness to warn about %d/%u signedness mismatch

[Joseph S. Myers]

On Tue, 18 Feb 2014, Tobias Burnus wrote:

> This patch adds a warning to -Wformat=2, which can also be used as
> -Wformat -Wformat-signedness and which warns when the signedness
> of the argument doesn't match the one of %x/%u/%d/%i/...
> 
> That was motivated by a check of cppcheck, which found some issues
> in a bigger code.
> 
> Bootstrapped and regtested on x86-64-gnu-linux.
> OK when Stage 1 opens again?

OK.

-- 
Joseph S. Myers
jos...@codesourcery.com

Fix PR tree-optimization/60174

[Eric Botcazou]

This is the failure of ACATS cc3305a on the ARM:

Unable to coalesce ssa_names 34 and 399 which are marked as MUST COALESCE.
i_34(ab) and  i_399(ab)
+===GNAT BUG DETECTED==+
| 4.9.0 20140209 (experimental) (armv7l-unknown-linux-gnueabihf) GCC error:|
| SSA corruption   |
| Error detected around cc3305a.adb:35:1

It's reassociation, namely optimize_range_tests, doing SSA_NAME propagation 
when building ranges in init_range_entry.  Immediate fix attached, tested on 
x86_64-suse-linux, pre-approved by Jakub and applied on the mainline.


2014-02-18  Eric Botcazou  

PR tree-optimization/60174
* tree-ssa-reassoc.c (init_range_entry): Do not look into the defining
statement of an SSA_NAME that occurs in an abnormal PHI node.


-- 
Eric BotcazouIndex: tree-ssa-reassoc.c
===
--- tree-ssa-reassoc.c	(revision 207796)
+++ tree-ssa-reassoc.c	(working copy)
@@ -1840,7 +1840,8 @@ init_range_entry (struct range_entry *r,
 
   if (exp != NULL_TREE)
 	{
-	  if (TREE_CODE (exp) != SSA_NAME)
+	  if (TREE_CODE (exp) != SSA_NAME
+	  || SSA_NAME_OCCURS_IN_ABNORMAL_PHI (exp))
 	break;
 
 	  stmt = SSA_NAME_DEF_STMT (exp);

Re: [PATCH] Fix PR c++/60064.

[Jason Merrill]

OK.

Jason

[PATCH] Fix PR c++/60064.

[Adam Butcher]

PR c++/60064
* parser.c (cp_parser_member_declaration): Pop fully implicit template
scope for generic friend declarations as well as for non-friends.

PR c++/60064
* g++.dg/cpp1y/pr60064.C: New testcase.
---
 gcc/cp/parser.c  |  8 +++-
 gcc/testsuite/g++.dg/cpp1y/pr60064.C | 21 +
 2 files changed, 24 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr60064.C

diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 23d54fb..9818213 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -20406,13 +20406,11 @@ cp_parser_member_declaration (cp_parser* parser)
  &decl_specifiers,
  declarator,
  attributes);
+ if (parser->fully_implicit_function_template_p)
+   decl = finish_fully_implicit_template (parser, decl);
  /* If the member was not a friend, declare it here.  */
  if (!friend_p)
-   {
- if (parser->fully_implicit_function_template_p)
-   decl = finish_fully_implicit_template (parser, decl);
- finish_member_declaration (decl);
-   }
+   finish_member_declaration (decl);
  /* Peek at the next token.  */
  token = cp_lexer_peek_token (parser->lexer);
  /* If the next token is a semicolon, consume it.  */
diff --git a/gcc/testsuite/g++.dg/cpp1y/pr60064.C 
b/gcc/testsuite/g++.dg/cpp1y/pr60064.C
new file mode 100644
index 000..21b043d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/pr60064.C
@@ -0,0 +1,21 @@
+// PR c++/60064
+// { dg-do compile }
+// { dg-options "-std=c++1y" }
+
+class A
+{
+  int m;
+  friend void foo (auto) {}
+  friend void foo2 (auto);
+};
+
+void foo2 (auto i)
+{
+  A a;
+  a.m = i;
+}
+
+int main ()
+{
+  foo2 (7);
+}
-- 
1.8.5.5

Re: [PATCH] PR 60203, fix little endian breakage of my PR 60203 fix

[Michael Meissner]

Whoops, the ChangeLog entry was not complete:

2014-02-18  Michael Meissner  

PR target/60203
* config/rs6000/rs6000.md (mov_64bit, TF/TDmode moves):
Split 64-bit moves into 2 patterns.  Do not allow the use of
direct move for TDmode in little endian, since the decimal value
has little endian bytes within a word, but the 64-bit pieces are
ordered in a big endian fashion, and normal subreg's of TDmode are
not allowed.
(mov_64bit_dm): Likewise.
(movtd_64bit_nodm): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [Patch, Fortran] PR49397 - Fix ICE with proc-pointers

[Tobias Burnus]

Hi Janus,

Janus Weil wrote:
your patch basically looks good to me. One minor nit about the 
trans-decl.c part: The comment above the code that you're changing 
("Only used for ...") seems wrong after the change.


Well, it also was kind of wrong before the change as well; I have 
changed it to:


   if (sym->attr.flavor == FL_PROCEDURE)
 {
-  /* Catch function declarations. Only used for actual parameters,
+  /* Catch functions. Only used for actual parameters,
 procedure pointers and procptr initialization targets.  */


Maybe just remove that sentence? About the previous version of the 
patch (in bugzilla) I was wondering if setting the EXTERNAL attribute 
is really the correct thing to do, but it seems that is not done any 
more in this version. To my taste the patch is ok for all of trunk, 
4.8 and 4.7. 


I also find it a bit problematic - an explicit "external" is (slightly) 
different to implicitly using it. In any case, the original version 
causes ICEs with some testcases, e.g. bessel_3.f90.


Committed as Rev. 207854 for the trunk; I will wait a while before 
backporting to 4.8 and 4.7.


Tobias

Re: Allow passing arrays in registers on AArch64

[Michael Hudson-Doyle]

Jakub Jelinek  writes:

> On Tue, Feb 11, 2014 at 02:51:08PM +, Marcus Shawcroft wrote:
>> On 6 February 2014 22:51, Michael Hudson-Doyle
>>  wrote:
>> 
>> > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
>> > index 16c51a8..958c667 100644
>> > --- a/gcc/config/aarch64/aarch64.c
>> > +++ b/gcc/config/aarch64/aarch64.c
>> > @@ -1187,14 +1187,10 @@ aarch64_pass_by_reference (cumulative_args_t pcum 
>> > ATTRIBUTE_UNUSED,
>> >size = (mode == BLKmode && type)
>> >  ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
>> >
>> > -  if (type)
>> > +  /* Aggregates are passed by reference based on their size.  */
>> > +  if (type && AGGREGATE_TYPE_P (type))
>> >  {
>> > -  /* Arrays always passed by reference.  */
>> > -  if (TREE_CODE (type) == ARRAY_TYPE)
>> > -   return true;
>> > -  /* Other aggregates based on their size.  */
>> > -  if (AGGREGATE_TYPE_P (type))
>> > -   size = int_size_in_bytes (type);
>> > +  size = int_size_in_bytes (type);
>> >  }
>> >
>> >/* Variable sized arguments are always returned by reference.  */
>> 
>> This version of the patch looks fine.  Since this is a bug I think it
>> should be committed now in stage 4.This is OK if release manager
>> agrees.
>
> Ok.

So, um, can someone commit this please?

Cheers,
mwh

[PATCH] PR 60203, fix little endian breakage of my PR 60203 fix

[Michael Meissner]

When I made my patches for PR target/60203 (allow use of ISA 2.07 direct move
instructions for long double and _Decimal128), I was not aware that little
endian TDmode has the double words in big endian order, but the bytes within
the double words in little endian order in memory.  This means that normal
SUBREG's of TDmode is not allowed.  That patch broke the little endian build,
and this patch fixes it.  In this patch, I don't allow doing direct move of
TDmode in little endian.

I have done bootstraps and make check on a big endian power7, big endian
power8, and little endian power8 systems.  The two big endian systems introduce
no regressions with the patch applied and without the patch.  The little endian
system now builds, and runs the test suite.  Is this patch ok to apply?

I did not write a test case, as the normal bootstrap on a little endian power8
system will catch regressions in the future.

2014-02-18  Michael Meissner  

PR target/60203
* config/rs6000/rs6000.md (mov_64bit, TF/TDmode moves):
Split 64-bit moves into 2 patterns.  Do not allow the use of
direct move for TDmode in little endian, since the decimal value
has little endian bytes within a word, but the 64-bit pieces are
ordered in a big endian fashion, and normal subreg's of TDmode are
not allowed.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===
--- gcc/config/rs6000/rs6000.md (revision 207853)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -9526,10 +9526,16 @@ (define_expand "mov"
 ;; It's important to list Y->r and r->Y before r->r because otherwise
 ;; reload, given m->r, will try to pick r->r and reload it, which
 ;; doesn't make progress.
-(define_insn_and_split "*mov_64bit"
+
+;; We can't split little endian direct moves of TDmode, because the words are
+;; not swapped like they are for TImode or TFmode.  Subregs therefore are
+;; problematical.  Don't allow direct move for this case.
+
+(define_insn_and_split "*mov_64bit_dm"
   [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
(match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
   "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
+   && (mode != TDmode || WORDS_BIG_ENDIAN)
&& (gpc_reg_operand (operands[0], mode)
|| gpc_reg_operand (operands[1], mode))"
   "#"
@@ -9538,6 +9544,18 @@ (define_insn_and_split "*mov_64bit
 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
   [(set_attr "length" "8,8,8,12,12,8,8,8")])
 
+(define_insn_and_split "*movtd_64bit_nodm"
+  [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
+   (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
+   && (gpc_reg_operand (operands[0], TDmode)
+   || gpc_reg_operand (operands[1], TDmode))"
+  "#"
+  "&& reload_completed"
+  [(pc)]
+{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
+  [(set_attr "length" "8,8,8,12,12,8")])
+
 (define_insn_and_split "*mov_32bit"
   [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
(match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]

RE: [PATCH] Properly check for _Cilk_spawn in return stmt (PR c/60197)

[Iyer, Balaji V]

> Yeah, it passed regtesting.  Note that we also ICE on e.g.
> int
> foo (void)
> {
>   int i;
>   i = (_Cilk_spawn foo ()) + 1;
>   return i;
> }
> 
> I don't know whether this is valid use of _Cilk_spawn though.  In any case,
> this patch addresses only _Cilk_spawn in return statements.

This is invalid.

Thanks,

Balaji V. Iyer.

Re: [AArch64 09/14] Add special cases of zero-extend w/ compare operations.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:

Can you add a testcase or two for this patch?  Having an example will
help people in the future understand why these patterns are added.

Thanks,
Andrew Pinski


> ---
>  gcc/config/aarch64/aarch64.md | 56 
> +++
>  1 file changed, 56 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 60e42af..c72d123 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2227,6 +2227,62 @@
>[(set_attr "type" "alus_ext")]
>  )
>
> +(define_insn "*zextqi3_compare0"
> +  [(set (reg:CC_ZESWP CC_REGNUM)
> +(compare:CC_ZESWP
> + (zero_extend:GPI (match_operand:QI 1 "register_operand" "r"))
> + (const_int 0)))
> +   (set (match_operand:GPI 0 "register_operand" "=r")
> +(zero_extend:GPI (match_dup 1)))]
> +  ""
> +  "ands\\t%0, %1, 0xFF"
> +  [(set_attr "type" "logics_imm")]
> +)
> +
> +(define_insn "*zexthi3_compare0"
> +  [(set (reg:CC_ZESWP CC_REGNUM)
> +(compare:CC_ZESWP
> + (zero_extend:GPI (match_operand:HI 1 "register_operand" "r"))
> + (const_int 0)))
> +   (set (match_operand:GPI 0 "register_operand" "=r")
> +(zero_extend:GPI (match_dup 1)))]
> +  ""
> +  "ands\\t%0, %1, 0x"
> +  [(set_attr "type" "logics_imm")]
> +)
> +
> +(define_insn "*zextdisi3_compare0"
> +  [(set (reg:CC_ZESWP CC_REGNUM)
> +(compare:CC_ZESWP
> + (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
> + (const_int 0)))
> +   (set (match_operand:DI 0 "register_operand" "=r")
> +(zero_extend:DI (match_dup 1)))]
> +  ""
> +  "ands\\t%x0, %x1, 0x"
> +  [(set_attr "type" "logics_imm")]
> +)
> +
> +(define_insn "*zextqi3nr_compare0"
> +  [(set (reg:CC_ZESWP CC_REGNUM)
> +(compare:CC_ZESWP
> + (match_operand:QI 0 "register_operand" "r")
> + (const_int 0)))]
> +  ""
> +  "tst\\t%w0, 0xFF"
> +  [(set_attr "type" "logics_imm")]
> +)
> +
> +(define_insn "*zexthi3nr_compare0"
> +  [(set (reg:CC_ZESWP CC_REGNUM)
> +(compare:CC_ZESWP
> + (match_operand:HI 0 "register_operand" "r")
> + (const_int 0)))]
> +  ""
> +  "tst\\t%w0, 0x"
> +  [(set_attr "type" "logics_imm")]
> +)
> +
>  ;; ---
>  ;; Store-flag and conditional select insns
>  ;; ---
> --
> 1.9.0
>

Re: [AArch64 08/14] Define a variant of cmp for the CC_NZ case.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:
> This pattern is not strictly necessary and a similar effect could
> be achieved through the use of a suitable compatibility relation
> for CC modes; in the meantime, this helps on some benchmarks.


Can you add a testcase or two for this patch?  Having an example will
help people in the future understand why these patterns are added.

Thanks,
Andrew Pinski

> ---
>  gcc/config/aarch64/aarch64.md | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 13a75d3..60e42af 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2159,6 +2159,19 @@
>[(set_attr "type" "alus_reg,alus_imm,alus_imm")]
>  )
>
> +;; variant that generates a CC_NZ output mode
> +(define_insn "*cmp_nz"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +   (compare:CC_NZ (match_operand:GPI 0 "register_operand" "r,r,r")
> +  (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J")))]
> +  ""
> +  "@
> +   cmp\\t%0, %1
> +   cmp\\t%0, %1
> +   cmn\\t%0, #%n1"
> +  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
> +)
> +
>  (define_insn "*cmp"
>[(set (reg:CCFP CC_REGNUM)
>  (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w")
> --
> 1.9.0
>

Re: [AArch64 12/14] Generate 'bics', when only interested in CC_NZ.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:
> A specialized variant of '*and_one_cmpl3_compare0' is needed
> to match some cases (during the combine stage) that could be folded
> into a bics, when the output result is not used (i.e. when only the
> condition code is of interest).
>
> This is useful both for CoreMark and SPEC workloads.

Can you add a testcase or two for this patch?  Having an example will
help people in the future understand why these patterns are added.

Thanks,
Andrew Pinski

> ---
>  gcc/config/aarch64/aarch64.md | 26 ++
>  1 file changed, 26 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 6feedd3..5c62868 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2747,6 +2747,18 @@
>[(set_attr "type" "logics_reg")]
>  )
>
> +;; variant of the above, that only uses the condition code
> +(define_insn "*and_one_cmpl3_compare0_internal2"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +(compare:CC_NZ
> + (and:GPI (not:GPI (match_operand:GPI 0 "register_operand" "r"))
> +  (match_operand:GPI 1 "register_operand" "r"))
> +(const_int 0)))]
> +  ""
> +  "bics\\tzr, %1, %0"
> +  [(set_attr "type" "logics_reg")]
> +)
> +
>  ;; zero_extend version of above
>  (define_insn "*and_one_cmplsi3_compare0_uxtw"
>[(set (reg:CC_NZ CC_REGNUM)
> @@ -2792,6 +2804,20 @@
>[(set_attr "type" "logics_shift_imm")]
>  )
>
> +(define_insn "*and_one_cmpl_3_compare0_internal2"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +   (compare:CC_NZ
> +(and:GPI (not:GPI
> +  (SHIFT:GPI
> +   (match_operand:GPI 0 "register_operand" "r")
> +   (match_operand:QI 1 "aarch64_shift_imm_" "n")))
> + (match_operand:GPI 2 "register_operand" "r"))
> +(const_int 0)))]
> +  ""
> +  "bics\\tzr, %2, %0,  %1"
> +  [(set_attr "type" "logics_shift_imm")]
> +)
> +
>  ;; zero_extend version of above
>  (define_insn "*and_one_cmpl_si3_compare0_uxtw"
>[(set (reg:CC_NZ CC_REGNUM)
> --
> 1.9.0
>

Re: [AArch64 11/14] Optimize and(s) patterns for HI/QI operands.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:
> HImode and QImode operands can be handled in a more optimal way for
> logical AND than for logical OR operations. An AND will never set
> bits that are not already set in its operands, so the resulting
> mode/precision depends on the least precision of its operands with
> an implicit zero-extension to any larger precision.
>
> These patterns help to avoid unnecessary zero-extension operations
> on benchmarks, including some SPEC workloads.

Can you add a testcase or two for this patch?  Having an example will
help people in the future understand why these patterns are added.

Thanks,
Andrew Pinski


> ---
>  gcc/config/aarch64/aarch64.md   | 62 
> ++---
>  gcc/config/aarch64/iterators.md |  2 ++
>  2 files changed, 60 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index b6453b6..6feedd3 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2551,8 +2551,8 @@
>
>  (define_insn "3"
>[(set (match_operand:GPI 0 "register_operand" "=r,rk")
> -   (LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r")
> -(match_operand:GPI 2 "aarch64_logical_operand" 
> "r,")))]
> +   (OR:GPI (match_operand:GPI 1 "register_operand" "%r,r")
> +   (match_operand:GPI 2 "aarch64_logical_operand" 
> "r,")))]
>""
>"\\t%0, %1, %2"
>[(set_attr "type" "logic_reg,logic_imm")]
> @@ -2569,6 +2569,27 @@
>[(set_attr "type" "logic_reg,logic_imm")]
>  )
>
> +;; specialized form of AND for HI and QI
> +(define_insn "and3"
> +  [(set (match_operand:ALLI 0 "register_operand" "=r,rk")
> +(and:ALLI (match_operand:ALLI 1 "register_operand" "%r,r")
> +  (match_operand:ALLI 2 "aarch64_logical_operand" 
> "r,")))]
> +  ""
> +  "and\\t%0, %1, %2"
> +  [(set_attr "type" "logic_reg,logic_imm")]
> +)
> +
> +;; zero_extend version of above
> +(define_insn "*and3_zeroextend"
> +  [(set (match_operand:GPI 0 "register_operand" "=r")
> +(zero_extend:GPI
> +  (and:ALLX (match_operand:ALLX 1 "register_operand" "r")
> +(match_operand:ALLX 2 "const_int_operand" 
> ""]
> +  ""
> +  "and\\t%w0, %w1, %w2"
> +  [(set_attr "type" "logic_imm")]
> +)
> +
>  (define_insn "*and3_compare0"
>[(set (reg:CC_NZ CC_REGNUM)
> (compare:CC_NZ
> @@ -2582,12 +2603,28 @@
>[(set_attr "type" "logics_reg,logics_imm")]
>  )
>
> +;; special variant for HI and QI operators (implicitly zero-extending)
> +(define_insn "*and3_compare0"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +(compare:CC_NZ
> +(and:GPI (match_operand:SHORT 1 "register_operand" "%r,r")
> + (match_operand:SHORT 2 "aarch64_logical_operand" 
> "r,"))
> +(const_int 0)))
> +   (set (match_operand:GPI 0 "register_operand" "=r,r")
> +(and:GPI (match_dup 1) (match_dup 2)))]
> +  ""
> +  "@
> +   ands\\t%0, %1, %2
> +   ands\\t%0, %1, %2"
> +  [(set_attr "type" "logic_reg,logic_imm")]
> +)
> +
>  ;; zero_extend version of above
>  (define_insn "*andsi3_compare0_uxtw"
>[(set (reg:CC_NZ CC_REGNUM)
> (compare:CC_NZ
> -(and:SI (match_operand:SI 1 "register_operand" "%r,r")
> -(match_operand:SI 2 "aarch64_logical_operand" "r,K"))
> +(and:SI (match_operand:ALLX 1 "register_operand" "%r,r")
> +(match_operand:ALLX 2 "aarch64_logical_operand" "r,K"))
>  (const_int 0)))
> (set (match_operand:DI 0 "register_operand" "=r,r")
> (zero_extend:DI (and:SI (match_dup 1) (match_dup 2]
> @@ -2628,6 +2665,23 @@
>[(set_attr "type" "logics_shift_imm")]
>  )
>
> +;; specialized form for bitfield tests
> +(define_insn "*ands3_zeroextract_internal2"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +(compare:CC_NZ
> + (zero_extract:GPI (match_operand:GPI 0 "register_operand" "r")
> +   (match_operand 1 "const_int_operand" "n")
> +   (match_operand 2 "const_int_operand" "n"))
> + (const_int 0)))]
> +  "aarch64_bitmask_immHOST_WIDE_INT)1 << (UINTVAL(operands[1]))) - 1) << 
> UINTVAL(operands[2]), mode)"
> +  "*
> +  {
> +operands[3] = GEN_INTHOST_WIDE_INT)1 << (UINTVAL(operands[1]))) - 1) 
> << UINTVAL(operands[2]));
> +return \"ands\\tzr, %0, %3\";
> +  }"
> +  [(set_attr "type" "logics_reg")]
> +)
> +
>  (define_insn "*_3"
>[(set (match_operand:GPI 0 "register_operand" "=r")
> (LOGICAL:GPI (SHIFT:GPI
> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
> index f1339b8..edba829 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -341,6 +341,7 @@
>
>  ;; Attribute to describe constants acceptable in logical operations
>  (define_mode_attr lconst [(SI "K") (DI "L")])
> +(define_mode_attr andconst [(QI "K") (HI "K") (SI "K") (DI "L")]

[PATCH, i386]: Warn for ABI changes only when -Wpsabi is enabled

[Uros Bizjak]

Hello!

Also use boolean AND instead of bitwise AND in a couple of places.

2014-02-18  Uros Bizjak  

PR target/59794
* config/i386/i386.c (type_natural_mode): Warn for ABI changes
only when -Wpsabi is enabled.

testsuite/ChangeLog:

2014-02-18  Uros Bizjak  

PR target/59794
* gcc.target/i386/pr39162.c: Add dg-prune-output.
(dg-options): Remove -Wno-psabi.
* gcc.target/i386/59794-2.c: Ditto.
* gcc.target/i386/60205-1.c: Ditto.
* gcc.target/i386/sse-5.c: Ditto.

Tested on x86_64-pc-linux-gnu {,-m32}, will commit tomorrow to
mainline SVN and 4.8 branch.

Uros.
Index: config/i386/i386.c
===
--- config/i386/i386.c  (revision 207851)
+++ config/i386/i386.c  (working copy)
@@ -6155,10 +6155,10 @@ init_cumulative_args (CUMULATIVE_ARGS *cum,  /* Ar
  cum->nregs = 0;
  cum->sse_nregs = 0;
  cum->mmx_nregs = 0;
- cum->warn_avx512f = 0;
- cum->warn_avx = 0;
- cum->warn_sse = 0;
- cum->warn_mmx = 0;
+ cum->warn_avx512f = false;
+ cum->warn_avx = false;
+ cum->warn_sse = false;
+ cum->warn_mmx = false;
  return;
}
 
@@ -6234,19 +6234,17 @@ type_natural_mode (const_tree type, const CUMULATI
static bool warnedavx512f;
static bool warnedavx512f_ret;
 
-   if (cum
-   && !warnedavx512f
-   && cum->warn_avx512f)
+   if (cum && cum->warn_avx512f && !warnedavx512f)
  {
-   warnedavx512f = true;
-   warning (0, "AVX512F vector argument without AVX512F "
-"enabled changes the ABI");
+   if (warning (OPT_Wpsabi, "AVX512F vector argument "
+"without AVX512F enabled changes the ABI"))
+ warnedavx512f = true;
  }
-   else if (in_return & !warnedavx512f_ret)
+   else if (in_return && !warnedavx512f_ret)
  {
-   warnedavx512f_ret = true;
-   warning (0, "AVX512F vector return without AVX512F "
-"enabled changes the ABI");
+   if (warning (OPT_Wpsabi, "AVX512F vector return "
+"without AVX512F enabled changes the ABI"))
+ warnedavx512f_ret = true;
  }
 
return TYPE_MODE (type);
@@ -6256,19 +6254,17 @@ type_natural_mode (const_tree type, const CUMULATI
static bool warnedavx;
static bool warnedavx_ret;
 
-   if (cum
-   && !warnedavx
-   && cum->warn_avx)
+   if (cum && cum->warn_avx && !warnedavx)
  {
-   warnedavx = true;
-   warning (0, "AVX vector argument without AVX "
-"enabled changes the ABI");
+   if (warning (OPT_Wpsabi, "AVX vector argument "
+"without AVX enabled changes the ABI"))
+ warnedavx = true;
  }
-   else if (in_return & !warnedavx_ret)
+   else if (in_return && !warnedavx_ret)
  {
-   warnedavx_ret = true;
-   warning (0, "AVX vector return without AVX "
-"enabled changes the ABI");
+   if (warning (OPT_Wpsabi, "AVX vector return "
+"without AVX enabled changes the ABI"))
+ warnedavx_ret = true;
  }
 
return TYPE_MODE (type);
@@ -6279,21 +6275,17 @@ type_natural_mode (const_tree type, const CUMULATI
static bool warnedsse;
static bool warnedsse_ret;
 
-   if (cum
-   && !warnedsse
-   && cum->warn_sse)
+   if (cum && cum->warn_sse && !warnedsse)
  {
-   warnedsse = true;
-   warning (0, "SSE vector argument without SSE "
-"enabled changes the ABI");
+   if (warning (OPT_Wpsabi, "SSE vector argument "
+"without SSE enabled changes the ABI"))
+ warnedsse = true;
  }
-   else if (!TARGET_64BIT
-&& in_return
-& !warnedsse_ret)
+   else if (!TARGET_64BIT && in_return && !warnedsse_ret)
  {
-   warnedsse_ret = true;
-

Re: [AArch64 10/14] Add movcc definition for GPF case.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:

  Can you add a testcase or two for this patch?

Thanks,
Andrew Pinski

> ---
>  gcc/config/aarch64/aarch64.md | 19 +++
>  1 file changed, 19 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index c72d123..b6453b6 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2460,6 +2460,25 @@
>}
>  )
>
> +(define_expand "movcc"
> +  [(set (match_operand:GPF 0 "register_operand" "")
> +  (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
> +(match_operand:GPF 2 "register_operand" "")
> +(match_operand:GPF 3 "register_operand" "")))]
> +  ""
> +  {
> +rtx ccreg;
> +enum rtx_code code = GET_CODE (operands[1]);
> +
> +if (code == UNEQ || code == LTGT)
> +  FAIL;
> +
> +ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
> +   XEXP (operands[1], 1));
> +operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
> +  }
> +)
> +
>  (define_expand "movcc"
>[(set (match_operand:GPI 0 "register_operand" "")
> (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
> --
> 1.9.0
>

[AArch64 12/14] Generate 'bics', when only interested in CC_NZ.

[Philipp Tomsich]

A specialized variant of '*and_one_cmpl3_compare0' is needed
to match some cases (during the combine stage) that could be folded
into a bics, when the output result is not used (i.e. when only the
condition code is of interest).

This is useful both for CoreMark and SPEC workloads.
---
 gcc/config/aarch64/aarch64.md | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 6feedd3..5c62868 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2747,6 +2747,18 @@
   [(set_attr "type" "logics_reg")]
 )
 
+;; variant of the above, that only uses the condition code
+(define_insn "*and_one_cmpl3_compare0_internal2"
+  [(set (reg:CC_NZ CC_REGNUM)
+(compare:CC_NZ
+ (and:GPI (not:GPI (match_operand:GPI 0 "register_operand" "r"))
+  (match_operand:GPI 1 "register_operand" "r"))
+(const_int 0)))]
+  ""
+  "bics\\tzr, %1, %0"
+  [(set_attr "type" "logics_reg")]
+)
+
 ;; zero_extend version of above
 (define_insn "*and_one_cmplsi3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)
@@ -2792,6 +2804,20 @@
   [(set_attr "type" "logics_shift_imm")]
 )
 
+(define_insn "*and_one_cmpl_3_compare0_internal2"
+  [(set (reg:CC_NZ CC_REGNUM)
+   (compare:CC_NZ
+(and:GPI (not:GPI
+  (SHIFT:GPI
+   (match_operand:GPI 0 "register_operand" "r")
+   (match_operand:QI 1 "aarch64_shift_imm_" "n")))
+ (match_operand:GPI 2 "register_operand" "r"))
+(const_int 0)))]
+  ""
+  "bics\\tzr, %2, %0,  %1"
+  [(set_attr "type" "logics_shift_imm")]
+)
+
 ;; zero_extend version of above
 (define_insn "*and_one_cmpl_si3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)
-- 
1.9.0

[AArch64 08/14] Define a variant of cmp for the CC_NZ case.

[Philipp Tomsich]

This pattern is not strictly necessary and a similar effect could
be achieved through the use of a suitable compatibility relation
for CC modes; in the meantime, this helps on some benchmarks.
---
 gcc/config/aarch64/aarch64.md | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 13a75d3..60e42af 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2159,6 +2159,19 @@
   [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
 )
 
+;; variant that generates a CC_NZ output mode
+(define_insn "*cmp_nz"
+  [(set (reg:CC_NZ CC_REGNUM)
+   (compare:CC_NZ (match_operand:GPI 0 "register_operand" "r,r,r")
+  (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J")))]
+  ""
+  "@
+   cmp\\t%0, %1
+   cmp\\t%0, %1
+   cmn\\t%0, #%n1"
+  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
+)
+
 (define_insn "*cmp"
   [(set (reg:CCFP CC_REGNUM)
 (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w")
-- 
1.9.0

[AArch64 09/14] Add special cases of zero-extend w/ compare operations.

[Philipp Tomsich]

---
 gcc/config/aarch64/aarch64.md | 56 +++
 1 file changed, 56 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 60e42af..c72d123 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2227,6 +2227,62 @@
   [(set_attr "type" "alus_ext")]
 )
 
+(define_insn "*zextqi3_compare0"
+  [(set (reg:CC_ZESWP CC_REGNUM)
+(compare:CC_ZESWP
+ (zero_extend:GPI (match_operand:QI 1 "register_operand" "r"))
+ (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+(zero_extend:GPI (match_dup 1)))]
+  ""
+  "ands\\t%0, %1, 0xFF"
+  [(set_attr "type" "logics_imm")]
+)
+
+(define_insn "*zexthi3_compare0"
+  [(set (reg:CC_ZESWP CC_REGNUM)
+(compare:CC_ZESWP
+ (zero_extend:GPI (match_operand:HI 1 "register_operand" "r"))
+ (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+(zero_extend:GPI (match_dup 1)))]
+  ""
+  "ands\\t%0, %1, 0x"
+  [(set_attr "type" "logics_imm")]
+)
+
+(define_insn "*zextdisi3_compare0"
+  [(set (reg:CC_ZESWP CC_REGNUM)
+(compare:CC_ZESWP
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+(zero_extend:DI (match_dup 1)))]
+  ""
+  "ands\\t%x0, %x1, 0x"
+  [(set_attr "type" "logics_imm")]
+)
+
+(define_insn "*zextqi3nr_compare0"
+  [(set (reg:CC_ZESWP CC_REGNUM)
+(compare:CC_ZESWP
+ (match_operand:QI 0 "register_operand" "r")
+ (const_int 0)))]
+  ""
+  "tst\\t%w0, 0xFF"
+  [(set_attr "type" "logics_imm")]
+)
+
+(define_insn "*zexthi3nr_compare0"
+  [(set (reg:CC_ZESWP CC_REGNUM)
+(compare:CC_ZESWP
+ (match_operand:HI 0 "register_operand" "r")
+ (const_int 0)))]
+  ""
+  "tst\\t%w0, 0x"
+  [(set_attr "type" "logics_imm")]
+)
+
 ;; ---
 ;; Store-flag and conditional select insns
 ;; ---
-- 
1.9.0

[AArch64 13/14] Initial tuning description for XGene-1 core.

[Philipp Tomsich]

The generic cost model for AArch64 can not be used to capture the
microarchitectural cost of XGene-1 in full detail.  For this reason,
we use the basic tuning model of the Cortex-A53 for now.
---
 gcc/config/aarch64/aarch64-cores.def |  2 +-
 gcc/config/aarch64/aarch64.c | 28 
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def
index b4f6c16..abbfea9 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -36,7 +36,7 @@
 
 AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa53)
 AARCH64_CORE("cortex-a57",  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO, generic)
-AARCH64_CORE("xgene1",  xgene1,xgene1,8,  AARCH64_FL_FPSIMD, 
generic)
+AARCH64_CORE("xgene1",  xgene1,xgene1,8,  AARCH64_FL_FPSIMD, 
xgene1)
 
 /* V8 big.LITTLE implementations.  */
 
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4327eb3..4c06f9b 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -192,6 +192,20 @@ static const struct cpu_regmove_cost generic_regmove_cost =
   NAMED_PARAM (FP2FP, 4)
 };
 
+static const struct cpu_regmove_cost xgene1_regmove_cost =
+{
+  NAMED_PARAM (GP2GP, 1),
+  /* We want all GP2FP and FP2GP moves to be handled by a reload.
+ A direct move instruction will have similar microarchitectural
+ cost to a store/load combination.  */
+  NAMED_PARAM (GP2FP, 4),
+  NAMED_PARAM (FP2GP, 4),
+  /* We currently do not provide direct support for TFmode Q->Q move.
+ Therefore we need to raise the cost above 2 in order to have
+ reload handle the situation.  */
+  NAMED_PARAM (FP2FP, 4)
+};
+
 /* Generic costs for vector insn classes.  */
 #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
 __extension__
@@ -237,6 +251,20 @@ static const struct tune_params cortexa53_tunings =
   NAMED_PARAM (branch_cost, 2)
 };
 
+/* We can't model the microarchitectural costs on XGene using  the default
+   cost model for AArch64.  So we leave the extra cost structure pointing
+   to the default cost model for the time being.  */
+static const struct tune_params xgene1_tunings =
+{
+  &cortexa53_extra_costs,
+  &generic_addrcost_table,
+  &xgene1_regmove_cost,
+  &generic_vector_cost,
+  NAMED_PARAM (memmov_cost, 4),
+  NAMED_PARAM (issue_rate, 4),
+  NAMED_PARAM (branch_cost, 2)
+};
+
 /* A processor implementing AArch64.  */
 struct processor
 {
-- 
1.9.0

[AArch64 14/14] Add cost-model for XGene-1.

[Philipp Tomsich]

This completely rewritten cost-model provides a like-for-like benefit
of approx. 3% on CoreMark.
---
 gcc/config/aarch64/aarch64.c | 885 ++-
 1 file changed, 881 insertions(+), 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4c06f9b..d5bdc9e 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -142,6 +142,8 @@ static bool aarch64_const_vec_all_same_int_p (rtx,
 static bool aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
 const unsigned char *sel);
 
+static bool xgene1_rtx_costs (rtx, int, int, int, int*, bool);
+
 /* The processor for which instructions should be scheduled.  */
 enum aarch64_processor aarch64_tune = cortexa53;
 
@@ -198,8 +200,8 @@ static const struct cpu_regmove_cost xgene1_regmove_cost =
   /* We want all GP2FP and FP2GP moves to be handled by a reload.
  A direct move instruction will have similar microarchitectural
  cost to a store/load combination.  */
-  NAMED_PARAM (GP2FP, 4),
-  NAMED_PARAM (FP2GP, 4),
+  NAMED_PARAM (GP2FP, 8),
+  NAMED_PARAM (FP2GP, 8),
   /* We currently do not provide direct support for TFmode Q->Q move.
  Therefore we need to raise the cost above 2 in order to have
  reload handle the situation.  */
@@ -252,8 +254,7 @@ static const struct tune_params cortexa53_tunings =
 };
 
 /* We can't model the microarchitectural costs on XGene using  the default
-   cost model for AArch64.  So we leave the extra cost structure pointing
-   to the default cost model for the time being.  */
+   cost model for AArch64.  */
 static const struct tune_params xgene1_tunings =
 {
   &cortexa53_extra_costs,
@@ -4546,6 +4547,9 @@ aarch64_rtx_costs (rtx x, int code, int outer 
ATTRIBUTE_UNUSED,
   const struct cpu_cost_table *extra_cost
 = aarch64_tune_params->insn_extra_cost;
 
+  if (selected_cpu->core == xgene1)
+return xgene1_rtx_costs(x, code, outer, param, cost, speed);
+
   switch (code)
 {
 case SET:
@@ -8331,6 +8335,879 @@ aarch64_cannot_change_mode_class (enum machine_mode 
from,
   return true;
 }
 
+/* This function aids the processing of an add/sub instruction that
+   may use the "extended register" or "shifted register" form.  For
+   many such cases, we can simply process the extend/shift as if it
+   were a separate isntruction, since the op cost is the same.
+   However, certain cases must be handled separately when the ops are
+   integrated into a single instruction.
+
+   Returns the inner operand if successful, or the original expression
+   on failure.  Also updates the cost if successful.  */
+static rtx
+xgene1_strip_extended_register (rtx op, int *cost, bool speed 
ATTRIBUTE_UNUSED, bool separate)
+{
+  /* If the operand is zero-extended from 32-bits, it is free. */
+  if (!separate
+  && GET_CODE (op) == ZERO_EXTEND
+  && GET_MODE (XEXP (op, 0)) == SImode)
+return XEXP (op, 0);
+
+  /*  A stand-alone multiply costs 4 or 5, so GCC will choose a cheaper
+  shift if it can.  But GCC will not transform a multiply embedded
+  inside another operation such as (plus (mult X const)).  Instead,
+  aarch64.md recognizes it as an operation with an embedded shift,
+  and we charge a cost accordingly. */
+  if (GET_CODE (op) == MULT)
+{
+  rtx op0 = XEXP (op, 0);
+  rtx op1 = XEXP (op, 1);
+
+  if (CONST_INT_P (op1)
+  && exact_log2 (INTVAL (op1)) > 0)
+{
+  if (exact_log2 (INTVAL (op1)) <= 4)
+{
+  *cost += COSTS_N_INSNS(1);
+
+  /* The extended register form can include a zero-
+ or sign-extend for free. */
+  if (GET_CODE (op0) == ZERO_EXTEND
+  || GET_CODE (op1) == SIGN_EXTEND)
+return XEXP (op0, 0);
+  else
+return op0;
+}
+  else
+{
+  /* The shifted register form can support a larger
+ left shift, but cannot include a free extend. */
+  *cost += COSTS_N_INSNS(2);
+  return op0;
+}
+}
+}
+
+  /* No candidates found.  Return op unchanged. */
+  return op;
+}
+
+/* Calculate the cost of calculating X, storing it in *COST.  Result
+   is true if the total cost of the operation has now been calculated.  */
+static bool
+xgene1_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
+  int param ATTRIBUTE_UNUSED, int *cost, bool speed)
+{
+  rtx op0, op1, op2, addr;
+  int n_minus_1;
+  enum machine_mode mode;
+
+  /* Throw away the default cost and start over.  */
+  /* A size N times larger than UNITS_PER_WORD (rounded up) probably
+ needs N times as many ops, so it executes in N-1 extra
+ cycles.  */
+  mode = GET_MODE (x);
+  n_minus_1 = (GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD;
+  /* If the mode size is less than UNITS_PER_WORD, then n_

[AArch64 11/14] Optimize and(s) patterns for HI/QI operands.

[Philipp Tomsich]

HImode and QImode operands can be handled in a more optimal way for
logical AND than for logical OR operations. An AND will never set
bits that are not already set in its operands, so the resulting
mode/precision depends on the least precision of its operands with
an implicit zero-extension to any larger precision.

These patterns help to avoid unnecessary zero-extension operations
on benchmarks, including some SPEC workloads.
---
 gcc/config/aarch64/aarch64.md   | 62 ++---
 gcc/config/aarch64/iterators.md |  2 ++
 2 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b6453b6..6feedd3 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2551,8 +2551,8 @@
 
 (define_insn "3"
   [(set (match_operand:GPI 0 "register_operand" "=r,rk")
-   (LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r")
-(match_operand:GPI 2 "aarch64_logical_operand" 
"r,")))]
+   (OR:GPI (match_operand:GPI 1 "register_operand" "%r,r")
+   (match_operand:GPI 2 "aarch64_logical_operand" "r,")))]
   ""
   "\\t%0, %1, %2"
   [(set_attr "type" "logic_reg,logic_imm")]
@@ -2569,6 +2569,27 @@
   [(set_attr "type" "logic_reg,logic_imm")]
 )
 
+;; specialized form of AND for HI and QI
+(define_insn "and3"
+  [(set (match_operand:ALLI 0 "register_operand" "=r,rk")
+(and:ALLI (match_operand:ALLI 1 "register_operand" "%r,r")
+  (match_operand:ALLI 2 "aarch64_logical_operand" 
"r,")))]
+  ""
+  "and\\t%0, %1, %2"
+  [(set_attr "type" "logic_reg,logic_imm")]
+)
+
+;; zero_extend version of above
+(define_insn "*and3_zeroextend"
+  [(set (match_operand:GPI 0 "register_operand" "=r")
+(zero_extend:GPI
+  (and:ALLX (match_operand:ALLX 1 "register_operand" "r")
+(match_operand:ALLX 2 "const_int_operand" ""]
+  ""
+  "and\\t%w0, %w1, %w2"
+  [(set_attr "type" "logic_imm")]
+)
+
 (define_insn "*and3_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
@@ -2582,12 +2603,28 @@
   [(set_attr "type" "logics_reg,logics_imm")]
 )
 
+;; special variant for HI and QI operators (implicitly zero-extending)
+(define_insn "*and3_compare0"
+  [(set (reg:CC_NZ CC_REGNUM)
+(compare:CC_NZ
+(and:GPI (match_operand:SHORT 1 "register_operand" "%r,r")
+ (match_operand:SHORT 2 "aarch64_logical_operand" 
"r,"))
+(const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r,r")
+(and:GPI (match_dup 1) (match_dup 2)))]
+  ""
+  "@
+   ands\\t%0, %1, %2
+   ands\\t%0, %1, %2"
+  [(set_attr "type" "logic_reg,logic_imm")]
+)
+
 ;; zero_extend version of above
 (define_insn "*andsi3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
-(and:SI (match_operand:SI 1 "register_operand" "%r,r")
-(match_operand:SI 2 "aarch64_logical_operand" "r,K"))
+(and:SI (match_operand:ALLX 1 "register_operand" "%r,r")
+(match_operand:ALLX 2 "aarch64_logical_operand" "r,K"))
 (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (and:SI (match_dup 1) (match_dup 2]
@@ -2628,6 +2665,23 @@
   [(set_attr "type" "logics_shift_imm")]
 )
 
+;; specialized form for bitfield tests
+(define_insn "*ands3_zeroextract_internal2"
+  [(set (reg:CC_NZ CC_REGNUM)
+(compare:CC_NZ
+ (zero_extract:GPI (match_operand:GPI 0 "register_operand" "r")
+   (match_operand 1 "const_int_operand" "n")
+   (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)))]
+  "aarch64_bitmask_immHOST_WIDE_INT)1 << (UINTVAL(operands[1]))) - 1) << 
UINTVAL(operands[2]), mode)"
+  "*
+  {
+operands[3] = GEN_INTHOST_WIDE_INT)1 << (UINTVAL(operands[1]))) - 1) 
<< UINTVAL(operands[2]));
+return \"ands\\tzr, %0, %3\";
+  }"
+  [(set_attr "type" "logics_reg")]
+)
+
 (define_insn "*_3"
   [(set (match_operand:GPI 0 "register_operand" "=r")
(LOGICAL:GPI (SHIFT:GPI
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index f1339b8..edba829 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -341,6 +341,7 @@
 
 ;; Attribute to describe constants acceptable in logical operations
 (define_mode_attr lconst [(SI "K") (DI "L")])
+(define_mode_attr andconst [(QI "K") (HI "K") (SI "K") (DI "L")])
 
 ;; Map a mode to a specific constraint character.
 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
@@ -627,6 +628,7 @@
 
 ;; Code iterator for logical operations
 (define_code_iterator LOGICAL [and ior xor])
+(define_code_iterator OR [ior xor])
 
 ;; Code iterator for sign/zero extension
 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
-- 
1.9.0

[AArch64 10/14] Add movcc definition for GPF case.

[Philipp Tomsich]

---
 gcc/config/aarch64/aarch64.md | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c72d123..b6453b6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2460,6 +2460,25 @@
   }
 )
 
+(define_expand "movcc"
+  [(set (match_operand:GPF 0 "register_operand" "")
+  (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
+(match_operand:GPF 2 "register_operand" "")
+(match_operand:GPF 3 "register_operand" "")))]
+  ""
+  {
+rtx ccreg;
+enum rtx_code code = GET_CODE (operands[1]);
+
+if (code == UNEQ || code == LTGT)
+  FAIL;
+
+ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+   XEXP (operands[1], 1));
+operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+  }
+)
+
 (define_expand "movcc"
   [(set (match_operand:GPI 0 "register_operand" "")
(if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
-- 
1.9.0

[jit] Support self-referential data structures (API changes).

[David Malcolm]

Committed to branch dmalcolm/jit:

New API type:
  - gcc_jit_struct

New API entrypoints:
  - gcc_jit_context_new_opaque_struct
  - gcc_jit_struct_as_type
  - gcc_jit_struct_set_fields
  - gcc_jit_context_null: get the NULL value for a pointer type.

Changed API entrypoint:
  - gcc_jit_context_new_struct_type: changed return type from
(gcc_jit_type *) to (gcc_jit_struct *).

Internally, split out populating the fields of a struct from the creation
of said struct.

Also, require conditionals to be of boolean type (so that conversions must,
for now, be explicit), since the implicit behavior of passing in a pointer
didn't match that of C.

gcc/jit/
* libgccjit.h (gcc_jit_struct): New.
(gcc_jit_context_new_struct_type): Change return type from gcc_jit_type
to gcc_jit_struct.
(gcc_jit_context_new_opaque_struct): New.
(gcc_jit_struct_as_type): New.
(gcc_jit_struct_set_fields): New.
(gcc_jit_context_null): New.

* libgccjit.map (gcc_jit_context_new_opaque_struct): New.
(gcc_jit_context_null): New.
(gcc_jit_struct_as_type): New.
(gcc_jit_struct_set_fields): New.

* libgccjit++.h (gccjit::context::new_struct_type): Return a
struct_ rather than a type.
(gccjit::context::new_opaque_struct_type): New.
(gccjit::struct_): New subclass of type.

* libgccjit.c (gcc_jit_struct): New.
(RETURN_VAL_IF_FAIL_PRINTF1): New.
(RETURN_VAL_IF_FAIL_PRINTF2): New.
(RETURN_NULL_IF_FAIL_PRINTF1): New.
(RETURN_IF_FAIL_PRINTF1): New.
(RETURN_IF_FAIL_PRINTF2): New.
(gcc_jit_context_new_struct_type): Return a gcc_jit_struct rather
than a gcc_jit_type; implement by creating the struct, then
setting the fields in it.
(gcc_jit_context_new_opaque_struct): New.
(gcc_jit_struct_as_type): New.
(gcc_jit_struct_set_fields): New.
(gcc_jit_context_null): New.
(gcc_jit_lvalue_access_field): Use the struct's context when
reporting on a NULL field; verify that the field has been placed
in a struct.
(gcc_jit_rvalue_access_field): Likewise.
(is_bool): New.
(gcc_jit_function_add_conditional): Use the function's context
when reporting errors; verify that boolval's type is indeed
boolean.
(gcc_jit_function_new_loop): Likewise.

* internal-api.h (gcc::jit::recording::context::new_struct_type):
Don't accept fields, and return a struct_ rather than a type_, so
that fields can be set later.
(gcc::jit::recording::struct_::struct_): Store a (fields *) rather
than a vec of fields.
(gcc::jit::recording::struct_::as_type): New.
(gcc::jit::recording::struct_::get_fields): New.
(gcc::jit::recording::struct_::set_fields): New.
(gcc::jit::recording::struct_::playback_struct): New.
(gcc::jit::recording::fields): New class.
(gcc::jit::playback::context::new_struct_type): Don't accept
fields, and return a struct_ rather than a type_, so that fields
can be set later.
(gcc::jit::playback::struct_): New subclass of type.

* internal-api.c (gcc::jit::recording::context::get_type): With
nested contexts, create basic types within the ultimate parent
context, allowing for a fast check for the boolean type using
pointer equality.
(gcc::jit::recording::context::new_struct_type): Don't accept
fields, and return a struct_ rather than a type_, so that fields
can be set later.
(gcc::jit::recording::context::get_opaque_FILE_type): Update for
struct-creation changes.
(gcc::jit::recording::struct_::struct_): Store a (fields *) rather
than a vec of fields.
(gcc::jit::recording::struct_::set_fields): New.
(gcc::jit::recording::struct_::replay_into): Don't playback the
fields, as this is now done by a fields instance.
(gcc::jit::recording::fields::fields): New.
(gcc::jit::recording::fields::replay_into): New.
(gcc::jit::recording::fields::make_debug_string): New.
(gcc::jit:: playback::context::new_struct_type): Don't accept
fields, and return a struct_ rather than a type_, so that fields
can be set later.
(gcc::jit::playback::struct_::set_fields): New.

* TODO.rst: Update.

gcc/testsuite/
* jit.dg/test-accessing-struct.c (create_code): Update for change to
return type of gcc_jit_context_new_struct_type.
* jit.dg/test-arrays.c (create_code): Likewise.
* jit.dg/test-error-accessing-field-in-other-struct.c (create_code):
Likewise.
* jit.dg/test-error-dereference-field-of-non-pointer.c (create_code):
Likewise.
* jit.dg/test-fuzzer.c (make_random_type): Likewise.
* jit.dg/test-nested-contexts.c (make_types): Likewise.
* jit.dg/test-quadratic.c

Re: [AArch64 04/14] Correct the maximum shift amount for shifted operands.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:

Can you add a testcase or two for this?

Thanks,
Andrew


> ---
>  gcc/config/aarch64/aarch64.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index 43e4612..4327eb3 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -4409,7 +4409,7 @@ aarch64_output_casesi (rtx *operands)
>  int
>  aarch64_uxt_size (int shift, HOST_WIDE_INT mask)
>  {
> -  if (shift >= 0 && shift <= 3)
> +  if (shift >= 0 && shift <= 4)
>  {
>int size;
>for (size = 8; size <= 32; size *= 2)
> --
> 1.9.0
>

Re: [AArch64 07/14] Define additional patterns for adds/subs.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:

Can you add a testcase or two for this?  This should show why they are
not matching before hand.

Thanks,
Andrew


> ---
>  gcc/config/aarch64/aarch64.md | 49 
> +++
>  1 file changed, 49 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 90f1ee9..13a75d3 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -1138,6 +1138,22 @@
>[(set_attr "type" "alus_reg,alus_imm,alus_imm")]
>  )
>
> +;; alternative using the condition output only
> +(define_insn "*add3_compare0_internal2"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +(compare:CC_NZ
> + (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r,r")
> +   (match_operand:GPI 2 "aarch64_plus_operand" "r,I,J"))
> +(const_int 0)))
> +   (clobber (match_scratch:GPI 0 "=r,r,r"))]
> +  ""
> +  "@
> +  adds\\t%0, %1, %2
> +  adds\\t%0, %1, %2
> +  subs\\t%0, %1, #%n2"
> +  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
> +)
> +
>  ;; zero_extend version of above
>  (define_insn "*addsi3_compare0_uxtw"
>[(set (reg:CC_NZ CC_REGNUM)
> @@ -1155,6 +1171,39 @@
>[(set_attr "type" "alus_reg,alus_imm,alus_imm")]
>  )
>
> +;; variant of the above using a swapped condition/comparator
> +(define_insn "*addsi3_compare0_uxtw_zeswp"
> +  [(set (reg:CC_ZESWP CC_REGNUM)
> +(compare:CC_ZESWP
> + (plus:SI (match_operand:SI 1 "register_operand" "%r,r,r")
> +  (match_operand:SI 2 "aarch64_plus_operand" "r,I,J"))
> +(const_int 0)))
> +   (set (match_operand:DI 0 "register_operand" "=r,r,r")
> +(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2]
> +  ""
> +  "@
> +  adds\\t%w0, %w1, %w2
> +  adds\\t%w0, %w1, %w2
> +  subs\\t%w0, %w1, #%n2"
> +  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
> +)
> +
> +;; alternative using the condition output only
> +(define_insn "*addsi3_compare0_uxtw_zeswp_internal2"
> +  [(set (reg:CC_ZESWP CC_REGNUM)
> + (compare:CC_ZESWP
> +(plus:SI (match_operand:SI 1 "register_operand" "%r,r,r")
> +  (match_operand:SI 2 "aarch64_plus_operand" "r,I,J"))
> +(const_int 0)))
> +   (clobber (match_scratch:DI 0 "=r,r,r"))]
> +  ""
> +  "@
> +  adds\\t%w0, %w1, %w2
> +  adds\\t%w0, %w1, %w2
> +  subs\\t%w0, %w1, #%n2"
> +  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
> +)
> +
>  (define_insn "*adds_mul_imm_"
>[(set (reg:CC_NZ CC_REGNUM)
> (compare:CC_NZ
> --
> 1.9.0
>

Re: [AArch64 06/14] Extend '*tb1'.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:
> The '*tb1' can safely be extended to match operands of
> any size, as long as the immediate operand (i.e. the bits tested)
> match the size of the register operand.
>
> This removes unnecessary zero-extension operations from the
> generated instruction stream.

Can you add a testcase or two for this?

Thanks,
Andrew

> ---
>  gcc/config/aarch64/aarch64.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index b972a1b..90f1ee9 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -382,14 +382,14 @@
>
>  (define_insn "*tb1"
>[(set (pc) (if_then_else
> - (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" 
> "r")
> + (EQL (zero_extract:DI (match_operand:ALLI 0 "register_operand" 
> "r")
> (const_int 1)
> (match_operand 1 "const_int_operand" "n"))
>(const_int 0))
>  (label_ref (match_operand 2 "" ""))
>  (pc)))
> (clobber (match_scratch:DI 3 "=r"))]
> -  ""
> +  "(UINTVAL(operands[1]) < GET_MODE_BITSIZE(mode))"
>"*
>if (get_attr_length (insn) == 8)
>  return \"ubfx\\t%3, %0, %1, #1\;\\t%3, %l2\";
> --
> 1.9.0
>

Re: [AArch64 05/14] Add AArch64 'prefetch'-pattern.

[Andrew Pinski]

On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
 wrote:

Can you add a testcase or two for this?

Thanks,
Andrew


> ---
>  gcc/config/aarch64/aarch64.md | 17 +
>  gcc/config/arm/types.md   |  2 ++
>  2 files changed, 19 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 99a6ac8..b972a1b 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -293,6 +293,23 @@
>[(set_attr "type" "no_insn")]
>  )
>
> +(define_insn "prefetch"
> +  [(prefetch (match_operand:DI 0 "register_operand" "r")
> +(match_operand:QI 1 "const_int_operand" "n")
> +(match_operand:QI 2 "const_int_operand" "n"))]
> +  ""
> +  "*
> +{
> +  if (INTVAL(operands[2]) == 0)
> + /* no temporal locality */
> + return (INTVAL(operands[1])) ? \"prfm\\tPSTL1STRM, [%0, #0]\" : 
> \"prfm\\tPLDL1STRM, [%0, #0]\";
> +
> +  /* temporal locality */
> +  return (INTVAL(operands[1])) ? \"prfm\\tPSTL1KEEP, [%0, #0]\" : 
> \"prfm\\tPLDL1KEEP, [%0, #0]\";
> +}"
> +  [(set_attr "type" "prefetch")]
> +)
> +
>  (define_insn "trap"
>[(trap_if (const_int 1) (const_int 8))]
>""
> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
> index cc39cd1..1d1280d 100644
> --- a/gcc/config/arm/types.md
> +++ b/gcc/config/arm/types.md
> @@ -117,6 +117,7 @@
>  ; mvn_shift_reg  inverting move instruction, shifted operand by a 
> register.
>  ; no_insnan insn which does not represent an instruction in the
>  ;final output, thus having no impact on scheduling.
> +; prefetch  a prefetch instruction
>  ; rbit   reverse bits.
>  ; revreverse bytes.
>  ; sdiv   signed division.
> @@ -553,6 +554,7 @@
>call,\
>clz,\
>no_insn,\
> +  prefetch,\
>csel,\
>crc,\
>extend,\
> --
> 1.9.0
>

Re: [Patch, Fortran] PR49397 - Fix ICE with proc-pointers

[Janus Weil]

Hi Tobias,

> This patch fixes an ICE on valid error - and a missed diagnostic.
>
> Wording from the standard F2008, Corr2:
>
> C729 (R742) A  shall be the name of a module or dummy
> procedure, a specific intrinsic function listed in 13.6 and not marked with
> a bullet ($\bullet$), a procedure point, or a specific intrinsic function
> listed in 13.6 and not marked with a bullet ($\bullet$), or an external
> procedure that is accessed by use or host association, referenced in the
> scoping unit as a procedure, or that has the EXTERNAL attribute.
>
>
> The ICE is a 4.7/4.8/4.9 regression.
>
> Build and regtested on x86-64-gnu-linux.
> OK for the trunk and 4.8? What about 4.7?

your patch basically looks good to me.

One minor nit about the trans-decl.c part: The comment above the code
that you're changing ("Only used for ...") seems wrong after the
change. Maybe just remove that sentence?

About the previous version of the patch (in bugzilla) I was wondering
if setting the EXTERNAL attribute is really the correct thing to do,
but it seems that is not done any more in this version.

To my taste the patch is ok for all of trunk, 4.8 and 4.7.

Thanks,
Janus

[AArch64 05/14] Add AArch64 'prefetch'-pattern.

[Philipp Tomsich]

---
 gcc/config/aarch64/aarch64.md | 17 +
 gcc/config/arm/types.md   |  2 ++
 2 files changed, 19 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 99a6ac8..b972a1b 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -293,6 +293,23 @@
   [(set_attr "type" "no_insn")]
 )
 
+(define_insn "prefetch"
+  [(prefetch (match_operand:DI 0 "register_operand" "r")
+(match_operand:QI 1 "const_int_operand" "n")
+(match_operand:QI 2 "const_int_operand" "n"))]
+  ""
+  "*
+{
+  if (INTVAL(operands[2]) == 0)
+ /* no temporal locality */
+ return (INTVAL(operands[1])) ? \"prfm\\tPSTL1STRM, [%0, #0]\" : 
\"prfm\\tPLDL1STRM, [%0, #0]\";
+
+  /* temporal locality */
+  return (INTVAL(operands[1])) ? \"prfm\\tPSTL1KEEP, [%0, #0]\" : 
\"prfm\\tPLDL1KEEP, [%0, #0]\";
+}"
+  [(set_attr "type" "prefetch")]
+)
+
 (define_insn "trap"
   [(trap_if (const_int 1) (const_int 8))]
   ""
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index cc39cd1..1d1280d 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -117,6 +117,7 @@
 ; mvn_shift_reg  inverting move instruction, shifted operand by a register.
 ; no_insnan insn which does not represent an instruction in the
 ;final output, thus having no impact on scheduling.
+; prefetch  a prefetch instruction
 ; rbit   reverse bits.
 ; revreverse bytes.
 ; sdiv   signed division.
@@ -553,6 +554,7 @@
   call,\
   clz,\
   no_insn,\
+  prefetch,\
   csel,\
   crc,\
   extend,\
-- 
1.9.0

[AArch64 04/14] Correct the maximum shift amount for shifted operands.

[Philipp Tomsich]

---
 gcc/config/aarch64/aarch64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 43e4612..4327eb3 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4409,7 +4409,7 @@ aarch64_output_casesi (rtx *operands)
 int
 aarch64_uxt_size (int shift, HOST_WIDE_INT mask)
 {
-  if (shift >= 0 && shift <= 3)
+  if (shift >= 0 && shift <= 4)
 {
   int size;
   for (size = 8; size <= 32; size *= 2)
-- 
1.9.0

[AArch64 07/14] Define additional patterns for adds/subs.

[Philipp Tomsich]

---
 gcc/config/aarch64/aarch64.md | 49 +++
 1 file changed, 49 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 90f1ee9..13a75d3 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1138,6 +1138,22 @@
   [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
 )
 
+;; alternative using the condition output only
+(define_insn "*add3_compare0_internal2"
+  [(set (reg:CC_NZ CC_REGNUM)
+(compare:CC_NZ
+ (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r,r")
+   (match_operand:GPI 2 "aarch64_plus_operand" "r,I,J"))
+(const_int 0)))
+   (clobber (match_scratch:GPI 0 "=r,r,r"))]
+  ""
+  "@
+  adds\\t%0, %1, %2
+  adds\\t%0, %1, %2
+  subs\\t%0, %1, #%n2"
+  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
+)
+
 ;; zero_extend version of above
 (define_insn "*addsi3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)
@@ -1155,6 +1171,39 @@
   [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
 )
 
+;; variant of the above using a swapped condition/comparator
+(define_insn "*addsi3_compare0_uxtw_zeswp"
+  [(set (reg:CC_ZESWP CC_REGNUM)
+(compare:CC_ZESWP
+ (plus:SI (match_operand:SI 1 "register_operand" "%r,r,r")
+  (match_operand:SI 2 "aarch64_plus_operand" "r,I,J"))
+(const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r,r,r")
+(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2]
+  ""
+  "@
+  adds\\t%w0, %w1, %w2
+  adds\\t%w0, %w1, %w2
+  subs\\t%w0, %w1, #%n2"
+  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
+)
+
+;; alternative using the condition output only
+(define_insn "*addsi3_compare0_uxtw_zeswp_internal2"
+  [(set (reg:CC_ZESWP CC_REGNUM)
+ (compare:CC_ZESWP
+(plus:SI (match_operand:SI 1 "register_operand" "%r,r,r")
+  (match_operand:SI 2 "aarch64_plus_operand" "r,I,J"))
+(const_int 0)))
+   (clobber (match_scratch:DI 0 "=r,r,r"))]
+  ""
+  "@
+  adds\\t%w0, %w1, %w2
+  adds\\t%w0, %w1, %w2
+  subs\\t%w0, %w1, #%n2"
+  [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
+)
+
 (define_insn "*adds_mul_imm_"
   [(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
-- 
1.9.0

[AArch64 06/14] Extend '*tb1'.

[Philipp Tomsich]

The '*tb1' can safely be extended to match operands of
any size, as long as the immediate operand (i.e. the bits tested)
match the size of the register operand.

This removes unnecessary zero-extension operations from the
generated instruction stream.
---
 gcc/config/aarch64/aarch64.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b972a1b..90f1ee9 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -382,14 +382,14 @@
 
 (define_insn "*tb1"
   [(set (pc) (if_then_else
- (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r")
+ (EQL (zero_extract:DI (match_operand:ALLI 0 "register_operand" 
"r")
(const_int 1)
(match_operand 1 "const_int_operand" "n"))
   (const_int 0))
 (label_ref (match_operand 2 "" ""))
 (pc)))
(clobber (match_scratch:DI 3 "=r"))]
-  ""
+  "(UINTVAL(operands[1]) < GET_MODE_BITSIZE(mode))"
   "*
   if (get_attr_length (insn) == 8)
 return \"ubfx\\t%3, %0, %1, #1\;\\t%3, %l2\";
-- 
1.9.0

[AArch64 03/14] Retrieve BRANCH_COST from tuning structure.

[Philipp Tomsich]

The BRANCH_COST affects whether conditional instructions (e.g.
conditional moves) will be used in transforms in the middle-end.
This change makes the branch_cost configurable from within the
target tuning structure.
---
 gcc/config/aarch64/aarch64-protos.h |  2 ++
 gcc/config/aarch64/aarch64.c| 13 +++--
 gcc/config/aarch64/aarch64.h|  6 --
 3 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-protos.h 
b/gcc/config/aarch64/aarch64-protos.h
index 5542f02..185bc64 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -157,6 +157,7 @@ struct tune_params
   const struct cpu_vector_cost *const vec_costs;
   const int memmov_cost;
   const int issue_rate;
+  const int branch_cost;
 };
 
 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
@@ -227,6 +228,7 @@ void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, 
const_tree, rtx,
 void aarch64_init_expanders (void);
 void aarch64_print_operand (FILE *, rtx, char);
 void aarch64_print_operand_address (FILE *, rtx);
+int aarch64_branch_cost (int, int);
 
 /* Initialize builtins for SIMD intrinsics.  */
 void init_aarch64_simd_builtins (void);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 70dda00..43e4612 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -222,7 +222,8 @@ static const struct tune_params generic_tunings =
   &generic_regmove_cost,
   &generic_vector_cost,
   NAMED_PARAM (memmov_cost, 4),
-  NAMED_PARAM (issue_rate, 2)
+  NAMED_PARAM (issue_rate, 2),
+  NAMED_PARAM (branch_cost, 2)
 };
 
 static const struct tune_params cortexa53_tunings =
@@ -232,7 +233,8 @@ static const struct tune_params cortexa53_tunings =
   &generic_regmove_cost,
   &generic_vector_cost,
   NAMED_PARAM (memmov_cost, 4),
-  NAMED_PARAM (issue_rate, 2)
+  NAMED_PARAM (issue_rate, 2),
+  NAMED_PARAM (branch_cost, 2)
 };
 
 /* A processor implementing AArch64.  */
@@ -4891,6 +4893,13 @@ aarch64_register_move_cost (enum machine_mode mode 
ATTRIBUTE_UNUSED,
   return regmove_cost->FP2FP;
 }
 
+int
+aarch64_branch_cost(int speed_p, int predictable_p)
+{
+  return (!(speed_p) ? 2 : (predictable_p) ? 0 : 
aarch64_tune_params->branch_cost);
+}
+
+
 static int
 aarch64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
  reg_class_t rclass ATTRIBUTE_UNUSED,
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index b66a6b4..fbdf745 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -765,8 +765,10 @@ do {   
 \
 #define MEMORY_MOVE_COST(M, CLASS, IN) \
   (GET_MODE_SIZE (M) < 8 ? 8 : GET_MODE_SIZE (M))
 
-/* To start with.  */
-#define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2
+/* A C expression for the cost of a branch instruction.  A value of 1
+   is the default; other values are interpreted relative to that.  */
+#define BRANCH_COST(speed_p, predictable_p) \
+  (aarch64_branch_cost(speed_p, predictable_p))
 
 
 /* Assembly output.  */
-- 
1.9.0

[AArch64 01/14] Use "generic" target, if no other default.

[Philipp Tomsich]

The default target should be "generic", as Cortex-A53 includes
optional ISA features (CRC and CRYPTO) that are not required for
architectural compliance. The key difference between generic (which
already uses the cortexa53 pipeline model for scheduling) is the
absence of any optional ISA features in the "generic" target.
---
 gcc/config/aarch64/aarch64.c | 2 +-
 gcc/config/aarch64/aarch64.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 784bfa3..70dda00 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -5244,7 +5244,7 @@ aarch64_override_options (void)
 
   /* If the user did not specify a processor, choose the default
  one for them.  This will be the CPU set during configuration using
- --with-cpu, otherwise it is "cortex-a53".  */
+ --with-cpu, otherwise it is "generic".  */
   if (!selected_cpu)
 {
   selected_cpu = &all_cores[TARGET_CPU_DEFAULT & 0x3f];
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 13c424c..b66a6b4 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -472,10 +472,10 @@ enum target_cpus
   TARGET_CPU_generic
 };
 
-/* If there is no CPU defined at configure, use "cortex-a53" as default.  */
+/* If there is no CPU defined at configure, use "generic" as default.  */
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT \
-  (TARGET_CPU_cortexa53 | (AARCH64_CPU_DEFAULT_FLAGS << 6))
+  (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
 #endif
 
 /* The processor for which instructions should be scheduled.  */
-- 
1.9.0

[AArch64 00/14] Pipeline-independent changes for XGene-1

[Philipp Tomsich]

The following patch-set contains the pipeline-independent changes to gcc
to support the APM XGene-1 and contains various enhancements derived from
real-world applications and benchmarks running on XGene-1.

As the pipeline model has not been fully adapted to the new instruction
typing shared between the ARM backend and the AArch64 backend, it is not
yet contained in these patches.

The most controversial part of these patches will likely consist in the
new cost-model, which has intentionally been provided as a "hook" that
intercepts the current cost-model when compiling for XGene-1. Given that
the matching/structure of this cost-model is different from the existing
implementation, we've chosen to keep this in a separate function for the
time being.


Philipp Tomsich (14):
  Use "generic" target, if no other default.
  Add "xgene1" core identifier.
  Retrieve BRANCH_COST from tuning structure.
  Correct the maximum shift amount for shifted operands.
  Add AArch64 'prefetch'-pattern.
  Extend '*tb1'.
  Define additional patterns for adds/subs.
  Define a variant of cmp for the CC_NZ case.
  Add special cases of zero-extend w/ compare operations.
  Add movcc definition for GPF case.
  Optimize and(s) patterns for HI/QI operands.
  Generate 'bics', when only interested in CC_NZ.
  Initial tuning description for XGene-1 core.
  Add cost-model for XGene-1.

 gcc/config/aarch64/aarch64-cores.def |   1 +
 gcc/config/aarch64/aarch64-protos.h  |   2 +
 gcc/config/aarch64/aarch64-tune.md   |   2 +-
 gcc/config/aarch64/aarch64.c | 922 ++-
 gcc/config/aarch64/aarch64.h |  10 +-
 gcc/config/aarch64/aarch64.md| 246 +-
 gcc/config/aarch64/iterators.md  |   2 +
 gcc/config/arm/types.md  |   2 +
 8 files changed, 1172 insertions(+), 15 deletions(-)

-- 
1.9.0

[AArch64 02/14] Add "xgene1" core identifier.

[Philipp Tomsich]

* aarch64/aarch64-cores.def: Add "xgene1".
---
 gcc/config/aarch64/aarch64-cores.def | 1 +
 gcc/config/aarch64/aarch64-tune.md   | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def
index 1039660..b4f6c16 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -36,6 +36,7 @@
 
 AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa53)
 AARCH64_CORE("cortex-a57",  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO, generic)
+AARCH64_CORE("xgene1",  xgene1,xgene1,8,  AARCH64_FL_FPSIMD, 
generic)
 
 /* V8 big.LITTLE implementations.  */
 
diff --git a/gcc/config/aarch64/aarch64-tune.md 
b/gcc/config/aarch64/aarch64-tune.md
index b7e40e0..a79d403 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-   "cortexa53,cortexa15,cortexa57cortexa53"
+   "cortexa53,cortexa15,xgene1,cortexa57cortexa53"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
-- 
1.9.0

Re: [PATCH] Fix PR c++/60190.

[Jason Merrill]

OK.

Jason

Re: [PATCH] [libgomp] make it possible to use OMP on both sides of a fork

[Richard Henderson]

On 02/16/2014 03:59 PM, Nathaniel Smith wrote:
> Yes, but the problem is that depending on what the user intends to do
> after forking, our pthread_atfork handler might help or it might hurt,
> and we don't know which. Consider these two cases:
>   - fork+exec
>   - fork+continue to use OMP in child
> The former case is totally POSIX-legal, even when performed at
> arbitrary places, even when another thread is, say, in the middle of
> calling malloc(). 

Point well taken.


r~

[Patch, Fortran] PR49397 - Fix ICE with proc-pointers

[Tobias Burnus]

This patch fixes an ICE on valid error - and a missed diagnostic.

Wording from the standard F2008, Corr2:

C729 (R742) A  shall be the name of a module or dummy 
procedure, a specific intrinsic function listed in 13.6 and not marked 
with a bullet ($\bullet$), a procedure point, or a specific intrinsic 
function listed in 13.6 and not marked with a bullet ($\bullet$), or an 
external procedure that is accessed by use or host association, 
referenced in the scoping unit as a procedure, or that has the EXTERNAL 
attribute.



The ICE is a 4.7/4.8/4.9 regression.

Build and regtested on x86-64-gnu-linux.
OK for the trunk and 4.8? What about 4.7?

Tobias
2014-02-18  Tobias Burnus  

	PR fortran/49397
	* expr.c (gfc_check_pointer_assign): Add check for
	F2008Cor2, C729.
	* trans-decl.c (gfc_get_symbol_decl): Correctly generate external
	decl in a corner case.

2014-02-18  Tobias Burnus  

	PR fortran/49397
	* gfortran.dg/proc_ptr_45.f90: New.
	* gfortran.dg/proc_ptr_46.f90: New.

diff --git a/gcc/fortran/expr.c b/gcc/fortran/expr.c
index 818212a..fe6eab5 100644
--- a/gcc/fortran/expr.c
+++ b/gcc/fortran/expr.c
@@ -3581,6 +3581,16 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue)
 	  return false;
 	}
 
+  /* Check F2008Cor2, C729.  */
+  if (!s2->attr.intrinsic && s2->attr.if_source == IFSRC_UNKNOWN
+	  && !s2->attr.external && !s2->attr.subroutine && !s2->attr.function)
+	{
+	  gfc_error ("Procedure pointer target '%s' at %L must be either an "
+		 "intrinsic, host or use associated, referenced or have "
+		 "the EXTERNAL attribute", s2->name, &rvalue->where);
+	  return false;
+	}
+
   return true;
 }
 
diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c
index 9c86653..407e55d 100644
--- a/gcc/fortran/trans-decl.c
+++ b/gcc/fortran/trans-decl.c
@@ -1364,7 +1364,8 @@ gfc_get_symbol_decl (gfc_symbol * sym)
 {
   /* Catch function declarations. Only used for actual parameters,
 	 procedure pointers and procptr initialization targets.  */
-  if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic)
+  if (sym->attr.use_assoc || sym->attr.intrinsic
+	  || sym->attr.if_source != IFSRC_DECL)
 	{
 	  decl = gfc_get_extern_function_decl (sym);
 	  gfc_set_decl_location (decl, &sym->declared_at);
diff --git a/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 b/gcc/testsuite/gfortran.dg/proc_ptr_45.f90
new file mode 100644
index 000..a506473
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/proc_ptr_45.f90
@@ -0,0 +1,24 @@
+! { dg-do compile }
+!
+! PR fortran/49397
+!
+! Valid per IR F08/0060 and F2008Corr2, C729
+!
+Program m5
+  Print *,f()
+Contains
+  Subroutine s
+Procedure(Real),Pointer :: p
+Print *,g()
+p => f   ! (1)
+Print *,p()
+p => g   ! (2)
+Print *,p()
+  End Subroutine
+End Program
+Function f()
+  f = 1
+End Function
+Function g()
+  g = 2
+End Function
diff --git a/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 b/gcc/testsuite/gfortran.dg/proc_ptr_46.f90
new file mode 100644
index 000..2c05f59
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/proc_ptr_46.f90
@@ -0,0 +1,14 @@
+! { dg-do compile }
+!
+! PR fortran/49397
+!
+! Invalid per IR F08/0060 and F2008Corr2, C729
+!
+
+!  Print *,f() ! << Valid when uncommented
+Contains
+  Subroutine s
+Procedure(Real),Pointer :: p
+p => f  ! { dg-error "Procedure pointer target 'f' at .1. must be either an intrinsic, host or use associated, referenced or have the EXTERNAL attribute" }
+  End Subroutine
+End

[PATCH] Fix PR c++/60190.

[Adam Butcher]

PR c++/60190
* parser.c (cp_parser_lambda_declarator_opt): Pop template parameter
scope whenever a template parameter list has been started, independent
of whether the function call operator was well-formed or not.

PR c++/60190
* g++.dg/cpp1y/pr60190.C: New testcase.
---
 gcc/cp/parser.c  | 16 
 gcc/testsuite/g++.dg/cpp1y/pr60190.C |  5 +
 2 files changed, 13 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr60190.C

diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 57001c6..15a1128 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -9127,15 +9127,15 @@ cp_parser_lambda_declarator_opt (cp_parser* parser, 
tree lambda_expr)
DECL_ARTIFICIAL (fco) = 1;
/* Give the object parameter a different name.  */
DECL_NAME (DECL_ARGUMENTS (fco)) = get_identifier ("__closure");
-   if (template_param_list)
- {
-   fco = finish_member_template_decl (fco);
-   finish_template_decl (template_param_list);
-   --parser->num_template_parameter_lists;
- }
-   else if (parser->fully_implicit_function_template_p)
- fco = finish_fully_implicit_template (parser, fco);
   }
+if (template_param_list)
+  {
+   fco = finish_member_template_decl (fco);
+   finish_template_decl (template_param_list);
+   --parser->num_template_parameter_lists;
+  }
+else if (parser->fully_implicit_function_template_p)
+  fco = finish_fully_implicit_template (parser, fco);
 
 finish_member_declaration (fco);
 
diff --git a/gcc/testsuite/g++.dg/cpp1y/pr60190.C 
b/gcc/testsuite/g++.dg/cpp1y/pr60190.C
new file mode 100644
index 000..d5e2567
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/pr60190.C
@@ -0,0 +1,5 @@
+// PR c++/60190
+// { dg-do compile }
+// { dg-options "-std=c++1y" }
+
+auto f = []() -> int() {}; // { dg-error "returning a function|expected" }
-- 
1.8.5.5

Re: [PATCH] Don't force line note on second basic block (PR sanitizer/60142)

[Richard Henderson]

On 02/18/2014 11:37 AM, Jakub Jelinek wrote:
> Bootstrapped/regtested on x86_64-linux and i686-linux, and Jan Kratochvil
> has tested it with GDB testsuite.  Ok for trunk?
> 
> 2014-02-18  Jakub Jelinek  
> 
>   PR sanitizer/60142
>   * final.c (SEEN_BB): Remove.
>   (SEEN_NOTE, SEEN_EMITTED): Renumber.
>   (final_scan_insn): Don't force_source_line on second
>   NOTE_INSN_BASIC_BLOCK.

Ok.


r~

[jit] Avoid using a NULL context when reporting errors

[David Malcolm]

Committed to branch dmalcolm/jit:

gcc/jit/
* libgccjit.c (gcc_jit_function_new_local): Use the context of the
function when reporting errors.
(gcc_jit_function_place_forward_label): Likewise.
(gcc_jit_function_add_eval): Likewise.
(gcc_jit_function_add_assignment_op): Likewise.
(gcc_jit_function_add_comment): Likewise.
(gcc_jit_function_add_jump): Likewise.
---
 gcc/jit/ChangeLog.jit | 10 ++
 gcc/jit/libgccjit.c   | 24 +++-
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/gcc/jit/ChangeLog.jit b/gcc/jit/ChangeLog.jit
index 39706f6..b0e12b1 100644
--- a/gcc/jit/ChangeLog.jit
+++ b/gcc/jit/ChangeLog.jit
@@ -1,3 +1,13 @@
+2014-02-18  David Malcolm  
+
+   * libgccjit.c (gcc_jit_function_new_local): Use the context of the
+   function when reporting errors.
+   (gcc_jit_function_place_forward_label): Likewise.
+   (gcc_jit_function_add_eval): Likewise.
+   (gcc_jit_function_add_assignment_op): Likewise.
+   (gcc_jit_function_add_comment): Likewise.
+   (gcc_jit_function_add_jump): Likewise.
+
 2014-02-14  David Malcolm  
 
* libgccjit++.h (gccjit::type::zero): New method.
diff --git a/gcc/jit/libgccjit.c b/gcc/jit/libgccjit.c
index e568b3f..b5b3968 100644
--- a/gcc/jit/libgccjit.c
+++ b/gcc/jit/libgccjit.c
@@ -827,11 +827,12 @@ gcc_jit_function_new_local (gcc_jit_function *func,
const char *name)
 {
   RETURN_NULL_IF_FAIL (func, NULL, "NULL function");
+  gcc::jit::recording::context *ctxt = func->m_ctxt;
   RETURN_NULL_IF_FAIL (func->get_kind () != GCC_JIT_FUNCTION_IMPORTED,
-  NULL,
+  ctxt,
   "Cannot add locals to an imported function");
-  RETURN_NULL_IF_FAIL (type, NULL, "NULL type");
-  RETURN_NULL_IF_FAIL (name, NULL, "NULL name");
+  RETURN_NULL_IF_FAIL (type, ctxt, "NULL type");
+  RETURN_NULL_IF_FAIL (name, ctxt, "NULL name");
 
   return (gcc_jit_lvalue *)func->new_local (loc, type, name);
 }
@@ -853,7 +854,8 @@ gcc_jit_function_place_forward_label (gcc_jit_function 
*func,
  gcc_jit_label *lab)
 {
   RETURN_IF_NOT_FUNC_DEFINITION (func);
-  RETURN_IF_FAIL (lab, NULL, "NULL label");
+  gcc::jit::recording::context *ctxt = func->m_ctxt;
+  RETURN_IF_FAIL (lab, ctxt, "NULL label");
 
   func->place_forward_label (loc, lab);
 }
@@ -864,7 +866,8 @@ gcc_jit_function_add_eval (gcc_jit_function *func,
   gcc_jit_rvalue *rvalue)
 {
   RETURN_IF_NOT_FUNC_DEFINITION (func);
-  RETURN_IF_FAIL (rvalue, NULL, "NULL rvalue");
+  gcc::jit::recording::context *ctxt = func->m_ctxt;
+  RETURN_IF_FAIL (rvalue, ctxt, "NULL rvalue");
 
   return func->add_eval (loc, rvalue);
 }
@@ -901,9 +904,10 @@ gcc_jit_function_add_assignment_op (gcc_jit_function *func,
gcc_jit_rvalue *rvalue)
 {
   RETURN_IF_NOT_FUNC_DEFINITION (func);
-  RETURN_IF_FAIL (lvalue, NULL, "NULL lvalue");
+  gcc::jit::recording::context *ctxt = func->m_ctxt;
+  RETURN_IF_FAIL (lvalue, ctxt, "NULL lvalue");
   /* FIXME: op is checked by new_binary_op */
-  RETURN_IF_FAIL (rvalue, NULL, "NULL rvalue");
+  RETURN_IF_FAIL (rvalue, ctxt, "NULL rvalue");
 
   return func->add_assignment_op (loc, lvalue, op, rvalue);
 }
@@ -929,7 +933,8 @@ gcc_jit_function_add_comment (gcc_jit_function *func,
  const char *text)
 {
   RETURN_IF_NOT_FUNC_DEFINITION (func);
-  RETURN_IF_FAIL (text, NULL, "NULL text");
+  gcc::jit::recording::context *ctxt = func->m_ctxt;
+  RETURN_IF_FAIL (text, ctxt, "NULL text");
 
   func->add_comment (loc, text);
 }
@@ -940,7 +945,8 @@ gcc_jit_function_add_jump (gcc_jit_function *func,
gcc_jit_label *target)
 {
   RETURN_IF_NOT_FUNC_DEFINITION (func);
-  RETURN_IF_FAIL (target, NULL, "NULL target");
+  gcc::jit::recording::context *ctxt = func->m_ctxt;
+  RETURN_IF_FAIL (target, ctxt, "NULL target");
 
   func->add_jump (loc, target);
 }
-- 
1.7.11.7

Re: [PATCH] Fix sanitizer build on sparc (PR sanitizer/59758)

[Konstantin Serebryany]

On Tue, Feb 18, 2014 at 10:00 PM, Jakub Jelinek  wrote:
>
> On Tue, Feb 18, 2014 at 06:55:51PM +0100, Jose E. Marchesi wrote:
> > This patch fixes builds with --enable-sanitizer, which seems to be the
> > default for sparc now.
> >
> > Build tested in a sparc64-*-linux-gnu system with linux 3.8.13 headers.
> >
> > 2014-02-18  Jose E. Marchesi  
> >
> >   PR sanitizer/59758
> >   * sanitizer_common/sanitizer_platform_limits_posix.h (__sanitizer):
> >   Define struct__old_kernel_stat_sz, struct_kernel_stat_sz and
> >   struct_kernel_stat64_sz for sparc targets (both 32 and 64 bits).
> >   (__sanitizer_ipc_perm): Adjust for sparc targets.
> >   (__sanitizer_shmid_ds): Likewise.
> >   (__sanitizer_sigaction): Likewise.
> >   (IOC_SIZE): Likewise.
> >
> >   * sanitizer_common/sanitizer_platform_limits_linux.cc (time_t):
> >   defined as __kernel_time_t, which is needed for sparc.
> >   (struct___old_kernel_stat_sz): Don't check if __sparc__ is defined.
>
> Please talk to Konstantin about getting this into the upstream compiler-rt
> repository, we don't need to wait for a merge from there, so once it
> is accepted there, the same patch can be applied to gcc too.

Right. Please read
https://code.google.com/p/address-sanitizer/wiki/HowToContribute

--kcc

>
> > Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
> > ===
> > --- libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h   
> > (revision 207826)
> > +++ libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h   
> > (working copy)
> > @@ -67,6 +67,14 @@
> >const unsigned struct___old_kernel_stat_sz = 0;
> >const unsigned struct_kernel_stat_sz = 144;
> >const unsigned struct_kernel_stat64_sz = 104;
> > +#elif defined(__sparc__) && defined(__arch64__)
> > +  const unsigned struct___old_kernel_stat_sz = 0;
> > +  const unsigned struct_kernel_stat_sz = 104;
> > +  const unsigned struct_kernel_stat64_sz = 144;
> > +#elif defined(__sparc__) && !defined(__arch64__)
> > +  const unsigned struct___old_kernel_stat_sz = 0;
> > +  const unsigned struct_kernel_stat_sz = 120;
> > +  const unsigned struct_kernel_stat64_sz = 104;
> >  #endif
> >struct __sanitizer_perf_event_attr {
> >  unsigned type;
> > @@ -145,6 +153,18 @@
> >  unsigned __seq;
> >  u64 __unused1;
> >  u64 __unused2;
> > +#elif defined(__sparc__)
> > +# if defined(__arch64__)
> > +unsigned mode;
> > +unsigned short __pad1;
> > +# else
> > +unsigned short __pad1;
> > +unsigned short  mode;
> > +unsigned short __pad2;
> > +# endif
> > +unsigned short __seq;
> > +unsigned long long __unused1;
> > +unsigned long long __unused2;
> >  #else
> >  unsigned short mode;
> >  unsigned short __pad1;
> > @@ -162,6 +182,26 @@
> >
> >struct __sanitizer_shmid_ds {
> >  __sanitizer_ipc_perm shm_perm;
> > +  #if defined(__sparc__)
> > +  # if !defined(__arch64__)
> > +u32 __pad1;
> > +  # endif
> > +s64 shm_atime;
> > +  # if !defined(__arch64__)
> > +u32 __pad2;
> > +  # endif
> > +s64 shm_dtime;
> > +  # if !defined(__arch64__)
> > +u32 __pad3;
> > +  # endif
> > +s64 shm_ctime;
> > +uptr shm_segsz;
> > +int shm_cpid;
> > +int shm_lpid;
> > +u64 shm_nattch;
> > +u64 __glibc_reserved1;
> > +u64 __glibc_reserved2;
> > +  #else
> >#ifndef __powerpc__
> >  uptr shm_segsz;
> >#elif !defined(__powerpc64__)
> > @@ -199,6 +239,7 @@
> >  uptr __unused4;
> >  uptr __unused5;
> >#endif
> > +#endif
> >};
> >#endif  // SANITIZER_LINUX && !SANITIZER_ANDROID
> >
> > @@ -365,7 +406,11 @@
> >void (*sa_sigaction)(int sig, void *siginfo, void *uctx);
> >  };
> >  __sanitizer_sigset_t sa_mask;
> > +#if defined(__sparc__)
> > +unsigned long sa_flags;
> > +#else
> >  int sa_flags;
> > +#endif
> >  #if SANITIZER_LINUX
> >  void (*sa_restorer)();
> >  #endif
> > @@ -511,7 +556,16 @@
> >};
> >  #endif
> >
> > -#define IOC_SIZE(nr) (((nr) >> 16) & 0x3fff)
> > +#if defined(__sparc__)
> > +// In sparc the 14 bits SIZE field overlaps with the
> > +// least significant bit of DIR, so either IOC_READ or
> > +// IOC_WRITE shall be 1 in order to get a non-zero SIZE.
> > +# define IOC_SIZE(nr)\
> > +  ((nr) >> 29) & 0x7) & (4U|2U)) == 0)? \
> > +   0: (((nr) >> 16) & 0x3fff))
> > +#else
> > +# define IOC_SIZE(nr) (((nr) >> 16) & 0x3fff)
> > +#endif
> >
> >extern unsigned struct_arpreq_sz;
> >extern unsigned struct_ifreq_sz;
> > Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
> > ===
> > --- libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc  
> > (revision 207826)
> > +++ libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc  
> > (working copy)
> > @@ -36,6 +36,7 @@
> > 

[C PATCH] Kill bogus warnings on _Atomics (PR c/60195)

[Marek Polacek]

This PR is about bogus warnings on _Atomics.  E.g., for _Atomic int,
the warning "right-hand operand of comma has no effect" makes no sense.  One
problem was that when making COMPOUND_EXPR out of atomic variable, we create
artificial variable via create_tmp_var, but we shouldn't warn on those.  So
I've set TREE_NO_WARNING on such variables.
Another issue is that we warned that a variable is unused, even when it's
actually used in __atomic_load; mark_exp_read fixed it.

Also I noticed a typo, so fixed (s/val/old/).

Regtested/bootstrapped on x86_64-linux, ok for 5.0?  (Or 4.9 instead?)

2014-02-18  Marek Polacek  

PR c/60195
c/
* c-typeck.c (convert_lvalue_to_rvalue): Set TREE_NO_WARNING on tmp.
Call mark_exp_read on exp.value.
(build_atomic_assign): Set TREE_NO_WARNING on val and old.  Set
TREE_ADDRESSABLE on old instead of val.
(emit_side_effect_warnings): Warn only if RHS has !TREE_NO_WARNING.
testsuite/
* gcc.dg/pr60195.c: New test.

diff --git gcc/c/c-typeck.c gcc/c/c-typeck.c
index da6a6fc..2b54290 100644
--- gcc/c/c-typeck.c
+++ gcc/c/c-typeck.c
@@ -2009,6 +2009,7 @@ convert_lvalue_to_rvalue (location_t loc, struct c_expr 
exp,
   tmp = create_tmp_var (nonatomic_type, NULL);
   tmp_addr = build_unary_op (loc, ADDR_EXPR, tmp, 0);
   TREE_ADDRESSABLE (tmp) = 1;
+  TREE_NO_WARNING (tmp) = 1;
 
   /* Issue __atomic_load (&expr, &tmp, SEQ_CST);  */
   fndecl = builtin_decl_explicit (BUILT_IN_ATOMIC_LOAD);
@@ -2017,6 +2018,9 @@ convert_lvalue_to_rvalue (location_t loc, struct c_expr 
exp,
   params->quick_push (seq_cst);
   func_call = build_function_call_vec (loc, vNULL, fndecl, params, NULL);
 
+  /* EXPR is always read.  */
+  mark_exp_read (exp.value);
+
   /* Return tmp which contains the value loaded.  */
   exp.value = build2 (COMPOUND_EXPR, nonatomic_type, func_call, tmp);
 }
@@ -3615,6 +3619,7 @@ build_atomic_assign (location_t loc, tree lhs, enum 
tree_code modifycode,
   nonatomic_rhs_type = build_qualified_type (rhs_type, TYPE_UNQUALIFIED);
   val = create_tmp_var (nonatomic_rhs_type, NULL);
   TREE_ADDRESSABLE (val) = 1;
+  TREE_NO_WARNING (val) = 1;
   rhs = build2 (MODIFY_EXPR, nonatomic_rhs_type, val, rhs);
   SET_EXPR_LOCATION (rhs, loc);
   add_stmt (rhs);
@@ -3643,7 +3648,8 @@ build_atomic_assign (location_t loc, tree lhs, enum 
tree_code modifycode,
   /* Create the variables and labels required for the op= form.  */
   old = create_tmp_var (nonatomic_lhs_type, NULL);
   old_addr = build_unary_op (loc, ADDR_EXPR, old, 0);
-  TREE_ADDRESSABLE (val) = 1;
+  TREE_ADDRESSABLE (old) = 1;
+  TREE_NO_WARNING (old) = 1;
 
   newval = create_tmp_var (nonatomic_lhs_type, NULL);
   newval_addr = build_unary_op (loc, ADDR_EXPR, newval, 0);
@@ -9661,6 +9667,7 @@ emit_side_effect_warnings (location_t loc, tree expr)
   if (!TREE_SIDE_EFFECTS (r)
  && !VOID_TYPE_P (TREE_TYPE (r))
  && !CONVERT_EXPR_P (r)
+ && !TREE_NO_WARNING (r)
  && !TREE_NO_WARNING (expr))
warning_at (cloc, OPT_Wunused_value,
"right-hand operand of comma expression has no effect");
diff --git gcc/testsuite/gcc.dg/pr60195.c gcc/testsuite/gcc.dg/pr60195.c
index e69de29..0a50a30 100644
--- gcc/testsuite/gcc.dg/pr60195.c
+++ gcc/testsuite/gcc.dg/pr60195.c
@@ -0,0 +1,56 @@
+/* PR c/60195 */
+/* { dg-do compile } */
+/* { dg-options "-std=c11 -Wpedantic -Wall" } */
+
+typedef _Atomic int atomic_int;
+
+atomic_int
+fn1 (void)
+{
+  atomic_int y = 0;
+  return y;
+}
+
+atomic_int
+fn2 (void)
+{
+  atomic_int y = 0;
+  y;
+  return y;
+}
+
+atomic_int
+fn3 (void)
+{
+  atomic_int y = 0;
+  y++;
+  return y;
+}
+
+void
+fn4 (void)
+{
+  atomic_int y;
+  y = 0;
+  (void) y;
+}
+
+void
+fn5 (void)
+{
+  atomic_int y = 0; /* { dg-warning "unused variable" } */
+}
+
+void
+fn6 (void)
+{
+  atomic_int y;  /* { dg-warning "set but not used" } */
+  y = 0;
+}
+
+void
+fn7 (void)
+{
+  atomic_int y = 0;
+  y++;
+}

Marek

Re: [PATCH, PR 55260] Use correct info in cgraph_edge_brings_all_agg_vals_for_node

[Jan Hubicka]

> On 2014.02.04 at 17:48 +0100, Martin Jambor wrote:
> > PR 55260 has been reopened because there is still one use of wrong
> > info, this time in cgraph_edge_brings_all_agg_vals_for_node when
> > checking whether aggregate lattices are set to bottom which can lead
> > to index out of bounds assert failures or even potentially ignoring
> > bottom lattices.
> > 
> > Fixed thusly.  Bootstrapped and tested on trunk on x86_64-linux,
> > bootstrap is still underway on the 4.8 branch where this exact fix is
> > also necessary.  OK for both?
> 
> Ping.
> 
> Libreoffice LTO build also fails right now because of this issue.
> 
> Honza, can you take a look at this patch?
> 
> Thanks.
> 
> > 2014-02-03  Martin Jambor  
> > 
> > PR ipa/55260
> > * ipa-cp.c (cgraph_edge_brings_all_agg_vals_for_node): Uce correct
> > info when checking whether lattices are bottom.
> > 
> > testsuite/
> > * gcc.dg/ipa/pr55260.c: New test.

OK, thanks!
Honza
> > 
> > diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c
> > index 10fa4b6..70bb33f 100644
> > --- a/gcc/ipa-cp.c
> > +++ b/gcc/ipa-cp.c
> > @@ -3178,6 +3178,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct 
> > cgraph_edge *cs,
> >   struct cgraph_node *node)
> >  {
> >struct ipa_node_params *orig_caller_info = IPA_NODE_REF (cs->caller);
> > +  struct ipa_node_params *orig_node_info;
> >struct ipa_agg_replacement_value *aggval;
> >int i, ec, count;
> >  
> > @@ -3192,6 +3193,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct 
> > cgraph_edge *cs,
> >if (aggval->index >= ec)
> > return false;
> >  
> > +  orig_node_info = IPA_NODE_REF (IPA_NODE_REF (node)->ipcp_orig_node);
> >if (orig_caller_info->ipcp_orig_node)
> >  orig_caller_info = IPA_NODE_REF (orig_caller_info->ipcp_orig_node);
> >  
> > @@ -3209,7 +3211,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct 
> > cgraph_edge *cs,
> >if (!interesting)
> > continue;
> >  
> > -  plats = ipa_get_parm_lattices (orig_caller_info, aggval->index);
> > +  plats = ipa_get_parm_lattices (orig_node_info, aggval->index);
> >if (plats->aggs_bottom)
> > return false;
> >  
> > diff --git a/gcc/testsuite/gcc.dg/ipa/pr55260.c 
> > b/gcc/testsuite/gcc.dg/ipa/pr55260.c
> > new file mode 100644
> > index 000..ef151b0
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.dg/ipa/pr55260.c
> > @@ -0,0 +1,38 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-O2 -fno-inline -fipa-cp-clone"  } */
> > +
> > +typedef struct {
> > +  int *ptr;
> > +  int len;
> > +} string;
> > +typedef struct {
> > +  string nantstr;
> > +  int *nant;
> > +} malv;
> > +typedef struct {
> > +  int *nor;
> > +} list_heads;
> > +int b;
> > +list_heads *fn1(string, int *, unsigned);
> > +void fn2(malv *p1, list_heads *p2, unsigned p3) {
> > +  string a = p1->nantstr;
> > +  fn1(a, p1->nant, p3);
> > +}
> > +
> > +void fn3(unsigned p1) { fn2(0, 0, p1); }
> > +
> > +list_heads *fn1(string p1, int *p2, unsigned p3) {
> > +  while (1) {
> > +if (p3)
> > +  fn3(1);
> > +if (b)
> > +  return 0;
> > +fn3(1);
> > +  }
> > +}
> > +
> > +void fn5() {
> > +  list_heads c;
> > +  c.nor = 0;
> > +  fn2(0, &c, 1);
> > +}
> > 
> 
> -- 
> Markus

Re: [PATCH] Reduce load on crgaph_get_node from estimate_num_insns

[Jan Hubicka]

> 
> It looks like the most heavy load on crgaph_get_node and the
> symtab hashtable (at least for PR60243), so the following avoids
> that when the call isn't builtin.
> 
> Bootstrap / regtest in progress on x86_64-unknown-linux-gnu, ok?

OK, thanks!
Honza

Re: [PATCH] Fix sanitizer build on sparc (PR sanitizer/59758)

[Jakub Jelinek]

On Tue, Feb 18, 2014 at 06:55:51PM +0100, Jose E. Marchesi wrote:
> This patch fixes builds with --enable-sanitizer, which seems to be the
> default for sparc now.
> 
> Build tested in a sparc64-*-linux-gnu system with linux 3.8.13 headers.
> 
> 2014-02-18  Jose E. Marchesi  
> 
>   PR sanitizer/59758
>   * sanitizer_common/sanitizer_platform_limits_posix.h (__sanitizer):
>   Define struct__old_kernel_stat_sz, struct_kernel_stat_sz and
>   struct_kernel_stat64_sz for sparc targets (both 32 and 64 bits).
>   (__sanitizer_ipc_perm): Adjust for sparc targets.
>   (__sanitizer_shmid_ds): Likewise.
>   (__sanitizer_sigaction): Likewise.
>   (IOC_SIZE): Likewise.
> 
>   * sanitizer_common/sanitizer_platform_limits_linux.cc (time_t):
>   defined as __kernel_time_t, which is needed for sparc.
>   (struct___old_kernel_stat_sz): Don't check if __sparc__ is defined.

Please talk to Konstantin about getting this into the upstream compiler-rt
repository, we don't need to wait for a merge from there, so once it
is accepted there, the same patch can be applied to gcc too.

> Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
> ===
> --- libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h   
> (revision 207826)
> +++ libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h   
> (working copy)
> @@ -67,6 +67,14 @@
>const unsigned struct___old_kernel_stat_sz = 0;
>const unsigned struct_kernel_stat_sz = 144;
>const unsigned struct_kernel_stat64_sz = 104;
> +#elif defined(__sparc__) && defined(__arch64__)
> +  const unsigned struct___old_kernel_stat_sz = 0;
> +  const unsigned struct_kernel_stat_sz = 104;
> +  const unsigned struct_kernel_stat64_sz = 144;
> +#elif defined(__sparc__) && !defined(__arch64__)
> +  const unsigned struct___old_kernel_stat_sz = 0;
> +  const unsigned struct_kernel_stat_sz = 120;
> +  const unsigned struct_kernel_stat64_sz = 104;
>  #endif
>struct __sanitizer_perf_event_attr {
>  unsigned type;
> @@ -145,6 +153,18 @@
>  unsigned __seq;
>  u64 __unused1;
>  u64 __unused2;
> +#elif defined(__sparc__)
> +# if defined(__arch64__)
> +unsigned mode;
> +unsigned short __pad1;
> +# else
> +unsigned short __pad1;
> +unsigned short  mode;
> +unsigned short __pad2;
> +# endif
> +unsigned short __seq;
> +unsigned long long __unused1;
> +unsigned long long __unused2;
>  #else
>  unsigned short mode;
>  unsigned short __pad1;
> @@ -162,6 +182,26 @@
>  
>struct __sanitizer_shmid_ds {
>  __sanitizer_ipc_perm shm_perm;
> +  #if defined(__sparc__)
> +  # if !defined(__arch64__)
> +u32 __pad1;
> +  # endif
> +s64 shm_atime;
> +  # if !defined(__arch64__)
> +u32 __pad2;
> +  # endif
> +s64 shm_dtime;
> +  # if !defined(__arch64__)
> +u32 __pad3;
> +  # endif
> +s64 shm_ctime;
> +uptr shm_segsz;
> +int shm_cpid;
> +int shm_lpid;
> +u64 shm_nattch;
> +u64 __glibc_reserved1;
> +u64 __glibc_reserved2;
> +  #else
>#ifndef __powerpc__
>  uptr shm_segsz;
>#elif !defined(__powerpc64__)
> @@ -199,6 +239,7 @@
>  uptr __unused4;
>  uptr __unused5;
>#endif
> +#endif
>};
>#endif  // SANITIZER_LINUX && !SANITIZER_ANDROID
>  
> @@ -365,7 +406,11 @@
>void (*sa_sigaction)(int sig, void *siginfo, void *uctx);
>  };
>  __sanitizer_sigset_t sa_mask;
> +#if defined(__sparc__)
> +unsigned long sa_flags;
> +#else
>  int sa_flags;
> +#endif
>  #if SANITIZER_LINUX
>  void (*sa_restorer)();
>  #endif
> @@ -511,7 +556,16 @@
>};
>  #endif
>  
> -#define IOC_SIZE(nr) (((nr) >> 16) & 0x3fff)
> +#if defined(__sparc__)
> +// In sparc the 14 bits SIZE field overlaps with the
> +// least significant bit of DIR, so either IOC_READ or
> +// IOC_WRITE shall be 1 in order to get a non-zero SIZE.
> +# define IOC_SIZE(nr)\
> +  ((nr) >> 29) & 0x7) & (4U|2U)) == 0)? \
> +   0: (((nr) >> 16) & 0x3fff))
> +#else
> +# define IOC_SIZE(nr) (((nr) >> 16) & 0x3fff)
> +#endif
>  
>extern unsigned struct_arpreq_sz;
>extern unsigned struct_ifreq_sz;
> Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
> ===
> --- libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc  
> (revision 207826)
> +++ libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc  
> (working copy)
> @@ -36,6 +36,7 @@
>  #define uid_t __kernel_uid_t
>  #define gid_t __kernel_gid_t
>  #define off_t __kernel_off_t
> +#define time_t __kernel_time_t
>  // This header seems to contain the definitions of _kernel_ stat* structs.
>  #include 
>  #undef ino_t
> @@ -62,7 +63,7 @@
>unsigned struct_statfs64_sz = sizeof(struct statfs64);
>  }  // namespace __sanitizer
>  
> -#if !defined(__powerpc64__) && !defined(__x86_64__)
> +#

[PATCH] Fix sanitizer build on sparc (PR sanitizer/59758)

[Jose E. Marchesi]

Hi.

This patch fixes builds with --enable-sanitizer, which seems to be the
default for sparc now.

Build tested in a sparc64-*-linux-gnu system with linux 3.8.13 headers.

2014-02-18  Jose E. Marchesi  

PR sanitizer/59758
* sanitizer_common/sanitizer_platform_limits_posix.h (__sanitizer):
Define struct__old_kernel_stat_sz, struct_kernel_stat_sz and
struct_kernel_stat64_sz for sparc targets (both 32 and 64 bits).
(__sanitizer_ipc_perm): Adjust for sparc targets.
(__sanitizer_shmid_ds): Likewise.
(__sanitizer_sigaction): Likewise.
(IOC_SIZE): Likewise.

* sanitizer_common/sanitizer_platform_limits_linux.cc (time_t):
defined as __kernel_time_t, which is needed for sparc.
(struct___old_kernel_stat_sz): Don't check if __sparc__ is defined.



Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
===
--- libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h 
(revision 207826)
+++ libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h 
(working copy)
@@ -67,6 +67,14 @@
   const unsigned struct___old_kernel_stat_sz = 0;
   const unsigned struct_kernel_stat_sz = 144;
   const unsigned struct_kernel_stat64_sz = 104;
+#elif defined(__sparc__) && defined(__arch64__)
+  const unsigned struct___old_kernel_stat_sz = 0;
+  const unsigned struct_kernel_stat_sz = 104;
+  const unsigned struct_kernel_stat64_sz = 144;
+#elif defined(__sparc__) && !defined(__arch64__)
+  const unsigned struct___old_kernel_stat_sz = 0;
+  const unsigned struct_kernel_stat_sz = 120;
+  const unsigned struct_kernel_stat64_sz = 104;
 #endif
   struct __sanitizer_perf_event_attr {
 unsigned type;
@@ -145,6 +153,18 @@
 unsigned __seq;
 u64 __unused1;
 u64 __unused2;
+#elif defined(__sparc__)
+# if defined(__arch64__)
+unsigned mode;
+unsigned short __pad1;
+# else
+unsigned short __pad1;
+unsigned short  mode;
+unsigned short __pad2;
+# endif
+unsigned short __seq;
+unsigned long long __unused1;
+unsigned long long __unused2;
 #else
 unsigned short mode;
 unsigned short __pad1;
@@ -162,6 +182,26 @@
 
   struct __sanitizer_shmid_ds {
 __sanitizer_ipc_perm shm_perm;
+  #if defined(__sparc__)
+  # if !defined(__arch64__)
+u32 __pad1;
+  # endif
+s64 shm_atime;
+  # if !defined(__arch64__)
+u32 __pad2;
+  # endif
+s64 shm_dtime;
+  # if !defined(__arch64__)
+u32 __pad3;
+  # endif
+s64 shm_ctime;
+uptr shm_segsz;
+int shm_cpid;
+int shm_lpid;
+u64 shm_nattch;
+u64 __glibc_reserved1;
+u64 __glibc_reserved2;
+  #else
   #ifndef __powerpc__
 uptr shm_segsz;
   #elif !defined(__powerpc64__)
@@ -199,6 +239,7 @@
 uptr __unused4;
 uptr __unused5;
   #endif
+#endif
   };
   #endif  // SANITIZER_LINUX && !SANITIZER_ANDROID
 
@@ -365,7 +406,11 @@
   void (*sa_sigaction)(int sig, void *siginfo, void *uctx);
 };
 __sanitizer_sigset_t sa_mask;
+#if defined(__sparc__)
+unsigned long sa_flags;
+#else
 int sa_flags;
+#endif
 #if SANITIZER_LINUX
 void (*sa_restorer)();
 #endif
@@ -511,7 +556,16 @@
   };
 #endif
 
-#define IOC_SIZE(nr) (((nr) >> 16) & 0x3fff)
+#if defined(__sparc__)
+// In sparc the 14 bits SIZE field overlaps with the
+// least significant bit of DIR, so either IOC_READ or
+// IOC_WRITE shall be 1 in order to get a non-zero SIZE.
+# define IOC_SIZE(nr)  \
+  ((nr) >> 29) & 0x7) & (4U|2U)) == 0)? \
+   0: (((nr) >> 16) & 0x3fff))
+#else
+# define IOC_SIZE(nr) (((nr) >> 16) & 0x3fff)
+#endif
 
   extern unsigned struct_arpreq_sz;
   extern unsigned struct_ifreq_sz;
Index: libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
===
--- libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
(revision 207826)
+++ libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
(working copy)
@@ -36,6 +36,7 @@
 #define uid_t __kernel_uid_t
 #define gid_t __kernel_gid_t
 #define off_t __kernel_off_t
+#define time_t __kernel_time_t
 // This header seems to contain the definitions of _kernel_ stat* structs.
 #include 
 #undef ino_t
@@ -62,7 +63,7 @@
   unsigned struct_statfs64_sz = sizeof(struct statfs64);
 }  // namespace __sanitizer
 
-#if !defined(__powerpc64__) && !defined(__x86_64__)
+#if !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__sparc__)
 COMPILER_CHECK(struct___old_kernel_stat_sz == sizeof(struct 
__old_kernel_stat));
 #endif

[PATCH] Don't force line note on second basic block (PR sanitizer/60142)

[Jakub Jelinek]

Hi!

As discussed in the PR, GDB is using the second line note as a marker
to find the end of prologue, but is confused if the prologue contains
multiple basic blocks.  This happens e.g. on x86_64 in stdarg function
which aren't known not to need floating point arguments (GDB apparently
has some hackish disassembling recognizer for that), or e.g. newly
with -fsanitize=address use-after-return prologues, which GDB just doesn't
handle.

My understanding from the
http://gcc.gnu.org/ml/gcc-patches/2004-01/msg01589.html
change that introduced this was that forcing the line note on the second
basic block was added just out of paranoia, so this patch attempts
to fix that by not doing that anymore.

Bootstrapped/regtested on x86_64-linux and i686-linux, and Jan Kratochvil
has tested it with GDB testsuite.  Ok for trunk?

2014-02-18  Jakub Jelinek  

PR sanitizer/60142
* final.c (SEEN_BB): Remove.
(SEEN_NOTE, SEEN_EMITTED): Renumber.
(final_scan_insn): Don't force_source_line on second
NOTE_INSN_BASIC_BLOCK.

--- gcc/final.c.jj  2014-01-03 11:40:35.0 +0100
+++ gcc/final.c 2014-02-18 14:50:36.675445581 +0100
@@ -112,9 +112,8 @@ along with GCC; see the file COPYING3.
 #endif
 
 /* Bitflags used by final_scan_insn.  */
-#define SEEN_BB1
-#define SEEN_NOTE  2
-#define SEEN_EMITTED   4
+#define SEEN_NOTE  1
+#define SEEN_EMITTED   2
 
 /* Last insn processed by final_scan_insn.  */
 static rtx debug_insn;
@@ -2128,9 +2127,7 @@ call_from_call_insn (rtx insn)
 
SEEN is used to track the end of the prologue, for emitting
debug information.  We force the emission of a line note after
-   both NOTE_INSN_PROLOGUE_END and NOTE_INSN_FUNCTION_BEG, or
-   at the beginning of the second basic block, whichever comes
-   first.  */
+   both NOTE_INSN_PROLOGUE_END and NOTE_INSN_FUNCTION_BEG.  */
 
 rtx
 final_scan_insn (rtx insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
@@ -2189,14 +2186,6 @@ final_scan_insn (rtx insn, FILE *file, i
  if (targetm.asm_out.unwind_emit)
targetm.asm_out.unwind_emit (asm_out_file, insn);
 
- if ((*seen & (SEEN_EMITTED | SEEN_BB)) == SEEN_BB)
-   {
- *seen |= SEEN_EMITTED;
- force_source_line = true;
-   }
- else
-   *seen |= SEEN_BB;
-
   discriminator = NOTE_BASIC_BLOCK (insn)->discriminator;
 
  break;

Jakub

[PATCH] Fix -ftrack-macro-expansion preprocessing of A######A (PR preprocessor/58844)

[Jakub Jelinek]

Hi!

The following testcase build with -ftrack-macro-expansion=0,
but don't build otherwise.  The problem seems to be that
the libcpp for macro redefinition warning/error purposes if it sees
more than one paste operator adds those extra CPP_PASTE tokens at the end,
after normal tokens from the macro.  For -ftrack-macro-expansion=0 we were
using macro_real_token_count (macro) to only use the real tokens for macro
expansion purposes, but for track_macro_expansion it used macro->count,
which includes also the extra tokens.

Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux,
ok for trunk (and after a while for 4.8)?

2014-02-18  Jakub Jelinek  

PR preprocessor/58844
* macro.c (enter_macro_context): Only push
macro_real_token_count (macro) tokens rather than
macro->count tokens, regardless of
CPP_OPTION (pfile, track-macro-expansion).

* c-c++-common/cpp/pr58844-1.c: New test.
* c-c++-common/cpp/pr58844-2.c: New test.

--- libcpp/macro.c.jj   2014-01-03 11:42:25.0 +0100
+++ libcpp/macro.c  2014-02-18 12:20:30.679451456 +0100
@@ -1115,21 +1115,22 @@ enter_macro_context (cpp_reader *pfile,
 
   if (macro->paramc == 0)
{
+ unsigned tokens_count = macro_real_token_count (macro);
  if (CPP_OPTION (pfile, track_macro_expansion))
{
- unsigned int i, count = macro->count;
+ unsigned int i;
  const cpp_token *src = macro->exp.tokens;
  const struct line_map *map;
  source_location *virt_locs = NULL;
- _cpp_buff *macro_tokens =
-   tokens_buff_new (pfile, count, &virt_locs);
+ _cpp_buff *macro_tokens
+   = tokens_buff_new (pfile, tokens_count, &virt_locs);
 
  /* Create a macro map to record the locations of the
 tokens that are involved in the expansion. LOCATION
 is the location of the macro expansion point.  */
- map  = linemap_enter_macro (pfile->line_table,
- node, location, count);
- for (i = 0; i < count; ++i)
+ map = linemap_enter_macro (pfile->line_table,
+node, location, tokens_count);
+ for (i = 0; i < tokens_count; ++i)
{
  tokens_buff_add_token (macro_tokens, virt_locs,
 src, src->src_loc,
@@ -1141,16 +1142,12 @@ enter_macro_context (cpp_reader *pfile,
virt_locs,
(const cpp_token **)
macro_tokens->base,
-   count);
- num_macro_tokens_counter += count;
+   tokens_count);
}
  else
-   {
- unsigned tokens_count = macro_real_token_count (macro);
- _cpp_push_token_context (pfile, node, macro->exp.tokens,
-  tokens_count);
- num_macro_tokens_counter += tokens_count;
-   }
+   _cpp_push_token_context (pfile, node, macro->exp.tokens,
+tokens_count);
+ num_macro_tokens_counter += tokens_count;
}
 
   if (pragma_buff)
--- gcc/testsuite/c-c++-common/cpp/pr58844-1.c.jj   2014-02-18 
12:18:40.501075448 +0100
+++ gcc/testsuite/c-c++-common/cpp/pr58844-1.c  2014-02-18 12:18:12.0 
+0100
@@ -0,0 +1,8 @@
+/* PR preprocessor/58844 */
+/* { dg-do compile } */
+/* { dg-options "-ftrack-macro-expansion=0" } */
+
+#define A x##x
+int A = 1;
+#define A x##x /* { dg-message "previous definition" } */
+#define A x##x /* { dg-warning "redefined" } */
--- gcc/testsuite/c-c++-common/cpp/pr58844-2.c.jj   2014-02-18 
12:18:47.415034981 +0100
+++ gcc/testsuite/c-c++-common/cpp/pr58844-2.c  2014-02-18 12:18:53.375009859 
+0100
@@ -0,0 +1,8 @@
+/* PR preprocessor/58844 */
+/* { dg-do compile } */
+/* { dg-options "-ftrack-macro-expansion=2" } */
+
+#define A x##x
+int A = 1;
+#define A x##x /* { dg-message "previous definition" } */
+#define A x##x /* { dg-warning "redefined" } */

Jakub

[PATCH, i386]: Fix PR 60205: No ABI warning for AVX-512

[Uros Bizjak]

Hello!

Just following what AVX warnings do.

2014-02-18  Uros Bizjak  

PR target/60205
* config/i386/i386.h (struct ix86_args): Add warn_avx512f.
* config/i386/i386.c (init_cumulative_args): Initialize warn_avx512f.
(type_natural_mode): Warn ABI change when %zmm register is not
available for AVX512F vector value passing.

testsuite/ChangeLog:

2014-02-18  Uros Bizjak  

PR target/60205
* gcc.target/i386/pr60205-1.c: New test.
* gcc.target/i386/pr60205-2.c: Ditto.

Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32} ,
will commit to mainline later today.

Uros.
Index: config/i386/i386.c
===
--- config/i386/i386.c  (revision 207846)
+++ config/i386/i386.c  (working copy)
@@ -6129,6 +6129,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum,  /* Ar
 }
   if (TARGET_MMX)
 cum->mmx_nregs = MMX_REGPARM_MAX;
+  cum->warn_avx512f = true;
   cum->warn_avx = true;
   cum->warn_sse = true;
   cum->warn_mmx = true;
@@ -6154,6 +6155,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum,  /* Ar
  cum->nregs = 0;
  cum->sse_nregs = 0;
  cum->mmx_nregs = 0;
+ cum->warn_avx512f = 0;
  cum->warn_avx = 0;
  cum->warn_sse = 0;
  cum->warn_mmx = 0;
@@ -6211,7 +6213,7 @@ type_natural_mode (const_tree type, const CUMULATI
   if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
 {
   HOST_WIDE_INT size = int_size_in_bytes (type);
-  if ((size == 8 || size == 16 || size == 32)
+  if ((size == 8 || size == 16 || size == 32 || size == 64)
  /* ??? Generic code allows us to create width 1 vectors.  Ignore.  */
  && TYPE_VECTOR_SUBPARTS (type) > 1)
{
@@ -6227,8 +6229,30 @@ type_natural_mode (const_tree type, const CUMULATI
if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
&& GET_MODE_INNER (mode) == innermode)
  {
-   if (size == 32 && !TARGET_AVX)
+   if (size == 64 && !TARGET_AVX512F)
  {
+   static bool warnedavx512f;
+   static bool warnedavx512f_ret;
+
+   if (cum
+   && !warnedavx512f
+   && cum->warn_avx512f)
+ {
+   warnedavx512f = true;
+   warning (0, "AVX512F vector argument without AVX512F "
+"enabled changes the ABI");
+ }
+   else if (in_return & !warnedavx512f_ret)
+ {
+   warnedavx512f_ret = true;
+   warning (0, "AVX512F vector return without AVX512F "
+"enabled changes the ABI");
+ }
+
+   return TYPE_MODE (type);
+ }
+   else if (size == 32 && !TARGET_AVX)
+ {
static bool warnedavx;
static bool warnedavx_ret;
 
Index: config/i386/i386.h
===
--- config/i386/i386.h  (revision 207846)
+++ config/i386/i386.h  (working copy)
@@ -1606,6 +1606,8 @@ typedef struct ix86_args {
   is used */
   int sse_words;   /* # sse words passed so far */
   int sse_nregs;   /* # sse registers available for passing */
+  int warn_avx512f;/* True when we want to warn
+  about AVX512F ABI.  */
   int warn_avx;/* True when we want to warn about AVX 
ABI.  */
   int warn_sse;/* True when we want to warn about SSE 
ABI.  */
   int warn_mmx;/* True when we want to warn about MMX 
ABI.  */
Index: testsuite/gcc.target/i386/pr60205-1.c
===
--- testsuite/gcc.target/i386/pr60205-1.c   (revision 0)
+++ testsuite/gcc.target/i386/pr60205-1.c   (working copy)
@@ -0,0 +1,14 @@
+/* PR target/60205 */
+/* { dg-options "-O2 -mno-avx512f -Wno-psabi" } */
+/* { dg-skip-if "no AVX512F vector" { *-*-mingw* } } */
+
+typedef int __v16si __attribute__ ((__vector_size__ (64)));
+
+extern __v16si x;
+
+extern void bar (__v16si);
+void
+foo (void)
+{
+  bar (x); /* { dg-message "warning: AVX512F vector argument without AVX512F 
enabled changes the ABI" } */
+}
Index: testsuite/gcc.target/i386/pr60205-2.c
===
--- testsuite/gcc.target/i386/pr60205-2.c   (revision 0)
+++ testsuite/gcc.target/i386/pr60205-2.c   (working copy)
@@ -0,0 +1,13 @@
+/* PR target/60205 */
+/* { dg-options "-O2 -mno-avx512f" } */
+/* { dg-skip-if "no AVX512F vector" { *-*-mingw* } } */
+
+typedef int __v16si __attribute__ ((__vector_size__ (64)));
+
+extern __v16si x;
+
+__v16si
+foo (void)
+{ /* { dg-warn

Re: [C++ Patch] PR 60225

[Jason Merrill]

OK.

Jason

Re: [PATCH] Fixing SEH exceptions for languages != C++

[Kai Tietz]

2014-02-18 17:43 GMT+01:00 Jonathan Schleifer :
> Am 18.02.2014 um 17:41 schrieb Kai Tietz :
>
>> Hi Mike,
>>
>> the patch is reasonable, and my testings haven't shown any
>> regressions.  So from that POV patch would be ok.
>> Nevertheless it would be good to have a bug-report for it, and it is a
>> regression from SjLj.
>
> I reported it being a regression before GCC 4.8.0 was released:
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56870
>
> --
> Jonathan

So patch is ok with proper ChangeLog mentioning PR.  Patch is ok for
back-port too.

Thanks,
Kai

Re: [gomp4] libgomp: Don't update copy_from for the existing mappings.

[Ilya Verbin]

2014-02-18 20:25 GMT+04:00 Thomas Schwinge :
> Sure; this was the consensus, as I understand it.  Though, wouldn't it
> make sense to also add a test case to a) test for this behavior, and also
> b) to document the "GCC interpretation of the OpenMP standard" in this
> case (including a link to the OpenMP issue tracker, or Jakub's email on
> this topic)?
>
> Grüße,
>  Thomas

This issue is not reproducible on the shared memory.  So, currently
(while we perform host fallback), it's impossible to create a
test-case.  But we're going to create a libgomp plugin, that will
emulate a target device with a private memory.  It will allow to run
tests for offloading without having accelerator device.

  -- Ilya

Re: [PATCH] Fixing SEH exceptions for languages != C++

[Jonathan Schleifer]

Am 18.02.2014 um 17:41 schrieb Kai Tietz :

> Hi Mike,
> 
> the patch is reasonable, and my testings haven't shown any
> regressions.  So from that POV patch would be ok.
> Nevertheless it would be good to have a bug-report for it, and it is a
> regression from SjLj.

I reported it being a regression before GCC 4.8.0 was released:

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56870

--
Jonathan

Re: RFA: Fix some gcc tests for 16-bit targets

[nick clifton]

Hi Richard,


Instead of modifying testcases I'd be less nervous if you'd make them require 
32bit. Otherwise you should reproduce the original issues with the modified 
testcases.


OK, I can do that.  How about this patch.

OK to apply ?

Cheers
  Nick

gcc/testsuite/ChangeLog
2014-02-18  Nick Clifton  

* gcc.dg/graphite/pr46966.c: Only run on 32-bit+ targets.
* gcc.dg/pr23623.c: Likewise.
* gcc.dg/pr48784-1.c: Likewise.
* gcc.dg/pr48784-2.c: Likewise.
* gcc.dg/pr56997-2.c: Likewise.
* gcc.dg/sms-6.c: Likewise.
* gcc.dg/torture/pr60183.c: Likewise.
* gcc.dg/torture/vec-cvt-1.c: Likewise.
* gcc.c-torture/execute/20061220-1.x: New.
* gcc.c-torture/execute/pr43220.x: New.
* gcc.c-torture/execute/pr51581-1.x: New.
* gcc.c-torture/execute/pr51581-2.x: New.
* gcc.c-torture/execute/pr58570.x: New.
* gcc.c-torture/unsorted/DFcmp.x: New.
* gcc.c-torture/unsorted/SFset.x: New.

Index: gcc/testsuite/gcc.dg/graphite/pr46966.c
===
--- gcc/testsuite/gcc.dg/graphite/pr46966.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/graphite/pr46966.c	(working copy)
@@ -1,5 +1,7 @@
 /* PR tree-optimization/46966 */
 /* { dg-do compile } */
+/* This test is too big for small targets.  */
+/* { dg-require-effective-target size32plus } */
 /* { dg-options "-O -floop-interchange -ffast-math -fno-tree-copy-prop -fno-tree-loop-im" } */
 
 int a[1000][1000];
Index: gcc/testsuite/gcc.dg/pr23623.c
===
--- gcc/testsuite/gcc.dg/pr23623.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/pr23623.c	(working copy)
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-require-effective-target size32plus } */
 /* { dg-options "-fstrict-volatile-bitfields -fdump-rtl-final" } */
 
 /* With -fstrict-volatile-bitfields, the volatile accesses to bf2.b
Index: gcc/testsuite/gcc.dg/pr48784-1.c
===
--- gcc/testsuite/gcc.dg/pr48784-1.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/pr48784-1.c	(working copy)
@@ -1,4 +1,5 @@
 /* { dg-do run } */
+/* { dg-require-effective-target size32plus } */
 /* { dg-options "-fstrict-volatile-bitfields" } */
 
 extern void abort (void);
Index: gcc/testsuite/gcc.dg/pr48784-2.c
===
--- gcc/testsuite/gcc.dg/pr48784-2.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/pr48784-2.c	(working copy)
@@ -1,4 +1,5 @@
 /* { dg-do run } */
+/* { dg-require-effective-target size32plus } */
 /* { dg-options "-fno-strict-volatile-bitfields" } */
 
 extern void abort (void);
Index: gcc/testsuite/gcc.dg/pr56997-2.c
===
--- gcc/testsuite/gcc.dg/pr56997-2.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/pr56997-2.c	(working copy)
@@ -1,5 +1,6 @@
 /* Test volatile access to unaligned field.  */
 /* { dg-do run } */
+/* { dg-require-effective-target size32plus } */
 /* { dg-options "-fstrict-volatile-bitfields" } */
 
 extern void abort (void);
Index: gcc/testsuite/gcc.dg/sms-6.c
===
--- gcc/testsuite/gcc.dg/sms-6.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/sms-6.c	(working copy)
@@ -1,4 +1,5 @@
 /* { dg-do run } */
+/* { dg-require-effective-target size32plus } */
 /* { dg-options "-O2 -fmodulo-sched -fdump-rtl-sms --param sms-min-sc=1" } */
 /* { dg-options "-O2 -fmodulo-sched -fdump-rtl-sms --param sms-min-sc=1 -fmodulo-sched-allow-regmoves" { target powerpc*-*-* } } */
 
Index: gcc/testsuite/gcc.dg/torture/pr60183.c
===
--- gcc/testsuite/gcc.dg/torture/pr60183.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/torture/pr60183.c	(working copy)
@@ -1,4 +1,5 @@
 /* { dg-do run } */
+/* { dg-require-effective-target size32plus } */
 
 /* Large so an out-of-bound read will crash.  */
 unsigned char c[0x30001] = { 1 };
Index: gcc/testsuite/gcc.dg/torture/vec-cvt-1.c
===
--- gcc/testsuite/gcc.dg/torture/vec-cvt-1.c	(revision 207836)
+++ gcc/testsuite/gcc.dg/torture/vec-cvt-1.c	(working copy)
@@ -1,4 +1,6 @@
 /* { dg-do run } */
+/* This test is too big for small targets.  */
+/* { dg-require-effective-target size32plus } */
 
 #include 
 
*** /dev/null	2014-02-18 08:00:55.971916261 +
--- gcc/testsuite/gcc.c-torture/execute/20061220-1.x	2014-02-12 17:20:52.601890142 +
***
*** 0 
--- 1,6 
+ # asm statements for the RL78 do not work as expected
+ if { [istarget "rl78-*-*"] } {
+ return 1;
+ }
+ 
+ return 0
*** /dev/null	2014-02-18 08:00:55.971916261 +
--- gcc/testsuite/gcc.c-torture/execute/pr43220.x	2014-02-18 13:07:38.953426402 +
***
*** 0 
--- 1,7 
+ load_lib target-supports.exp
+ 
+ if { [ch

Re: [PATCH] Fixing SEH exceptions for languages != C++

[Kai Tietz]

2014-02-17 12:22 GMT+01:00 Jonathan Schleifer :
> Am 16.02.2014 um 16:47 schrieb Mike Stump :
>
>> On Feb 15, 2014, at 9:27 AM, Jonathan Schleifer  wrote:
>>> The following patch fixes a bug in SEH exception handling that made it
>>> crash with ObjC
>>
>> From an ObjC perspective, I'm fine with the work; though, an seh person 
>> needs to weigh in.  I'm fine with the back port as well.
>
> Is there anybody specific whom I should ping, like a maintainer for SEH 
> exceptions in GCC?
>
> --
> Jonathan

Hi Mike,

the patch is reasonable, and my testings haven't shown any
regressions.  So from that POV patch would be ok.
Nevertheless it would be good to have a bug-report for it, and it is a
regression from SjLj.

Kai

[C++ Patch] PR 60225

[Paolo Carlini]

Hi,

as noticed by Marc, this ICE on invalid regression is essentially due to 
the fact that ensure_literal_type_for_constexpr_object, at variance with 
literal_type_p, doesn't use strip_array_types, thus, in:


  if (CLASS_TYPE_P (type) && !COMPLETE_TYPE_P (complete_type (type)))
/* Don't complain here, we'll complain about incompleteness
when we try to initialize the variable.  */;
   else if (!literal_type_p (type))

doesn't look through ARRAY_TYPEs and ends up calling literal_type_p, 
which asserts COMPLETE_TYPE_P (t) which ICEs for the testcase at issue. 
I'm proposing restoring the consistency in the below obvious way. Tested 
x86_64-linux.


Thanks,
Paolo.

///
/cp
2014-02-18  Paolo Carlini  

PR c++/60225
* semantics.c (ensure_literal_type_for_constexpr_object): Use
strip_array_types.

/testsuite
2014-02-18  Paolo Carlini  

PR c++/60225
* g++.dg/cpp0x/constexpr-ice10.C: New.
Index: cp/semantics.c
===
--- cp/semantics.c  (revision 207837)
+++ cp/semantics.c  (working copy)
@@ -7380,7 +7380,8 @@ ensure_literal_type_for_constexpr_object (tree dec
   if (VAR_P (decl) && DECL_DECLARED_CONSTEXPR_P (decl)
   && !processing_template_decl)
 {
-  if (CLASS_TYPE_P (type) && !COMPLETE_TYPE_P (complete_type (type)))
+  tree stype = strip_array_types (type);
+  if (CLASS_TYPE_P (stype) && !COMPLETE_TYPE_P (complete_type (stype)))
/* Don't complain here, we'll complain about incompleteness
   when we try to initialize the variable.  */;
   else if (!literal_type_p (type))
Index: testsuite/g++.dg/cpp0x/constexpr-ice10.C
===
--- testsuite/g++.dg/cpp0x/constexpr-ice10.C(revision 0)
+++ testsuite/g++.dg/cpp0x/constexpr-ice10.C(working copy)
@@ -0,0 +1,8 @@
+// PR c++/60225
+// { dg-do compile { target c++11 } }
+
+struct A
+{
+  constexpr A() {}
+  static constexpr A a[2] = {};  // { dg-error "incomplete" }
+};

Re: [gomp4] libgomp: Don't update copy_from for the existing mappings.

[Thomas Schwinge]

Hi Ilya!

On Mon, 17 Feb 2014 21:06:41 +0400, Ilya Verbin  wrote:
> Here is the fix for the issue discussed in 
> http://gcc.gnu.org/ml/gcc/2014-02/msg00257.html
> 
> OK to commit to gomp-4_0-branch?

> + * target.c (gomp_map_vars_existing): Don't update copy_from for the
> + existing mappings.

> --- a/libgomp/target.c
> +++ b/libgomp/target.c
> @@ -171,11 +171,6 @@ gomp_map_vars_existing (splay_tree_key oldn, 
> splay_tree_key newn,
>   "[%p..%p) is already mapped",
>   (void *) newn->host_start, (void *) newn->host_end,
>   (void *) oldn->host_start, (void *) oldn->host_end);
> -  if (((kind & 7) == 2 || (kind & 7) == 3)
> -  && !oldn->copy_from
> -  && oldn->host_start == newn->host_start
> -  && oldn->host_end == newn->host_end)
> -oldn->copy_from = true;
>oldn->refcount++;
>  }

Sure; this was the consensus, as I understand it.  Though, wouldn't it
make sense to also add a test case to a) test for this behavior, and also
b) to document the "GCC interpretation of the OpenMP standard" in this
case (including a link to the OpenMP issue tracker, or Jakub's email on
this topic)?


Grüße,
 Thomas


pgpkQQKsIlfYO.pgp
Description: PGP signature

Re: [PATCH, PR 55260] Use correct info in cgraph_edge_brings_all_agg_vals_for_node

[Markus Trippelsdorf]

On 2014.02.04 at 17:48 +0100, Martin Jambor wrote:
> PR 55260 has been reopened because there is still one use of wrong
> info, this time in cgraph_edge_brings_all_agg_vals_for_node when
> checking whether aggregate lattices are set to bottom which can lead
> to index out of bounds assert failures or even potentially ignoring
> bottom lattices.
> 
> Fixed thusly.  Bootstrapped and tested on trunk on x86_64-linux,
> bootstrap is still underway on the 4.8 branch where this exact fix is
> also necessary.  OK for both?

Ping.

Libreoffice LTO build also fails right now because of this issue.

Honza, can you take a look at this patch?

Thanks.

> 2014-02-03  Martin Jambor  
> 
>   PR ipa/55260
>   * ipa-cp.c (cgraph_edge_brings_all_agg_vals_for_node): Uce correct
>   info when checking whether lattices are bottom.
> 
> testsuite/
>   * gcc.dg/ipa/pr55260.c: New test.
> 
> diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c
> index 10fa4b6..70bb33f 100644
> --- a/gcc/ipa-cp.c
> +++ b/gcc/ipa-cp.c
> @@ -3178,6 +3178,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct 
> cgraph_edge *cs,
> struct cgraph_node *node)
>  {
>struct ipa_node_params *orig_caller_info = IPA_NODE_REF (cs->caller);
> +  struct ipa_node_params *orig_node_info;
>struct ipa_agg_replacement_value *aggval;
>int i, ec, count;
>  
> @@ -3192,6 +3193,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct 
> cgraph_edge *cs,
>if (aggval->index >= ec)
>   return false;
>  
> +  orig_node_info = IPA_NODE_REF (IPA_NODE_REF (node)->ipcp_orig_node);
>if (orig_caller_info->ipcp_orig_node)
>  orig_caller_info = IPA_NODE_REF (orig_caller_info->ipcp_orig_node);
>  
> @@ -3209,7 +3211,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct 
> cgraph_edge *cs,
>if (!interesting)
>   continue;
>  
> -  plats = ipa_get_parm_lattices (orig_caller_info, aggval->index);
> +  plats = ipa_get_parm_lattices (orig_node_info, aggval->index);
>if (plats->aggs_bottom)
>   return false;
>  
> diff --git a/gcc/testsuite/gcc.dg/ipa/pr55260.c 
> b/gcc/testsuite/gcc.dg/ipa/pr55260.c
> new file mode 100644
> index 000..ef151b0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/ipa/pr55260.c
> @@ -0,0 +1,38 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fno-inline -fipa-cp-clone"  } */
> +
> +typedef struct {
> +  int *ptr;
> +  int len;
> +} string;
> +typedef struct {
> +  string nantstr;
> +  int *nant;
> +} malv;
> +typedef struct {
> +  int *nor;
> +} list_heads;
> +int b;
> +list_heads *fn1(string, int *, unsigned);
> +void fn2(malv *p1, list_heads *p2, unsigned p3) {
> +  string a = p1->nantstr;
> +  fn1(a, p1->nant, p3);
> +}
> +
> +void fn3(unsigned p1) { fn2(0, 0, p1); }
> +
> +list_heads *fn1(string p1, int *p2, unsigned p3) {
> +  while (1) {
> +if (p3)
> +  fn3(1);
> +if (b)
> +  return 0;
> +fn3(1);
> +  }
> +}
> +
> +void fn5() {
> +  list_heads c;
> +  c.nor = 0;
> +  fn2(0, &c, 1);
> +}
> 

-- 
Markus

[5.0] PR60194 [c-family] add -Wformat-signedness to warn about %d/%u signedness mismatch

[Tobias Burnus]

This patch adds a warning to -Wformat=2, which can also be used as
-Wformat -Wformat-signedness and which warns when the signedness
of the argument doesn't match the one of %x/%u/%d/%i/...

That was motivated by a check of cppcheck, which found some issues
in a bigger code.

Bootstrapped and regtested on x86-64-gnu-linux.
OK when Stage 1 opens again?

Tobias
2014-02-18  Tobias Burnus  

	PR c/60194

gcc/c-family/
	* c.opt (Wformat-signedness): Add
	* c-format.c(check_format_types): Use it.

gcc/
	* doc/invoke.texi (-Wformat-signedness): Document it.
	(Wformat=2): Mention that this enables -Wformat-signedness.

gcc/testsuite/:
	* g++.dg/warn/warn_format_signedness.C: New.
	* gcc.dg/format/warn-signedness.c


diff --git a/gcc/c-family/c-format.c b/gcc/c-family/c-format.c
index cdc09c4..4c0313d 100644
--- a/gcc/c-family/c-format.c
+++ b/gcc/c-family/c-format.c
@@ -2418,7 +2418,9 @@ check_format_types (format_wanted_type *types)
 	 a second level of indirection.  */
   if (TREE_CODE (wanted_type) == INTEGER_TYPE
 	  && TREE_CODE (cur_type) == INTEGER_TYPE
-	  && (!pedantic || i == 0 || (i == 1 && char_type_flag))
+	  && ((!pedantic && !warn_format_signedness)
+	  || (i == 0 && !warn_format_signedness)
+	  || (i == 1 && char_type_flag))
 	  && (TYPE_UNSIGNED (wanted_type)
 	  ? wanted_type == c_common_unsigned_type (cur_type)
 	  : wanted_type == c_common_signed_type (cur_type)))
diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
index aad54e2..7fa6381 100644
--- a/gcc/c-family/c.opt
+++ b/gcc/c-family/c.opt
@@ -415,6 +415,10 @@ Wformat-security
 C ObjC C++ ObjC++ Var(warn_format_security) Warning LangEnabledBy(C ObjC C++ ObjC++,Wformat=, warn_format >= 2, 0)
 Warn about possible security problems with format functions
 
+Wformat-signedness
+C ObjC C++ ObjC++ Var(warn_format_signedness) Warning LangEnabledBy(C ObjC C++ ObjC++,Wformat=, warn_format >= 2, 0)
+Warn about sign differences with format functions
+
 Wformat-y2k
 C ObjC C++ ObjC++ Var(warn_format_y2k) Warning LangEnabledBy(C ObjC C++ ObjC++,Wformat=,warn_format >= 2, 0)
 Warn about strftime formats yielding 2-digit years
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4d1b657..ab8101d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -246,7 +246,7 @@ Objective-C and Objective-C++ Dialects}.
 -Wno-endif-labels -Werror  -Werror=* @gol
 -Wfatal-errors  -Wfloat-equal  -Wformat  -Wformat=2 @gol
 -Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol
--Wformat-security  -Wformat-y2k @gol
+-Wformat-security  -Wformat-signedness  -Wformat-y2k @gol
 -Wframe-larger-than=@var{len} -Wno-free-nonheap-object -Wjump-misses-init @gol
 -Wignored-qualifiers @gol
 -Wimplicit  -Wimplicit-function-declaration  -Wimplicit-int @gol
@@ -3564,7 +3564,7 @@ The C standard specifies that zero-length formats are allowed.
 @opindex Wformat=2
 Enable @option{-Wformat} plus additional format checks.  Currently
 equivalent to @option{-Wformat -Wformat-nonliteral -Wformat-security
--Wformat-y2k}.
+-Wformat-signedness -Wformat-y2k}.
 
 @item -Wformat-nonliteral
 @opindex Wformat-nonliteral
@@ -3586,6 +3586,12 @@ currently a subset of what @option{-Wformat-nonliteral} warns about, but
 in future warnings may be added to @option{-Wformat-security} that are not
 included in @option{-Wformat-nonliteral}.)
 
+@item -Wformat-signedness
+@opindex Wformat-signedness
+@opindex Wno-format-signedness
+If @option{-Wformat} is specified, also warn if the format string
+requires an unsigned argument and the argument is signed and vice versa.
+
 @item -Wformat-y2k
 @opindex Wformat-y2k
 @opindex Wno-format-y2k
diff --git a/gcc/testsuite/g++.dg/warn/warn_format_signedness.C b/gcc/testsuite/g++.dg/warn/warn_format_signedness.C
new file mode 100644
index 000..473d522
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/warn_format_signedness.C
@@ -0,0 +1,11 @@
+/* { dg-do compile }  */
+/* { dg-options "-Wformat -Wformat-signedness" }  */
+
+/* PR c/60194  */
+
+void foo(unsigned u, int i, unsigned char uc, signed char sc) {
+  __builtin_printf("%d\n", u);  /* { dg-warning "expects argument of type 'int', but argument 2 has type 'unsigned int'" } */
+  __builtin_printf("%u\n", i);  /* { dg-warning "expects argument of type 'unsigned int', but argument 2 has type 'int'" } */
+  __builtin_printf("%c\n", sc);
+  __builtin_printf("%c\n", uc);
+}
diff --git a/gcc/testsuite/gcc.dg/format/warn-signedness.c b/gcc/testsuite/gcc.dg/format/warn-signedness.c
new file mode 100644
index 000..473d522
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/format/warn-signedness.c
@@ -0,0 +1,11 @@
+/* { dg-do compile }  */
+/* { dg-options "-Wformat -Wformat-signedness" }  */
+
+/* PR c/60194  */
+
+void foo(unsigned u, int i, unsigned char uc, signed char sc) {
+  __builtin_printf("%d\n", u);  /* { dg-warning "expects argument of type 'int', but argument 2 has type 'unsigned int'" } */
+  __builtin_printf("%u\n", i);  /* { dg-warning "expects argument of type 'unsigned

Re: [PATCH ARM] Fix PR60264 (ICE in dwarf2out_frame_debug_adjust_cfa)

[Christian Bruel]

probably easier to review with patch attached...

2014-02-18  Christian Bruel  

	PR target/60264
	* config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Restore cfa register.
	(arm_expand_epilogue_apcs_frame): Set RTX_FRAME_RELATED_P.

2014-02-18  Christian Bruel  

	PR target/60264
	* gcc.target/arm/pr60264.c
	* gcc.target/arm/pr60264-2.c

Index: gcc/config/arm/arm.c
===
--- gcc/config/arm/arm.c	(revision 207817)
+++ gcc/config/arm/arm.c	(working copy)
@@ -19909,8 +19909,13 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int num
   par = emit_insn (par);
   REG_NOTES (par) = dwarf;
 
+  /* Make sure cfa doesn't leave with IP_REGNUM.  */
+  if (TARGET_VFP && REGNO (base_reg) == IP_REGNUM)
+add_reg_note (par, REG_CFA_DEF_CFA, hard_frame_pointer_rtx);
+
   arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
 			   base_reg, base_reg);
+
 }
 
 /* Generate and emit a pattern that will be recognized as LDRD pattern.  If even
@@ -27103,10 +27108,12 @@ arm_expand_epilogue_apcs_frame (bool really_return
   int saved_size = arm_get_vfp_saved_size ();
   if (saved_size > 0)
 {
-  floats_from_frame += saved_size;
-  emit_insn (gen_addsi3 (gen_rtx_REG (SImode, IP_REGNUM),
- hard_frame_pointer_rtx,
- GEN_INT (-floats_from_frame)));
+	  rtx insn;
+	  floats_from_frame += saved_size;
+	  insn = emit_insn (gen_addsi3 (gen_rtx_REG (SImode, IP_REGNUM),
+	hard_frame_pointer_rtx,
+	GEN_INT (-floats_from_frame)));
+	  RTX_FRAME_RELATED_P (insn) = 1;
 }
 
   /* Generate VFP register multi-pop.  */
@@ -27179,11 +27186,13 @@ arm_expand_epilogue_apcs_frame (bool really_return
   num_regs = bit_count (saved_regs_mask);
   if ((offsets->outgoing_args != (1 + num_regs)) || cfun->calls_alloca)
 {
+  rtx insn;
   emit_insn (gen_blockage ());
   /* Unwind the stack to just below the saved registers.  */
-  emit_insn (gen_addsi3 (stack_pointer_rtx,
- hard_frame_pointer_rtx,
- GEN_INT (- 4 * num_regs)));
+  insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
+hard_frame_pointer_rtx,
+GEN_INT (- 4 * num_regs)));
+  RTX_FRAME_RELATED_P (insn) = 1;
 }
 
   arm_emit_multi_reg_pop (saved_regs_mask);
Index: gcc/testsuite/gcc.target/arm/pr60264-2.c
===
--- gcc/testsuite/gcc.target/arm/pr60264-2.c	(revision 0)
+++ gcc/testsuite/gcc.target/arm/pr60264-2.c	(working copy)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mapcs -mfloat-abi=hard  -g" } */
+
+double bar(void);
+
+int foo(void)
+{
+  int i = bar() + bar();
+
+  return i;
+}
+
Index: gcc/testsuite/gcc.target/arm/pr60264.c
===
--- gcc/testsuite/gcc.target/arm/pr60264.c	(revision 0)
+++ gcc/testsuite/gcc.target/arm/pr60264.c	(working copy)
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mapcs -g" } */
+
+void
+bar()
+{
+  foo();
+  foo();
+}

[PATCH ARM] Fix PR60264 (ICE in dwarf2out_frame_debug_adjust_cfa)

[Christian Bruel]

Hello,

Considering the attached trivial case with the epilogue:

 sub sp, fp, #12
 ldmia   sp, {fp, sp, lr}frame_related_p
 
the sub instruction should also be frame_related_fp. (a gcc_assert
triggers in dwarf2out_frame_debug_adjust_cfa)

This patch sets RTX_FRAME_RELATED_P on stack restore instructions for
the -mapcs ABI.

A second problem arise with -mfloat-abi=hard, hidden by the above. a vrp
poping instruction in the epilogue (see tescase from the PR)  sets the
cfa register to IP, although the following instruction updates FP

 fldmfdd ip!, {d8}frame_related_p
 sub sp, fp, #12   frame_related_p
 ldmia   sp, {fp, sp, lr}frame_related_p

This patch adds a  REG_CFA_DEF_CFA note so the sub instruction gets the
FP as expected.

Regression tested for  for armv7-a
--target_board=arm-sim/\{,-mapcs-frame\}. Fixes a large number of
compilation errors in the testsuite.

OK for trunk ?

Many Thanks

Re: RFA: RL78: Add missing instruction patterns

[nick clifton]

Hi DJ,


I'm OK with adding patterns in general, but I wonder if gcc would
produce better code if they were split into QImode ops earlier?


Probably.  In fact I double checked and I can no longer find the tests 
that triggered the need for the new "andhi3" and "xorhi3" patterns, so 
the revised patch below removes them,


Cheers
  Nick


gcc/ChangeLog
2014-02-18  Nick Clifton  

* config/rl78/rl78-real.md (cbranchsi4_real_signed): Add
anti-cacnonical alternatives.
(negandhi3_real): New pattern.
* config/rl78/rl78-virt.md (negandhi3_virt): New pattern.


Index: gcc/config/rl78/rl78-real.md
===
--- gcc/config/rl78/rl78-real.md(revision 207836)
+++ gcc/config/rl78/rl78-real.md(working copy)
@@ -411,8 +411,8 @@
 (define_insn "*cbranchsi4_real_signed"
   [(set (pc) (if_then_else
  (match_operator 0 "rl78_cmp_operator_signed"
- [(match_operand:SI 1 "nonimmediate_operand" 
"vU,vU,vU")
-  (match_operand:SI 2 "nonmemory_operand" 
"ISsi,i,v")])
+ [(match_operand:SI 1 "general_operand"   
"vU,vU,vU,i,i")
+  (match_operand:SI 2 "nonmemory_operand" 
"ISsi,i,v,S,v")])
   (label_ref (match_operand 3 "" ""))
  (pc)))
(clobber (reg:HI AX_REG))
@@ -421,7 +421,9 @@
   "@
movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;not1 CY\;  movw 
ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;   movw 
ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
-   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw 
ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3"
+   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw 
ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
+   movw ax, %H1\; cmpw  ax, %H2\; xor1 CY, a.7\; not1 CY\; movw ax, %h1 
\;sknz\; cmpw  ax, %h2 \;sk%0 \;br\t!!%3
+   movw ax, %H1\; cmpw  ax, %H2\; xor1 CY, a.7\; movw ax, %h1\; sknz\; 
cmpw ax, %h2\; sk%0\; br\t!!%3"

   )

 (define_insn "*cbranchsi4_real"
@@ -549,3 +551,12 @@
   [(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
   )

+(define_insn "*negandhi3_real"
+  [(set (match_operand:HI 0 "register_operand"  "=A")
+   (and:HI (neg:HI (match_operand:HI 1 "register_operand"  "0"))
+   (match_operand:HI 2 "immediate_operand" "n")))
+   ]
+  "rl78_real_insns_ok ()"
+  "xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ 
and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x"

+)
+
Index: gcc/config/rl78/rl78-virt.md
===
--- gcc/config/rl78/rl78-virt.md(revision 207836)
+++ gcc/config/rl78/rl78-virt.md(working copy)
@@ -405,3 +405,12 @@
]
   "rl78_setup_peep_movhi (operands);"
   )
+
+(define_insn "*negandhi3_virt"
+  [(set (match_operand:HI 0 "register_operand" "=v")
+   (and:HI (neg:HI (match_operand:HI 1 "register_operand"  "0"))
+   (match_operand:HI 2 "immediate_operand" "n")))
+   ]
+  "rl78_virt_insns_ok ()"
+  "v.nand\t%0, %1, %2"
+)

[testsuite] XFAIL gcc.dg/torture/pr60092.c execution on Solaris 11

[Rainer Orth]

As described in PR middle-end/60092, gcc.dg/torture/pr60092.c execution
FAILs at -O0 on Solaris 11.  posix_memalign modifies it's first arg in
the error case, which is at least a QOI issue.

Therefore I'd like to XFAIL the test like this.  Tested with the
appropriate runtest invocation on i386-pc-solaris2.10,
i386-pc-solaris2.11, sparc-sun-solaris2.11, and
x86_64-unknown-linux-gnu.

Ok for mainline?

Rainer


2014-02-18  Rainer Orth  

* gcc.dg/torture/pr60092.c: xfail execution on *-*-solaris2.11* at -O0.

# HG changeset patch
# Parent 6bae6f59c3da3dbde951b8044014c788747c3849
XFAIL gcc.dg/torture/pr60092.c execution on Solaris 11

diff --git a/gcc/testsuite/gcc.dg/torture/pr60092.c b/gcc/testsuite/gcc.dg/torture/pr60092.c
--- a/gcc/testsuite/gcc.dg/torture/pr60092.c
+++ b/gcc/testsuite/gcc.dg/torture/pr60092.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-weak "" } */
+/* { dg-xfail-run-if "posix_memalign modifies first arg on error" { *-*-solaris2.11* } { "-O0" } } */
 
 typedef __SIZE_TYPE__ size_t;
 extern int posix_memalign(void **memptr, size_t alignment, size_t size) __attribute__((weak));

-- 
-
Rainer Orth, Center for Biotechnology, Bielefeld University

[PATCH] Fix libjava install with --enable-version-specific-runtime-libs

[Richard Biener]

The following two pieces fix the fallout of

2013-05-22  Mark Mitchell  
Sandra Loosemore  

* configure.ac (dbexecdir): Base on $(toolexeclibdir), not
$(libdir).
...

that makes a wreck out of my 4.9-based libjava installs.

First it avoids to break dbexecdir with MULTSUBDIR= by removing
the redundant but non-version-specific-aware multilib addition.

Second, it makes sure that gcc_version, used in the
version-specific path, is defined at all in classpath/ and its
subdirs.

Tested for my particular configuration, I'll do a default,
non-version-specific one as well (but expect no changes).

Ok for trunk?

Thanks,
Richard.

2014-02-18  Richard Biener  

PR libjava/60261
* configure.ac (dbexecdir): Remove redundant multilib addition.
* Makefile.am (gcc_version): Export.
* configure: Regenerate.
* Makefile.in: Likewise.

Index: libjava/configure.ac
===
--- libjava/configure.ac(revision 207837)
+++ libjava/configure.ac(working copy)
@@ -1596,15 +1596,7 @@ AC_DEFINE_UNQUOTED(GCJVERSION, "$GCJVERS
 # Determine where the standard .db file and GNU Classpath JNI
 # libraries are found.
 gcjsubdir=gcj-$gcjversion-$libgcj_soversion
-multi_os_directory=`$CC -print-multi-os-directory`
-case $multi_os_directory in
-  .)
-   dbexecdir='$(toolexeclibdir)/'$gcjsubdir # Avoid /.
-   ;;
-  *)
-   dbexecdir='$(toolexeclibdir)/'$multi_os_directory/$gcjsubdir
-   ;;
-esac
+dbexecdir='$(toolexeclibdir)/'$gcjsubdir
 AC_SUBST(dbexecdir)
 AC_SUBST(gcjsubdir)
 
Index: libjava/configure
===
--- libjava/configure   (revision 207837)
+++ libjava/configure   (working copy)
@@ -24016,15 +24016,7 @@ _ACEOF
 # Determine where the standard .db file and GNU Classpath JNI
 # libraries are found.
 gcjsubdir=gcj-$gcjversion-$libgcj_soversion
-multi_os_directory=`$CC -print-multi-os-directory`
-case $multi_os_directory in
-  .)
-   dbexecdir='$(toolexeclibdir)/'$gcjsubdir # Avoid /.
-   ;;
-  *)
-   dbexecdir='$(toolexeclibdir)/'$multi_os_directory/$gcjsubdir
-   ;;
-esac
+dbexecdir='$(toolexeclibdir)/'$gcjsubdir
 
 
 
Index: libjava/Makefile.am
===
--- libjava/Makefile.am (revision 207837)
+++ libjava/Makefile.am (working copy)
@@ -6,6 +6,7 @@ ACLOCAL_AMFLAGS = -I . -I .. -I ../confi
 
 # May be used by various substitution variables.
 gcc_version := $(shell cat $(top_srcdir)/../gcc/BASE-VER)
+export gcc_version
 
 SUBDIRS = $(DIRLTDL) gcj include classpath
 if TESTSUBDIR
Index: libjava/Makefile.in
===
--- libjava/Makefile.in (revision 207837)
+++ libjava/Makefile.in (working copy)
@@ -10581,6 +10581,7 @@ uninstall-am: uninstall-binPROGRAMS unin
uninstall-libexecsubPROGRAMS uninstall-toolexeclibLTLIBRARIES \
uninstall-toolexecmainlibDATA
 
+export gcc_version
 
 interpret.lo:  AM_CXXFLAGS += -fwrapv
 prims.lo: AM_CXXFLAGS += -fno-omit-frame-pointer

[PATCH] Fix PR60221

[Richard Biener]

This makes sure to run cleanup-all-empty-eh even at -O0 via ehcleanup2.

Bootstrapped and tested on x86_64-unknown-linux-gnu, ok for trunk
(and branches?)

Thanks,
Richard.

2014-02-18  Richard Biener  

PR middle-end/60221
* tree-eh.c (execute_cleanup_eh_1): Also cleanup empty EH
regions at -O0.

Index: gcc/tree-eh.c
===
*** gcc/tree-eh.c   (revision 207837)
--- gcc/tree-eh.c   (working copy)
*** execute_cleanup_eh_1 (void)
*** 4557,4567 
remove_unreachable_handlers ();
  
/* Watch out for the region tree vanishing due to all unreachable.  */
!   if (cfun->eh->region_tree && optimize)
  {
bool changed = false;
  
!   changed |= unsplit_all_eh ();
changed |= cleanup_all_empty_eh ();
  
if (changed)
--- 4557,4568 
remove_unreachable_handlers ();
  
/* Watch out for the region tree vanishing due to all unreachable.  */
!   if (cfun->eh->region_tree)
  {
bool changed = false;
  
!   if (optimize)
!   changed |= unsplit_all_eh ();
changed |= cleanup_all_empty_eh ();
  
if (changed)

[AArch64] Relax modes_tieable_p and cannot_change_mode_class

[James Greenhalgh]

Hi,

We aim to improve code generation for the vector structure types
such as int64x2x4_t, as used in the vld/st{2,3,4} lane neon
intrinsics.

It should be possible and cheap to get individual vectors in
and out of these structures - these structures are implemented as
opaque integer modes straddling multiple vector registers.

To do this, we want to weaken the conditions for
aarch64_cannot_change_mode_class - to permit cheap subreg
operations - and for TARGET_MODES_TIEABLE_P - to allow all combinations
of vector structure and vector types to coexist.

Regression tested on aarch64-none-elf with no issues.

This is a bit too intrusive for Stage 4, but is it OK to
queue for Stage 1?

Thanks,
James

---
gcc/

2014-02-18  James Greenhalgh  

* config/aarch64/aarch64-protos.h (aarch64_modes_tieable_p): New.
* config/aarch64/aarch64.c
(aarch64_cannot_change_mode_class): Weaken conditions.
(aarch64_modes_tieable_p): New.
* config/aarch64/aarch64.h (MODES_TIEABLE_P): Use it.
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 5542f02..04cbc78 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -175,6 +175,8 @@ bool aarch64_is_extend_from_extract (enum machine_mode, rtx, rtx);
 bool aarch64_is_long_call_p (rtx);
 bool aarch64_label_mentioned_p (rtx);
 bool aarch64_legitimate_pic_operand_p (rtx);
+bool aarch64_modes_tieable_p (enum machine_mode mode1,
+			  enum machine_mode mode2);
 bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
 bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
 			enum machine_mode);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ea90311..853d1a9 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -8283,7 +8283,8 @@ aarch64_cannot_change_mode_class (enum machine_mode from,
   /* Limited combinations of subregs are safe on FPREGs.  Particularly,
  1. Vector Mode to Scalar mode where 1 unit of the vector is accessed.
  2. Scalar to Scalar for integer modes or same size float modes.
- 3. Vector to Vector modes.  */
+ 3. Vector to Vector modes.
+ 4. On little-endian only, Vector-Structure to Vector modes.  */
   if (GET_MODE_SIZE (from) > GET_MODE_SIZE (to))
 {
   if (aarch64_vector_mode_supported_p (from)
@@ -8299,11 +8300,41 @@ aarch64_cannot_change_mode_class (enum machine_mode from,
   if (aarch64_vector_mode_supported_p (from)
 	  && aarch64_vector_mode_supported_p (to))
 	return false;
+
+  /* Within an vector structure straddling multiple vector registers
+	 we are in a mixed-endian representation.  As such, we can't
+	 easily change modes for BYTES_BIG_ENDIAN.  Otherwise, we can
+	 switch between vectors and vector structures cheaply.  */
+  if (!BYTES_BIG_ENDIAN)
+	if ((aarch64_vector_mode_supported_p (from)
+	  && aarch64_vect_struct_mode_p (to))
+	|| (aarch64_vector_mode_supported_p (to)
+	  && aarch64_vect_struct_mode_p (from)))
+	  return false;
 }
 
   return true;
 }
 
+/* Implement MODES_TIEABLE_P.  */
+
+bool
+aarch64_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
+{
+  if (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2))
+return true;
+
+  /* We specifically want to allow elements of "structure" modes to
+ be tieable to the structure.  This more general condition allows
+ other rarer situations too.  */
+  if (TARGET_SIMD
+  && aarch64_vector_mode_p (mode1)
+  && aarch64_vector_mode_p (mode2))
+return true;
+
+  return false;
+}
+
 #undef TARGET_ADDRESS_COST
 #define TARGET_ADDRESS_COST aarch64_address_cost
 
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 13c424c..a85de99 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -362,8 +362,7 @@ extern unsigned long aarch64_tune_flags;
 
 #define HARD_REGNO_MODE_OK(REGNO, MODE)	aarch64_hard_regno_mode_ok (REGNO, MODE)
 
-#define MODES_TIEABLE_P(MODE1, MODE2)			\
-  (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
+#define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2)
 
 #define DWARF2_UNWIND_INFO 1
 

[AArch64 testsuite] Make vect-abs.c C99 compliant

[James Greenhalgh]

Hi,

This test fails on a linux build because it tries to use the
LONG_LONG_{MAX/MIN} macros from "types.h". These are not guaranteed
to exist, and my system "types.h" doesn't provide them. C99 provides
LLONG_{MIN/MAX} for this purpose.

A gnu89 baremetal compiler doesn't seem to carry these macros
so we must add -std=c99.

But then this testcase doesn't properly declare its functions, relying
on an implicit int return type.

So I've fixed those up and now the test passes on aarch64-none-elf and
aarch64-none-linux-gnu.

I guess the patch is obvious and low risk as it is a target
specific test, but as we are late in Stage 4 I'd like
approval before I commit.

OK?

Thanks,
James

---
gcc/testsuite/

2014-02-18  James Greenhalgh  

* gcc.target/aarch64/vect-abs.c (dg-options): Add -std=c99.
(LONG_LONG): Use LLONG.
(set_rvector_long): Explicitly return void.
(set_vector_long): Likewise.
(check_vector_long): Likewise.
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-abs.c b/gcc/testsuite/gcc.target/aarch64/vect-abs.c
index 954b106..9e0ed99 100644
--- a/gcc/testsuite/gcc.target/aarch64/vect-abs.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect-abs.c
@@ -1,6 +1,6 @@
 
 /* { dg-do run } */
-/* { dg-options "-O3" } */
+/* { dg-options "-O3 -std=c99" } */
 
 #include "limits.h"
 
@@ -37,8 +37,9 @@ extern void abort (void);
 SET_RVEC (8, SCHAR)
 SET_RVEC (16, SHRT)
 SET_RVEC (32, INT)
-SET_RVEC (64, LONG_LONG)
+SET_RVEC (64, LLONG)
 
+void
 set_rvector_long (pRLONG a)
 {
   int i;
@@ -49,8 +50,9 @@ set_rvector_long (pRLONG a)
 SET_VEC (8, SCHAR)
 SET_VEC (16, SHRT)
 SET_VEC (32, INT)
-SET_VEC (64, LONG_LONG)
+SET_VEC (64, LLONG)
 
+void
 set_vector_long (long *__restrict__ a)
 {
   long i;
@@ -63,6 +65,7 @@ CHECK_VEC (16)
 CHECK_VEC (32)
 CHECK_VEC (64)
 
+void
 check_vector_long (long *__restrict__ a, long *__restrict__ b)
 {
   long i;

[PATCH] Reduce load on crgaph_get_node from estimate_num_insns

[Richard Biener]

It looks like the most heavy load on crgaph_get_node and the
symtab hashtable (at least for PR60243), so the following avoids
that when the call isn't builtin.

Bootstrap / regtest in progress on x86_64-unknown-linux-gnu, ok?

Thanks,
Richard.

2014-02-18  Richard Biener  

PR ipa/60243
* tree-inline.c (estimate_num_insns): Avoid calling cgraph_get_node
for all calls.

Index: gcc/tree-inline.c
===
*** gcc/tree-inline.c   (revision 207837)
--- gcc/tree-inline.c   (working copy)
*** estimate_num_insns (gimple stmt, eni_wei
*** 3826,3865 
tree decl;
struct cgraph_node *node = NULL;
  
-   /* Do not special case builtins where we see the body.
-  This just confuse inliner.  */
if (gimple_call_internal_p (stmt))
  return 0;
!   else if (!(decl = gimple_call_fndecl (stmt))
!|| !(node = cgraph_get_node (decl))
!|| node->definition)
! ;
!   /* For buitins that are likely expanded to nothing or
!  inlined do not account operand costs.  */
!   else if (is_simple_builtin (decl))
! return 0;
!   else if (is_inexpensive_builtin (decl))
! return weights->target_builtin_call_cost;
!   else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
  {
!   /* We canonicalize x * x to pow (x, 2.0) with -ffast-math, so
!  specialize the cheap expansion we do here.
!  ???  This asks for a more general solution.  */
!   switch (DECL_FUNCTION_CODE (decl))
  {
!   case BUILT_IN_POW:
!   case BUILT_IN_POWF:
!   case BUILT_IN_POWL:
! if (TREE_CODE (gimple_call_arg (stmt, 1)) == REAL_CST
! && REAL_VALUES_EQUAL
!  (TREE_REAL_CST (gimple_call_arg (stmt, 1)), dconst2))
!   return estimate_operator_cost (MULT_EXPR, weights,
!  gimple_call_arg (stmt, 0),
!  gimple_call_arg (stmt, 0));
! break;
  
!   default:
! break;
  }
  }
  
--- 3830,3872 
tree decl;
struct cgraph_node *node = NULL;
  
if (gimple_call_internal_p (stmt))
  return 0;
!   else if ((decl = gimple_call_fndecl (stmt))
!&& DECL_BUILT_IN (decl))
  {
!   /* Do not special case builtins where we see the body.
!  This just confuse inliner.  */
!   if (!(node = cgraph_get_node (decl))
!   || node->definition)
! ;
!   /* For buitins that are likely expanded to nothing or
!  inlined do not account operand costs.  */
!   else if (is_simple_builtin (decl))
! return 0;
!   else if (is_inexpensive_builtin (decl))
! return weights->target_builtin_call_cost;
!   else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
  {
!   /* We canonicalize x * x to pow (x, 2.0) with -ffast-math, so
!  specialize the cheap expansion we do here.
!  ???  This asks for a more general solution.  */
!   switch (DECL_FUNCTION_CODE (decl))
! {
!   case BUILT_IN_POW:
!   case BUILT_IN_POWF:
!   case BUILT_IN_POWL:
! if (TREE_CODE (gimple_call_arg (stmt, 1)) == REAL_CST
! && REAL_VALUES_EQUAL
! (TREE_REAL_CST (gimple_call_arg (stmt, 1)), dconst2))
!   return estimate_operator_cost
!   (MULT_EXPR, weights, gimple_call_arg (stmt, 0),
!gimple_call_arg (stmt, 0));
! break;
  
!   default:
! break;
! }
  }
  }
  

[Ada] Use of attributes 'Old and 'Result and local entities in another 'Old

[Arnaud Charlet]

This patch implements the following sentence from Ada RM 6.1.1 (27/3):

   The prefix of an Old attribute_reference shall not contain a Result
   attribute_reference, nor an Old attribute_reference, nor a use of an entity
   declared within the postcondition expression but not within prefix itself
   (for example, the loop parameter of an enclosing quantified_expression).


-- Source --


--  semantics.ads

package Semantics is
   Stuff : array (1 .. 5) of Integer;

   procedure Local_Entity_In_Spec
 with Post =>
   (for all Index in 1 .. 5 =>
  Stuff (Index) = Stuff (Index)'Old - 1);

   procedure Nested_Old_In_Spec (Param : in out Integer)
 with Post =>
   Param = Param'Old'Old;
end Semantics

--  semantics.adb

package body Semantics is
   procedure Local_Entity_In_Body
 with Post =>
   (for all Index in 1 .. 5 =>
  Stuff (Index) = Stuff (Index)'Old - 1)
   is begin null; end Local_Entity_In_Body;

   procedure Local_Entity_In_Spec is begin null; end Local_Entity_In_Spec;

   procedure Nested_Old_In_Body (Param : in out Integer)
 with Post =>
   Param = Param'Old'Old
   is begin null; end Nested_Old_In_Body;

   procedure Nested_Old_In_Spec (Param : in out Integer) is
   begin null; end Nested_Old_In_Spec;
end Semantics;


-- Compilation and output --


$ gcc -c semantics.adb
semantics.adb:5:34: prefix of attribute "Old" cannot reference local entities
semantics.adb:12:21: attribute "Old" cannot appear in the prefix of attribute
  "Old"
semantics.ads:7:34: prefix of attribute "Old" cannot reference local entities
semantics.ads:11:21: attribute "Old" cannot appear in the prefix of attribute
  "Old"

Tested on x86_64-pc-linux-gnu, committed on trunk

2014-02-18  Hristian Kirtchev  

* sem_attr.adb (Analyze_Attribute): Comment
and code reformatting. Use separate routines to check the
legality of attribute 'Old in certain pragmas. Verify
the use of 'Old, 'Result and locally declared entities
within the prefix of 'Old.
(Check_References_In_Prefix): New routine.
(Check_Use_In_Contract_Cases): New routine.
(Check_Use_In_Test_Case): New routine.

Index: sem_attr.adb
===
--- sem_attr.adb(revision 207558)
+++ sem_attr.adb(working copy)
@@ -4373,6 +4373,137 @@
   -
 
   when Attribute_Old => Old : declare
+ procedure Check_References_In_Prefix (Subp_Id : Entity_Id);
+ --  Inspect the contents of the prefix and detect illegal uses of a
+ --  nested 'Old, attribute 'Result or a use of an entity declared in
+ --  the related postcondition expression. Subp_Id is the subprogram to
+ --  which the related postcondition applies.
+
+ procedure Check_Use_In_Contract_Cases (Prag : Node_Id);
+ --  Perform various semantic checks related to the placement of the
+ --  attribute in pragma Contract_Cases.
+
+ procedure Check_Use_In_Test_Case (Prag : Node_Id);
+ --  Perform various semantic checks related to the placement of the
+ --  attribute in pragma Contract_Cases.
+
+ 
+ -- Check_References_In_Prefix --
+ 
+
+ procedure Check_References_In_Prefix (Subp_Id : Entity_Id) is
+function Check_Reference (Nod : Node_Id) return Traverse_Result;
+--  Detect attribute 'Old, attribute 'Result of a use of an entity
+--  and perform the appropriate semantic check.
+
+-
+-- Check_Reference --
+-
+
+function Check_Reference (Nod : Node_Id) return Traverse_Result is
+begin
+   --  Attributes 'Old and 'Result cannot appear in the prefix of
+   --  another attribute 'Old.
+
+   if Nkind (Nod) = N_Attribute_Reference
+ and then Nam_In (Attribute_Name (Nod), Name_Old,
+Name_Result)
+   then
+  Error_Msg_Name_1 := Attribute_Name (Nod);
+  Error_Msg_Name_2 := Name_Old;
+  Error_Msg_N
+("attribute % cannot appear in the prefix of attribute %",
+ Nod);
+  return Abandon;
+
+   --  Entities mentioned within the prefix of attribute 'Old must
+   --  be global to the related postcondition. If this is not the
+   --  case, then the scope of the local entity is be nested within
+   --  that of the subprogram.
+
+   elsif Nkind (Nod) = N_Identifier
+ and then Present (Entity (Nod))
+ and then Scope_Within (Scope (Entity (Nod)), Subp_Id)
+  

[Ada] Reduce use of N_Reference nodes in generated code

[Arnaud Charlet]

This is an internal optimization that reduces the number of cases
in which we generate N_Reference nodes. Generally has no effect
on functional behavior, but the following test:

 1. function StrangeRef (A, B : Integer) return Integer is
 2.X : Integer;
 3. begin
 4.X := Integer'Max ((if A > 4 then B else 15), B);
 5.return X;
 6. end StrangeRef;

compiled with -gnatG and -gnatd.u can be used to see that we do properly
optimize this case and avoid generating an N_Reference node which is what
we used to do:

Source recreated from tree for Strangeref (body)

function strangeref (a : integer; b : integer) return integer is
   x : integer;
begin
   R1b : constant integer := (if a > 4 then integer(b) else 15);
   x := (if (R1b) >= b then (R1b) else integer(b));
   return x;
end strangeref;

Previously R1b generated an N_Reference node

Tested on x86_64-pc-linux-gnu, committed on trunk

2014-02-18  Robert Dewar  

* exp_attr.adb: Minor reformatting.
* exp_ch4.ads, exp_ch4.adb (Expand_N_Reference): New procedure.
* exp_util.adb (Remove_Side_Effects): Add conditional expressions
as another case where we don't generate N_Reference nodes for
primitive types.
* expander.adb (Expand): Add call to Expand_N_Reference.

Index: exp_util.adb
===
--- exp_util.adb(revision 207537)
+++ exp_util.adb(working copy)
@@ -6972,17 +6972,28 @@
   Scope_Suppress.Suppress := (others => True);
 
   --  If it is a scalar type and we need to capture the value, just make
-  --  a copy. Likewise for a function call, an attribute reference, an
-  --  allocator, or an operator. And if we have a volatile reference and
-  --  Name_Req is not set (see comments above for Side_Effect_Free).
+  --  a copy. Likewise for a function call, an attribute reference, a
+  --  conditional expression, an allocator, or an operator. And if we have
+  --  a volatile reference and Name_Req is not set (see comments above for
+  --  Side_Effect_Free).
 
   if Is_Elementary_Type (Exp_Type)
+
+--  Note: this test is rather mysterious??? Why can't we just test ONLY
+--  Is_Elementary_Type and be done with it. If we try that approach, we
+--  get some failures (infinite recursions) from the Duplicate_Subexpr
+--  call at the end of Checks.Apply_Predicate_Check. To be
+--  investigated ???
+
 and then (Variable_Ref
-   or else Nkind_In (Exp, N_Function_Call,
-  N_Attribute_Reference,
-  N_Allocator)
+   or else Nkind_In (Exp, N_Attribute_Reference,
+  N_Allocator,
+  N_Case_Expression,
+  N_If_Expression,
+  N_Function_Call)
or else Nkind (Exp) in N_Op
-   or else (not Name_Req and then Is_Volatile_Reference (Exp)))
+   or else (not Name_Req
+ and then Is_Volatile_Reference (Exp)))
   then
  Def_Id := Make_Temporary (Loc, 'R', Exp);
  Set_Etype (Def_Id, Exp_Type);
@@ -7230,6 +7241,7 @@
  E := Exp;
  if Nkind (E) = N_Explicit_Dereference then
 New_Exp := Relocate_Node (Prefix (E));
+
  else
 E := Relocate_Node (E);
 
Index: exp_attr.adb
===
--- exp_attr.adb(revision 207559)
+++ exp_attr.adb(working copy)
@@ -1132,20 +1132,20 @@
 --  copies from being created when the unchecked conversion
 --  is expanded (which would happen in Remove_Side_Effects
 --  if Expand_N_Unchecked_Conversion were allowed to call
---  Force_Evaluation). The copy could violate Ada semantics
---  in cases such as an actual that is an out parameter.
---  Note that this approach is also used in exp_ch7 for calls
---  to controlled type operations to prevent problems with
---  actuals wrapped in unchecked conversions.
+--  Force_Evaluation). The copy could violate Ada semantics in
+--  cases such as an actual that is an out parameter. Note that
+--  this approach is also used in exp_ch7 for calls to controlled
+--  type operations to prevent problems with actuals wrapped in
+--  unchecked conversions.
 
 if Is_Untagged_Derivation (Etype (Expression (Item))) then
Set_Assignment_OK (Item);
 end if;
  end if;
 
- --  The stream operation to call maybe a renaming created by
- --  an attribute definition clause, and may not be frozen yet.
- -- 

Re: [PATCH i386 13/8] [AVX-512] Fix argument order for perm and recp intrinsics.

[Uros Bizjak]

On Tue, Feb 18, 2014 at 11:06 AM, Kirill Yukhin  wrote:

>> >> >> Please don't change srcp pattern, it should be defined similar to
>> >> >> vrcpss (aka sse_vmrcpv4sf). You need to switch operand order
>> >> >> elsewhere.
>> >> >
>> >> > No, you are correct. Operands should be swapped as in your patch.
>> >>
>> >> Eh, sorry that after some more thinking, I have to again revert this 
>> >> decision.
>> >>
>> >> The srcp pattern should remain as is, and you should swap operands in
>> >> avx512fintrin.h instead:
>> >
>> > In the bottom there's updated patch.
>> >
>> > Added "sse" type. mem operand made second.
>> > Built-ins & tests fixed.
>> >
>> > Testing in progress.
>> >
>> > Is it ok for mainline if pass?
>>
>> No, you got operand order wrong.
>>
>> To correctly calculate "memory" attribute, all "sse" type insns expect
>> the operands in the way sse_vmrcpv4sf2 is defined. You should keep
>> nonimmedate operand as operand_1 and switch operands in builtins and
>> insn mnemonics to fulfill required operand order *in the pattern*.
> Patch updated. It is in the bottom.
> gcc/
> * config/i386/avx512erintrin.h (_mm_rcp28_round_sd): Swap operands.
> (_mm_rcp28_round_ss): Ditto.
> (_mm_rsqrt28_round_sd): Ditto.
> (_mm_rsqrt28_round_ss): Ditto.
> * config/i386/avx512erintrin.h (_mm_rcp14_round_sd): Ditto.
> (_mm_rcp14_round_ss): Ditto.
> (_mm_rsqrt14_round_sd): Ditto.
> (_mm_rsqrt14_round_ss): Ditto.
> * config/i386/sse.md (rsqrt14): Make memory first operand.

"Put nonimmediate operand as the first input operand." (and in similar
way below).

> (avx512er_exp2): Set type
> attribute to sse.
> (avx512er_rcp28):
> Ditto.
> (avx512er_vmrcp28): Make memory first
> operand, set type attribute.
> (avx512er_rsqrt28):
> Set type attribute.
> (avx512er_vmrsqrt28): Make memory first
> operand, Set type attribute.
>
> gcc/testsuite/
> * gcc.target/i386/avx512er-vrcp28sd-2.c: Distinguish src1 and src2.
> * gcc.target/i386/avx512er-vrcp28ss-2.c: Call correct intrinsic.
> * gcc.target/i386/avx512er-vrsqrt28sd-2.c: Distinguish src1 and src2.
> * gcc.target/i386/avx512er-vrsqrt28ss-2.c: Ditto.
> * gcc.target/i386/avx512f-vrcp14sd-2.c: Fix reference calculation.
> * gcc.target/i386/avx512f-vrcp14ss-2.c: Ditto.

OK with a slight adjustement to vrcp14 patter below.

> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -1551,13 +1551,13 @@
>[(set (match_operand:VF_128 0 "register_operand" "=v")
> (vec_merge:VF_128
>   (unspec:VF_128
> -   [(match_operand:VF_128 1 "register_operand" "v")
> -(match_operand:VF_128 2 "nonimmediate_operand" "vm")]
> +   [(match_operand:VF_128 2 "register_operand" "v")
> +(match_operand:VF_128 1 "nonimmediate_operand" "vm")]
> UNSPEC_RSQRT14)
>   (match_dup 1)
>   (const_int 1)))]
>"TARGET_AVX512F"
> -  "vrsqrt14\t{%2, %1, %0|%0, %1, %2}"
> +  "vrsqrt14\t{%1, %2, %0|%0, %2, %1}"

This pattern should probably read the same as other vmrsqrt patterns
(e.g. sse_vmrsqrtv4sf2 and avx512er_vmrsqrt28...):

   (vec_merge:VF_128
 (unspec:VF_128
   [(match_operand:VF_128 1 "nonimmediate_operand" "vm")]
   UNSPEC_RSQRT14)
 (match_operand:VF_128 2 "register_operand" "v")
 (const_int 1)))]
  "TARGET_AVX512F"
  "vrsqrt14\t{%1, %2, %0|%0, %2, %1}"

OK with the change above.

Thanks,
Uros.

Re: [PATCH i386 13/8] [AVX-512] Fix argument order for perm and recp intrinsics.

[Kirill Yukhin]

Hello Uroš,
On 17 Feb 13:41, Uros Bizjak wrote:
> On Mon, Feb 17, 2014 at 1:26 PM, Kirill Yukhin  
> wrote:
> 
> >> >> Please don't change srcp pattern, it should be defined similar to
> >> >> vrcpss (aka sse_vmrcpv4sf). You need to switch operand order
> >> >> elsewhere.
> >> >
> >> > No, you are correct. Operands should be swapped as in your patch.
> >>
> >> Eh, sorry that after some more thinking, I have to again revert this 
> >> decision.
> >>
> >> The srcp pattern should remain as is, and you should swap operands in
> >> avx512fintrin.h instead:
> >
> > In the bottom there's updated patch.
> >
> > Added "sse" type. mem operand made second.
> > Built-ins & tests fixed.
> >
> > Testing in progress.
> >
> > Is it ok for mainline if pass?
> 
> No, you got operand order wrong.
> 
> To correctly calculate "memory" attribute, all "sse" type insns expect
> the operands in the way sse_vmrcpv4sf2 is defined. You should keep
> nonimmedate operand as operand_1 and switch operands in builtins and
> insn mnemonics to fulfill required operand order *in the pattern*.
Patch updated. It is in the bottom.
gcc/
* config/i386/avx512erintrin.h (_mm_rcp28_round_sd): Swap operands.
(_mm_rcp28_round_ss): Ditto.
(_mm_rsqrt28_round_sd): Ditto.
(_mm_rsqrt28_round_ss): Ditto.
* config/i386/avx512erintrin.h (_mm_rcp14_round_sd): Ditto.
(_mm_rcp14_round_ss): Ditto.
(_mm_rsqrt14_round_sd): Ditto.
(_mm_rsqrt14_round_ss): Ditto.
* config/i386/sse.md (rsqrt14): Make memory first operand.
(avx512er_exp2): Set type
attribute to sse.
(avx512er_rcp28):
Ditto.
(avx512er_vmrcp28): Make memory first
operand, set type attribute.
(avx512er_rsqrt28):
Set type attribute.
(avx512er_vmrsqrt28): Make memory first
operand, Set type attribute.

gcc/testsuite/
* gcc.target/i386/avx512er-vrcp28sd-2.c: Distinguish src1 and src2.
* gcc.target/i386/avx512er-vrcp28ss-2.c: Call correct intrinsic.
* gcc.target/i386/avx512er-vrsqrt28sd-2.c: Distinguish src1 and src2.
* gcc.target/i386/avx512er-vrsqrt28ss-2.c: Ditto.
* gcc.target/i386/avx512f-vrcp14sd-2.c: Fix reference calculation.
* gcc.target/i386/avx512f-vrcp14ss-2.c: Ditto.

--
Thanks, K

diff --git a/gcc/config/i386/avx512erintrin.h b/gcc/config/i386/avx512erintrin.h
index 6fe05bc..f6870a5 100644
--- a/gcc/config/i386/avx512erintrin.h
+++ b/gcc/config/i386/avx512erintrin.h
@@ -163,8 +163,8 @@ extern __inline __m128d
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_rcp28_round_sd (__m128d __A, __m128d __B, int __R)
 {
-  return (__m128d) __builtin_ia32_rcp28sd_round ((__v2df) __A,
-(__v2df) __B,
+  return (__m128d) __builtin_ia32_rcp28sd_round ((__v2df) __B,
+(__v2df) __A,
 __R);
 }
 
@@ -172,8 +172,8 @@ extern __inline __m128
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_rcp28_round_ss (__m128 __A, __m128 __B, int __R)
 {
-  return (__m128) __builtin_ia32_rcp28ss_round ((__v4sf) __A,
-   (__v4sf) __B,
+  return (__m128) __builtin_ia32_rcp28ss_round ((__v4sf) __B,
+   (__v4sf) __A,
__R);
 }
 
@@ -237,8 +237,8 @@ extern __inline __m128d
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_rsqrt28_round_sd (__m128d __A, __m128d __B, int __R)
 {
-  return (__m128d) __builtin_ia32_rsqrt28sd_round ((__v2df) __A,
-  (__v2df) __B,
+  return (__m128d) __builtin_ia32_rsqrt28sd_round ((__v2df) __B,
+  (__v2df) __A,
   __R);
 }
 
@@ -246,8 +246,8 @@ extern __inline __m128
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_rsqrt28_round_ss (__m128 __A, __m128 __B, int __R)
 {
-  return (__m128) __builtin_ia32_rsqrt28ss_round ((__v4sf) __A,
- (__v4sf) __B,
+  return (__m128) __builtin_ia32_rsqrt28ss_round ((__v4sf) __B,
+ (__v4sf) __A,
  __R);
 }
 
@@ -375,16 +375,16 @@ _mm_rsqrt28_round_ss (__m128 __A, __m128 __B, int __R)
 _mm512_maskz_rsqrt28_round_ps(U, A, _MM_FROUND_CUR_DIRECTION)
 
 #define _mm_rcp28_sd(A, B) \
-__builtin_ia32_rcp28sd_round(A, B, _MM_FROUND_CUR_DIRECTION)
+__builtin_ia32_rcp28sd_round(B, A, _MM_FROUND_CUR_DIRECTION)
 
 #define _mm_rcp28_ss(A, B) \
-__builtin_ia32_rcp28ss_round(A, B, _MM_FROUND_CUR_DIRECTION)
+__builtin_ia32_rcp28ss_round(B, A, _MM_FROUND_CUR_DIRECTION)
 
 #define _mm_rsqrt28_sd(A, B)   \
-__builtin_

[C++ Patch] PR 60215

[Paolo Carlini]

Hi,

we fixed c++/58647 with:

9672 case COMPONENT_REF:
9673   if (is_overloaded_fn (t))
9674 {
9675   /* We can only get here in checking mode via
9676  build_non_dependent_expr,  because any expression that
9677  calls or takes the address of the function will have
9678  pulled a FUNCTION_DECL out of the COMPONENT_REF.  */
9679   gcc_checking_assert (allow_non_constant);
9680   *non_constant_p = true;
9681   return t;
9682 }


which also added a gcc_checking_assert. In the new issue the assert 
triggers during error recovery and I guess we can simply loosen it a bit 
with || errorcount, the below passes testing.


Thanks,
Paolo.

//

/cp
2014-02-18  Paolo Carlini  

PR c++/60215
* semantics.c (cxx_eval_constant_expression, [COMPONENT_REF]):
During error recovery allow_non_constant may be false.

/testsuite
2014-02-18  Paolo Carlini  

PR c++/60215
* g++.dg/cpp0x/pr60215.C: New.
Index: cp/semantics.c
===
--- cp/semantics.c  (revision 207837)
+++ cp/semantics.c  (working copy)
@@ -9676,7 +9677,7 @@ cxx_eval_constant_expression (const constexpr_call
 build_non_dependent_expr,  because any expression that
 calls or takes the address of the function will have
 pulled a FUNCTION_DECL out of the COMPONENT_REF.  */
- gcc_checking_assert (allow_non_constant);
+ gcc_checking_assert (allow_non_constant || errorcount);
  *non_constant_p = true;
  return t;
}
Index: testsuite/g++.dg/cpp0x/pr60215.C
===
--- testsuite/g++.dg/cpp0x/pr60215.C(revision 0)
+++ testsuite/g++.dg/cpp0x/pr60215.C(working copy)
@@ -0,0 +1,8 @@
+// PR c++/60215
+// { dg-do compile { target c++11 } }
+
+struct A
+{
+  void foo();
+  int i : foo;  // { dg-error "width" }
+};

[wwwdocs] 4.9/changes.html: Mention -Wopenmp-simd/-fsimd-cost-model; Fortran update

[Tobias Burnus]

Hi all,

is the wording okay - and/or do you have further suggestions?

Tobias


Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.9/changes.html,v
retrieving revision 1.55
diff -p -u -r1.55 changes.html
--- changes.html17 Feb 2014 08:01:18 -  1.55
+++ changes.html18 Feb 2014 08:53:48 -
@@ -94,7 +94,12 @@
 Version 4.0 of the http://openmp.org/wp/openmp-specifications/";
>OpenMP specification is now supported for the C and C++ compilers.
The new -fopenmp-simd option can be used to enable OpenMP's
-   SIMD directives, while ignoring other OpenMP directives.
+   SIMD directives, while ignoring other OpenMP directives. The new http://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#index-fsimd-cost-model-908";
+>-fsimd-cost-model option permits to tune the
+vectorization cost model for loops annotated with OpenMP and Cilk
+Plus simd directives; -Wopenmp-simd warns when the
+current costmodel overrides simd directive set by the user.
 The -Wdate-time option has been added for the C, C++ and
Fortran compilers, which warns when the __DATE__,
__TIME__ or __TIMESTAMP__ macros are used.
@@ -217,7 +222,7 @@ void f(int n) {
 
 class A;
 int bar(int n);
-#if __cplusplus > 201103
+#if __cplusplus > 201103
 class [[deprecated("A is deprecated in C++14; Use B instead")]] A;
 [[deprecated("bar is unsafe; use foo() instead")]]
 int bar(int n);
@@ -333,6 +338,12 @@ auto incr = [](auto x) { return x++; };
 Fortran 2008, the standard explicitly states that variables declared
 in the Fortran main program automatically have the SAVE
 attribute.
+  When opening files, the close-on-exec flag is set if the system
+supports such a feature. This is generally considered good practice
+these days, but if there is a need to pass file descriptors to child
+processes the parent process must now remember to clear the
+close-on-exec flag by calling fcntl(), e.g. via
+ISO_C_BINDING, before executing the child process.
 
 The deprecated command-line option -fno-whole-file
   has been removed. (-fwhole-file is the default since
@@ -376,6 +387,13 @@ auto incr = [](auto x) { return x++; };
 href="http://gcc.gnu.org/onlinedocs/gfortran/Debugging-Options.html";
 >-ffpe-summary= command-line option can be used to fine-tune
 for which exception the warning should be shown.
+  Rounding on input (READ) is now handled on systems where
+strtod honours the rounding mode. (For output, rounding is
+supported since GCC 4.5.) Note that for input, the
+compatible rounding mode is handled as 
nearest
+(i.e., for a tie, rounding to an even last significant
+[cf. IEC 60559:1989] – while compatible rounds away
+from zero for a tie).
 
   

[gomp4] Merge trunk r207818 (2014-02-17) into gomp-4_0-branch

[Thomas Schwinge]

Hi!

In r207837, I have committed a merge from trunk r207818 (2014-02-17) into
gomp-4_0-branch.  No regressions, as far as I call -- trunk is
stabilizing, yay!


Grüße,
 Thomas


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