[Ping][PATCH v2] Fix Incorrect ASan global variables alignment on arm (PR sanitizer/81697)

[Maxim Ostapenko]

Hi,

I would like to ping the following patch:
https://gcc.gnu.org/ml/gcc-patches/2017-10/msg02288.html

Thanks,
-Maxim
gcc/ChangeLog:

2017-11-13  Maxim Ostapenko  

	PR sanitizer/81697
	* asan.c (asan_protect_global): Add new ignore_decl_rtl_set_p
	parameter. Return true if ignore_decl_rtl_set_p is true and other
	conditions are satisfied.
	* asan.h (asan_protect_global): Add new parameter.
	* varasm.c (categorize_decl_for_section): Pass true as second parameter
	to asan_protect_global calls.

gcc/testsuite/ChangeLog:

2017-11-13  Maxim Ostapenko  

	PR sanitizer/81697
	* g++.dg/asan/global-alignment.C: New test.

diff --git a/gcc/asan.c b/gcc/asan.c
index d5128aa..78c3b60 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1605,7 +1605,7 @@ is_odr_indicator (tree decl)
ASAN_RED_ZONE_SIZE bytes.  */
 
 bool
-asan_protect_global (tree decl)
+asan_protect_global (tree decl, bool ignore_decl_rtl_set_p)
 {
   if (!ASAN_GLOBALS)
 return false;
@@ -1627,7 +1627,13 @@ asan_protect_global (tree decl)
   || DECL_THREAD_LOCAL_P (decl)
   /* Externs will be protected elsewhere.  */
   || DECL_EXTERNAL (decl)
-  || !DECL_RTL_SET_P (decl)
+  /* PR sanitizer/81697: For architectures that use section anchors first
+	 call to asan_protect_global may occur before DECL_RTL (decl) is set.
+	 We should ignore DECL_RTL_SET_P then, because otherwise the first call
+	 to asan_protect_global will return FALSE and the following calls on the
+	 same decl after setting DECL_RTL (decl) will return TRUE and we'll end
+	 up with inconsistency at runtime.  */
+  || (!DECL_RTL_SET_P (decl) && !ignore_decl_rtl_set_p)
   /* Comdat vars pose an ABI problem, we can't know if
 	 the var that is selected by the linker will have
 	 padding or not.  */
@@ -1651,6 +1657,9 @@ asan_protect_global (tree decl)
   || is_odr_indicator (decl))
 return false;
 
+  if (ignore_decl_rtl_set_p)
+return true;
+
   rtl = DECL_RTL (decl);
   if (!MEM_P (rtl) || GET_CODE (XEXP (rtl, 0)) != SYMBOL_REF)
 return false;
diff --git a/gcc/asan.h b/gcc/asan.h
index c82d4d9..885b47e 100644
--- a/gcc/asan.h
+++ b/gcc/asan.h
@@ -26,7 +26,7 @@ extern void asan_finish_file (void);
 extern rtx_insn *asan_emit_stack_protection (rtx, rtx, unsigned int,
 	 HOST_WIDE_INT *, tree *, int);
 extern rtx_insn *asan_emit_allocas_unpoison (rtx, rtx, rtx_insn *);
-extern bool asan_protect_global (tree);
+extern bool asan_protect_global (tree, bool ignore_decl_rtl_set_p = false);
 extern void initialize_sanitizer_builtins (void);
 extern tree asan_dynamic_init_call (bool);
 extern bool asan_expand_check_ifn (gimple_stmt_iterator *, bool);
diff --git a/gcc/testsuite/g++.dg/asan/global-alignment.C b/gcc/testsuite/g++.dg/asan/global-alignment.C
new file mode 100644
index 000..84dac37
--- /dev/null
+++ b/gcc/testsuite/g++.dg/asan/global-alignment.C
@@ -0,0 +1,18 @@
+/* { dg-options "-fmerge-all-constants" } */
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+#include 
+#include 
+
+const char kRecoveryInstallString[] = "NEW";
+const char kRecoveryUpdateString[] = "UPDATE";
+const char kRecoveryUninstallationString[] = "UNINSTALL";
+
+const std::map kStringToRequestMap = {
+  {kRecoveryInstallString, 0},
+  {kRecoveryUpdateString, 0},
+  {kRecoveryUninstallationString, 0},
+};
+
+/* { dg-final { scan-assembler-times {\.section\s+\.rodata\n(?:(?!\.section).)*\.\w+\s+"NEW} 1 } } */
diff --git a/gcc/varasm.c b/gcc/varasm.c
index a139151..849eae0 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -6508,7 +6508,7 @@ categorize_decl_for_section (const_tree decl, int reloc)
   else if (TREE_CODE (decl) == STRING_CST)
 {
   if ((flag_sanitize & SANITIZE_ADDRESS)
-	  && asan_protect_global (CONST_CAST_TREE (decl)))
+	  && asan_protect_global (CONST_CAST_TREE (decl), true))
   /* or !flag_merge_constants */
 return SECCAT_RODATA;
   else
@@ -6536,7 +6536,7 @@ categorize_decl_for_section (const_tree decl, int reloc)
 	ret = reloc == 1 ? SECCAT_DATA_REL_RO_LOCAL : SECCAT_DATA_REL_RO;
   else if (reloc || flag_merge_constants < 2
 	   || ((flag_sanitize & SANITIZE_ADDRESS)
-		   && asan_protect_global (CONST_CAST_TREE (decl
+		   && asan_protect_global (CONST_CAST_TREE (decl), true)))
 	/* C and C++ don't allow different variables to share the same
 	   location.  -fmerge-all-constants allows even that (at the
 	   expense of not conforming).  */

[PATCH] detect nonstring arguments to string functions (PR 82945)

[Martin Sebor]

The recently introduced -Wstringop-truncation warning relies
on the new nonstring attribute to allow the historical use case
of calling strncpy to completely fill the destination with a copy
of a string without adding a terminating nul.  Glibc is currently
considering making use of the attribute to decorate some of its
data members.  To help find misuses of such data members in
arguments to string functions like strlen or strdup, the attached
patch adds checking for this new attribute in these contexts.
The checking is intentionally done late so  that uses such arrays
that can be proven to be safe (and thus folded) are not diagnosed.

While testing this simple enhancement I noticed that the handling
I added for the nul termination in cases like

  strncpy (array, s, sizeof array);
  array[sizeof array - 1] = 0;

to avoid the new warning wasn't quite as robust as it could and
arguably should be so I improved it a bit to silently accept
more forms of the idiom.  For instance, this is now correctly
handled (and not diagnosed):

  *stpcpy (array, s, sizeof array - 1) = 0;

Martin

PS A useful future enhancement would be to detect the one byte
overflow in:

  *stpcpy (array, s, sizeof array) = 0;
PR tree-optimization/82945 - add warning for passing non-strings to functions that expect string arguments

gcc/ChangeLog:

	PR tree-optimization/82945
	* calls.c (get_attr_nonstring_decl, maybe_warn_nonstring_arg): New
	functions.
	(initialize_argument_information): Call maybe_warn_nonstring_arg.
	* calls.h (get_attr_nonstring_decl): Declare new function.
	* doc/extend.texi (attribute nonstring): Update.
	* gimple-fold.c (gimple_fold_builtin_strncpy): Call
	get_attr_nonstring_decl and handle it.
	* tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Same.  Improve
	detection of nul-termination.

gcc/testsuite/ChangeLog:

	PR tree-optimization/82945
	* c-c++-common/Wstringop-truncation-2.c: New test.
	* c-c++-common/Wstringop-truncation.c: Adjust.
	* c-c++-common/attr-nonstring-2.c: Adjust.
	* c-c++-common/attr-nonstring-3.c: New test.

diff --git a/gcc/calls.c b/gcc/calls.c
index 3730f43..c555f9a 100644
--- a/gcc/calls.c
+++ b/gcc/calls.c
@@ -1494,6 +1494,139 @@ maybe_warn_alloc_args_overflow (tree fn, tree exp, tree args[2], int idx[2])
 }
 }
 
+/* If EXPR refers to a character array or pointer declared attribute
+   nonstring return a decl for that array or pointer and set *REF to
+   the referenced enclosing object or pointer.  Otherwise return
+   null.  */
+
+tree
+get_attr_nonstring_decl (tree expr, tree *ref)
+{
+  tree dcl = expr;
+  if (TREE_CODE (dcl) == SSA_NAME)
+{
+  if (SSA_NAME_IS_DEFAULT_DEF (dcl))
+	dcl = SSA_NAME_VAR (dcl);
+  else
+	{
+	  gimple *def = SSA_NAME_DEF_STMT (dcl);
+
+	  if (is_gimple_assign (def))
+	{
+	  tree_code code = gimple_assign_rhs_code (def);
+	  if (code == ADDR_EXPR
+		  || code == COMPONENT_REF
+		  || code == VAR_DECL)
+		dcl = gimple_assign_rhs1 (def);
+	}
+	}
+}
+
+  if (TREE_CODE (dcl) == ADDR_EXPR)
+dcl = TREE_OPERAND (dcl, 0);
+
+  if (ref)
+*ref = dcl;
+
+  if (TREE_CODE (dcl) == COMPONENT_REF)
+dcl = TREE_OPERAND (dcl, 1);
+
+  if (DECL_P (dcl)
+  && lookup_attribute ("nonstring", DECL_ATTRIBUTES (dcl)))
+return dcl;
+
+  return NULL_TREE;
+}
+
+/* Warn about passing a non-string array/pointer to a function that
+   expects a nul-terminated string argument.  */
+
+static void
+maybe_warn_nonstring_arg (tree fndecl, tree exp)
+{
+  if (!fndecl || DECL_BUILT_IN_CLASS (fndecl) != BUILT_IN_NORMAL)
+return;
+
+  /* -1 terminated array of zero-based string arguments.  */
+  unsigned argno[] = { -1, -1, -1 };
+
+  switch (DECL_FUNCTION_CODE (fndecl))
+{
+case BUILT_IN_STRCASECMP:
+case BUILT_IN_STRCMP:
+case BUILT_IN_STRCSPN:
+case BUILT_IN_STRSPN:
+case BUILT_IN_STRNCMP:
+case BUILT_IN_STRNCASECMP:
+case BUILT_IN_VSSCANF:
+  argno[0] = 0;
+  argno[1] = 1;
+  break;
+
+case BUILT_IN_STPCPY:
+case BUILT_IN_STPNCPY:
+case BUILT_IN_STRCAT:
+case BUILT_IN_STRCPY:
+case BUILT_IN_STRNCAT:
+case BUILT_IN_STRNCPY:
+  argno[0] = 1;
+  break;
+
+case BUILT_IN_FPRINTF:
+case BUILT_IN_FPUTS:
+case BUILT_IN_SPRINTF:
+case BUILT_IN_STPCPY_CHK:
+case BUILT_IN_STPNCPY_CHK:
+case BUILT_IN_STRCAT_CHK:
+case BUILT_IN_STRCPY_CHK:
+case BUILT_IN_STRNCAT_CHK:
+case BUILT_IN_STRNCPY_CHK:
+case BUILT_IN_VFPRINTF:
+case BUILT_IN_VSPRINTF:
+case BUILT_IN_VFSCANF:
+  argno[0] = 1;
+  break;
+
+case BUILT_IN_SNPRINTF:
+case BUILT_IN_VSNPRINTF:
+  argno[0] = 2;
+  break;
+
+case BUILT_IN_PRINTF:
+case BUILT_IN_PRINTF_UNLOCKED:
+case BUILT_IN_PUTS:
+case BUILT_IN_PUTS_UNLOCKED:
+case BUILT_IN_STRCHR:
+case BUILT_IN_STRDUP:
+case BUILT_IN_STRLEN:
+  argno[0] = 0;
+  break;
+
+default:
+  return;
+}
+
+  for (unsigned i = 0; argno[i] != -1U; ++i)
+{
+

Re: [PATCH v3 1/14] D: The front-end (DMD) language implementation and license.

[Andrei Alexandrescu]

On 11/06/2017 01:46 PM, Iain Buclaw wrote:

On 25 October 2017 at 03:06, Jeff Law  wrote:

On 10/18/2017 01:33 AM, Iain Buclaw wrote:

On 6 October 2017 at 14:51, Ian Lance Taylor  wrote:

On Fri, Oct 6, 2017 at 1:34 AM, Iain Buclaw  wrote:


Out of curiosity, I did have a look at some of the tops of gofrontend
sources this morning.  They are all copyright the Go Authors, and are
licensed as BSD.  So I'm not sure if having copyright FSF and
distributing under GPL is strictly required.  And from a maintenance
point of view, it would be easier to merge in upstream changes as-is
without some diff/merging tool.


The GCC steering committee accepted the gofrontend code under a
non-GPL license with the understanding that the master code would live
in a separate repository that would be mirrored into the GCC repo (the
master repository for gofrontend is currently at
https://go.googlesource.com/gofrontend/).  Personally I don't see a
problem with doing the same for the D frontend.

Ian


Should I request that maybe Donald from FSF chime in here?  I'd rather
avoid another stalemate on this.

Absolutely, though RMS should probably be included on any discussion
with Donald.  I think the FSF needs to chime in and I think the steering
committee needs to chime in once we've got guidance from the FSF.

The first and most important question that needs to be answered is
whether or not the FSF would be OK including the DMD bits with the
license (boost) as-is into GCC.

If that's not acceptable, then we'd have to look at some kind of script
to fix the copyrights.
Jeff



Assuming then, that we'll ship with all copyright notices amended to
be copyright FSF and GPL licensed - that can be fixed up in a later
patch - is there anything further needed to push this review process
further?

Iain.


Hi Jeff, Ian, Joseph: thanks for your consideration. Is there anything 
we can do on our side to move things forward? Please advise, thanks!


Andrei

Re: [riscv] Wrap ASM_OUTPUT_LABELREF in do {} while (0)

[Andrew Waterman]

Thanks, Tom.

On Sun, Nov 12, 2017 at 8:44 AM, Tom de Vries 
wrote:

> Hi,
>
> this patch wraps riscv.h's ASM_OUTPUT_LABELREF in "do {} while (0)".
>
> Build for riscv64.
>
> Committed as obvious.
>
> Thanks,
> - Tom
>

Re: [PATCH] Handle different bit_not_p in store merging (PR tree-optimization/78821)

[Jakub Jelinek]

On Fri, Nov 10, 2017 at 04:51:19PM +, Kyrill Tkachov wrote:
> Hi Jakub,
> 
> On 10/11/17 13:59, Jakub Jelinek wrote:
> > This is something Uros requested in the PR, at least with BIT_NOT_EXPRs
> > it is easy.  Previous store merging changes required that bit_not_p
> > is equal on all stores in the group (in all 3 spots, i.e. on the result
> > of BIT_{AND,IOR,XOR}_EXPR and on both of the operands).
> > 
> > This patch handles mixed values of that flag.  If none of the
> > orig_stores have a particular bit_not_p set, then as previously nothing
> > is inverted, if all of them have it set, then as previously we
> > BIT_NOT_EXPR
> > the particular SSA_NAME, and newly if there is a mix of false and true
> > in a particular bit_not_p, we compute a mask and BIT_XOR_EXPR it, this
> > invert only the bits that were bit_not_p and not the others.
> > 
> > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
> > 
> 
> Might be worth doing a sanity check test run on a big-endian target
> since there is a bit of BYTES_BIG_ENDIAN logic in the patch (though it looks
> correct to me).

Indeed.  Successfully bootstrapped/regtested also on powerpc64{,le}-linux
now.

Jakub

[PATCH] Fix store-merging of cst followed by load (PR tree-optimization/82954)

[Jakub Jelinek]

Hi!

The conditions split groups if some operand is loaded in first stmt
and the second load is incompatible with it, or if it is loaded and
second stmt has constant in there instead of load.
But as this testcase shows, I didn't handle properly the case when
some operand is a constant first and in second stmt changes into a load.
We need to split group between those too.

Bootstrapped/regtested on {x86_64,i686,powerpc64{,le}}-linux, ok for trunk?

2017-11-12  Jakub Jelinek  

PR tree-optimization/82954
* gimple-ssa-store-merging.c
(imm_store_chain_info::coalesce_immediate_stores): If
!infof->ops[N].base_addr, split group if info->ops[N].base_addr.

* gcc.c-torture/execute/pr82954.c: New test.

--- gcc/gimple-ssa-store-merging.c.jj   2017-11-10 15:42:39.0 +0100
+++ gcc/gimple-ssa-store-merging.c  2017-11-12 15:18:16.614785829 +0100
@@ -1198,10 +1198,12 @@ imm_store_chain_info::coalesce_immediate
  std::swap (info->ops[0], info->ops[1]);
  info->ops_swapped_p = true;
}
- if ((!infof->ops[0].base_addr
-  || compatible_load_p (merged_store, info, base_addr, 0))
- && (!infof->ops[1].base_addr
- || compatible_load_p (merged_store, info, base_addr, 1)))
+ if ((infof->ops[0].base_addr
+  ? compatible_load_p (merged_store, info, base_addr, 0)
+  : !info->ops[0].base_addr)
+ && (infof->ops[1].base_addr
+ ? compatible_load_p (merged_store, info, base_addr, 1)
+ : !info->ops[1].base_addr))
{
  merged_store->merge_into (info);
  continue;
--- gcc/testsuite/gcc.c-torture/execute/pr82954.c.jj2017-11-12 
15:27:44.478188823 +0100
+++ gcc/testsuite/gcc.c-torture/execute/pr82954.c   2017-11-12 
15:27:27.0 +0100
@@ -0,0 +1,22 @@
+/* PR tree-optimization/82954 */
+
+__attribute__((noipa)) void
+foo (int *__restrict p, int *__restrict q)
+{
+  p[0] = p[0] ^ 1;
+  p[1] = p[1] ^ 2;
+  p[2] = p[2] ^ q[2];
+  p[3] = p[3] ^ q[3];
+}
+
+int
+main ()
+{
+  int p[4] = { 16, 32, 64, 128 };
+  int q[4] = { 8, 4, 2, 1 };
+  asm volatile ("" : : "g" (p), "g" (q) : "memory");
+  foo (p, q);
+  if (p[0] != 17 || p[1] != 34 || p[2] != 66 || p[3] != 129)
+__builtin_abort ();
+  return 0;
+}

Jakub

Re: VRP: x+1 and -x cannot be INT_MIN

[Marc Glisse]

On Sun, 12 Nov 2017, Martin Sebor wrote:


On 11/11/2017 03:03 PM, Marc Glisse wrote:

Hello,

with undefined overflow, just because we know nothing about one of the
arguments of an addition doesn't mean we can't say something about the
result. We could constrain more the cases where we replace VR_VARYING
with a full VR_RANGE, but I didn't want to duplicate too much logic.

The 20040409 testcases were introduced to test an RTL transformation, so
I don't feel too bad adding -fwrapv to work around the undefined
overflows they exhibit.

Bootstrap+regtest on powerpc64le-unknown-linux-gnu.

2017-11-13  Marc Glisse  

gcc/
* tree-vrp.c (extract_range_from_binary_expr_1) [PLUS_EXPR,
MINUS_EXPR]: Use a full range for VR_VARYING.

gcc/testsuite/
PR testsuite/82951
* gcc.c-torture/execute/20040409-1.c: Use -fwrapv.
* gcc.c-torture/execute/20040409-2.c: Likewise.
* gcc.c-torture/execute/20040409-3.c: Likewise.
* gcc.dg/tree-ssa/vrp118.c: New file.



I'm curious about the 4 in the added test case (copied below).
Is there some significance to it or is actually meant to be
(or could it be) a 2?

FWIW, if there's some significance to the 4 then it would be
nice to have a comment there explaining it.  If there isn't
any then may I suggest to either change it to 2 or, perhaps
even better, change the second if condition to
(x < -__INT_MAX__ + 3) to make the effect on the range of
x clear and (presumably) also obviate questions like this
one.


I picked 4 (I was too lazy to type '2' and make it the usual 42) so there 
would be some margin, and people reading the testcase (i.e. me) wouldn't 
need to think too hard to know that -INT_MAX (shorter to type than 
-INT_MAX-1) falls in the forbidden region. Otherwise I would need to think 
if the inequality is strict, if I may have an off-by-1 error, etc. The 
goal is to check if a range computation is happening at all, not to check 
the exact bounds computed. If we want to make it tight, I guess we could 
test y<=0 and x==-INT_MAX-1 for instance.


My first idea was a test that -z can never be INT_MIN, but we have 
transformations that move negate_expr to the other side of comparisons, so 
that was more complicated to test than the addition.



Martin

+++ gcc/testsuite/gcc.dg/tree-ssa/vrp118.c  (working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+void eliminate_me();
+void f(int x,int y){
+if (y < 4)
+  __builtin_unreachable();
+x += y;
+if (x == -__INT_MAX__)
+  eliminate_me ();
+}
+
+/* { dg-final { scan-tree-dump-not "eliminate_me" "optimized" } } */


--
Marc Glisse

Re: VRP: x+1 and -x cannot be INT_MIN

[Martin Sebor]

On 11/11/2017 03:03 PM, Marc Glisse wrote:

Hello,

with undefined overflow, just because we know nothing about one of the
arguments of an addition doesn't mean we can't say something about the
result. We could constrain more the cases where we replace VR_VARYING
with a full VR_RANGE, but I didn't want to duplicate too much logic.

The 20040409 testcases were introduced to test an RTL transformation, so
I don't feel too bad adding -fwrapv to work around the undefined
overflows they exhibit.

Bootstrap+regtest on powerpc64le-unknown-linux-gnu.

2017-11-13  Marc Glisse  

gcc/
* tree-vrp.c (extract_range_from_binary_expr_1) [PLUS_EXPR,
MINUS_EXPR]: Use a full range for VR_VARYING.

gcc/testsuite/
PR testsuite/82951
* gcc.c-torture/execute/20040409-1.c: Use -fwrapv.
* gcc.c-torture/execute/20040409-2.c: Likewise.
* gcc.c-torture/execute/20040409-3.c: Likewise.
* gcc.dg/tree-ssa/vrp118.c: New file.



I'm curious about the 4 in the added test case (copied below).
Is there some significance to it or is actually meant to be
(or could it be) a 2?

FWIW, if there's some significance to the 4 then it would be
nice to have a comment there explaining it.  If there isn't
any then may I suggest to either change it to 2 or, perhaps
even better, change the second if condition to
(x < -__INT_MAX__ + 3) to make the effect on the range of
x clear and (presumably) also obviate questions like this
one.

Martin

+++ gcc/testsuite/gcc.dg/tree-ssa/vrp118.c  (working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+void eliminate_me();
+void f(int x,int y){
+if (y < 4)
+  __builtin_unreachable();
+x += y;
+if (x == -__INT_MAX__)
+  eliminate_me ();
+}
+
+/* { dg-final { scan-tree-dump-not "eliminate_me" "optimized" } } */

[PATCH] gdbinit: break on gfc_internal_error

[Bernhard Reutner-Fischer]

Hi!

Ok for trunk?

gcc/ChangeLog:

2017-11-12  Bernhard Reutner-Fischer  

* gdbinit.in: Break on gfc_internal_error.

Signed-off-by: Bernhard Reutner-Fischer 
---
 gcc/gdbinit.in | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/gdbinit.in b/gcc/gdbinit.in
index be56b0ee25b..ab777158c76 100644
--- a/gcc/gdbinit.in
+++ b/gcc/gdbinit.in
@@ -225,6 +225,7 @@ b fancy_abort
 
 # Put a breakpoint on internal_error to help with debugging ICEs.
 b internal_error
+b gfc_internal_error
 
 set complaints 0
 # Don't let abort actually run, as it will make
-- 
2.15.0

Re: [patch][x86] -march=icelake

[Sandra Loosemore]

On 11/11/2017 05:04 PM, Koval, Julia wrote:

Hi, this patch adds new option -march=icelake.
[snip]

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index bc6e86f..891c283 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -25331,6 +25331,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, 
CLFLUSHOPT, XSAVEC,
 XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
 AVX512IFMA, SHA, CLWB and UMIP instruction set support.
 
+@item Icelake

+Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
+AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
+AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
+
 @item k6
 AMD K6 CPU with MMX instruction set support.


Since it's -march=icelake (all lower case),

s/@item Icelake/@item icelake/

-Sandra

[riscv] Wrap ASM_OUTPUT_LABELREF in do {} while (0)

[Tom de Vries]

Hi,

this patch wraps riscv.h's ASM_OUTPUT_LABELREF in "do {} while (0)".

Build for riscv64.

Committed as obvious.

Thanks,
- Tom
[riscv] Wrap ASM_OUTPUT_LABELREF in do {} while (0)

2017-11-12  Tom de Vries  

	* config/riscv/riscv.h (ASM_OUTPUT_LABELREF): Wrap in do {} while (0).

---
 gcc/config/riscv/riscv.h | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 91a9c33..fe09e84 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -585,12 +585,15 @@ typedef struct {
 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
'the start of the function that this code is output in'.  */
 
-#define ASM_OUTPUT_LABELREF(FILE,NAME)  \
-  if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)\
-asm_fprintf ((FILE), "%U%s",	\
-		 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));	\
-  else	\
-asm_fprintf ((FILE), "%U%s", (NAME))
+#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
+  do {	\
+if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)			\
+  asm_fprintf ((FILE), "%U%s",	\
+		   XSTR (XEXP (DECL_RTL (current_function_decl),	\
+			   0), 0));	\
+else\
+  asm_fprintf ((FILE), "%U%s", (NAME));\
+  } while (0)
 
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode

[committed] Remove semicolon after ASM_OUTPUT_ASCII

[Tom de Vries]

Hi,

this patch removes a semicolon after the ASM_OUTPUT_ASCII macro body in 
elfos.h.


Build for x86_64.

Committed as obvious.

Thanks,
- Tom
Remove semicolon after ASM_OUTPUT_ASCII

2017-11-12  Tom de Vries  

	* config/elfos.h (ASM_OUTPUT_ASCII): Remove semicolon after macro body.

---
 gcc/config/elfos.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h
index 0f79de7..8149c81 100644
--- a/gcc/config/elfos.h
+++ b/gcc/config/elfos.h
@@ -444,7 +444,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 
 #undef  ASM_OUTPUT_ASCII
 #define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)			\
-  default_elf_asm_output_ascii ((FILE), (STR), (LENGTH));
+  default_elf_asm_output_ascii ((FILE), (STR), (LENGTH))
 
 /* Allow the use of the -frecord-gcc-switches switch via the
elf_record_gcc_switches function defined in varasm.c.  */

[cr16, powerpcspe, rs6000] Remove semicolon after ASM_OUTPUT_LABELREF macro body

[Tom de Vries]

Hi,

this removes a semicolon after the ASM_OUTPUT_LABELREF macro body.

Committed as obvious.

Thanks,
- Tom
[cr16, powerpcspe, rs6000] Remove semicolon after ASM_OUTPUT_LABELREF macro body

2017-11-12  Tom de Vries  

	* config/cr16/cr16.h (ASM_OUTPUT_LABELREF): Remove semicolon after macro
	body.
	* config/powerpcspe/xcoff.h (ASM_OUTPUT_LABELREF): Same.
	* config/rs6000/xcoff.h (ASM_OUTPUT_LABELREF): Same.
	* defaults.h (ASM_OUTPUT_LABELREF): Same.

---
 gcc/config/cr16/cr16.h| 2 +-
 gcc/config/powerpcspe/xcoff.h | 2 +-
 gcc/config/rs6000/xcoff.h | 2 +-
 gcc/defaults.h| 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index 29f5b85..b0ad34f 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -479,7 +479,7 @@ struct cumulative_args
 
 #undef ASM_OUTPUT_LABELREF
 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
-  asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));
+  asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME))
 
 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL)   \
   do\
diff --git a/gcc/config/powerpcspe/xcoff.h b/gcc/config/powerpcspe/xcoff.h
index 36f40f4..1eeb75c 100644
--- a/gcc/config/powerpcspe/xcoff.h
+++ b/gcc/config/powerpcspe/xcoff.h
@@ -179,7 +179,7 @@
`assemble_name' uses this.  */
 
 #define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  asm_fprintf ((FILE), "%U%s", rs6000_xcoff_strip_dollar (NAME));
+  asm_fprintf ((FILE), "%U%s", rs6000_xcoff_strip_dollar (NAME))
 
 /* This is how to output an internal label prefix.  rs6000.c uses this
when generating traceback tables.  */
diff --git a/gcc/config/rs6000/xcoff.h b/gcc/config/rs6000/xcoff.h
index 36f40f4..1eeb75c 100644
--- a/gcc/config/rs6000/xcoff.h
+++ b/gcc/config/rs6000/xcoff.h
@@ -179,7 +179,7 @@
`assemble_name' uses this.  */
 
 #define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  asm_fprintf ((FILE), "%U%s", rs6000_xcoff_strip_dollar (NAME));
+  asm_fprintf ((FILE), "%U%s", rs6000_xcoff_strip_dollar (NAME))
 
 /* This is how to output an internal label prefix.  rs6000.c uses this
when generating traceback tables.  */
diff --git a/gcc/defaults.h b/gcc/defaults.h
index 768c987..978ec98 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -170,7 +170,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
   do {			\
 fputs (user_label_prefix, (FILE));			\
 fputs ((NAME), (FILE));\
-  } while (0);
+  } while (0)
 #endif
 
 /* Allow target to print debug info labels specially.  This is useful for

Re: [patch][x86] -march=icelake

[Uros Bizjak]

On Sun, Nov 12, 2017 at 1:04 AM, Koval, Julia  wrote:
> Hi, this patch adds new option -march=icelake. Isasets defined in: 
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> I didn't add arch code to driver-i386.c, because there is no code available 
> in SDM yet, only for cannonlake 
> (https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
>  Chapter 2).

This means the driver will go through generic detection for
-march=native. Perhaps a comment should be added, so we won't forget
to add the model number when one is available.

> gcc/
> * config.gcc: Add -march=icelake.
> * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
> * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
> * config/i386/i386.c (processor_costs): Add m_ICELAKE.
> (PTA_ICELAKE, PTA2_ICELAKE, PTA2_GFNI, PTA2_AVX512VBMI2, PTA2_VAES,
> PTA2_AVX512VNNI, PTA2_VPCLMULQDQ, PTA2_RDPID, PTA2_AVX512BITALG): New.
> (processor_target_table): Add icelake.
> (ix86_option_override_internal): Add flags2 for new PTA, handle GFNI, 
> RDPID.
> (get_builtin_code_for_version): Handle icelake.
> (M_INTEL_COREI7_ICELAKE): New.
> * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
> * doc/invoke.texi: Add -march=icelake.
> gcc/testsuite/
> * gcc.target/i386/funcspec-56.inc: Handle new march.
> * g++.dg/ext/mv16.C: Ditto.
> libgcc/
> * config/i386/cpuinfo.h (processor_subtypes): Add 
> INTEL_COREI7_ICELAKE.

@@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p,
 #define PTA_AVX5124FMAPS(HOST_WIDE_INT_1 << 61)
 #define PTA_AVX512VPOPCNTDQ(HOST_WIDE_INT_1 << 62)
 #define PTA_SGX(HOST_WIDE_INT_1 << 63)
+#define PTA2_GFNI(HOST_WIDE_INT_1 << 0)
+#define PTA2_AVX512VBMI2(HOST_WIDE_INT_1 << 1)
+#define PTA2_VAES(HOST_WIDE_INT_1 << 2)
+#define PTA2_AVX512VNNI(HOST_WIDE_INT_1 << 3)
+#define PTA2_VPCLMULQDQ(HOST_WIDE_INT_1 << 4)
+#define PTA2_RDPID(HOST_WIDE_INT_1 << 5)
+#define PTA2_AVX512BITALG(HOST_WIDE_INT_1 << 6)

Please add these options first.

On a related note, there should probably be a better way to extend
various bitmapped flag variables beyond 64bit words. We are constantly
going over 64bit sizes in target option masks, now the number of
processor flags doesn't fit in a word anymore. There are several
places one has to keep in mind in which word some specific flag lives,
and this  approach opens several ways to make a hard to detect
mistake. Does C++ offer a more elegant way?

Bellow, please find a suggestion of a couple of cosmetic changes.

Thanks,
Uros.

@@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p,
 #define PTA_AVX5124FMAPS(HOST_WIDE_INT_1 << 61)
 #define PTA_AVX512VPOPCNTDQ(HOST_WIDE_INT_1 << 62)
 #define PTA_SGX(HOST_WIDE_INT_1 << 63)

Please add a comment here, that the folowing belongs to flags2.

+#define PTA2_GFNI(HOST_WIDE_INT_1 << 0)
+#define PTA2_AVX512VBMI2(HOST_WIDE_INT_1 << 1)
+#define PTA2_VAES(HOST_WIDE_INT_1 << 2)


@@ -4105,6 +4124,12 @@ ix86_option_override_internal (bool main_args_p,
 if (processor_alias_table[i].flags & PTA_SGX
 && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
   opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;

Please add vertical space here to visually separate flags and flags2 processing.

+if (processor_alias_table[i].flags2 & PTA2_RDPID
+&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
+  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;

Re: [x86][patch] Add -march=cannonlake.

[Uros Bizjak]

On Sat, Nov 11, 2017 at 10:10 PM, Koval, Julia  wrote:
> Hi Uros,
> I fixed comments.
> Btw, I haven't found skylake-avx512 in driver-i386.c at all. Is it intended 
> or should I add it?

It looks like an oversight to me. If there are no "skylake-avx512"
model, then the driver goes through "This is unknown ..." for
-march=native and hopefully chooses the next most appropriate choice.
Please add "skylake-avx512" in a follow-up patch.

> Thanks,
> Julia
>
> gcc/
> * config.gcc: Add -march=cannonlake.
> * config/i386/driver-i386.c (host_detect_local_cpu): Detect 
> cannonlake.
> * config/i386/i386-c.c (ix86_target_macros_internal): Handle 
> cannonlake.
> * config/i386/i386.c (processor_costs): Add m_CANNONLAKE.
> (PTA_CANNONLAKE): New.
> (processor_target_table): Add cannonlake.
> (ix86_option_override_internal): Ditto.
> (fold_builtin_cpu): Ditto.
> (get_builtin_code_for_version): Handle cannonlake.
> (M_INTEL_COREI7_CANNONLAKE): New.
> * config/i386/i386.h (TARGET_CANNONLAKE, PROCESSOR_CANNONLAKE): New.
> * doc/invoke.texi: Add -march=cannonlake.
> gcc/testsuite/
> * gcc.target/i386/funcspec-56.inc: Handle new march.
> * g++.dg/ext/mv16.C: Ditto.
> libgcc/
> * config/i386/cpuinfo.c (get_intel_cpu): Handle cannonlake.
> * config/i386/cpuinfo.h (processor_subtypes): Add 
> INTEL_COREI7_CANNONLAKE.

OK.

Thanks,
Uros.

Re: [PATCH] Fixes for PR68356, PR81210, and PR81693

[H.J. Lu]

On Sun, Nov 12, 2017 at 6:22 AM, Dominique d'Humières
 wrote:
> The following patch fixes PR68356, PR81210, and PR81693 on darwin.
>
> --- ../_clean/gcc/testsuite/gcc.dg/torture/pr68264.c2016-01-28 
> 00:30:03.0 +0100
> +++ gcc/testsuite/gcc.dg/torture/pr68264.c  2017-11-11 17:16:58.0 
> +0100
> @@ -1,4 +1,5 @@
>  /* { dg-do run } */
> +/* { dg-xfail-run-if "PR68356 no math-errno on darwin" { "*-*-darwin*" } } */
>  /* { dg-add-options ieee } */
>  /* { dg-require-effective-target fenv_exceptions } */
>
> --- ../_clean/gcc/testsuite/gcc.dg/torture/pr68037-1.c  2016-06-10 
> 15:22:50.0 +0200
> +++ gcc/testsuite/gcc.dg/torture/pr68037-1.c2017-11-11 18:43:16.0 
> +0100
> @@ -1,4 +1,5 @@
>  /* { dg-do run { target i?86-*-* x86_64-*-* } } */
> +/* { dg-xfail-run-if "PR81210" { *-*-darwin* && lp64 } } */
>  /* { dg-options "-mgeneral-regs-only" } */
>
>  extern void exit (int);
> --- ../_clean/gcc/testsuite/gcc.dg/torture/pr68037-2.c  2016-06-10 
> 15:22:50.0 +0200
> +++ gcc/testsuite/gcc.dg/torture/pr68037-2.c2017-11-11 18:44:08.0 
> +0100
> @@ -1,4 +1,5 @@
>  /* { dg-do run { target i?86-*-* x86_64-*-* } } */
> +/* { dg-xfail-run-if "PR81210" { *-*-darwin* && lp64 } } */
>  /* { dg-options "-mgeneral-regs-only" } */
>
>  extern void exit (int);
> --- ../_clean/gcc/testsuite/gcc.dg/torture/pr68037-3.c  2016-06-10 
> 15:22:50.0 +0200
> +++ gcc/testsuite/gcc.dg/torture/pr68037-3.c2017-11-11 18:49:10.0 
> +0100
> @@ -1,4 +1,5 @@
>  /* { dg-do run { target i?86-*-* x86_64-*-* } } */
> +/* { dg-xfail-run-if "PR81210" { *-*-darwin* && lp64 } { "-O1" "-O2" "-O3" 
> "-Os" } } */
>  /* { dg-options "-mgeneral-regs-only" } */
>
>  #include 
> --- ../_clean/gcc/testsuite/gcc.dg/torture/pr25967-1.c  2017-10-26 
> 07:16:19.0 +0200
> +++ gcc/testsuite/gcc.dg/torture/pr25967-1.c2017-11-11 19:36:30.0 
> +0100
> @@ -1,4 +1,5 @@
>  /* { dg-do run { target i?86-*-* x86_64-*-* } } */
> +/* { dg-xfail-run-if "PR81693" { "*-*-darwin*" } } */
>  /* { dg-options "-mgeneral-regs-only" } */
>
>  extern void exit (int);
> --- ../_clean/gcc/testsuite/gcc.dg/torture/pr25967-2.c  2017-10-26 
> 07:16:19.0 +0200
> +++ gcc/testsuite/gcc.dg/torture/pr25967-2.c2017-11-11 19:36:02.0 
> +0100
> @@ -1,4 +1,5 @@
>  /* { dg-do run { target i?86-*-* x86_64-*-* } } */
> +/* { dg-xfail-run-if "PR81693" { *-*-darwin* && ilp32 } } */
>  /* { dg-options "-mgeneral-regs-only" } */
>
>
> Is it OK?

I wrote these tests.  These tests don't align stack to 16 bytes and
should be skipped on Darwin.


-- 
H.J.

[PATCH] Fixes for PR68356, PR81210, and PR81693

[Dominique d'Humières]

The following patch fixes PR68356, PR81210, and PR81693 on darwin.

--- ../_clean/gcc/testsuite/gcc.dg/torture/pr68264.c2016-01-28 
00:30:03.0 +0100
+++ gcc/testsuite/gcc.dg/torture/pr68264.c  2017-11-11 17:16:58.0 
+0100
@@ -1,4 +1,5 @@
 /* { dg-do run } */
+/* { dg-xfail-run-if "PR68356 no math-errno on darwin" { "*-*-darwin*" } } */
 /* { dg-add-options ieee } */
 /* { dg-require-effective-target fenv_exceptions } */
 
--- ../_clean/gcc/testsuite/gcc.dg/torture/pr68037-1.c  2016-06-10 
15:22:50.0 +0200
+++ gcc/testsuite/gcc.dg/torture/pr68037-1.c2017-11-11 18:43:16.0 
+0100
@@ -1,4 +1,5 @@
 /* { dg-do run { target i?86-*-* x86_64-*-* } } */
+/* { dg-xfail-run-if "PR81210" { *-*-darwin* && lp64 } } */
 /* { dg-options "-mgeneral-regs-only" } */
 
 extern void exit (int);
--- ../_clean/gcc/testsuite/gcc.dg/torture/pr68037-2.c  2016-06-10 
15:22:50.0 +0200
+++ gcc/testsuite/gcc.dg/torture/pr68037-2.c2017-11-11 18:44:08.0 
+0100
@@ -1,4 +1,5 @@
 /* { dg-do run { target i?86-*-* x86_64-*-* } } */
+/* { dg-xfail-run-if "PR81210" { *-*-darwin* && lp64 } } */
 /* { dg-options "-mgeneral-regs-only" } */
 
 extern void exit (int);
--- ../_clean/gcc/testsuite/gcc.dg/torture/pr68037-3.c  2016-06-10 
15:22:50.0 +0200
+++ gcc/testsuite/gcc.dg/torture/pr68037-3.c2017-11-11 18:49:10.0 
+0100
@@ -1,4 +1,5 @@
 /* { dg-do run { target i?86-*-* x86_64-*-* } } */
+/* { dg-xfail-run-if "PR81210" { *-*-darwin* && lp64 } { "-O1" "-O2" "-O3" 
"-Os" } } */
 /* { dg-options "-mgeneral-regs-only" } */
 
 #include 
--- ../_clean/gcc/testsuite/gcc.dg/torture/pr25967-1.c  2017-10-26 
07:16:19.0 +0200
+++ gcc/testsuite/gcc.dg/torture/pr25967-1.c2017-11-11 19:36:30.0 
+0100
@@ -1,4 +1,5 @@
 /* { dg-do run { target i?86-*-* x86_64-*-* } } */
+/* { dg-xfail-run-if "PR81693" { "*-*-darwin*" } } */
 /* { dg-options "-mgeneral-regs-only" } */
 
 extern void exit (int);
--- ../_clean/gcc/testsuite/gcc.dg/torture/pr25967-2.c  2017-10-26 
07:16:19.0 +0200
+++ gcc/testsuite/gcc.dg/torture/pr25967-2.c2017-11-11 19:36:02.0 
+0100
@@ -1,4 +1,5 @@
 /* { dg-do run { target i?86-*-* x86_64-*-* } } */
+/* { dg-xfail-run-if "PR81693" { *-*-darwin* && ilp32 } } */
 /* { dg-options "-mgeneral-regs-only" } */
 

Is it OK?

TIA

Dominique

[PATCH] Fix pr81706 tests on darwin

[Dominique d'Humières]

The following patch fixes pr81706 tests on darwin

--- ../_clean/gcc/testsuite/gcc.target/i386/pr81706.c   2017-10-26 
07:16:18.0 +0200
+++ gcc/testsuite/gcc.target/i386/pr81706.c 2017-11-11 16:02:36.0 
+0100
@@ -1,8 +1,8 @@
 /* PR libstdc++/81706 */
 /* { dg-do compile } */
 /* { dg-options "-O3 -mavx2 -mno-avx512f" } */
-/* { dg-final { scan-assembler "call\[^\n\r]_ZGVdN4v_cos" } } */
-/* { dg-final { scan-assembler "call\[^\n\r]_ZGVdN4v_sin" } } */
+/* { dg-final { scan-assembler "call\[^\n\r]__?ZGVdN4v_cos" } } */
+/* { dg-final { scan-assembler "call\[^\n\r]__?ZGVdN4v_sin" } } */
 
 #ifdef __cplusplus
 extern "C" {
--- ../_clean/gcc/testsuite/g++.dg/ext/pr81706.C2017-10-26 
07:16:21.0 +0200
+++ gcc/testsuite/g++.dg/ext/pr81706.C  2017-11-09 21:41:36.0 +0100
@@ -1,8 +1,8 @@
 // PR libstdc++/81706
 // { dg-do compile { target i?86-*-* x86_64-*-* } }
 // { dg-options "-O3 -mavx2 -mno-avx512f" }
-// { dg-final { scan-assembler "call\[^\n\r]_ZGVdN4v_cos" } }
-// { dg-final { scan-assembler "call\[^\n\r]_ZGVdN4v_sin" } }
+// { dg-final { scan-assembler "call\[^\n\r]__?ZGVdN4v_cos" } }
+// { dg-final { scan-assembler "call\[^\n\r]__?ZGVdN4v_sin" } }
 
 #ifdef __cplusplus
 extern "C {

Is it OK?

TIA

Dominique

[RFC gfortran] PR53478 - gfortran segfaults when module name clashes with C binding name of procedure

[Dominique d'Humières]

This patch implement the requirement

> ... Furthermore, a binding label shall not be
> the same as the global identifier of any other global entity, ignoring
> differences in case."

While looking at the code, I noticed that several %s should be %qs. This is 
fixed as well by the patch along with the needed adjustment of the test suite.

Tested on darwin.

TIA

Dominique

2017-1-12  Dominique d'Humieres  

PR fortran/53478
* gfortran.h (gfc_find_case_gsymbol): New prototype.
* symbol.c (gfc_find_case_gsymbol): New procedure, case
insensistive version of gfc_find_gsymbol.
* resolve.c (resolve_common_blocks): Use it.
Replace %s with %qs where needed.

2017-11-12  Dominique d'Humieres  

PR fortran/53478
* gfortran.dg/binding_label_tests_4.f03: Update dg-error.
* gfortran.dg/binding_label_tests_6.f03: Likewise.
* gfortran.dg/binding_label_tests_7.f03: Likewise.
* gfortran.dg/binding_label_tests_8.f03: Likewise.
* gfortran.dg/binding_label_tests_10_main.f03: Likewise.
* gfortran.dg/binding_label_tests_11_main.f03: Likewise.
* gfortran.dg/binding_label_tests_13_main.f03: Likewise.
* gfortran.dg/test_common_binding_labels_3_main.f03: Likewise.
* gfortran.dg/binding_label_tests_29.f90: New test.



patch-56440
Description: Binary data

[patch][x86,avx] Enable AVX512BITALG

[Koval, Julia]

Hi, this patch enables AVX512BITALG and AVX512VPOPCNTDQ instructions from 
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf.
 Ok for trunk?

Thanks,
Julia


Julia Koval 
Sebastian Peryt 
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BITALG_SET,
OPTION_MASK_ISA_AVX512BITALG_UNSET): New.
(ix86_handle_option): Handle -mavx512bitalg, fix 4VNNIW formatting.
* config.gcc: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h.
* config/i386/avx512bitalgintrin.h (_mm512_popcnt_epi8, 
_mm512_popcnt_epi16,
_mm512_mask_popcnt_epi8, _mm512_maskz_popcnt_epi8, 
_mm512_mask_popcnt_epi16,
_mm512_maskz_popcnt_epi16, _mm512_bitshuffle_epi64_mask, 
_mm256_popcnt_epi8,
_mm512_mask_bitshuffle_epi64_mask, _mm256_mask_popcnt_epi8, 
_mm_popcnt_epi8,
_mm256_maskz_popcnt_epi8, _mm_bitshuffle_epi64_mask, 
_mm256_popcnt_epi16,
_mm_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask,
_mm256_mask_bitshuffle_epi64_mask, _mm_popcnt_epi16, 
_mm_maskz_popcnt_epi8,
_mm256_mask_popcnt_epi16, _mm256_maskz_popcnt_epi16, 
_mm_mask_popcnt_epi8,
_mm_mask_popcnt_epi16, _mm_maskz_popcnt_epi16): New intrinsics.
* config/i386/avx512vpopcntdqvlintrin.h (_mm_popcnt_epi32, 
_mm_popcnt_epi64,
_mm_mask_popcnt_epi32, _mm_maskz_popcnt_epi32, _mm256_popcnt_epi32,
_mm256_mask_popcnt_epi32, _mm256_maskz_popcnt_epi32, 
_mm_mask_popcnt_epi64,
_mm_maskz_popcnt_epi64, _mm256_popcnt_epi64, _mm256_mask_popcnt_epi64,
_mm256_maskz_popcnt_epi64): New intrinsics.
* config/i386/cpuid.h (bit_AVX512BITALG): New bit.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect 
-mavx512bitalg.
* config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI, 
V64QI_FTYPE_V64QI,
V4DI_FTYPE_V4DI, UHI_FTYPE_V2DI_V2DI_UHI, USI_FTYPE_V4DI_V4DI_USI,
V4SI_FTYPE_V4SI_V4SI_UHI, V8SI_FTYPE_V8SI_V8SI_UHI): New types.
* config/i386/i386-builtin.def (__builtin_ia32_vpopcountq_v4di,
__builtin_ia32_vpopcountq_v4di_mask, __builtin_ia32_vpopcountq_v2di,
__builtin_ia32_vpopcountq_v2di_mask, __builtin_ia32_vpopcountd_v4si,
__builtin_ia32_vpopcountd_v4si_mask, __builtin_ia32_vpopcountd_v8si,
__builtin_ia32_vpopcountd_v8si_mask, __builtin_ia32_vpopcountb_v64qi,
__builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountb_v32qi,
__builtin_ia32_vpopcountb_v32qi_mask, __builtin_ia32_vpopcountb_v16qi,
__builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v32hi,
__builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpopcountw_v16hi,
__builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi,
__builtin_ia32_vpopcountw_v8hi_mask, 
__builtin_ia32_vpshufbitqmb128_mask,
__builtin_ia32_vpshufbitqmb256_mask,
__builtin_ia32_vpshufbitqmb512_mask): New builtins.
* config/i386/i386-c.c (__AVX512BITALG__): New.
* config/i386/i386.c (isa2_opts): Add -mavx512bitalg.
(ix86_valid_target_attribute_inner_p): Ditto.
(ix86_expand_args_builtin): Handle new types.
* config/i386/i386.h (TARGET_AVX512BITALG, TARGET_AVX512BITALG_P): New.
* config/i386/i386.opt: Add -mavx512bitalg.
* config/i386/immintrin.h: Add avx512vpopcntdqvlintrin.h and
avx512bitalgintrin.h.
* config/i386/sse.md (VI48_AVX512VLBW): New iterator.
(vpopcount): Add more types.
(avx512vl_vpshufbitqmb): New.
* doc/invoke.texi: Add -mavx512bitalg and -mavx512vpopcntdq.
gcc/testsuite/
* g++.dg/other/i386-2.C: Add new options.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx512-check.h: Handle bit_AVX512BITALG.
* gcc.target/i386/avx512bitalg-vpopcntb-1.c: New.
* gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto.
* gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto.
* gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdqvl-vpopcntd-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdqvl-vpopcntq-1.c: Ditto.
* gcc.target/i386/i386.exp (check_effective_target_avx512bitalg): New.
* gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: 

Re: Drop frequencies from cgraph edges

[Andreas Schwab]

This causes bootstrap comparison failures on ia64.  For example:

$ diff -u <(nm stage{2,3}-gcc/gcov.o)
--- /dev/fd/63  2017-11-12 12:12:14.174568108 +0100
+++ /dev/fd/62  2017-11-12 12:12:14.174568108 +0100
@@ -33,9 +33,9 @@
 0050 s _ZL15flag_long_names
 0044 s _ZL15flag_use_colors
 04c0 t _ZL15gcov_read_wordsj
-3900 t _ZL15read_count_fileP13function_info
+3cc0 t _ZL15read_count_fileP13function_info
 2280 t _ZL16executed_summaryjj.part.10
-4680 t _ZL16function_summaryPK13coverage_infoPKc
+3900 t _ZL16function_summaryPK13coverage_infoPKc
 3740 t _ZL16gcov_read_stringv
 8940 t _ZL16generate_resultsPKc
 7b80 t _ZL16get_cycles_countR9line_infob
 
Andreas.

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
"And now for something completely different."