Re: [PATCH] Fix tree-loop-distribution.c ICE with -ftrapv (PR tree-optimization/89278)
On Fri, Feb 15, 2019 at 08:33:44AM +0100, Jakub Jelinek wrote: > On Fri, Feb 15, 2019 at 03:25:33PM +0800, Bin.Cheng wrote: > > So with what condition we can safely rewrite trapping operations into > > non trapping one? Does the rewrite nullify -ftrapv which requires > > trap behavior? > > For the particular expression? Yes, otherwise no. > > -ftrapv should be either replaced with -fsanitize=signed-integer-overflow > -fsanitize-undefined-trap-on-error, or at least implemented that way in the > middle-end (perhaps with a separate ifn, so that we can pattern recognize it > during expansion and use library calls where the inline call is not small > enough). We haven't done that yet though. To clarify, the current -ftrapv implementation doesn't guarantee you get traps on overflow, it will happily optimize computations away at any time during GIMPLE optimizations, or turn stuff into unsigned computations etc. (not just through this rewrite function, but many other ways). For -fsanitize=signed-integer-overflow -fsanitize-undefined-trap-on-error there are no guarantees either, but we try hard not to optimize those away, we have TYPE_OVERFLOW_SANITIZED checks that punt certain optimizations in fold-const.c/match.pd and early (right after going into ssa form) we turn the arithmetics into ifns, which are optimized away only if we can prove there will be no overflow. On the other side, it can hinder other optimizations (a lot). And possibly overflowing computations introduced during later optimizations are not sanitized. The question is what -ftrapv users want, plus right now they have a choice, catch perhaps less UB with more optimization opportunities (-ftrapv) or catch more optimize less (UBSan). Jakub
Re: [PATCH] Fix tree-loop-distribution.c ICE with -ftrapv (PR tree-optimization/89278)
On Fri, Feb 15, 2019 at 03:25:33PM +0800, Bin.Cheng wrote: > So with what condition we can safely rewrite trapping operations into > non trapping one? Does the rewrite nullify -ftrapv which requires > trap behavior? For the particular expression? Yes, otherwise no. -ftrapv should be either replaced with -fsanitize=signed-integer-overflow -fsanitize-undefined-trap-on-error, or at least implemented that way in the middle-end (perhaps with a separate ifn, so that we can pattern recognize it during expansion and use library calls where the inline call is not small enough). We haven't done that yet though. Jakub
Re: [PATCH] Fix tree-loop-distribution.c ICE with -ftrapv (PR tree-optimization/89278)
On Fri, Feb 15, 2019 at 6:52 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase ICEs, because we try to gimplify a complex expression
> that with -ftrapv wants to emit multiple bbs. Fixed by using
> rewrite_to_non_trapping_overflow. Bootstrapped/regtested on x86_64-linux
So with what condition we can safely rewrite trapping operations into
non trapping one? Does the rewrite nullify -ftrapv which requires
trap behavior?
Thanks,
bin
> and i686-linux, ok for trunk and 8.3?
>
> 2019-02-14 Richard Biener
> Jakub Jelinek
>
> PR tree-optimization/89278
> * tree-loop-distribution.c: Include tree-eh.h.
> (generate_memset_builtin, generate_memcpy_builtin): Call
> rewrite_to_non_trapping_overflow on builtin->size before passing it
> to force_gimple_operand_gsi.
>
> * gcc.dg/pr89278.c: New test.
>
> --- gcc/tree-loop-distribution.c.jj 2019-01-10 11:43:02.255576992 +0100
> +++ gcc/tree-loop-distribution.c2019-02-14 12:17:24.403403131 +0100
> @@ -114,6 +114,7 @@ along with GCC; see the file COPYING3.
> #include "tree-scalar-evolution.h"
> #include "params.h"
> #include "tree-vectorizer.h"
> +#include "tree-eh.h"
>
>
> #define MAX_DATAREFS_NUM \
> @@ -996,7 +997,7 @@ generate_memset_builtin (struct loop *lo
>/* The new statements will be placed before LOOP. */
>gsi = gsi_last_bb (loop_preheader_edge (loop)->src);
>
> - nb_bytes = builtin->size;
> + nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
>nb_bytes = force_gimple_operand_gsi (, nb_bytes, true, NULL_TREE,
>false, GSI_CONTINUE_LINKING);
>mem = builtin->dst_base;
> @@ -1048,7 +1049,7 @@ generate_memcpy_builtin (struct loop *lo
>/* The new statements will be placed before LOOP. */
>gsi = gsi_last_bb (loop_preheader_edge (loop)->src);
>
> - nb_bytes = builtin->size;
> + nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
>nb_bytes = force_gimple_operand_gsi (, nb_bytes, true, NULL_TREE,
>false, GSI_CONTINUE_LINKING);
>dest = builtin->dst_base;
> --- gcc/testsuite/gcc.dg/pr89278.c.jj 2019-02-14 12:18:38.778173413 +0100
> +++ gcc/testsuite/gcc.dg/pr89278.c 2019-02-14 12:18:19.065499344 +0100
> @@ -0,0 +1,23 @@
> +/* PR tree-optimization/89278 */
> +/* { dg-do compile } */
> +/* { dg-options "-O1 -ftrapv -ftree-loop-distribute-patterns --param
> max-loop-header-insns=2" } */
> +
> +void
> +foo (int *w, int x, int y, int z)
> +{
> + while (x < y + z)
> +{
> + w[x] = 0;
> + ++x;
> +}
> +}
> +
> +void
> +bar (int *__restrict u, int *__restrict w, int x, int y, int z)
> +{
> + while (x < y + z)
> +{
> + w[x] = u[x];
> + ++x;
> +}
> +}
>
> Jakub
Re: [PATCH] Avoid assuming valid_constant_size_p argument is a constant expression (PR 89294)
> The attached patch removes the assumption introduced earlier today > in my fix for bug 87996 that the valid_constant_size_p argument is > a constant expression. I couldn't come up with a C/C++ test case > where this isn't true but apparently it can happen in Ada which I > inadvertently didn't build. Can we do something here? Our internal testers have been down for 3 days because of this blunder... -- Eric Botcazou
Re: [PATCH] Fix tree-loop-distribution.c ICE with -ftrapv (PR tree-optimization/89278)
On February 14, 2019 11:52:17 PM GMT+01:00, Jakub Jelinek
wrote:
>Hi!
>
>The following testcase ICEs, because we try to gimplify a complex
>expression
>that with -ftrapv wants to emit multiple bbs. Fixed by using
>rewrite_to_non_trapping_overflow. Bootstrapped/regtested on
>x86_64-linux
>and i686-linux, ok for trunk and 8.3?
OK.
Richard.
>2019-02-14 Richard Biener
> Jakub Jelinek
>
> PR tree-optimization/89278
> * tree-loop-distribution.c: Include tree-eh.h.
> (generate_memset_builtin, generate_memcpy_builtin): Call
> rewrite_to_non_trapping_overflow on builtin->size before passing it
> to force_gimple_operand_gsi.
>
> * gcc.dg/pr89278.c: New test.
>
>--- gcc/tree-loop-distribution.c.jj2019-01-10 11:43:02.255576992 +0100
>+++ gcc/tree-loop-distribution.c 2019-02-14 12:17:24.403403131 +0100
>@@ -114,6 +114,7 @@ along with GCC; see the file COPYING3.
> #include "tree-scalar-evolution.h"
> #include "params.h"
> #include "tree-vectorizer.h"
>+#include "tree-eh.h"
>
>
> #define MAX_DATAREFS_NUM \
>@@ -996,7 +997,7 @@ generate_memset_builtin (struct loop *lo
> /* The new statements will be placed before LOOP. */
> gsi = gsi_last_bb (loop_preheader_edge (loop)->src);
>
>- nb_bytes = builtin->size;
>+ nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
> nb_bytes = force_gimple_operand_gsi (, nb_bytes, true, NULL_TREE,
> false, GSI_CONTINUE_LINKING);
> mem = builtin->dst_base;
>@@ -1048,7 +1049,7 @@ generate_memcpy_builtin (struct loop *lo
> /* The new statements will be placed before LOOP. */
> gsi = gsi_last_bb (loop_preheader_edge (loop)->src);
>
>- nb_bytes = builtin->size;
>+ nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
> nb_bytes = force_gimple_operand_gsi (, nb_bytes, true, NULL_TREE,
> false, GSI_CONTINUE_LINKING);
> dest = builtin->dst_base;
>--- gcc/testsuite/gcc.dg/pr89278.c.jj 2019-02-14 12:18:38.778173413
>+0100
>+++ gcc/testsuite/gcc.dg/pr89278.c 2019-02-14 12:18:19.065499344 +0100
>@@ -0,0 +1,23 @@
>+/* PR tree-optimization/89278 */
>+/* { dg-do compile } */
>+/* { dg-options "-O1 -ftrapv -ftree-loop-distribute-patterns --param
>max-loop-header-insns=2" } */
>+
>+void
>+foo (int *w, int x, int y, int z)
>+{
>+ while (x < y + z)
>+{
>+ w[x] = 0;
>+ ++x;
>+}
>+}
>+
>+void
>+bar (int *__restrict u, int *__restrict w, int x, int y, int z)
>+{
>+ while (x < y + z)
>+{
>+ w[x] = u[x];
>+ ++x;
>+}
>+}
>
> Jakub
[PATCH] i386: Insert ENDBR for NOTE_INSN_DELETED_LABEL only if needed
NOTE_INSN_DELETED_LABEL is used to mark what used to be a 'code_label',
but was not used for other purposes than taking its address and was
transformed to mark that no code jumps to it. NOTE_INSN_DELETED_LABEL
is generated only in 3 places:
1. When delete_insn sees an unused label which is an explicit label in
the input source code or its address is taken, it turns the label into
a NOTE_INSN_DELETED_LABEL note.
2. When rtl_tidy_fallthru_edge deletes a tablejump, it turns the
tablejump into a NOTE_INSN_DELETED_LABEL note.
3. ix86_init_large_pic_reg creats a NOTE_INSN_DELETED_LABEL note, .L2,
to initialize large model PIC register:
L2:
movabsq $_GLOBAL_OFFSET_TABLE_-.L2, %r11
leaq.L2(%rip), %rax
movabsq $val@GOT, %rdx
addq%r11, %rax
Among of them, ENDBR is needed only when the label address is taken.
rest_of_insert_endbranch has
if ((LABEL_P (insn) && LABEL_PRESERVE_P (insn))
|| (NOTE_P (insn)
&& NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
/* TODO. Check /s bit also. */
{
cet_eb = gen_nop_endbr ();
emit_insn_after (cet_eb, insn);
continue;
}
For NOTE_INSN_DELETED_LABEL, we should check if forced_labels to see
if its address is taken. Also ix86_init_large_pic_reg shouldn't set
LABEL_PRESERVE_P (in_struct) since NOTE_INSN_DELETED_LABEL is suffcient
to keep the label.
gcc/
PR target/89355
* config/i386/i386.c (rest_of_insert_endbranch): Check
forced_labels to see if the address of NOTE_INSN_DELETED_LABEL
is taken.
(ix86_init_large_pic_reg): Don't set LABEL_PRESERVE_P.
gcc/testsuite/
PR target/89355
* gcc.target/i386/cet-label-3.c: New test.
* gcc.target/i386/cet-label-4.c: Likewise.
* gcc.target/i386/cet-label-5.c: Likewise.
---
gcc/config/i386/i386.c | 9 +---
gcc/testsuite/gcc.target/i386/cet-label-3.c | 23 +
gcc/testsuite/gcc.target/i386/cet-label-4.c | 12 +++
gcc/testsuite/gcc.target/i386/cet-label-5.c | 13
4 files changed, 54 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/cet-label-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/cet-label-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/cet-label-5.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index fd05873ba39..ed53fbea9ae 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2734,10 +2734,14 @@ rest_of_insert_endbranch (void)
continue;
}
+ /* NB: Add an ENDBR for NOTE_INSN_DELETED_LABEL only if its
+addresss is taken. */
if ((LABEL_P (insn) && LABEL_PRESERVE_P (insn))
|| (NOTE_P (insn)
- && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
- /* TODO. Check /s bit also. */
+ && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL
+ && vec_safe_contains
+ (forced_labels,
+ static_cast (insn
{
cet_eb = gen_nop_endbr ();
emit_insn_after (cet_eb, insn);
@@ -7002,7 +7006,6 @@ ix86_init_large_pic_reg (unsigned int tmp_regno)
gcc_assert (Pmode == DImode);
label = gen_label_rtx ();
emit_label (label);
- LABEL_PRESERVE_P (label) = 1;
tmp_reg = gen_rtx_REG (Pmode, tmp_regno);
gcc_assert (REGNO (pic_offset_table_rtx) != tmp_regno);
emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx,
diff --git a/gcc/testsuite/gcc.target/i386/cet-label-3.c
b/gcc/testsuite/gcc.target/i386/cet-label-3.c
new file mode 100644
index 000..9f427a866f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cet-label-3.c
@@ -0,0 +1,23 @@
+/* PR target/89355 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fcf-protection" } */
+/* { dg-final { scan-assembler-times "endbr32" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "endbr64" 1 { target { ! ia32 } } } } */
+int
+test (int* val)
+{
+ int status = 99;
+
+ if (!val)
+{
+ status = 22;
+ goto end;
+}
+
+ extern int x;
+ *val = x;
+
+ status = 0;
+end:
+ return status;
+}
diff --git a/gcc/testsuite/gcc.target/i386/cet-label-4.c
b/gcc/testsuite/gcc.target/i386/cet-label-4.c
new file mode 100644
index 000..d743d2bf202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cet-label-4.c
@@ -0,0 +1,12 @@
+/* PR target/89355 */
+/* { dg-do compile { target { fpic && lp64 } } } */
+/* { dg-options "-O2 -fcf-protection -fPIC -mcmodel=large" } */
+/* { dg-final { scan-assembler-times "endbr64" 1 } } */
+
+extern int val;
+
+int
+test (void)
+{
+ return val;
+}
diff --git a/gcc/testsuite/gcc.target/i386/cet-label-5.c
b/gcc/testsuite/gcc.target/i386/cet-label-5.c
new file mode 100644
index 000..4d5ca816598
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cet-label-5.c
@@ -0,0 +1,13
Re: [PATCH] Add testcases for multiple -fsanitize=, -fno-sanitize= or -fno-sanitize-recover= options (take 2)
On Feb 14, 2019, at 6:15 AM, Jakub Jelinek wrote: > Ah, yes, UNRESOLVED doesn't show up visible when running tests by hand, > rather than doing test_summary. Here is an updated patch that adds the > needed dg-skip-if directives. Ok for trunk? Ok.
Re: [PATCH] Fix up and improve allow_blank_lines testsuite handling (PR other/69006, PR testsuite/88920)
On Feb 13, 2019, at 1:09 AM, Jakub Jelinek wrote: > > ok for trunk? Ok.
Re: [PATCH] Fix up and improve allow_blank_lines testsuite handling (PR other/69006, PR testsuite/88920, take 2)
On Feb 13, 2019, at 5:37 AM, Jakub Jelinek wrote: > Here is an updated patch that documents it. Bootstrapped/regtested on > x86_64-linux and i686-linux, ok for trunk? Ok.
Go patch committed: Harmonize types referenced by both C and Go
This patch to the Go frontend and libgo by Nikhil Benesch harmonizes
types referenced by both C and Go. Compiling with LTO revealed a
number of cases in the runtime and standard library where C and Go
disagreed about the type of an object or function (or where Go and
code generated by the compiler disagreed). In all cases the
underlying representation was the same (e.g., uintptr vs.void*), so
this wasn't causing actual problems, but it did result in a number of
annoying warnings when compiling with LTO. Bootstrapped and ran Go
testsuite on x86_64-pc-linux-gnu. Committed to mainline.
Ian
Index: gcc/go/gofrontend/MERGE
===
--- gcc/go/gofrontend/MERGE (revision 268922)
+++ gcc/go/gofrontend/MERGE (working copy)
@@ -1,4 +1,4 @@
-4a6f2bb2c8d3f00966f001a5b03c57cb4a278265
+03e28273a4fcb114f5204d52ed107591404002f4
The first line of this file holds the git revision number of the last
merge done from the gofrontend repository.
Index: gcc/go/gofrontend/expressions.cc
===
--- gcc/go/gofrontend/expressions.cc(revision 268891)
+++ gcc/go/gofrontend/expressions.cc(working copy)
@@ -1344,7 +1344,7 @@ Func_descriptor_expression::make_func_de
if (Func_descriptor_expression::descriptor_type != NULL)
return;
Type* uintptr_type = Type::lookup_integer_type("uintptr");
- Type* struct_type = Type::make_builtin_struct_type(1, "code", uintptr_type);
+ Type* struct_type = Type::make_builtin_struct_type(1, "fn", uintptr_type);
Func_descriptor_expression::descriptor_type =
Type::make_builtin_named_type("functionDescriptor", struct_type);
}
@@ -3874,7 +3874,9 @@ Unsafe_type_conversion_expression::do_ge
|| et->integer_type() != NULL
|| et->is_nil_type());
else if (et->is_unsafe_pointer_type())
-go_assert(t->points_to() != NULL);
+go_assert(t->points_to() != NULL
+ || (t->integer_type() != NULL
+ && t->integer_type() ==
Type::lookup_integer_type("uintptr")->real_type()));
else if (t->interface_type() != NULL)
{
bool empty_iface = t->interface_type()->is_empty();
Index: gcc/go/gofrontend/gogo.cc
===
--- gcc/go/gofrontend/gogo.cc (revision 268891)
+++ gcc/go/gofrontend/gogo.cc (working copy)
@@ -4513,13 +4513,13 @@ Build_recover_thunks::can_recover_arg(Lo
builtin_return_address =
Gogo::declare_builtin_rf_address("__builtin_return_address");
+ Type* uintptr_type = Type::lookup_integer_type("uintptr");
static Named_object* can_recover;
if (can_recover == NULL)
{
const Location bloc = Linemap::predeclared_location();
Typed_identifier_list* param_types = new Typed_identifier_list();
- Type* voidptr_type = Type::make_pointer_type(Type::make_void_type());
- param_types->push_back(Typed_identifier("a", voidptr_type, bloc));
+ param_types->push_back(Typed_identifier("a", uintptr_type, bloc));
Type* boolean_type = Type::lookup_bool_type();
Typed_identifier_list* results = new Typed_identifier_list();
results->push_back(Typed_identifier("", boolean_type, bloc));
@@ -4539,6 +4539,7 @@ Build_recover_thunks::can_recover_arg(Lo
args->push_back(zexpr);
Expression* call = Expression::make_call(fn, args, false, location);
+ call = Expression::make_unsafe_cast(uintptr_type, call, location);
args = new Expression_list();
args->push_back(call);
Index: gcc/go/gofrontend/runtime.cc
===
--- gcc/go/gofrontend/runtime.cc(revision 268369)
+++ gcc/go/gofrontend/runtime.cc(working copy)
@@ -60,8 +60,6 @@ enum Runtime_function_type
RFT_IFACE,
// Go type interface{}, C type struct __go_empty_interface.
RFT_EFACE,
- // Go type func(unsafe.Pointer), C type void (*) (void *).
- RFT_FUNC_PTR,
// Pointer to Go type descriptor.
RFT_TYPE,
// [2]string.
@@ -176,15 +174,6 @@ runtime_function_type(Runtime_function_t
t = Type::make_empty_interface_type(bloc);
break;
- case RFT_FUNC_PTR:
- {
- Typed_identifier_list* param_types = new Typed_identifier_list();
- Type* ptrtype = runtime_function_type(RFT_POINTER);
- param_types->push_back(Typed_identifier("", ptrtype, bloc));
- t = Type::make_function_type(NULL, param_types, NULL, bloc);
- }
- break;
-
case RFT_TYPE:
t = Type::make_type_descriptor_ptr_type();
break;
@@ -265,7 +254,6 @@ convert_to_runtime_function_type(Runtime
case RFT_COMPLEX128:
case RFT_STRING:
case RFT_POINTER:
-case RFT_FUNC_PTR:
{
Type* t = runtime_function_type(bft);
if (!Type::are_identical(t, e->type(), true, NULL))
Index: gcc/go/gofrontend/runtime.def
Re: [C PATCH] Reject weak nested functions (PR c/89340)
On Fri, 15 Feb 2019, Jakub Jelinek wrote:
> Hi!
>
> We ICE on the following testcase, because C nested functions are turned into
> !TREE_PUBLIC ones very soon, and the IPA code asserts that DECL_WEAK
> functions
> are either TREE_PUBLIC or DECL_EXTERNAL.
> As we reject static __attribute__((weak)) void foo () {}, I think we should
> reject weak nested functions, they don't make much sense either, they are
> TU local too.
>
> The following patch fixes that. The other effect of the patch is that leaf
> attribute is warned and ignored on the nested function, but similarly, we
> ignore and warn for leaf attribute on other TU local functions, we see the
> nested function body and can analyze everything in it.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
OK.
--
Joseph S. Myers
jos...@codesourcery.com
Re: [PATCH] Fix ICE with optimize("Ofast") due to option handling (PR other/89342)
On Thu, 14 Feb 2019, Jakub Jelinek wrote:
> Hi!
>
> We ICE on the following testcase, because while we save optimize,
> and optimize_{size,debug} vars during option saving/restoring, we don't save
> optimize_fast, and because of that end up with optimize 0 optimize_fast 1
> which the option handling code ICEs on -
> if (fast)
> gcc_assert (level == 3);
> in maybe_default_option. Fixed thusly, just treat optimize_fast like
> the other flags, bootstrapped/regtested on x86_64-linux and i686-linux, ok
> for trunk/8.3?
OK.
--
Joseph S. Myers
jos...@codesourcery.com
libgo patch committed: Run examples
This patch to the libgo gotest script runs examples when appropriate
in the libgo testsuite. An example with a "// Output:" comment is
supposed to be run, comparing the output of the example with the text
in the comment. Up until now we were not actually doing that, so we
were in effect skipping some tests. This changes that. The changes
to the script are not fully general for all Go code, but should be
sufficient for the code that actually appears in libgo. One example
had to be tweaked to match the output generated by gccgo.
This patch also cleans up some cruft in gotest, and should fix GCC PR 89168.
Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
to mainline.
Ian
Index: gcc/go/gofrontend/MERGE
===
--- gcc/go/gofrontend/MERGE (revision 268904)
+++ gcc/go/gofrontend/MERGE (working copy)
@@ -1,4 +1,4 @@
-c2fc3b83d832725accd4fa5874a5b5ca02dd90dc
+4a6f2bb2c8d3f00966f001a5b03c57cb4a278265
The first line of this file holds the git revision number of the last
merge done from the gofrontend repository.
Index: libgo/go/runtime/example_test.go
===
--- libgo/go/runtime/example_test.go(revision 268369)
+++ libgo/go/runtime/example_test.go(working copy)
@@ -31,7 +31,7 @@ func ExampleFrames() {
// To keep this example's output stable
// even if there are changes in the testing package,
// stop unwinding when we leave package runtime.
- if !strings.Contains(frame.File, "runtime/") {
+ if !strings.Contains(frame.File, "runtime/") &&
!strings.Contains(frame.File, "/test/") {
break
}
fmt.Printf("- more:%v | %s\n", more, frame.Function)
@@ -47,8 +47,8 @@ func ExampleFrames() {
a()
// Output:
// - more:true | runtime.Callers
- // - more:true | runtime_test.ExampleFrames.func1
- // - more:true | runtime_test.ExampleFrames.func2
- // - more:true | runtime_test.ExampleFrames.func3
+ // - more:true | runtime_test.ExampleFrames..func1
+ // - more:true | runtime_test.ExampleFrames..func2
+ // - more:true | runtime_test.ExampleFrames..func3
// - more:true | runtime_test.ExampleFrames
}
Index: libgo/testsuite/gotest
===
--- libgo/testsuite/gotest (revision 268369)
+++ libgo/testsuite/gotest (working copy)
@@ -289,12 +289,6 @@ x)
;;
esac
-# Some tests expect the _obj directory created by the gc Makefiles.
-mkdir _obj
-
-# Some tests expect the _test directory created by the gc Makefiles.
-mkdir _test
-
case "x$gofiles" in
x)
for f in `ls *_test.go`; do
@@ -404,14 +398,6 @@ x)
;;
esac
-# Run any commands given in sources, like
-# // gotest: $GC foo.go
-# to build any test-only dependencies.
-holdGC="$GC"
-GC="$GC -g -c -I ."
-sed -n 's/^\/\/ gotest: //p' $gofiles | sh
-GC="$holdGC"
-
case "x$pkgfiles" in
x)
pkgbasefiles=`ls *.go | grep -v _test.go 2>/dev/null`
@@ -514,26 +500,29 @@ localname() {
#
symtogo() {
result=""
- for tp in $*
- do
+ for tp in $*; do
s=$(echo "$tp" | sed -e 's/\.\.z2f/%/g' | sed -e 's/.*%//')
-# screen out methods (X.Y.Z)
+# Screen out methods (X.Y.Z).
if ! expr "$s" : '^[^.]*\.[^.]*$' >/dev/null 2>&1; then
continue
fi
-echo "$s"
+tname=$(testname $s)
+# Skip TestMain.
+if test x$tname = xTestMain; then
+ continue
+fi
+# Check that the function is defined in a test file,
+# not an ordinary non-test file.
+if grep "^func $tname(" $gofiles $xgofiles >/dev/null 2>&1; then
+ echo "$s"
+fi
done
}
{
- text="T"
-
# On systems using PPC64 ELF ABI v1 function symbols show up
- # as descriptors in the data section. We assume that $goarch
- # distinguishes v1 (ppc64) from v2 (ppc64le).
- if test "$goos" != "aix" && test "$goarch" = "ppc64"; then
- text="[TD]"
- fi
+ # as descriptors in the data section.
+ text="[TD]"
# test functions are named TestFoo
# the grep -v eliminates methods and other special names
@@ -575,13 +564,10 @@ symtogo() {
# test array
echo
echo 'var tests = []testing.InternalTest {'
- for i in $tests
- do
+ for i in $tests; do
n=$(testname $i)
- if test "$n" != "TestMain"; then
- j=$(localname $i)
- echo ' {"'$n'", '$j'},'
- fi
+ j=$(localname $i)
+ echo ' {"'$n'", '$j'},'
done
echo '}'
@@ -589,8 +575,7 @@ symtogo() {
# The comment makes the multiline declaration
# gofmt-safe even when there
Re: Go patch committed: Compile thunks with -Os
On Wed, Feb 13, 2019 at 5:21 PM Ian Lance Taylor wrote:
>
> Nikhil Benesch noticed that changes in the GCC backend were making the
> use of defer functions that call recover less efficient. A defer
> thunk is a generated function that looks like this (this is the entire
> function body):
>
> if !runtime.setdeferretaddr() {
> deferredFunction()
> }
> L:
>
> The idea is that the address of the label passed to setdeferretaddr is
> the address to which deferredFunction returns. The code in canrecover
> compares the return address of the function to this saved address to
> see whether the recover function can return non-nil. This is
> explained in marginally more detail at
> https://www.airs.com/blog/archives/376 .
>
> When the return address does not match, the canrecover code does a
> more costly check that requires unwinding the stack. What Nikhil
> Benesch noticed is that we were always taking that fallback.
>
> It turned out that the label address passed to setdeferretaddr was not
> the label to which the deferred function would return. And that was
> because the epilogue was being duplicated by the bb-reorder pass, and
> the label was moved to one copy of the epilogue while the deferred
> function returned to the other epilogue.
>
> Of course there is no reason to duplicate the epilogue in such a small
> function. One easy way to disable that epilogue duplication is to
> compile the function with -Os. That is what this patch does. This
> patch compiles all thunks, not just defer thunks, with -Os, but since
> they are all small that does no harm.
>
> Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
> to mainline.
>
> Ian
>
> 2019-02-13 Ian Lance Taylor
>
> * go-gcc.cc: #include "opts.h".
> (Gcc_backend::function): Compile thunks with -Os.
This change revealed that changing function optimization attributes
can cause the compiler to switch to the options stored in
optimization_default_node. That caused the change to
flag_strict_aliasing in go_imported_unsafe to be lost. I fixed that
with this patch, which simply updates optimization_default_node. I
don't know if there is a better way to do this. For this patch
bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
to mainline.
Ian
2019-02-14 Ian Lance Taylor
* go-backend.c (go_imported_unsafe): Update
optimization_default_node.
Index: go-backend.c
===
--- go-backend.c(revision 268917)
+++ go-backend.c(working copy)
@@ -89,6 +89,7 @@ void
go_imported_unsafe (void)
{
flag_strict_aliasing = false;
+ TREE_OPTIMIZATION (optimization_default_node)->x_flag_strict_aliasing =
false;
/* Let the backend know that the options have changed. */
targetm.override_options_after_change ();
[PATCH wwwdocs] changes.html for "asm inline"
Hi! I did the following patch for the GCC 8 changes.html (in the 8.3 section): Index: htdocs/gcc-8/changes.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-8/changes.html,v retrieving revision 1.98 diff -u -r1.98 changes.html --- htdocs/gcc-8/changes.html 29 Dec 2018 21:09:09 - 1.98 +++ htdocs/gcc-8/changes.html 14 Feb 2019 23:39:34 - @@ -1354,6 +1354,14 @@ GCC 8.3 is not yet released. +C family + + + Support has been added for asm inline. An asm + that is inline is counted as minimum length for inlining + decisions, irrespective of how big it looks otherwise. + + Windows Is that okay? Also okay for GCC 7.5? And for GCC 9? Segher
[PATCH, i386]: Enable MMX, SSE and SSE2 by default in TARGET_SUBTARGET64_ISA_DEFAULT
No functional changes.
2019-02-15 Uroš Bizjak
* config/i386/i386.h (TARGET_SUBTARGET64_ISA_DEFAULT):
Enable MMX, SSE and SSE2 by default.
* config/i386/i386.c (ix86_option_override_internal): Do not
explicitly set MMX, SSE and SSE2 flags for TARGET_64BIT here.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
Index: config/i386/i386.c
===
--- config/i386/i386.c (revision 268907)
+++ config/i386/i386.c (working copy)
@@ -4165,14 +4165,9 @@ ix86_option_override_internal (bool main_args_p,
opts->x_target_flags
|= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
- /* Enable by default the SSE and MMX builtins. Do allow the user to
-explicitly disable any of these. In particular, disabling SSE and
-MMX for kernel code is extremely useful. */
if (!ix86_arch_specified)
- opts->x_ix86_isa_flags
- |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
-| TARGET_SUBTARGET64_ISA_DEFAULT)
-& ~opts->x_ix86_isa_flags_explicit);
+ opts->x_ix86_isa_flags
+ |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;
if (TARGET_RTD_P (opts->x_target_flags))
warning (0,
Index: config/i386/i386.h
===
--- config/i386/i386.h (revision 268907)
+++ config/i386/i386.h (working copy)
@@ -633,7 +633,9 @@ extern tree x86_mfence;
/* Extra bits to force on w/ 64-bit mode. */
#define TARGET_SUBTARGET64_DEFAULT 0
-#define TARGET_SUBTARGET64_ISA_DEFAULT 0
+/* Enable MMX, SSE and SSE2 by default. */
+#define TARGET_SUBTARGET64_ISA_DEFAULT \
+ (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2)
/* Replace MACH-O, ifdefs by in-line tests, where possible.
(a) Macros defined in config/i386/darwin.h */
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 3:21 PM Uros Bizjak wrote:
>
> On Fri, Feb 15, 2019 at 12:14 AM H.J. Lu wrote:
>
> > > > > > > > > gcc/
> > > > > > > > >
> > > > > > > > > PR target/89021
> > > > > > > > > * config/i386/i386-builtin.def: Enable MMX intrinsics
> > > > > > > > > with
> > > > > > > > > SSE/SSE2/SSSE3.
> > > > > > > > > * config/i386/i386.c (ix86_option_override_internal):
> > > > > > > > > Don't
> > > > > > > > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > > > > > > > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics
> > > > > > > > > with
> > > > > > > > > SSE/SSE2/SSSE3.
> > > > > > > > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to
> > > > > > > > > emulate MMX
> > > > > > > > > intrinsics with TARGET_MMX_WITH_SSE.
> > > > > > > > > * config/i386/mmintrin.h: Don't require MMX in 64-bit
> > > > > > > > > mode.
> > > > > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > > > > > > > index a9abbe8706b..1d417e08734 100644
> > > > > > > > > --- a/gcc/config/i386/i386.c
> > > > > > > > > +++ b/gcc/config/i386/i386.c
> > > > > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool
> > > > > > > > > main_args_p,
> > > > > > > > >opts->x_target_flags
> > > > > > > > > |= TARGET_SUBTARGET64_DEFAULT &
> > > > > > > > > ~opts_set->x_target_flags;
> > > > > > > > >
> > > > > > > > > - /* Enable by default the SSE and MMX builtins. Do
> > > > > > > > > allow the user to
> > > > > > > > > -explicitly disable any of these. In particular,
> > > > > > > > > disabling SSE and
> > > > > > > > > -MMX for kernel code is extremely useful. */
> > > > > > > > > + /* Enable the SSE and MMX builtins by default. Don't
> > > > > > > > > enable MMX
> > > > > > > > > + ISA with TARGET_MMX_WITH_SSE by default. Do allow
> > > > > > > > > the user to
> > > > > > > > > +explicitly disable any of these. In particular,
> > > > > > > > > disabling SSE
> > > > > > > > > +and MMX for kernel code is extremely useful. */
> > > > > > > > >if (!ix86_arch_specified)
> > > > > > > > >opts->x_ix86_isa_flags
> > > > > > > > > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > > > > > > > > OPTION_MASK_ISA_MMX
> > > > > > > > > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > > > > > > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > > > > > > + ? 0 : OPTION_MASK_ISA_MMX)
> > > > > > > > > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > > > > > > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > > > > >
> > > > > > > > Please split the above into two clauses, the first that sets
> > > > > > > > SSE and
> > > > > > > > MMX by default, and the second to or with
> > > > > > > >
> > > > > > > > opts->x_ix86_isa_flags
> > > > > > > > |= TARGET_SUBTARGET64_ISA_DEFAULT &
> > > > > > > > ~opts->x_ix86_isa_flags_explicit
> > > > > > > >
> > > > > > >
> > > > > > > Like this?
> > > > > >
> > > > > > Yes, but also split the comment.
> > > > >
> > > > > I will go with
> > > > >
> > > > > /* Enable by default the SSE and MMX builtins. Do allow the
> > > > > user to
> > > > > explicitly disable any of these. In particular, disabling
> > > > > SSE and
> > > > > MMX for kernel code is extremely useful. */
> > > > > if (!ix86_arch_specified)
> > > > > {
> > > > > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > > > > opts->x_ix86_isa_flags
> > > > > |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > > | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > > ? 0 : OPTION_MASK_ISA_MMX))
> > > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > > opts->x_ix86_isa_flags
> > > > > |= (TARGET_SUBTARGET64_ISA_DEFAULT
> > > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > > }
> > > >
> > > > I'll commit the following patch that finally defines
> > > > TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX
> > > > bit from x_i86_isa_flags, like:
> > > >
> > > > if (!ix86_arch_specified)
> > > > opts->x_ix86_isa_flags
> > > > |= TARGET_SUBTARGET64_ISA_DEFAULT &
> > > > ~opts->x_ix86_isa_flags_explicit;
> > > >
> > > > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > > > if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
> > > > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
> > >
> > > I think it should be:
> > >
> > > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > > if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)
> > I meant opts->x_ix86_isa_flags_explicit.
> > > && TARGET_MMX_WITH_SSE_P
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Fri, Feb 15, 2019 at 12:14 AM H.J. Lu wrote:
> > > > > > > > gcc/
> > > > > > > >
> > > > > > > > PR target/89021
> > > > > > > > * config/i386/i386-builtin.def: Enable MMX intrinsics
> > > > > > > > with
> > > > > > > > SSE/SSE2/SSSE3.
> > > > > > > > * config/i386/i386.c (ix86_option_override_internal):
> > > > > > > > Don't
> > > > > > > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > > > > > > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
> > > > > > > > SSE/SSE2/SSSE3.
> > > > > > > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate
> > > > > > > > MMX
> > > > > > > > intrinsics with TARGET_MMX_WITH_SSE.
> > > > > > > > * config/i386/mmintrin.h: Don't require MMX in 64-bit
> > > > > > > > mode.
> > > > > > > >
> > > > > >
> > > > > > >
> > > > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > > > > > > index a9abbe8706b..1d417e08734 100644
> > > > > > > > --- a/gcc/config/i386/i386.c
> > > > > > > > +++ b/gcc/config/i386/i386.c
> > > > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool
> > > > > > > > main_args_p,
> > > > > > > >opts->x_target_flags
> > > > > > > > |= TARGET_SUBTARGET64_DEFAULT &
> > > > > > > > ~opts_set->x_target_flags;
> > > > > > > >
> > > > > > > > - /* Enable by default the SSE and MMX builtins. Do allow
> > > > > > > > the user to
> > > > > > > > -explicitly disable any of these. In particular,
> > > > > > > > disabling SSE and
> > > > > > > > -MMX for kernel code is extremely useful. */
> > > > > > > > + /* Enable the SSE and MMX builtins by default. Don't
> > > > > > > > enable MMX
> > > > > > > > + ISA with TARGET_MMX_WITH_SSE by default. Do allow
> > > > > > > > the user to
> > > > > > > > +explicitly disable any of these. In particular,
> > > > > > > > disabling SSE
> > > > > > > > +and MMX for kernel code is extremely useful. */
> > > > > > > >if (!ix86_arch_specified)
> > > > > > > >opts->x_ix86_isa_flags
> > > > > > > > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > > > > > > > OPTION_MASK_ISA_MMX
> > > > > > > > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > > > > > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > > > > > + ? 0 : OPTION_MASK_ISA_MMX)
> > > > > > > > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > > > > > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > > > >
> > > > > > > Please split the above into two clauses, the first that sets SSE
> > > > > > > and
> > > > > > > MMX by default, and the second to or with
> > > > > > >
> > > > > > > opts->x_ix86_isa_flags
> > > > > > > |= TARGET_SUBTARGET64_ISA_DEFAULT &
> > > > > > > ~opts->x_ix86_isa_flags_explicit
> > > > > > >
> > > > > >
> > > > > > Like this?
> > > > >
> > > > > Yes, but also split the comment.
> > > >
> > > > I will go with
> > > >
> > > > /* Enable by default the SSE and MMX builtins. Do allow the user
> > > > to
> > > > explicitly disable any of these. In particular, disabling SSE
> > > > and
> > > > MMX for kernel code is extremely useful. */
> > > > if (!ix86_arch_specified)
> > > > {
> > > > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > > > opts->x_ix86_isa_flags
> > > > |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > ? 0 : OPTION_MASK_ISA_MMX))
> > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > opts->x_ix86_isa_flags
> > > > |= (TARGET_SUBTARGET64_ISA_DEFAULT
> > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > }
> > >
> > > I'll commit the following patch that finally defines
> > > TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX
> > > bit from x_i86_isa_flags, like:
> > >
> > > if (!ix86_arch_specified)
> > > opts->x_ix86_isa_flags
> > > |= TARGET_SUBTARGET64_ISA_DEFAULT &
> > > ~opts->x_ix86_isa_flags_explicit;
> > >
> > > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > > if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
> > > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
> >
> > I think it should be:
> >
> > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)
> I meant opts->x_ix86_isa_flags_explicit.
> > && TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
> > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
Well ... I didn't test this part. OTOH, maybe this part is not needed,
MMX disabling can go *after*
/* Turn on MMX builtins for -msse. */
if (TARGET_SSE_P (opts->x_ix86_isa_flags))
[committed] Fix combiner's make_extraction (PR rtl-optimization/89354)
Hi!
The following testcase is miscompiled on i686-linux, because
make_extraction is asked to make an extraction of 33 bits from DImode MEM
at position 0 and happily returns ZERO_EXTRACT with SImode (even when SImode
can hold only 32 bits), the caller (make_field_assignment) then on this
testcase because of that throws away the |= 0x1ULL.
Fixed thusly, bootstrapped/regtested on {x86_64,i686,powerpc64{,le}}-linux,
preapproved by Segher on IRC, committed to trunk and 8.x branch.
I've also gathered statistics and the only time during those bootstraps and
(except for still pending (second) powerpc64-linux regtest) regtests the
only time this patch made any difference was on this newly added testcase on
i686-linux.
2019-02-14 Jakub Jelinek
PR rtl-optimization/89354
* combine.c (make_extraction): Punt if extraction_mode is narrower
than len bits.
* gcc.dg/pr89354.c: New test.
--- gcc/combine.c.jj2019-02-05 16:38:28.0 +0100
+++ gcc/combine.c 2019-02-14 16:45:41.445096523 +0100
@@ -7830,6 +7830,10 @@ make_extraction (machine_mode mode, rtx
&& partial_subreg_p (extraction_mode, mode))
extraction_mode = mode;
+ /* Punt if len is too large for extraction_mode. */
+ if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
+return NULL_RTX;
+
if (!MEM_P (inner))
wanted_inner_mode = wanted_inner_reg_mode;
else
--- gcc/testsuite/gcc.dg/pr89354.c.jj 2019-02-14 17:02:26.013552853 +0100
+++ gcc/testsuite/gcc.dg/pr89354.c 2019-02-14 17:01:44.431237813 +0100
@@ -0,0 +1,22 @@
+/* PR rtl-optimization/89354 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* { dg-additional-options "-msse2" { target sse2_runtime } } */
+
+static unsigned long long q = 0;
+
+__attribute__((noipa)) static void
+foo (void)
+{
+ q = (q & ~0x1ULL) | 0x1ULL;
+}
+
+int
+main ()
+{
+ __asm volatile ("" : "+m" (q));
+ foo ();
+ if (q != 0x1ULL)
+__builtin_abort ();
+ return 0;
+}
Jakub
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 3:12 PM H.J. Lu wrote:
>
> On Thu, Feb 14, 2019 at 2:57 PM Uros Bizjak wrote:
> >
> > On Thu, Feb 14, 2019 at 10:02 PM H.J. Lu wrote:
> >
> > > > > > > gcc/
> > > > > > >
> > > > > > > PR target/89021
> > > > > > > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > > > > > > SSE/SSE2/SSSE3.
> > > > > > > * config/i386/i386.c (ix86_option_override_internal):
> > > > > > > Don't
> > > > > > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > > > > > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
> > > > > > > SSE/SSE2/SSSE3.
> > > > > > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > > > > > > intrinsics with TARGET_MMX_WITH_SSE.
> > > > > > > * config/i386/mmintrin.h: Don't require MMX in 64-bit
> > > > > > > mode.
> > > > > > >
> > > > >
> > > > > >
> > > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > > > > > index a9abbe8706b..1d417e08734 100644
> > > > > > > --- a/gcc/config/i386/i386.c
> > > > > > > +++ b/gcc/config/i386/i386.c
> > > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool
> > > > > > > main_args_p,
> > > > > > >opts->x_target_flags
> > > > > > > |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
> > > > > > >
> > > > > > > - /* Enable by default the SSE and MMX builtins. Do allow
> > > > > > > the user to
> > > > > > > -explicitly disable any of these. In particular,
> > > > > > > disabling SSE and
> > > > > > > -MMX for kernel code is extremely useful. */
> > > > > > > + /* Enable the SSE and MMX builtins by default. Don't
> > > > > > > enable MMX
> > > > > > > + ISA with TARGET_MMX_WITH_SSE by default. Do allow the
> > > > > > > user to
> > > > > > > +explicitly disable any of these. In particular,
> > > > > > > disabling SSE
> > > > > > > +and MMX for kernel code is extremely useful. */
> > > > > > >if (!ix86_arch_specified)
> > > > > > >opts->x_ix86_isa_flags
> > > > > > > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > > > > > > OPTION_MASK_ISA_MMX
> > > > > > > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > > > > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > > > > + ? 0 : OPTION_MASK_ISA_MMX)
> > > > > > > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > > > > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > > >
> > > > > > Please split the above into two clauses, the first that sets SSE and
> > > > > > MMX by default, and the second to or with
> > > > > >
> > > > > > opts->x_ix86_isa_flags
> > > > > > |= TARGET_SUBTARGET64_ISA_DEFAULT &
> > > > > > ~opts->x_ix86_isa_flags_explicit
> > > > > >
> > > > >
> > > > > Like this?
> > > >
> > > > Yes, but also split the comment.
> > >
> > > I will go with
> > >
> > > /* Enable by default the SSE and MMX builtins. Do allow the user to
> > > explicitly disable any of these. In particular, disabling SSE
> > > and
> > > MMX for kernel code is extremely useful. */
> > > if (!ix86_arch_specified)
> > > {
> > > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > > opts->x_ix86_isa_flags
> > > |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > ? 0 : OPTION_MASK_ISA_MMX))
> > > & ~opts->x_ix86_isa_flags_explicit);
> > > opts->x_ix86_isa_flags
> > > |= (TARGET_SUBTARGET64_ISA_DEFAULT
> > > & ~opts->x_ix86_isa_flags_explicit);
> > > }
> >
> > I'll commit the following patch that finally defines
> > TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX
> > bit from x_i86_isa_flags, like:
> >
> > if (!ix86_arch_specified)
> > opts->x_ix86_isa_flags
> > |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;
> >
> > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
> > opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
>
> I think it should be:
>
> /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)
I meant opts->x_ix86_isa_flags_explicit.
> && TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
>
> Thanks.
>
> --
> H.J.
--
H.J.
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 2:57 PM Uros Bizjak wrote:
>
> On Thu, Feb 14, 2019 at 10:02 PM H.J. Lu wrote:
>
> > > > > > gcc/
> > > > > >
> > > > > > PR target/89021
> > > > > > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > > > > > SSE/SSE2/SSSE3.
> > > > > > * config/i386/i386.c (ix86_option_override_internal): Don't
> > > > > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > > > > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
> > > > > > SSE/SSE2/SSSE3.
> > > > > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > > > > > intrinsics with TARGET_MMX_WITH_SSE.
> > > > > > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
> > > > > >
> > > >
> > > > >
> > > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > > > > index a9abbe8706b..1d417e08734 100644
> > > > > > --- a/gcc/config/i386/i386.c
> > > > > > +++ b/gcc/config/i386/i386.c
> > > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool
> > > > > > main_args_p,
> > > > > >opts->x_target_flags
> > > > > > |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
> > > > > >
> > > > > > - /* Enable by default the SSE and MMX builtins. Do allow the
> > > > > > user to
> > > > > > -explicitly disable any of these. In particular, disabling
> > > > > > SSE and
> > > > > > -MMX for kernel code is extremely useful. */
> > > > > > + /* Enable the SSE and MMX builtins by default. Don't enable
> > > > > > MMX
> > > > > > + ISA with TARGET_MMX_WITH_SSE by default. Do allow the
> > > > > > user to
> > > > > > +explicitly disable any of these. In particular, disabling
> > > > > > SSE
> > > > > > +and MMX for kernel code is extremely useful. */
> > > > > >if (!ix86_arch_specified)
> > > > > >opts->x_ix86_isa_flags
> > > > > > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > > > > > OPTION_MASK_ISA_MMX
> > > > > > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > > > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > > > + ? 0 : OPTION_MASK_ISA_MMX)
> > > > > > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > > > > > & ~opts->x_ix86_isa_flags_explicit);
> > > > >
> > > > > Please split the above into two clauses, the first that sets SSE and
> > > > > MMX by default, and the second to or with
> > > > >
> > > > > opts->x_ix86_isa_flags
> > > > > |= TARGET_SUBTARGET64_ISA_DEFAULT &
> > > > > ~opts->x_ix86_isa_flags_explicit
> > > > >
> > > >
> > > > Like this?
> > >
> > > Yes, but also split the comment.
> >
> > I will go with
> >
> > /* Enable by default the SSE and MMX builtins. Do allow the user to
> > explicitly disable any of these. In particular, disabling SSE and
> > MMX for kernel code is extremely useful. */
> > if (!ix86_arch_specified)
> > {
> > /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> > opts->x_ix86_isa_flags
> > |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > ? 0 : OPTION_MASK_ISA_MMX))
> > & ~opts->x_ix86_isa_flags_explicit);
> > opts->x_ix86_isa_flags
> > |= (TARGET_SUBTARGET64_ISA_DEFAULT
> > & ~opts->x_ix86_isa_flags_explicit);
> > }
>
> I'll commit the following patch that finally defines
> TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX
> bit from x_i86_isa_flags, like:
>
> if (!ix86_arch_specified)
> opts->x_ix86_isa_flags
> |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;
>
> /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
I think it should be:
/* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
if (!(opts->x_ix86_isa_flags & OPTION_MASK_ISA_MMX)
&& TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
Thanks.
--
H.J.
Re: [PATCH][DOC] Document new features for GCC 9.
On 2/14/19 3:37 PM, David Malcolm wrote: On Thu, 2019-02-14 at 14:19 -0700, Martin Sebor wrote: On 2/13/19 6:48 AM, Martin Liška wrote: Hi. I'm sending patch where I document changes I made during GCC 9 development. I would appreciate both language and factical comments about the patch. Nothing technical, just a few very minor language nits/suggestions. Martin diff --git a/htdocs/gcc-9/changes.html b/htdocs/gcc-9/changes.html index 13243c2..9fec9e2 100644 --- a/htdocs/gcc-9/changes.html +++ b/htdocs/gcc-9/changes.html @@ -50,11 +50,64 @@ a work-in-progress. General Improvements -A new option -flive-patching=[inline-only-static|inline-clone] is +A new option -flive-patching=[inline-only-static|inline-clone] is s/is/has been/ would be better (and either a comma after option or a definite article without the comma). introduced to provide a safe compilation for live-patching. At the same time, provides multiple-level control on the enabled IPA optimizations. See the user guide for further information about the option for more -details. +details. Ideally we should add URLs any time we mention an option, linking to the docs for that option. texinfo's HTML toolchain does give us per- option anchors. They're not visible [1], but "View Source" shows us that they do exist; in the form: https://gcc.gnu.org/onlinedocs/gcc/SOMETHING.html#indexOPTION though annoyingly the SOMETHING varies depending on what kind of option it is. The pertinent one here is: https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#index-flive-patching (FWIW, I have a patch for GCC 10 that emits terminal sequences to "linkify" the output when diagnostics mention option names, adding a URL to the docs for the pertinent option). That sounds awesome! Martin [...snip...] Dave [1] I've emailed the texinfo project about this
Re: [C++ PATCH] preview: Fix braces around scalar initializer (C++/88572) Inbox x
On 2/12/19 6:04 PM, will wray wrote:
A proposed patch for Bug 88572 is attached to the bug report along
with a short description and Change Log (a link there gives a pretty
diff of the patch):
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88572#c15
I'd appreciate any review of this patch, as well as testing on more
platforms. The patch with updated tests passes for me on x86_64.
There's also test code in bug comment #1 that demonstrates SFINAE
based on the nesting of braces. It could also be added to the
testsuite - I'm not sure how to do that or if it is needed.
+ if (cxx_dialect < cxx11 || first_initializer_p)
I would expect this to miss the error in
struct A { int i; } a = {{{42}}};
I see that we end up complaining about this in convert_like_real because
implicit_conversion catches the problem here, but I think we ought to
catch it in reshape_init_r as well. So, also complain if the element of
the CONSTRUCTOR is also BRACE_ENCLOSED_INITIALIZER_P.
Jason
[C PATCH] Reject weak nested functions (PR c/89340)
Hi!
We ICE on the following testcase, because C nested functions are turned into
!TREE_PUBLIC ones very soon, and the IPA code asserts that DECL_WEAK functions
are either TREE_PUBLIC or DECL_EXTERNAL.
As we reject static __attribute__((weak)) void foo () {}, I think we should
reject weak nested functions, they don't make much sense either, they are
TU local too.
The following patch fixes that. The other effect of the patch is that leaf
attribute is warned and ignored on the nested function, but similarly, we
ignore and warn for leaf attribute on other TU local functions, we see the
nested function body and can analyze everything in it.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2019-02-14 Jakub Jelinek
PR c/89340
* c-decl.c (start_function): Clear TREE_PUBLIC on nested functions
before c_decl_attributes rather than after it.
* gcc.dg/pr89340.c: New test.
* gcc.dg/torture/pr57036-2.c (jpgDecode_convert): Expect a warning
that leaf attribute on nested function is useless.
--- gcc/c/c-decl.c.jj 2019-02-06 09:53:49.0 +0100
+++ gcc/c/c-decl.c 2019-02-14 14:03:23.630109817 +0100
@@ -8904,6 +8904,10 @@ start_function (struct c_declspecs *decl
loc = DECL_SOURCE_LOCATION (decl1);
+ /* A nested function is not global. */
+ if (current_function_decl != NULL_TREE)
+TREE_PUBLIC (decl1) = 0;
+
c_decl_attributes (, attributes, 0);
if (DECL_DECLARED_INLINE_P (decl1)
@@ -8945,10 +8949,6 @@ start_function (struct c_declspecs *decl
error_mark_node is replaced below (in pop_scope) with the BLOCK. */
DECL_INITIAL (decl1) = error_mark_node;
- /* A nested function is not global. */
- if (current_function_decl != NULL_TREE)
-TREE_PUBLIC (decl1) = 0;
-
/* If this definition isn't a prototype and we had a prototype declaration
before, copy the arg type info from that prototype. */
old_decl = lookup_name_in_scope (DECL_NAME (decl1), current_scope);
--- gcc/testsuite/gcc.dg/pr89340.c.jj 2019-02-14 14:16:35.998034363 +0100
+++ gcc/testsuite/gcc.dg/pr89340.c 2019-02-14 14:10:31.936033775 +0100
@@ -0,0 +1,9 @@
+/* PR c/89340 */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+void bar (void)
+{
+ __attribute__((weak)) void foo () {} /* { dg-error "weak declaration of
'foo' must be public" } */
+ foo ();
+}
--- gcc/testsuite/gcc.dg/torture/pr57036-2.c.jj 2014-11-11 00:06:07.247079690
+0100
+++ gcc/testsuite/gcc.dg/torture/pr57036-2.c2019-02-14 22:04:04.936850407
+0100
@@ -9,7 +9,7 @@ int jpgDecode_convert (unsigned i)
int j;
inline void __attribute__((always_inline,leaf)) f(void)
-{
+{ /* { dg-warning "'leaf' attribute has no effect" } */
g();
}
Jakub
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 10:02 PM H.J. Lu wrote:
> > > > > gcc/
> > > > >
> > > > > PR target/89021
> > > > > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > > > > SSE/SSE2/SSSE3.
> > > > > * config/i386/i386.c (ix86_option_override_internal): Don't
> > > > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > > > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
> > > > > SSE/SSE2/SSSE3.
> > > > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > > > > intrinsics with TARGET_MMX_WITH_SSE.
> > > > > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
> > > > >
> > >
> > > >
> > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > > > index a9abbe8706b..1d417e08734 100644
> > > > > --- a/gcc/config/i386/i386.c
> > > > > +++ b/gcc/config/i386/i386.c
> > > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool
> > > > > main_args_p,
> > > > >opts->x_target_flags
> > > > > |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
> > > > >
> > > > > - /* Enable by default the SSE and MMX builtins. Do allow the
> > > > > user to
> > > > > -explicitly disable any of these. In particular, disabling
> > > > > SSE and
> > > > > -MMX for kernel code is extremely useful. */
> > > > > + /* Enable the SSE and MMX builtins by default. Don't enable
> > > > > MMX
> > > > > + ISA with TARGET_MMX_WITH_SSE by default. Do allow the user
> > > > > to
> > > > > +explicitly disable any of these. In particular, disabling
> > > > > SSE
> > > > > +and MMX for kernel code is extremely useful. */
> > > > >if (!ix86_arch_specified)
> > > > >opts->x_ix86_isa_flags
> > > > > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > > > > OPTION_MASK_ISA_MMX
> > > > > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > > + ? 0 : OPTION_MASK_ISA_MMX)
> > > > > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > > > > & ~opts->x_ix86_isa_flags_explicit);
> > > >
> > > > Please split the above into two clauses, the first that sets SSE and
> > > > MMX by default, and the second to or with
> > > >
> > > > opts->x_ix86_isa_flags
> > > > |= TARGET_SUBTARGET64_ISA_DEFAULT &
> > > > ~opts->x_ix86_isa_flags_explicit
> > > >
> > >
> > > Like this?
> >
> > Yes, but also split the comment.
>
> I will go with
>
> /* Enable by default the SSE and MMX builtins. Do allow the user to
> explicitly disable any of these. In particular, disabling SSE and
> MMX for kernel code is extremely useful. */
> if (!ix86_arch_specified)
> {
> /* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
> opts->x_ix86_isa_flags
> |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> ? 0 : OPTION_MASK_ISA_MMX))
> & ~opts->x_ix86_isa_flags_explicit);
> opts->x_ix86_isa_flags
> |= (TARGET_SUBTARGET64_ISA_DEFAULT
> & ~opts->x_ix86_isa_flags_explicit);
> }
I'll commit the following patch that finally defines
TARGET_SUBTARGET64_ISA_DEFAULT. You could then simply clear the MMX
bit from x_i86_isa_flags, like:
if (!ix86_arch_specified)
opts->x_ix86_isa_flags
|= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;
/* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
if (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags))
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX;
Uros.
Index: config/i386/i386.c
===
--- config/i386/i386.c (revision 268907)
+++ config/i386/i386.c (working copy)
@@ -4165,14 +4165,9 @@ ix86_option_override_internal (bool main_args_p,
opts->x_target_flags
|= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
- /* Enable by default the SSE and MMX builtins. Do allow the user to
-explicitly disable any of these. In particular, disabling SSE and
-MMX for kernel code is extremely useful. */
if (!ix86_arch_specified)
- opts->x_ix86_isa_flags
- |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
-| TARGET_SUBTARGET64_ISA_DEFAULT)
-& ~opts->x_ix86_isa_flags_explicit);
+ opts->x_ix86_isa_flags
+ |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit;
if (TARGET_RTD_P (opts->x_target_flags))
warning (0,
Index: config/i386/i386.h
===
--- config/i386/i386.h (revision 268907)
+++ config/i386/i386.h (working copy)
@@ -633,7 +633,9 @@ extern tree x86_mfence;
/* Extra bits
[PATCH] Fix ICE with optimize("Ofast") due to option handling (PR other/89342)
Hi!
We ICE on the following testcase, because while we save optimize,
and optimize_{size,debug} vars during option saving/restoring, we don't save
optimize_fast, and because of that end up with optimize 0 optimize_fast 1
which the option handling code ICEs on -
if (fast)
gcc_assert (level == 3);
in maybe_default_option. Fixed thusly, just treat optimize_fast like
the other flags, bootstrapped/regtested on x86_64-linux and i686-linux, ok
for trunk/8.3?
2019-02-14 Jakub Jelinek
PR other/89342
* optc-save-gen.awk: Handle optimize_fast like optimize_size or
optimize_debug.
* opth-gen.awk: Likewise.
* gcc.dg/pr89342.c: New test.
--- gcc/optc-save-gen.awk.jj2019-02-14 08:06:39.436519588 +0100
+++ gcc/optc-save-gen.awk 2019-02-14 13:12:37.789488847 +0100
@@ -81,7 +81,7 @@ print "void";
print "cl_optimization_save (struct cl_optimization *ptr, struct gcc_options
*opts)";
print "{";
-n_opt_char = 3;
+n_opt_char = 4;
n_opt_short = 0;
n_opt_int = 0;
n_opt_enum = 0;
@@ -90,9 +90,11 @@ n_opt_other = 0;
var_opt_char[0] = "optimize";
var_opt_char[1] = "optimize_size";
var_opt_char[2] = "optimize_debug";
+var_opt_char[3] = "optimize_fast";
var_opt_range["optimize"] = "0, 255";
var_opt_range["optimize_size"] = "0, 1";
var_opt_range["optimize_debug"] = "0, 1";
+var_opt_range["optimize_fast"] = "0, 1";
# Sort by size to mimic how the structure is laid out to be friendlier to the
# cache.
@@ -767,16 +769,19 @@ for (i = 0; i < n_target_val; i++) {
print "}";
-n_opt_val = 3;
+n_opt_val = 4;
var_opt_val[0] = "x_optimize"
var_opt_val_type[0] = "char "
var_opt_hash[0] = 1;
var_opt_val[1] = "x_optimize_size"
+var_opt_val_type[1] = "char "
var_opt_hash[1] = 1;
var_opt_val[2] = "x_optimize_debug"
-var_opt_hash[2] = 1;
-var_opt_val_type[1] = "char "
var_opt_val_type[2] = "char "
+var_opt_hash[2] = 1;
+var_opt_val[3] = "x_optimize_fast"
+var_opt_val_type[3] = "char "
+var_opt_hash[3] = 1;
for (i = 0; i < n_opts; i++) {
if (flag_set_p("(Optimization|PerFunction)", flags[i])) {
name = var_name(flags[i])
--- gcc/opth-gen.awk.jj 2019-01-01 12:37:18.562951898 +0100
+++ gcc/opth-gen.awk2019-02-14 13:13:15.919858043 +0100
@@ -132,7 +132,7 @@ print "/* Structure to save/restore opti
print "struct GTY(()) cl_optimization";
print "{";
-n_opt_char = 3;
+n_opt_char = 4;
n_opt_short = 0;
n_opt_int = 0;
n_opt_enum = 0;
@@ -140,6 +140,7 @@ n_opt_other = 0;
var_opt_char[0] = "unsigned char x_optimize";
var_opt_char[1] = "unsigned char x_optimize_size";
var_opt_char[2] = "unsigned char x_optimize_debug";
+var_opt_char[3] = "unsigned char x_optimize_fast";
for (i = 0; i < n_opts; i++) {
if (flag_set_p("(Optimization|PerFunction)", flags[i])) {
--- gcc/testsuite/gcc.dg/pr89342.c.jj 2019-02-14 13:17:48.061355967 +0100
+++ gcc/testsuite/gcc.dg/pr89342.c 2019-02-14 13:17:03.494093205 +0100
@@ -0,0 +1,11 @@
+/* PR other/89342 */
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+__attribute__((optimize("Ofast")))
+void foo (void)
+{
+ __attribute__((optimize("no-inline")))
+ void bar (void) {}
+ bar ();
+}
Jakub
[PATCH] Fix tree-loop-distribution.c ICE with -ftrapv (PR tree-optimization/89278)
Hi!
The following testcase ICEs, because we try to gimplify a complex expression
that with -ftrapv wants to emit multiple bbs. Fixed by using
rewrite_to_non_trapping_overflow. Bootstrapped/regtested on x86_64-linux
and i686-linux, ok for trunk and 8.3?
2019-02-14 Richard Biener
Jakub Jelinek
PR tree-optimization/89278
* tree-loop-distribution.c: Include tree-eh.h.
(generate_memset_builtin, generate_memcpy_builtin): Call
rewrite_to_non_trapping_overflow on builtin->size before passing it
to force_gimple_operand_gsi.
* gcc.dg/pr89278.c: New test.
--- gcc/tree-loop-distribution.c.jj 2019-01-10 11:43:02.255576992 +0100
+++ gcc/tree-loop-distribution.c2019-02-14 12:17:24.403403131 +0100
@@ -114,6 +114,7 @@ along with GCC; see the file COPYING3.
#include "tree-scalar-evolution.h"
#include "params.h"
#include "tree-vectorizer.h"
+#include "tree-eh.h"
#define MAX_DATAREFS_NUM \
@@ -996,7 +997,7 @@ generate_memset_builtin (struct loop *lo
/* The new statements will be placed before LOOP. */
gsi = gsi_last_bb (loop_preheader_edge (loop)->src);
- nb_bytes = builtin->size;
+ nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
nb_bytes = force_gimple_operand_gsi (, nb_bytes, true, NULL_TREE,
false, GSI_CONTINUE_LINKING);
mem = builtin->dst_base;
@@ -1048,7 +1049,7 @@ generate_memcpy_builtin (struct loop *lo
/* The new statements will be placed before LOOP. */
gsi = gsi_last_bb (loop_preheader_edge (loop)->src);
- nb_bytes = builtin->size;
+ nb_bytes = rewrite_to_non_trapping_overflow (builtin->size);
nb_bytes = force_gimple_operand_gsi (, nb_bytes, true, NULL_TREE,
false, GSI_CONTINUE_LINKING);
dest = builtin->dst_base;
--- gcc/testsuite/gcc.dg/pr89278.c.jj 2019-02-14 12:18:38.778173413 +0100
+++ gcc/testsuite/gcc.dg/pr89278.c 2019-02-14 12:18:19.065499344 +0100
@@ -0,0 +1,23 @@
+/* PR tree-optimization/89278 */
+/* { dg-do compile } */
+/* { dg-options "-O1 -ftrapv -ftree-loop-distribute-patterns --param
max-loop-header-insns=2" } */
+
+void
+foo (int *w, int x, int y, int z)
+{
+ while (x < y + z)
+{
+ w[x] = 0;
+ ++x;
+}
+}
+
+void
+bar (int *__restrict u, int *__restrict w, int x, int y, int z)
+{
+ while (x < y + z)
+{
+ w[x] = u[x];
+ ++x;
+}
+}
Jakub
Re: Backport of various patches to gcc 8
On Thu, Feb 14, 2019 at 06:23:37PM -0500, David Malcolm wrote: > It's not clear to me what the rules are on backports (do > I need approval, or re-review?) but the following have > all been bootstrapped and regression-tested relative to > today's gcc-8-branch (on x86_64-pc-linux-gnu): > > r259720: "Don't offer suggestions for compiler-generated variables (PR > c++/85515)" > r262199: "C++: don't offer bogus "._0" suggestions (PR c++/86329)" > r263275: "Fix memory leak of pretty_printer prefixes" > r263295: "docs: fix stray duplicated words" > r263339: "Fix memory leak in selftest::test_expansion_to_rtl" > r267957: "Fix ICE on class-template argument deduction (PR c++/88795)" > r268847: "C++ concepts: fix ICE with requires on dtors (PR c++/89036)" > > Are these OK for gcc-8-branch? Ok, thanks. Jakub
Re: [PATCH][DOC] Document new features for GCC 9.
On Thu, 2019-02-14 at 14:19 -0700, Martin Sebor wrote: > On 2/13/19 6:48 AM, Martin Liška wrote: > > Hi. > > > > I'm sending patch where I document changes I made during GCC 9 > > development. I would appreciate both language and factical comments > > about the patch. > > Nothing technical, just a few very minor language nits/suggestions. > > Martin > > diff --git a/htdocs/gcc-9/changes.html b/htdocs/gcc-9/changes.html > index 13243c2..9fec9e2 100644 > --- a/htdocs/gcc-9/changes.html > +++ b/htdocs/gcc-9/changes.html > @@ -50,11 +50,64 @@ a work-in-progress. > General Improvements > > > -A new option -flive-patching=[inline-only-static|inline-clone] > is > +A new option > -flive-patching=[inline-only-static|inline-clone] is > > s/is/has been/ would be better (and either a comma after option or > a definite article without the comma). > > introduced to provide a safe compilation for live-patching. At > the > same > time, provides multiple-level control on the enabled IPA > optimizations. > See the user guide for further information about the option for > more > -details. > +details. Ideally we should add URLs any time we mention an option, linking to the docs for that option. texinfo's HTML toolchain does give us per- option anchors. They're not visible [1], but "View Source" shows us that they do exist; in the form: https://gcc.gnu.org/onlinedocs/gcc/SOMETHING.html#indexOPTION though annoyingly the SOMETHING varies depending on what kind of option it is. The pertinent one here is: https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#index-flive-patching (FWIW, I have a patch for GCC 10 that emits terminal sequences to "linkify" the output when diagnostics mention option names, adding a URL to the docs for the pertinent option). [...snip...] Dave [1] I've emailed the texinfo project about this
[PATCH 5/7] Fix memory leak in selftest::test_expansion_to_rtl
"make selftest-valgrind" shows: 187 bytes in 1 blocks are definitely lost in loss record 567 of 669 at 0x4A081D4: calloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) by 0x1F08260: xcalloc (xmalloc.c:162) by 0xB24F32: init_emit() (emit-rtl.c:5843) by 0xC10080: prepare_function_start() (function.c:4803) by 0xC10254: init_function_start(tree_node*) (function.c:4877) by 0x1CDF92A: selftest::test_expansion_to_rtl() (function-tests.c:595) by 0x1CE007C: selftest::function_tests_c_tests() (function-tests.c:676) by 0x1E010E7: selftest::run_tests() (selftest-run-tests.c:98) by 0x1062D1E: toplev::run_self_tests() (toplev.c:2225) by 0x1062F40: toplev::main(int, char**) (toplev.c:2303) by 0x1E5B90A: main (main.c:39) The allocation in question is: crtl->emit.regno_pointer_align = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); This patch fixes this leak (and makes the output of "make selftest-valgrind" clean) by calling free_after_compilation at the end of the selftest in question. gcc/ChangeLog: Backport of r263339 from trunk. 2018-08-06 David Malcolm * function-tests.c (selftest::test_expansion_to_rtl): Call free_after_compilation. --- gcc/function-tests.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/function-tests.c b/gcc/function-tests.c index 1b5ebf3..196b3a3 100644 --- a/gcc/function-tests.c +++ b/gcc/function-tests.c @@ -661,6 +661,7 @@ test_expansion_to_rtl () ASSERT_STR_CONTAINS (dump, ") ;; function \"test_fn\"\n"); free (dump); + free_after_compilation (fun); } /* Run all of the selftests within this file. */ -- 1.8.5.3
[PATCH 3/7] Fix memory leak of pretty_printer prefixes
We were rather sloppy about handling the ownership of prefixes for
pretty_printer, and this lead to a memory leak for any time a
diagnostic_show_locus call emits multiple line spans.
This showed up in "make selftest-valgrind" as:
3,976 bytes in 28 blocks are definitely lost in loss record 632 of 669
at 0x4A0645D: malloc (in
/usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so)
by 0x1F08227: xmalloc (xmalloc.c:147)
by 0x1F083E6: xvasprintf (xvasprintf.c:58)
by 0x1E7EC7D: build_message_string(char const*, ...) (diagnostic.c:78)
by 0x1E7F438: diagnostic_get_location_text(diagnostic_context*,
expanded_location) (diagnostic.c:328)
by 0x1E7FD54: default_diagnostic_start_span_fn(diagnostic_context*,
expanded_location) (diagnostic.c:626)
by 0x1EB3508:
selftest::test_diagnostic_context::start_span_cb(diagnostic_context*,
expanded_location) (selftest-diagnostic.c:57)
by 0x1E89215: diagnostic_show_locus(diagnostic_context*, rich_location*,
diagnostic_t) (diagnostic-show-locus.c:1992)
by 0x1E8ECAD:
selftest::test_fixit_insert_containing_newline_2(selftest::line_table_case
const&) (diagnostic-show-locus.c:3044)
by 0x1EB0606: selftest::for_each_line_table_case(void
(*)(selftest::line_table_case const&)) (input.c:3525)
by 0x1E8F3F5: selftest::diagnostic_show_locus_c_tests()
(diagnostic-show-locus.c:3164)
by 0x1E010BF: selftest::run_tests() (selftest-run-tests.c:88)
4,004 bytes in 28 blocks are definitely lost in loss record 633 of 669
at 0x4A0645D: malloc (in
/usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so)
by 0x1F08227: xmalloc (xmalloc.c:147)
by 0x1F083E6: xvasprintf (xvasprintf.c:58)
by 0x1E7EC7D: build_message_string(char const*, ...) (diagnostic.c:78)
by 0x1E7F438: diagnostic_get_location_text(diagnostic_context*,
expanded_location) (diagnostic.c:328)
by 0x1E7FD54: default_diagnostic_start_span_fn(diagnostic_context*,
expanded_location) (diagnostic.c:626)
by 0x1EB3508:
selftest::test_diagnostic_context::start_span_cb(diagnostic_context*,
expanded_location) (selftest-diagnostic.c:57)
by 0x1E89215: diagnostic_show_locus(diagnostic_context*, rich_location*,
diagnostic_t) (diagnostic-show-locus.c:1992)
by 0x1E8B373:
selftest::test_diagnostic_show_locus_fixit_lines(selftest::line_table_case
const&) (diagnostic-show-locus.c:2500)
by 0x1EB0606: selftest::for_each_line_table_case(void
(*)(selftest::line_table_case const&)) (input.c:3525)
by 0x1E8F3B9: selftest::diagnostic_show_locus_c_tests()
(diagnostic-show-locus.c:3159)
by 0x1E010BF: selftest::run_tests() (selftest-run-tests.c:88)
This patch fixes the leaks by ensuring that the pretty_printer "owns"
the prefix if it's non-NULL, freeing it in the dtor and in pp_set_prefix.
gcc/cp/ChangeLog:
Backport of r263275 from trunk.
2018-08-02 David Malcolm
* error.c (cxx_print_error_function): Duplicate "file" before
passing it to pp_set_prefix.
(cp_print_error_function): Use pp_take_prefix when saving the
existing prefix.
gcc/ChangeLog:
Backport of r263275 from trunk.
2018-08-02 David Malcolm
* diagnostic-show-locus.c (diagnostic_show_locus): Use
pp_take_prefix when saving the existing prefix.
* diagnostic.c (diagnostic_append_note): Likewise.
* langhooks.c (lhd_print_error_function): Likewise.
* pretty-print.c (pp_set_prefix): Drop the "const" from "prefix"
param's type. Free the existing prefix.
(pp_take_prefix): New function.
(pretty_printer::pretty_printer): Drop the prefix parameter.
Rename the length parameter to match the comment.
(pretty_printer::~pretty_printer): Free the prefix.
* pretty-print.h (pretty_printer::pretty_printer): Drop the prefix
parameter.
(struct pretty_printer): Drop the "const" from "prefix" field's
type and clarify memory management.
(pp_set_prefix): Drop the "const" from the 2nd param.
(pp_take_prefix): New decl.
---
gcc/cp/error.c | 9 +++--
gcc/diagnostic-show-locus.c | 2 +-
gcc/diagnostic.c| 3 +--
gcc/langhooks.c | 2 +-
gcc/pretty-print.c | 31 +++
gcc/pretty-print.h | 14 --
6 files changed, 41 insertions(+), 20 deletions(-)
diff --git a/gcc/cp/error.c b/gcc/cp/error.c
index 95b8b84..f7895de 100644
--- a/gcc/cp/error.c
+++ b/gcc/cp/error.c
@@ -3286,8 +3286,13 @@ void
cxx_print_error_function (diagnostic_context *context, const char *file,
diagnostic_info *diagnostic)
{
+ char *prefix;
+ if (file)
+prefix = xstrdup (file);
+ else
+prefix = NULL;
lhd_print_error_function (context, file, diagnostic);
- pp_set_prefix (context->printer, file);
+ pp_set_prefix (context->printer, prefix);
maybe_print_instantiation_context (context);
}
@@ -3315,7 +3320,7 @@ cp_print_error_function
[PATCH 6/7] Fix ICE on class-template argument deduction (PR c++/88795)
PR c++/88795 reports an ICE building a function_type for a deduction guide
when the substitution into the function signature fails, due to an
error_mark_node being returned from tsubst_arg_types but not being checked
for. This error_mark_node gets used as the TYPE_ARG_TYPES, leading to
ICEs in various places that assume this is a TREE_LIST.
This patch checks the result of tsubst_arg_types and propagates the failure
if it returns error_mark_node. It also adds an assertion to
build_function_type, to fail faster if passed in error_mark_node.
gcc/cp/ChangeLog:
Backport of r267957 from trunk.
2019-01-15 David Malcolm
PR c++/88795
* pt.c (build_deduction_guide): Bail out if tsubst_arg_types
fails.
gcc/testsuite/ChangeLog:
Backport of r267957 from trunk.
2019-01-15 David Malcolm
PR c++/88795
* g++.dg/template/pr88795.C: New test.
gcc/ChangeLog:
Backport of r267957 from trunk.
2019-01-15 David Malcolm
PR c++/88795
* tree.c (build_function_type): Assert that arg_types is not
error_mark_node.
---
gcc/cp/pt.c | 2 ++
gcc/testsuite/g++.dg/template/pr88795.C | 23 +++
gcc/tree.c | 2 ++
3 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/template/pr88795.C
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 72dc1e0..895cb5a 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -26494,6 +26494,8 @@ build_deduction_guide (tree ctor, tree outer_args,
tsubst_flags_t complain)
targs = template_parms_to_args (tparms);
fparms = tsubst_arg_types (fparms, tsubst_args, NULL_TREE,
complain, ctor);
+ if (fparms == error_mark_node)
+ ok = false;
fargs = tsubst (fargs, tsubst_args, complain, ctor);
if (ci)
ci = tsubst_constraint_info (ci, tsubst_args, complain, ctor);
diff --git a/gcc/testsuite/g++.dg/template/pr88795.C
b/gcc/testsuite/g++.dg/template/pr88795.C
new file mode 100644
index 000..918aa6d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/pr88795.C
@@ -0,0 +1,23 @@
+// { dg-do compile { target c++17 } }
+
+template
+struct Array {};
+
+template
+struct Foo {
+ static constexpr int size() {
+ return size_;
+ }
+
+ template
+ Foo(U, Array) {}
+};
+
+template
+Foo(U, Array) -> Foo;
+
+int main() {
+ Array arr{};
+
+ Foo foo{2.0, arr};
+}
diff --git a/gcc/tree.c b/gcc/tree.c
index ca5d810..091a63a 100644
--- a/gcc/tree.c
+++ b/gcc/tree.c
@@ -8023,6 +8023,8 @@ build_function_type (tree value_type, tree arg_types)
bool any_structural_p, any_noncanonical_p;
tree canon_argtypes;
+ gcc_assert (arg_types != error_mark_node);
+
if (TREE_CODE (value_type) == FUNCTION_TYPE)
{
error ("function return type cannot be function");
--
1.8.5.3
[PATCH 7/7] C++ concepts: fix ICE with requires on dtors (PR c++/89036)
PR c++/89036 reports an ICE due to this assertion failing
1136 /* A class should never have more than one destructor. */
1137 gcc_assert (!current_fns || via_using || !DECL_DESTRUCTOR_P (method));
on this template with a pair of dtors, with
mutually exclusive "requires" clauses:
template
struct Y {
~Y() requires(true) = default;
~Y() requires(false) {}
};
Nathan introduced this assertion as part of:
ca9219bf18c68a001d62ecb981bc9176b0feaf12 (aka r251340):
2017-08-24 Nathan Sidwell
Conversion operators kept on single overload set
which, amongst other changes to add_method had this:
/* A class should never have more than one destructor. */
- if (current_fns && DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (method))
-return false;
+ gcc_assert (!current_fns || !DECL_DESTRUCTOR_P (method));
The following patch drops the assertion.
gcc/cp/ChangeLog:
2019-02-13 David Malcolm
Backport of r268847 from trunk.
PR c++/89036
* class.c (add_method): Drop destructor assertion.
gcc/testsuite/ChangeLog:
2019-02-13 David Malcolm
Backport of r268847 from trunk.
PR c++/89036
* g++.dg/concepts/pr89036.C: New test.
---
gcc/cp/class.c | 3 ---
gcc/testsuite/g++.dg/concepts/pr89036.C | 8
2 files changed, 8 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/concepts/pr89036.C
diff --git a/gcc/cp/class.c b/gcc/cp/class.c
index d524a98..834ba17 100644
--- a/gcc/cp/class.c
+++ b/gcc/cp/class.c
@@ -1141,9 +1141,6 @@ add_method (tree type, tree method, bool via_using)
}
}
- /* A class should never have more than one destructor. */
- gcc_assert (!current_fns || !DECL_DESTRUCTOR_P (method));
-
current_fns = ovl_insert (method, current_fns, via_using);
if (!COMPLETE_TYPE_P (type) && !DECL_CONV_FN_P (method)
diff --git a/gcc/testsuite/g++.dg/concepts/pr89036.C
b/gcc/testsuite/g++.dg/concepts/pr89036.C
new file mode 100644
index 000..f83ef8b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/concepts/pr89036.C
@@ -0,0 +1,8 @@
+// { dg-do compile { target c++11 } }
+// { dg-options "-fconcepts" }
+
+template
+struct Y {
+ ~Y() requires(true) = default;
+ ~Y() requires(false) {}
+};
--
1.8.5.3
[PATCH 2/7] C++: don't offer bogus "._0" suggestions (PR c++/86329)
PR c++/86329 reports that the C++ frontend can offer bogus suggestions like:
#include
int compare()
{
return __n1 - __n2;
}
suggested.cc: In function 'int compare()':
suggested.cc:5:10: error: '__n1' was not declared in this scope
return __n1 - __n2;
^~~~
suggested.cc:5:10: note: suggested alternative: '._61'
return __n1 - __n2;
^~~~
._61
suggested.cc:5:17: error: '__n2' was not declared in this scope
return __n1 - __n2;
^~~~
suggested.cc:5:17: note: suggested alternative: '._72'
return __n1 - __n2;
^~~~
._72
The dot-prefixed names are an implementation detail of how we implement
anonymous enums found in the header files, generated via
anon_aggrname_format in make_anon_name.
This patch uses anon_aggrname_p to filter them out when considering
which names to suggest.
gcc/cp/ChangeLog:
Backport of r262199 from trunk.
2018-06-27 David Malcolm
PR c++/86329
* name-lookup.c (consider_binding_level): Filter out names that
match anon_aggrname_p.
gcc/testsuite/ChangeLog:
Backport of r262199 from trunk.
2018-06-27 David Malcolm
PR c++/86329
* g++.dg/lookup/pr86329.C: New test.
---
gcc/cp/name-lookup.c | 5 +
gcc/testsuite/g++.dg/lookup/pr86329.C | 11 +++
2 files changed, 16 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/lookup/pr86329.C
diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c
index 86fa03b..4e8263b 100644
--- a/gcc/cp/name-lookup.c
+++ b/gcc/cp/name-lookup.c
@@ -5873,6 +5873,11 @@ consider_binding_level (tree name, best_match ,
if (!suggestion)
continue;
+ /* Don't suggest names that are for anonymous aggregate types, as
+they are an implementation detail generated by the compiler. */
+ if (anon_aggrname_p (suggestion))
+ continue;
+
const char *suggestion_str = IDENTIFIER_POINTER (suggestion);
/* Ignore internal names with spaces in them. */
diff --git a/gcc/testsuite/g++.dg/lookup/pr86329.C
b/gcc/testsuite/g++.dg/lookup/pr86329.C
new file mode 100644
index 000..fc091ba
--- /dev/null
+++ b/gcc/testsuite/g++.dg/lookup/pr86329.C
@@ -0,0 +1,11 @@
+/* PR c++/86329: ensure we don't erroneously offer suggestions like "._0",
+ which are an implementation detail of how e.g. anonymous enums are
+ handled internally. */
+
+enum {NONEMPTY};
+
+int test()
+{
+ return __0; // { dg-error "'__0' was not declared in this scope" }
+ // { dg-bogus "suggested alternative" "" { target *-*-* } .-1 }
+}
--
1.8.5.3
Backport of various patches to gcc 8
It's not clear to me what the rules are on backports (do I need approval, or re-review?) but the following have all been bootstrapped and regression-tested relative to today's gcc-8-branch (on x86_64-pc-linux-gnu): r259720: "Don't offer suggestions for compiler-generated variables (PR c++/85515)" r262199: "C++: don't offer bogus "._0" suggestions (PR c++/86329)" r263275: "Fix memory leak of pretty_printer prefixes" r263295: "docs: fix stray duplicated words" r263339: "Fix memory leak in selftest::test_expansion_to_rtl" r267957: "Fix ICE on class-template argument deduction (PR c++/88795)" r268847: "C++ concepts: fix ICE with requires on dtors (PR c++/89036)" Are these OK for gcc-8-branch? Thanks Dave David Malcolm (7): Don't offer suggestions for compiler-generated variables (PR c++/85515) C++: don't offer bogus "._0" suggestions (PR c++/86329) Fix memory leak of pretty_printer prefixes docs: fix stray duplicated words Fix memory leak in selftest::test_expansion_to_rtl Fix ICE on class-template argument deduction (PR c++/88795) C++ concepts: fix ICE with requires on dtors (PR c++/89036) gcc/cp/class.c | 3 --- gcc/cp/error.c | 9 +++-- gcc/cp/name-lookup.c| 11 +++ gcc/cp/pt.c | 2 ++ gcc/cp/search.c | 13 ++--- gcc/diagnostic-show-locus.c | 2 +- gcc/diagnostic.c| 3 +-- gcc/doc/gcov.texi | 2 +- gcc/doc/invoke.texi | 14 +++--- gcc/function-tests.c| 1 + gcc/langhooks.c | 2 +- gcc/pretty-print.c | 31 +++ gcc/pretty-print.h | 14 -- gcc/testsuite/g++.dg/concepts/pr89036.C | 8 gcc/testsuite/g++.dg/lookup/pr86329.C | 11 +++ gcc/testsuite/g++.dg/pr85515-1.C| 18 ++ gcc/testsuite/g++.dg/pr85515-2.C| 22 ++ gcc/testsuite/g++.dg/template/pr88795.C | 23 +++ gcc/tree.c | 2 ++ 19 files changed, 157 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/g++.dg/concepts/pr89036.C create mode 100644 gcc/testsuite/g++.dg/lookup/pr86329.C create mode 100644 gcc/testsuite/g++.dg/pr85515-1.C create mode 100644 gcc/testsuite/g++.dg/pr85515-2.C create mode 100644 gcc/testsuite/g++.dg/template/pr88795.C -- 1.8.5.3
[PATCH 4/7] docs: fix stray duplicated words
gcc/ChangeLog:
Backport of 263295 from trunk.
2018-08-03 David Malcolm
* doc/gcov.texi (-x): Remove duplicate "to".
* doc/invoke.texi (-Wnoexcept-type): Remove duplicate "calls".
(-Wif-not-aligned): Remove duplicate "is".
(-flto): Remove duplicate "the".
(MicroBlaze Options): In examples of "-mcpu=cpu-type", remove
duplicate "v5.00.b".
(MSP430 Options): Remove duplicate "and" from the description
of "-mgprel-sec=regexp".
(x86 Options): Remove duplicate copies of "vmldLog102" and
vmlsLog104 from description of "-mveclibabi=type".
---
gcc/doc/gcov.texi | 2 +-
gcc/doc/invoke.texi | 14 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/doc/gcov.texi b/gcc/doc/gcov.texi
index 5923587..cc1376f 100644
--- a/gcc/doc/gcov.texi
+++ b/gcc/doc/gcov.texi
@@ -333,7 +333,7 @@ Print verbose informations related to basic blocks and arcs.
@item -x
@itemx --hash-filenames
-By default, gcov uses the full pathname of the source files to to create
+By default, gcov uses the full pathname of the source files to create
an output filename. This can lead to long filenames that can overflow
filesystem limits. This option creates names of the form
@file{@var{source-file}##@var{md5}.gcov},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8ec5f01..e5c4e81 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -3020,7 +3020,7 @@ void h() @{ f(g); @}
@end smallexample
@noindent
-In C++14, @code{f} calls calls @code{f}, but in
+In C++14, @code{f} calls @code{f}, but in
C++17 it calls @code{f}.
@item -Wclass-memaccess @r{(C++ and Objective-C++ only)}
@@ -4539,7 +4539,7 @@ The @option{-Wimplicit-fallthrough=3} warning is enabled
by @option{-Wextra}.
@opindex Wif-not-aligned
@opindex Wno-if-not-aligned
Control if warning triggered by the @code{warn_if_not_aligned} attribute
-should be issued. This is is enabled by default.
+should be issued. This is enabled by default.
Use @option{-Wno-if-not-aligned} to disable it.
@item -Wignored-qualifiers @r{(C and C++ only)}
@@ -9479,7 +9479,7 @@ for LTO, use @command{gcc-ar} and @command{gcc-ranlib}
instead of @command{ar}
and @command{ranlib};
to show the symbols of object files with GIMPLE bytecode, use
@command{gcc-nm}. Those commands require that @command{ar}, @command{ranlib}
-and @command{nm} have been compiled with plugin support. At link time, use
the the
+and @command{nm} have been compiled with plugin support. At link time, use the
flag @option{-fuse-linker-plugin} to ensure that the library participates in
the LTO optimization process:
@@ -20084,7 +20084,7 @@ Use features of, and schedule code for, the given CPU.
Supported values are in the format @samp{v@var{X}.@var{YY}.@var{Z}},
where @var{X} is a major version, @var{YY} is the minor version, and
@var{Z} is compatibility code. Example values are @samp{v3.00.a},
-@samp{v4.00.b}, @samp{v5.00.a}, @samp{v5.00.b}, @samp{v5.00.b}, @samp{v6.00.a}.
+@samp{v4.00.b}, @samp{v5.00.a}, @samp{v5.00.b}, @samp{v6.00.a}.
@item -mxl-soft-mul
@opindex mxl-soft-mul
@@ -21746,7 +21746,7 @@ GP-relative addressing. It is most useful in
conjunction with
The @var{regexp} is a POSIX Extended Regular Expression.
This option does not affect the behavior of the @option{-G} option, and
-and the specified sections are in addition to the standard @code{.sdata}
+the specified sections are in addition to the standard @code{.sdata}
and @code{.sbss} small-data sections that are recognized by @option{-mgpopt}.
@item -mr0rel-sec=@var{regexp}
@@ -27588,11 +27588,11 @@ To use this option, both @option{-ftree-vectorize} and
ABI-compatible library must be specified at link time.
GCC currently emits calls to @code{vmldExp2},
-@code{vmldLn2}, @code{vmldLog102}, @code{vmldLog102}, @code{vmldPow2},
+@code{vmldLn2}, @code{vmldLog102}, @code{vmldPow2},
@code{vmldTanh2}, @code{vmldTan2}, @code{vmldAtan2}, @code{vmldAtanh2},
@code{vmldCbrt2}, @code{vmldSinh2}, @code{vmldSin2}, @code{vmldAsinh2},
@code{vmldAsin2}, @code{vmldCosh2}, @code{vmldCos2}, @code{vmldAcosh2},
-@code{vmldAcos2}, @code{vmlsExp4}, @code{vmlsLn4}, @code{vmlsLog104},
+@code{vmldAcos2}, @code{vmlsExp4}, @code{vmlsLn4},
@code{vmlsLog104}, @code{vmlsPow4}, @code{vmlsTanh4}, @code{vmlsTan4},
@code{vmlsAtan4}, @code{vmlsAtanh4}, @code{vmlsCbrt4}, @code{vmlsSinh4},
@code{vmlsSin4}, @code{vmlsAsinh4}, @code{vmlsAsin4}, @code{vmlsCosh4},
--
1.8.5.3
[PATCH 1/7] Don't offer suggestions for compiler-generated variables (PR c++/85515)
gcc/cp/ChangeLog:
Backport of r259720 from trunk.
2018-04-27 David Malcolm
PR c++/85515
* name-lookup.c (consider_binding_level): Skip compiler-generated
variables.
* search.c (lookup_field_fuzzy_info::fuzzy_lookup_field): Flatten
nested if statements into a series of rejection tests. Reject
lambda-ignored entities as suggestions.
gcc/testsuite/ChangeLog:
Backport of r259720 from trunk.
2018-04-27 David Malcolm
PR c++/85515
* g++.dg/pr85515-1.C: New test.
* g++.dg/pr85515-2.C: New test.
---
gcc/cp/name-lookup.c | 6 ++
gcc/cp/search.c | 13 ++---
gcc/testsuite/g++.dg/pr85515-1.C | 18 ++
gcc/testsuite/g++.dg/pr85515-2.C | 22 ++
4 files changed, 56 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/pr85515-1.C
create mode 100644 gcc/testsuite/g++.dg/pr85515-2.C
diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c
index 4ce632c..86fa03b 100644
--- a/gcc/cp/name-lookup.c
+++ b/gcc/cp/name-lookup.c
@@ -5863,6 +5863,12 @@ consider_binding_level (tree name, best_match ,
&& DECL_ANTICIPATED (d))
continue;
+ /* Skip compiler-generated variables (e.g. __for_begin/__for_end
+within range for). */
+ if (TREE_CODE (d) == VAR_DECL
+ && DECL_ARTIFICIAL (d))
+ continue;
+
tree suggestion = DECL_NAME (d);
if (!suggestion)
continue;
diff --git a/gcc/cp/search.c b/gcc/cp/search.c
index ca04dca..d4214d4 100644
--- a/gcc/cp/search.c
+++ b/gcc/cp/search.c
@@ -1227,9 +1227,16 @@ lookup_field_fuzzy_info::fuzzy_lookup_field (tree type)
for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
{
- if (!m_want_type_p || DECL_DECLARES_TYPE_P (field))
- if (DECL_NAME (field))
- m_candidates.safe_push (DECL_NAME (field));
+ if (m_want_type_p && !DECL_DECLARES_TYPE_P (field))
+ continue;
+
+ if (!DECL_NAME (field))
+ continue;
+
+ if (is_lambda_ignored_entity (field))
+ continue;
+
+ m_candidates.safe_push (DECL_NAME (field));
}
}
diff --git a/gcc/testsuite/g++.dg/pr85515-1.C b/gcc/testsuite/g++.dg/pr85515-1.C
new file mode 100644
index 000..0e27a9d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr85515-1.C
@@ -0,0 +1,18 @@
+// { dg-require-effective-target c++14 }
+
+void test_1 ()
+{
+ auto lambda = [val = 2](){};
+ lambda.val; // { dg-bogus "did you mean" }
+ // { dg-error "has no member named 'val'" "" { target *-*-* } .-1 }
+}
+
+int test_2 ()
+{
+ auto lambda = [val = 2](){ return val; };
+
+ // TODO: should we issue an error for the following assignment?
+ lambda.__val = 4;
+
+ return lambda();
+}
diff --git a/gcc/testsuite/g++.dg/pr85515-2.C b/gcc/testsuite/g++.dg/pr85515-2.C
new file mode 100644
index 000..621ddb8
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr85515-2.C
@@ -0,0 +1,22 @@
+// { dg-require-effective-target c++11 }
+
+void test_1 ()
+{
+ int arr[] = {1, 2, 3, 4, 5};
+ for (const auto v: arr) {
+_forbegin; // { dg-bogus "suggested alternative" }
+// { dg-error "'_forbegin' was not declared in this scope" "" { target
*-*-*} .-1 }
+ }
+}
+
+int test_2 ()
+{
+ int arr[] = {1, 2, 3, 4, 5};
+ int sum = 0;
+ for (const auto v: arr) {
+sum += v;
+// TODO: should we issue an error for the following assignment?
+__for_begin = __for_end;
+ }
+ return sum;
+}
--
1.8.5.3
[PATCH, testsuite]: Re-enable 64-bit form in gcc.target/i386/ssse3-*.c on AVX targets
2019-02-14 Uroš Bizjak
* gcc.target/i386/ssse3-pabsb.c: Re-enable 64-bit form on AVX targets.
* gcc.target/i386/ssse3-pabsd.c: Ditto.
* gcc.target/i386/ssse3-pabsw.c: Ditto.
* gcc.target/i386/ssse3-palignr.c: Ditto.
* gcc.target/i386/ssse3-phaddd.c: Ditto.
* gcc.target/i386/ssse3-phaddsw.c: Ditto.
* gcc.target/i386/ssse3-phaddw.c: Ditto.
* gcc.target/i386/ssse3-phsubd.c: Ditto.
* gcc.target/i386/ssse3-phsubsw.c: Ditto.
* gcc.target/i386/ssse3-phsubw.c: Ditto.
* gcc.target/i386/ssse3-pmaddubsw.c: Ditto.
* gcc.target/i386/ssse3-pmulhrsw.c: Ditto.
* gcc.target/i386/ssse3-pshufb.c: Ditto.
* gcc.target/i386/ssse3-psignb.c: Ditto.
* gcc.target/i386/ssse3-psignd.c: Ditto.
* gcc.target/i386/ssse3-psignw.c: Ditto.
Tested on x86_64-linux-gnu {,-m32} w/ and w/o -mavx.
Committed to mainline SVN.
Uros.
Index: gcc.target/i386/ssse3-pabsb.c
===
--- gcc.target/i386/ssse3-pabsb.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsb.c (working copy)
@@ -15,7 +15,6 @@
#include "ssse3-vals.h"
#include
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsb (int *i1, int *r)
@@ -24,7 +23,6 @@
*(__m64 *) r = _mm_abs_pi8 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -63,12 +61,10 @@
/* Manually compute the result */
compute_correct_result([i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsb ([i + 0], [0]);
ssse3_test_pabsb ([i + 2], [2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsb128 ([i + 0], r);
Index: gcc.target/i386/ssse3-pabsd.c
===
--- gcc.target/i386/ssse3-pabsd.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsd.c (working copy)
@@ -16,7 +16,6 @@
#include
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsd (int *i1, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_abs_pi32 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -62,12 +60,10 @@
/* Manually compute the result */
compute_correct_result([i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsd ([i + 0], [0]);
ssse3_test_pabsd ([i + 2], [2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsd128 ([i + 0], r);
Index: gcc.target/i386/ssse3-pabsw.c
===
--- gcc.target/i386/ssse3-pabsw.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsw.c (working copy)
@@ -16,7 +16,6 @@
#include
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsw (int *i1, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_abs_pi16 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -64,12 +62,10 @@
/* Manually compute the result */
compute_correct_result ([i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsw ([i + 0], [0]);
ssse3_test_pabsw ([i + 2], [2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsw128 ([i + 0], r);
Index: gcc.target/i386/ssse3-palignr.c
===
--- gcc.target/i386/ssse3-palignr.c (revision 268854)
+++ gcc.target/i386/ssse3-palignr.c (working copy)
@@ -17,7 +17,6 @@
#include
#include
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_palignr (int *i1, int *i2, unsigned int imm, int *r)
@@ -82,7 +81,6 @@
_mm_empty();
}
-#endif
/* Test the 128-bit form */
static void
@@ -214,7 +212,6 @@
bout[i] = buf[imm + i];
}
-#ifndef __AVX__
static void
compute_correct_result_64 (int *i1, int *i2, unsigned int imm, int *r)
{
@@ -242,7 +239,6 @@
else
bout[i + 8] = buf[imm + i];
}
-#endif
static void
TEST (void)
@@ -256,7 +252,6 @@
for (i = 0; i < 256; i += 8)
for (imm = 0; imm < 100; imm++)
{
-#ifndef __AVX__
/* Manually compute the result */
compute_correct_result_64 ([i + 0], [i + 4], imm, ck);
@@ -264,7 +259,6 @@
ssse3_test_palignr ([i + 0], [i + 4], imm, [0]);
ssse3_test_palignr ([i + 2], [i + 6], imm, [2]);
fail += chk_128 (ck, r);
-#endif
/* Recompute the results for 128-bits */
compute_correct_result_128 ([i + 0], [i + 4], imm, ck);
Index: gcc.target/i386/ssse3-phaddd.c
===
--- gcc.target/i386/ssse3-phaddd.c (revision 268854)
+++ gcc.target/i386/ssse3-phaddd.c (working copy)
@@ -16,7 +16,6 @@
#include
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_phaddd (int *i1, int *i2, int *r)
@@ -26,7
[PATCH, fortran] PR 81552 Improve and document -flag-init-integer
Make the option handling code parse the -flag-init-integer value as a
C long type, allowing a larger range on systems where long is a larger
type than int. Document the behavior.
Regtested on x86_64-pc-linux-gnu, committed as obvious.
2019-02-14 Janne Blomqvist
PR fortran/81552
* gfortran.h (gfc_option_t): Make flag_init_integer_value a long.
* options.c (gfc_handle_option): Use strtol instead of atoi.
* invoke.texi: Document -finit-integer behavior in more detail.
---
gcc/fortran/gfortran.h | 2 +-
gcc/fortran/invoke.texi | 5 +
gcc/fortran/options.c | 2 +-
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index 0a0fef81d9f..526897c4170 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -2681,7 +2681,7 @@ typedef struct
int flag_preprocessed;
int flag_d_lines;
int flag_init_integer;
- int flag_init_integer_value;
+ long flag_init_integer_value;
int flag_init_logical;
int flag_init_character;
char flag_init_character_value;
diff --git a/gcc/fortran/invoke.texi b/gcc/fortran/invoke.texi
index 0e0c2bcb20d..a5d81960a61 100644
--- a/gcc/fortran/invoke.texi
+++ b/gcc/fortran/invoke.texi
@@ -1779,6 +1779,11 @@ use @option{-finit-real=snan}; note, however, that
compile-time
optimizations may convert them into quiet NaN and that trapping
needs to be enabled (e.g. via @option{-ffpe-trap}).
+The @option{-finit-integer} option will parse the value into an
+integer of type @code{INTEGER(kind=C_LONG)} on the host. Said value
+is then assigned to the integer variables in the Fortran code, which
+might result in wraparound if the value is too large for the kind.
+
Finally, note that enabling any of the @option{-finit-*} options will
silence warnings that would have been emitted by @option{-Wuninitialized}
for the affected local variables.
diff --git a/gcc/fortran/options.c b/gcc/fortran/options.c
index 4e55adec6fe..f2a0151670e 100644
--- a/gcc/fortran/options.c
+++ b/gcc/fortran/options.c
@@ -708,7 +708,7 @@ gfc_handle_option (size_t scode, const char *arg,
HOST_WIDE_INT value,
case OPT_finit_integer_:
gfc_option.flag_init_integer = GFC_INIT_INTEGER_ON;
- gfc_option.flag_init_integer_value = atoi (arg);
+ gfc_option.flag_init_integer_value = strtol (arg, NULL, 10);
break;
case OPT_finit_character_:
--
2.17.1
[PATCH, d] Committed Add netbsd support to GDC
Hi,
This is a combine of netbsd patches sent by Maya, and related upstream
druntime changes.
Bootstrapped and regression tested on x86_64-linux-gnu, which only
confirms that the scoping is correct. I trust that Maya tested the
netbsd-d.c part, nothing looks out of place there anyway.
Committed to trunk as r268905.
--
Iain
---
gcc/ChangeLog:
2019-02-14 Maya Rashish
* config.gcc (*-*-netbsd*): Add netbsd-d.o
* config/netbsd-d.c: New file.
* config/t-netbsd: Add netbsd-d.o
gcc/d/ChangeLog:
2019-02-14 Maya Rashish
* d-system.h: NetBSD is POSIX.
libphobos/ChangeLog:
2019-02-14 Maya Rashish
* configure.tgt: Add netbsd/x86 as supported target.
---
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 31b47c51b7b..3ee31c5993d 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -839,6 +839,7 @@ case ${target} in
tm_p_file="${tm_p_file} netbsd-protos.h"
tmake_file="t-netbsd t-slibgcc"
extra_objs="${extra_objs} netbsd.o"
+ d_target_objs="${d_target_objs} netbsd-d.o"
gas=yes
gnu_ld=yes
use_gcc_stdint=wrap
@@ -847,6 +848,7 @@ case ${target} in
esac
nbsd_tm_file="netbsd.h netbsd-stdint.h netbsd-elf.h"
default_use_cxa_atexit=yes
+ target_has_targetdm=yes
;;
*-*-openbsd*)
tmake_file="t-openbsd"
diff --git a/gcc/config/netbsd-d.c b/gcc/config/netbsd-d.c
new file mode 100644
index 000..76342aacae3
--- /dev/null
+++ b/gcc/config/netbsd-d.c
@@ -0,0 +1,41 @@
+/* Functions for generic NetBSD as target machine for GNU D compiler.
+ Copyright (C) 2019 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+
Re: [PATCH][DOC] Document new features for GCC 9.
On 2/13/19 6:48 AM, Martin Liška wrote:
Hi.
I'm sending patch where I document changes I made during GCC 9
development. I would appreciate both language and factical comments
about the patch.
Nothing technical, just a few very minor language nits/suggestions.
Martin
diff --git a/htdocs/gcc-9/changes.html b/htdocs/gcc-9/changes.html
index 13243c2..9fec9e2 100644
--- a/htdocs/gcc-9/changes.html
+++ b/htdocs/gcc-9/changes.html
@@ -50,11 +50,64 @@ a work-in-progress.
General Improvements
-A new option -flive-patching=[inline-only-static|inline-clone] is
+A new option
-flive-patching=[inline-only-static|inline-clone] is
s/is/has been/ would be better (and either a comma after option or
a definite article without the comma).
introduced to provide a safe compilation for live-patching. At the
same
time, provides multiple-level control on the enabled IPA
optimizations.
See the user guide for further information about the option for more
-details.
+details.
It seems we should choose between "for further information" and "for
more details" but we don't need both.
+
+
+ A new option --completion<\>code is added to provide more fine
+ option completion in a shell. It is intended for Bash-completion
project.
Missing article: for "a Bash-completion project" (or perhaps "to be
used by Bash completion." not sure exactly what project it refers to).
+
+
+ Alignment-related options -falign-functions,
Since you're naming them use a definite article: "The alignment-related
options..."
+ -falign-labels, -falign-loops
+ and -falign-jumps received support for a secondary
+ alignment (e.g. -falign-loops=n:m:n2:m2).
+
+
+ A new built-in __builtin_expect_with_probability has
been added.
I'm really nit-picking now but again, since you are referring to
a specific option a definite article would be more appropriate.
Alternatively: "A new built-in function,
__builtin_expect_with_probability, has been added.
+
+
+ Switch expansion has been improved by using a different strategy
+ (jump table, bit test, decision tree) for a subset of switch cases.
+
+
+ A linear function expression defined as switch statement with cases
Maybe a missing article? "defined as a switch statement with cases"
(if that's what you meant.)
+ can be transformed by -ftree-switch-conversion. For
example:
+
+int
+foo (int how)
+{
+ switch (how) {
+case 2: how = 205; break;
+case 3: how = 305; break;
+case 4: how = 405; break;
+case 5: how = 505; break;
+case 6: how = 605; break;
+ }
+ return how;
+}
+
+ can be transformed into 100 * how + 5 (for values
defined
+ in the switch statement).
+
+
+ The gcov tool received a new option --use-hotness-colors
+ (-q) that can provide perf-like coloring of hot
functions.
+
+
+ The gcov tool has changed intermediate format to a new JSON format.
Missing article: "has changed an (or "its?") intermediate format..."
depending on how many intermediate formats it has.
+
+
+ New pair of profiling options (-fprofile-filter-files
+ and -fprofile-exclude-files) has been added.
+ The options help to filter which source files are instrumented.
+
+
+ AddressSanitizer generates more compact red-zones for automatic
variables.
+ That helps to reduce memory footprint of a sanitized binary.
@@ -137,7 +190,7 @@ a work-in-progress.
D
Support for the D programming language has been added to GCC,
-implementing version 2.076 of the language and run-time library.
+implementing version 2.076 of the language and run-time library.
@@ -294,7 +347,11 @@ a work-in-progress.
-
+IA-32/x86-64
+
+ Support of Intel MPX (Memory Protection Extensions) has been
removed.
+
+
Re: Fortran vector math header
On Wed, 2019-02-13 at 12:34 +0100, Martin Liška wrote: > May I please ping this so that we can reach mainline soon? > > Thanks, > Martin Martin, I can't approve this patch but I can say that I have used it on Aarch64 and created a follow up patch for aarch64 to create a get_multilib_abi_name target function for that platform. Everything seemed to work fine for me and I did not have any problems or see any regressions when using your patch. I hope it gets approved and checked in soon. Steve Ellcey sell...@marvell.com
Go patch committed: Copy has_padding field if struct backend type exists
This patch fixes the Go frontend to copy the has_padding field if a struct backend type already exists. The has_padding field is set when creating the struct backend type, and checked when creating a composite literal of that struct type. When two structs shared the same backend type, because they were identical, the has_padding field was not set correctly for the second struct. This fixes that problem. The test case is https://golang.org/cl/162617. This fixes GCC PR 89321. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === --- gcc/go/gofrontend/MERGE (revision 268891) +++ gcc/go/gofrontend/MERGE (working copy) @@ -1,4 +1,4 @@ -a487c86418488f6a17dab4f9945e2a5d495e3ddb +c2fc3b83d832725accd4fa5874a5b5ca02dd90dc The first line of this file holds the git revision number of the last merge done from the gofrontend repository. Index: gcc/go/gofrontend/types.cc === --- gcc/go/gofrontend/types.cc (revision 268891) +++ gcc/go/gofrontend/types.cc (working copy) @@ -1003,6 +1003,16 @@ Type::get_backend(Gogo* gogo) ins.first->second.is_placeholder = false; } + // We set the has_padding field of a Struct_type when we convert + // to the backend type, so if we have multiple Struct_type's + // mapping to the same backend type we need to copy the + // has_padding field. FIXME: This is awkward. We shouldn't + // really change the type when setting the backend type, but + // there isn't any other good time to add the padding field. + if (ins.first->first->struct_type() != NULL + && ins.first->first->struct_type()->has_padding()) + this->struct_type()->set_has_padding(); + return ins.first->second.btype; }
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 12:54 PM Uros Bizjak wrote:
>
> On Thu, Feb 14, 2019 at 9:50 PM H.J. Lu wrote:
> >
> > On Thu, Feb 14, 2019 at 12:07 PM Uros Bizjak wrote:
> > >
> > > On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu wrote:
> > > >
> > > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
> > > > by default with TARGET_MMX_WITH_SSE.
> > > >
> > > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> > > > mode since MMX intrinsics can be emulated wit SSE.
> > > >
> > > > gcc/
> > > >
> > > > PR target/89021
> > > > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > > > SSE/SSE2/SSSE3.
> > > > * config/i386/i386.c (ix86_option_override_internal): Don't
> > > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
> > > > SSE/SSE2/SSSE3.
> > > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > > > intrinsics with TARGET_MMX_WITH_SSE.
> > > > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
> > > >
> >
> > >
> > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > > index a9abbe8706b..1d417e08734 100644
> > > > --- a/gcc/config/i386/i386.c
> > > > +++ b/gcc/config/i386/i386.c
> > > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,
> > > >opts->x_target_flags
> > > > |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
> > > >
> > > > - /* Enable by default the SSE and MMX builtins. Do allow the
> > > > user to
> > > > -explicitly disable any of these. In particular, disabling SSE
> > > > and
> > > > -MMX for kernel code is extremely useful. */
> > > > + /* Enable the SSE and MMX builtins by default. Don't enable MMX
> > > > + ISA with TARGET_MMX_WITH_SSE by default. Do allow the user to
> > > > +explicitly disable any of these. In particular, disabling SSE
> > > > +and MMX for kernel code is extremely useful. */
> > > >if (!ix86_arch_specified)
> > > >opts->x_ix86_isa_flags
> > > > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > > > OPTION_MASK_ISA_MMX
> > > > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > > + ? 0 : OPTION_MASK_ISA_MMX)
> > > > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > > > & ~opts->x_ix86_isa_flags_explicit);
> > >
> > > Please split the above into two clauses, the first that sets SSE and
> > > MMX by default, and the second to or with
> > >
> > > opts->x_ix86_isa_flags
> > > |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit
> > >
> >
> > Like this?
>
> Yes, but also split the comment.
I will go with
/* Enable by default the SSE and MMX builtins. Do allow the user to
explicitly disable any of these. In particular, disabling SSE and
MMX for kernel code is extremely useful. */
if (!ix86_arch_specified)
{
/* Don't enable MMX ISA with TARGET_MMX_WITH_SSE. */
opts->x_ix86_isa_flags
|= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
? 0 : OPTION_MASK_ISA_MMX))
& ~opts->x_ix86_isa_flags_explicit);
opts->x_ix86_isa_flags
|= (TARGET_SUBTARGET64_ISA_DEFAULT
& ~opts->x_ix86_isa_flags_explicit);
}
--
H.J.
Re: [Committed][PATCH][GCC][Arm] Fix test directive
On Thu, 14 Feb 2019 at 19:27, Tamar Christina wrote: > > Hi All, > > This patch fixes a failing testcase due to a use of dg-options instead of > dg-additional-options. > Makes sense. It doesn't fail in any of the configurations I test though, in what case do you see it failing? > Committed under the GCC obvious > > Bootstrapped Regtested on arm-none-eabi and no issues. > > Ok for trunk? > > Thanks, > Tamar > > gcc/testsuite/ChangeLog: > > 2019-02-14 Tamar Christina > > * gcc.target/arm/pr88850.c: change options to additional option. > > --
Re: [PATCH 40/40] i386: Also enable SSSE3 __m64 tests in 64-bit mode
On Thu, Feb 14, 2019 at 12:43 PM Uros Bizjak wrote:
>
> On Thu, Feb 14, 2019 at 9:21 PM Uros Bizjak wrote:
> >
> > On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
> > >
> > > Since we now emulate MMX intrinsics with SSE in 64-bit mode, we can
> > > enable SSSE3 __m64 tests even when AVX is enabled.
> > >
> > > PR target/89021
> > > * gcc.target/i386/ssse3-pabsb.c: Also enable __m64 check in
> > > 64-bit mode.
> > > * gcc.target/i386/ssse3-pabsd.c: Likewise.
> > > * gcc.target/i386/ssse3-pabsw.c: Likewise.
> > > * gcc.target/i386/ssse3-palignr.c: Likewise.
> > > * gcc.target/i386/ssse3-phaddd.c: Likewise.
> > > * gcc.target/i386/ssse3-phaddsw.c: Likewise.
> > > * gcc.target/i386/ssse3-phaddw.c: Likewise.
> > > * gcc.target/i386/ssse3-phsubd.c: Likewise.
> > > * gcc.target/i386/ssse3-phsubsw.c: Likewise.
> > > * gcc.target/i386/ssse3-phsubw.c: Likewise.
> > > * gcc.target/i386/ssse3-pmaddubsw.c: Likewise.
> > > * gcc.target/i386/ssse3-pmulhrsw.c: Likewise.
> > > * gcc.target/i386/ssse3-pshufb.c: Likewise.
> > > * gcc.target/i386/ssse3-psignb.c: Likewise.
> > > * gcc.target/i386/ssse3-psignd.c: Likewise.
> > > * gcc.target/i386/ssse3-psignw.c: Likewise.
> > > ---
> > > gcc/testsuite/gcc.target/i386/ssse3-pabsb.c | 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-pabsd.c | 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-pabsw.c | 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-palignr.c | 6 +++---
> > > gcc/testsuite/gcc.target/i386/ssse3-phaddd.c| 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c | 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-phaddw.c| 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-phsubd.c| 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c | 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-phsubw.c| 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c | 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c | 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-pshufb.c| 6 +++---
> > > gcc/testsuite/gcc.target/i386/ssse3-psignb.c| 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-psignd.c| 4 ++--
> > > gcc/testsuite/gcc.target/i386/ssse3-psignw.c| 4 ++--
> > > 16 files changed, 34 insertions(+), 34 deletions(-)
> > >
> > > diff --git a/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > > b/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > > index 7caa1b6c3a6..eef4ccae222 100644
> > > --- a/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > > +++ b/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > > @@ -15,7 +15,7 @@
> > > #include "ssse3-vals.h"
> > > #include
> > >
> > > -#ifndef __AVX__
> > > +#if !defined __AVX__ || defined __x86_64__
> >
> > Better add || defined __x86_64__.
> >
> > I also wonder why AVX has to be disabled here. MMX should be orthogonal to
> > AVX.
>
> Actually, current trunk passes tests with #ifndef __AVX__ removed and:
I don't remember why AVX was disabled. It is possible that AVX SDE at
the time didn't
support MMX with AVX.Can you check in a separate patch to remove
__AVX__ check?
Thanks.
> gmake -k check-gcc
> RUNTESTFLAGS="--target_board=unix\{,-m32\}\{,-mavx\}
> i386.exp=ssse3-*.c"
>
> === gcc tests ===
>
> Schedule of variations:
> unix
> unix/-mavx
> unix/-m32
> unix/-m32/-mavx
>
> === gcc Summary ===
>
> # of expected passes128
>
> Uros.
--
H.J.
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 9:50 PM H.J. Lu wrote:
>
> On Thu, Feb 14, 2019 at 12:07 PM Uros Bizjak wrote:
> >
> > On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu wrote:
> > >
> > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
> > > by default with TARGET_MMX_WITH_SSE.
> > >
> > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> > > mode since MMX intrinsics can be emulated wit SSE.
> > >
> > > gcc/
> > >
> > > PR target/89021
> > > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > > SSE/SSE2/SSSE3.
> > > * config/i386/i386.c (ix86_option_override_internal): Don't
> > > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
> > > SSE/SSE2/SSSE3.
> > > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > > intrinsics with TARGET_MMX_WITH_SSE.
> > > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
> > >
>
> >
> > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > index a9abbe8706b..1d417e08734 100644
> > > --- a/gcc/config/i386/i386.c
> > > +++ b/gcc/config/i386/i386.c
> > > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,
> > >opts->x_target_flags
> > > |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
> > >
> > > - /* Enable by default the SSE and MMX builtins. Do allow the user
> > > to
> > > -explicitly disable any of these. In particular, disabling SSE
> > > and
> > > -MMX for kernel code is extremely useful. */
> > > + /* Enable the SSE and MMX builtins by default. Don't enable MMX
> > > + ISA with TARGET_MMX_WITH_SSE by default. Do allow the user to
> > > +explicitly disable any of these. In particular, disabling SSE
> > > +and MMX for kernel code is extremely useful. */
> > >if (!ix86_arch_specified)
> > >opts->x_ix86_isa_flags
> > > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > > OPTION_MASK_ISA_MMX
> > > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > > + ? 0 : OPTION_MASK_ISA_MMX)
> > > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > > & ~opts->x_ix86_isa_flags_explicit);
> >
> > Please split the above into two clauses, the first that sets SSE and
> > MMX by default, and the second to or with
> >
> > opts->x_ix86_isa_flags
> > |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit
> >
>
> Like this?
Yes, but also split the comment.
Thanks,
Uros.
> /* Enable the SSE and MMX builtins by default. Don't enable MMX
> ISA with TARGET_MMX_WITH_SSE by default. Do allow the user to
> explicitly disable any of these. In particular, disabling SSE
> and MMX for kernel code is extremely useful. */
> if (!ix86_arch_specified)
> {
> opts->x_ix86_isa_flags
> |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> | (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> ? 0 : OPTION_MASK_ISA_MMX))
> & ~opts->x_ix86_isa_flags_explicit);
> opts->x_ix86_isa_flags
> |= (TARGET_SUBTARGET64_ISA_DEFAULT
> & ~opts->x_ix86_isa_flags_explicit);
> }
>
>
> > > diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
> > > index 238b3df3121..7b613658111 100644
> > > --- a/gcc/config/i386/mmintrin.h
> > > +++ b/gcc/config/i386/mmintrin.h
> > > @@ -30,7 +30,7 @@
> > > #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__
> > > #pragma GCC push_options
> > > #ifdef __x86_64__
> > > -#pragma GCC target("sse,mmx")
> > > +#pragma GCC target("sse2")
> >
> > You will need to involve __MMX_WITH_SSE__ here, probably to something like:
> >
> > #ifdef __MMX_WITH_SSE__
> > #pragma GCC target("sse2")
> > #elif defined __x86_64__
> > #pragma GCC target("sse,mmx")
> > #else
> > #pragma GCC target("mmx")
> > #endif
> >
> > > #else
> > > #pragma GCC target("mmx")
> > > #endif
> > > @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)
> > > /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> > > #ifndef __SSE2__
> > > #pragma GCC push_options
> > > +#ifdef __x86_64__
> >
> > #ifdef __MMX_WITH_SSE__
> >
> > > +#pragma GCC target("sse2")
> > > +#else
> > > #pragma GCC target("sse2,mmx")
> > > +#endif
> > > #define __DISABLE_SSE2__
> > > #endif /* __SSE2__ */
> > >
> > > @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)
> > > /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> > > #ifndef __SSE2__
> > > #pragma GCC push_options
> > > +#ifdef __x86_64__
> >
> > #ifdef __MMX_WITH_SSE__
> >
> > > +#pragma GCC target("sse2")
> > > +#else
> > > #pragma GCC target("sse2,mmx")
> > > +#endif
> > > #define __DISABLE_SSE2__
> > >
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 12:07 PM Uros Bizjak wrote:
>
> On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu wrote:
> >
> > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
> > by default with TARGET_MMX_WITH_SSE.
> >
> > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> > mode since MMX intrinsics can be emulated wit SSE.
> >
> > gcc/
> >
> > PR target/89021
> > * config/i386/i386-builtin.def: Enable MMX intrinsics with
> > SSE/SSE2/SSSE3.
> > * config/i386/i386.c (ix86_option_override_internal): Don't
> > enable MMX ISA with TARGET_MMX_WITH_SSE by default.
> > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with
> > SSE/SSE2/SSSE3.
> > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX
> > intrinsics with TARGET_MMX_WITH_SSE.
> > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode.
> >
>
> > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > index a9abbe8706b..1d417e08734 100644
> > --- a/gcc/config/i386/i386.c
> > +++ b/gcc/config/i386/i386.c
> > @@ -4165,12 +4165,15 @@ ix86_option_override_internal (bool main_args_p,
> >opts->x_target_flags
> > |= TARGET_SUBTARGET64_DEFAULT & ~opts_set->x_target_flags;
> >
> > - /* Enable by default the SSE and MMX builtins. Do allow the user to
> > -explicitly disable any of these. In particular, disabling SSE and
> > -MMX for kernel code is extremely useful. */
> > + /* Enable the SSE and MMX builtins by default. Don't enable MMX
> > + ISA with TARGET_MMX_WITH_SSE by default. Do allow the user to
> > +explicitly disable any of these. In particular, disabling SSE
> > +and MMX for kernel code is extremely useful. */
> >if (!ix86_arch_specified)
> >opts->x_ix86_isa_flags
> > - |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE |
> > OPTION_MASK_ISA_MMX
> > + |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
> > +| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
> > + ? 0 : OPTION_MASK_ISA_MMX)
> > | TARGET_SUBTARGET64_ISA_DEFAULT)
> > & ~opts->x_ix86_isa_flags_explicit);
>
> Please split the above into two clauses, the first that sets SSE and
> MMX by default, and the second to or with
>
> opts->x_ix86_isa_flags
> |= TARGET_SUBTARGET64_ISA_DEFAULT & ~opts->x_ix86_isa_flags_explicit
>
Like this?
/* Enable the SSE and MMX builtins by default. Don't enable MMX
ISA with TARGET_MMX_WITH_SSE by default. Do allow the user to
explicitly disable any of these. In particular, disabling SSE
and MMX for kernel code is extremely useful. */
if (!ix86_arch_specified)
{
opts->x_ix86_isa_flags
|= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE
| (TARGET_MMX_WITH_SSE_P (opts->x_ix86_isa_flags)
? 0 : OPTION_MASK_ISA_MMX))
& ~opts->x_ix86_isa_flags_explicit);
opts->x_ix86_isa_flags
|= (TARGET_SUBTARGET64_ISA_DEFAULT
& ~opts->x_ix86_isa_flags_explicit);
}
> > diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
> > index 238b3df3121..7b613658111 100644
> > --- a/gcc/config/i386/mmintrin.h
> > +++ b/gcc/config/i386/mmintrin.h
> > @@ -30,7 +30,7 @@
> > #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__
> > #pragma GCC push_options
> > #ifdef __x86_64__
> > -#pragma GCC target("sse,mmx")
> > +#pragma GCC target("sse2")
>
> You will need to involve __MMX_WITH_SSE__ here, probably to something like:
>
> #ifdef __MMX_WITH_SSE__
> #pragma GCC target("sse2")
> #elif defined __x86_64__
> #pragma GCC target("sse,mmx")
> #else
> #pragma GCC target("mmx")
> #endif
>
> > #else
> > #pragma GCC target("mmx")
> > #endif
> > @@ -315,7 +315,11 @@ _m_paddd (__m64 __m1, __m64 __m2)
> > /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> > #ifndef __SSE2__
> > #pragma GCC push_options
> > +#ifdef __x86_64__
>
> #ifdef __MMX_WITH_SSE__
>
> > +#pragma GCC target("sse2")
> > +#else
> > #pragma GCC target("sse2,mmx")
> > +#endif
> > #define __DISABLE_SSE2__
> > #endif /* __SSE2__ */
> >
> > @@ -427,7 +431,11 @@ _m_psubd (__m64 __m1, __m64 __m2)
> > /* Add the 64-bit values in M1 to the 64-bit values in M2. */
> > #ifndef __SSE2__
> > #pragma GCC push_options
> > +#ifdef __x86_64__
>
> #ifdef __MMX_WITH_SSE__
>
> > +#pragma GCC target("sse2")
> > +#else
> > #pragma GCC target("sse2,mmx")
> > +#endif
> > #define __DISABLE_SSE2__
> > #endif /* __SSE2__ */
> >
> > diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c
> > b/gcc/testsuite/gcc.target/i386/pr82483-1.c
I will do
diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
index 238b3df3121..c4b2e0c7b25 100644
--- a/gcc/config/i386/mmintrin.h
+++ b/gcc/config/i386/mmintrin.h
@@ -29,7 +29,9 @@
#if defined __x86_64__ &&
Re: [PATCH 40/40] i386: Also enable SSSE3 __m64 tests in 64-bit mode
On Thu, Feb 14, 2019 at 9:21 PM Uros Bizjak wrote:
>
> On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
> >
> > Since we now emulate MMX intrinsics with SSE in 64-bit mode, we can
> > enable SSSE3 __m64 tests even when AVX is enabled.
> >
> > PR target/89021
> > * gcc.target/i386/ssse3-pabsb.c: Also enable __m64 check in
> > 64-bit mode.
> > * gcc.target/i386/ssse3-pabsd.c: Likewise.
> > * gcc.target/i386/ssse3-pabsw.c: Likewise.
> > * gcc.target/i386/ssse3-palignr.c: Likewise.
> > * gcc.target/i386/ssse3-phaddd.c: Likewise.
> > * gcc.target/i386/ssse3-phaddsw.c: Likewise.
> > * gcc.target/i386/ssse3-phaddw.c: Likewise.
> > * gcc.target/i386/ssse3-phsubd.c: Likewise.
> > * gcc.target/i386/ssse3-phsubsw.c: Likewise.
> > * gcc.target/i386/ssse3-phsubw.c: Likewise.
> > * gcc.target/i386/ssse3-pmaddubsw.c: Likewise.
> > * gcc.target/i386/ssse3-pmulhrsw.c: Likewise.
> > * gcc.target/i386/ssse3-pshufb.c: Likewise.
> > * gcc.target/i386/ssse3-psignb.c: Likewise.
> > * gcc.target/i386/ssse3-psignd.c: Likewise.
> > * gcc.target/i386/ssse3-psignw.c: Likewise.
> > ---
> > gcc/testsuite/gcc.target/i386/ssse3-pabsb.c | 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-pabsd.c | 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-pabsw.c | 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-palignr.c | 6 +++---
> > gcc/testsuite/gcc.target/i386/ssse3-phaddd.c| 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c | 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-phaddw.c| 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-phsubd.c| 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c | 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-phsubw.c| 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c | 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c | 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-pshufb.c| 6 +++---
> > gcc/testsuite/gcc.target/i386/ssse3-psignb.c| 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-psignd.c| 4 ++--
> > gcc/testsuite/gcc.target/i386/ssse3-psignw.c| 4 ++--
> > 16 files changed, 34 insertions(+), 34 deletions(-)
> >
> > diff --git a/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > b/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > index 7caa1b6c3a6..eef4ccae222 100644
> > --- a/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > +++ b/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
> > @@ -15,7 +15,7 @@
> > #include "ssse3-vals.h"
> > #include
> >
> > -#ifndef __AVX__
> > +#if !defined __AVX__ || defined __x86_64__
>
> Better add || defined __x86_64__.
>
> I also wonder why AVX has to be disabled here. MMX should be orthogonal to
> AVX.
Actually, current trunk passes tests with #ifndef __AVX__ removed and:
gmake -k check-gcc
RUNTESTFLAGS="--target_board=unix\{,-m32\}\{,-mavx\}
i386.exp=ssse3-*.c"
=== gcc tests ===
Schedule of variations:
unix
unix/-mavx
unix/-m32
unix/-m32/-mavx
=== gcc Summary ===
# of expected passes128
Uros.
Index: gcc.target/i386/ssse3-pabsb.c
===
--- gcc.target/i386/ssse3-pabsb.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsb.c (working copy)
@@ -15,7 +15,6 @@
#include "ssse3-vals.h"
#include
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsb (int *i1, int *r)
@@ -24,7 +23,6 @@
*(__m64 *) r = _mm_abs_pi8 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -63,12 +61,10 @@
/* Manually compute the result */
compute_correct_result([i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsb ([i + 0], [0]);
ssse3_test_pabsb ([i + 2], [2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsb128 ([i + 0], r);
Index: gcc.target/i386/ssse3-pabsd.c
===
--- gcc.target/i386/ssse3-pabsd.c (revision 268854)
+++ gcc.target/i386/ssse3-pabsd.c (working copy)
@@ -16,7 +16,6 @@
#include
-#ifndef __AVX__
/* Test the 64-bit form */
static void
ssse3_test_pabsd (int *i1, int *r)
@@ -25,7 +24,6 @@
*(__m64 *) r = _mm_abs_pi32 (t1);
_mm_empty ();
}
-#endif
/* Test the 128-bit form */
static void
@@ -62,12 +60,10 @@
/* Manually compute the result */
compute_correct_result([i + 0], ck);
-#ifndef __AVX__
/* Run the 64-bit tests */
ssse3_test_pabsd ([i + 0], [0]);
ssse3_test_pabsd ([i + 2], [2]);
fail += chk_128 (ck, r);
-#endif
/* Run the 128-bit tests */
ssse3_test_pabsd128 ([i + 0], r);
Index: gcc.target/i386/ssse3-pabsw.c
===
--- gcc.target/i386/ssse3-pabsw.c (revision
[PATCH] v2: Fix excess warnings from -Wtype-limits with location wrappers (PR c++/88680)
On Thu, 2019-02-14 at 17:32 +0100, Jakub Jelinek wrote:
> On Thu, Feb 14, 2019 at 11:26:15AM -0500, David Malcolm wrote:
> > There's an asymmetry in the warning; it's looking for a comparison
> > of a
> > LHS expression against an RHS constant 0, spelled as "0".
> >
> > If we fold_for_warn on the RHS, then that folding introduces a
> > warning
> > for expressions that aren't spelled as "0" but can be folded to 0,
> > e.g., with:
> >
> > enum { FOO, BAR };
>
> So, shouldn't it be made symmetric? Check if one argument is literal
> 0
> before folding, and only if it is, fold_for_warn the other argument?
>
> Jakub
The reference to symmetry in my earlier email was somewhat
misleading, sorry.
The test happens after a canonicalization of the ordering happens
here, near the top of shorten_compare:
/* If first arg is constant, swap the args (changing operation
so value is preserved), for canonicalization. Don't do this if
the second arg is 0. */
so this already gives us symmetry.
Here's an updated version of the patch which add the fold_for_warn in
a slightly later place, and adds a comment, and some more test cases.
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
OK for trunk?
Blurb from v1:
PR c++/88680 reports excess warnings from -Wtype-limits after the C++
FE's use of location wrappers was extended in r267272 for cases such as:
const unsigned n = 8;
static_assert (n >= 0 && n % 2 == 0, "");
t.C:3:18: warning: comparison of unsigned expression >= 0 is always true
[-Wtype-limits]
3 | static_assert (n >= 0 && n % 2 == 0, "");
|~~^~~~
The root cause is that the location wrapper around "n" breaks the
suppression of the warning for the "if OP0 is a constant that is >= 0"
case.
This patch fixes it by calling fold_for_warn on OP0, extracting the
constant.
gcc/c-family/ChangeLog:
PR c++/88680
* c-common.c (shorten_compare): Call fold_for_warn on op0 when
implementing -Wtype-limits.
gcc/testsuite/ChangeLog:
PR c++/88680
* g++.dg/wrappers/pr88680.C: New test.
---
gcc/c-family/c-common.c | 13 ++--
gcc/testsuite/g++.dg/wrappers/pr88680.C | 56 +
2 files changed, 66 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/wrappers/pr88680.C
diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c
index ae23e59..c6856c9 100644
--- a/gcc/c-family/c-common.c
+++ b/gcc/c-family/c-common.c
@@ -3117,6 +3117,12 @@ shorten_compare (location_t loc, tree *op0_ptr, tree
*op1_ptr,
primop0 = op0;
primop1 = op1;
+ /* We want to fold unsigned comparisons of >= and < against zero.
+For these, we may also issue a warning if we have a non-constant
+compared against zero, where the zero was spelled as "0" (rather
+than merely folding to it).
+If we have at least one constant, then op1 is constant
+and we may have a non-constant expression as op0. */
if (!real1 && !real2 && integer_zerop (primop1)
&& TYPE_UNSIGNED (*restype_ptr))
{
@@ -3125,13 +3131,14 @@ shorten_compare (location_t loc, tree *op0_ptr, tree
*op1_ptr,
if OP0 is a constant that is >= 0, the signedness of
the comparison isn't an issue, so suppress the
warning. */
+ tree folded_op0 = fold_for_warn (op0);
bool warn =
warn_type_limits && !in_system_header_at (loc)
- && !(TREE_CODE (primop0) == INTEGER_CST
+ && !(TREE_CODE (folded_op0) == INTEGER_CST
&& !TREE_OVERFLOW (convert (c_common_signed_type (type),
-primop0)))
+folded_op0)))
/* Do not warn for enumeration types. */
- && (TREE_CODE (expr_original_type (primop0)) != ENUMERAL_TYPE);
+ && (TREE_CODE (expr_original_type (folded_op0)) != ENUMERAL_TYPE);
switch (code)
{
diff --git a/gcc/testsuite/g++.dg/wrappers/pr88680.C
b/gcc/testsuite/g++.dg/wrappers/pr88680.C
new file mode 100644
index 000..5497cda
--- /dev/null
+++ b/gcc/testsuite/g++.dg/wrappers/pr88680.C
@@ -0,0 +1,56 @@
+// { dg-do compile { target c++11 } }
+// { dg-options "-Wtype-limits" }
+
+const unsigned N = 8;
+const unsigned P = 0;
+
+enum { FOO, BAR };
+
+static_assert (N >= 0 && N % 2 == 0, "");
+static_assert (FOO >= 0, "");
+static_assert (FOO >= FOO, "");
+static_assert (FOO >= P, "");
+static_assert (BAR >= P, "");
+static_assert (N >= FOO, "");
+
+void test(unsigned n)
+{
+ if (N >= 0 && N % 2 == 0)
+return;
+ if (FOO >= 0)
+return;
+ if (FOO >= FOO)
+return;
+ if (FOO >= P)
+return;
+ if (BAR >= P)
+return;
+ if (N >= FOO)
+return;
+ if (n >= 0) // { dg-warning ">= 0 is always true" }
+return;
+ if (n < 0) // { dg-warning "< 0 is always false" }
+return;
+ if (n >= FOO)
Re: [PR fortran/88248, patch] - [F18] Bogus warning about obsolescent feature: Labeled DO statement
Commited as rev. 268895: Sendinggcc/fortran/ChangeLog Sendinggcc/fortran/symbol.c Sendinggcc/testsuite/ChangeLog Sendinggcc/testsuite/gfortran.dg/f2018_obs.f90 Adding gcc/testsuite/gfortran.dg/pr88248.f90 Transmitting file data .done Committing transaction... Committed revision 268895. Thanks for the review, Jerry. Harald On 02/14/19 01:45, Jerry DeLisle wrote: > On 2/13/19 2:38 PM, Harald Anlauf wrote: >> The attached patch moves the check for labeled DO statements to >> the place where a label is referenced instead of where a label >> was defined, which lead to false positives. >> >> Regtested on x86_64-pc-linux-gnu. >> >> OK for trunk? >> > > Thanks Harald, > > All OK with test case. > > Jerry >
Re: [PATCH 40/40] i386: Also enable SSSE3 __m64 tests in 64-bit mode
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote: > > Since we now emulate MMX intrinsics with SSE in 64-bit mode, we can > enable SSSE3 __m64 tests even when AVX is enabled. > > PR target/89021 > * gcc.target/i386/ssse3-pabsb.c: Also enable __m64 check in > 64-bit mode. > * gcc.target/i386/ssse3-pabsd.c: Likewise. > * gcc.target/i386/ssse3-pabsw.c: Likewise. > * gcc.target/i386/ssse3-palignr.c: Likewise. > * gcc.target/i386/ssse3-phaddd.c: Likewise. > * gcc.target/i386/ssse3-phaddsw.c: Likewise. > * gcc.target/i386/ssse3-phaddw.c: Likewise. > * gcc.target/i386/ssse3-phsubd.c: Likewise. > * gcc.target/i386/ssse3-phsubsw.c: Likewise. > * gcc.target/i386/ssse3-phsubw.c: Likewise. > * gcc.target/i386/ssse3-pmaddubsw.c: Likewise. > * gcc.target/i386/ssse3-pmulhrsw.c: Likewise. > * gcc.target/i386/ssse3-pshufb.c: Likewise. > * gcc.target/i386/ssse3-psignb.c: Likewise. > * gcc.target/i386/ssse3-psignd.c: Likewise. > * gcc.target/i386/ssse3-psignw.c: Likewise. > --- > gcc/testsuite/gcc.target/i386/ssse3-pabsb.c | 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-pabsd.c | 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-pabsw.c | 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-palignr.c | 6 +++--- > gcc/testsuite/gcc.target/i386/ssse3-phaddd.c| 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c | 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-phaddw.c| 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-phsubd.c| 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c | 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-phsubw.c| 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c | 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c | 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-pshufb.c| 6 +++--- > gcc/testsuite/gcc.target/i386/ssse3-psignb.c| 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-psignd.c| 4 ++-- > gcc/testsuite/gcc.target/i386/ssse3-psignw.c| 4 ++-- > 16 files changed, 34 insertions(+), 34 deletions(-) > > diff --git a/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c > b/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c > index 7caa1b6c3a6..eef4ccae222 100644 > --- a/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c > +++ b/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c > @@ -15,7 +15,7 @@ > #include "ssse3-vals.h" > #include > > -#ifndef __AVX__ > +#if !defined __AVX__ || defined __x86_64__ Better add || defined __x86_64__. I also wonder why AVX has to be disabled here. MMX should be orthogonal to AVX. Uros. > /* Test the 64-bit form */ > static void > ssse3_test_pabsb (int *i1, int *r) > @@ -63,7 +63,7 @@ TEST (void) >/* Manually compute the result */ >compute_correct_result([i + 0], ck); > > -#ifndef __AVX__ > +#if !defined __AVX__ || defined __x86_64__ >/* Run the 64-bit tests */ >ssse3_test_pabsb ([i + 0], [0]); >ssse3_test_pabsb ([i + 2], [2]); > diff --git a/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c > b/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c > index 3a73cf01170..60043bad4a4 100644 > --- a/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c > +++ b/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c > @@ -16,7 +16,7 @@ > > #include > > -#ifndef __AVX__ > +#if !defined __AVX__ || defined __x86_64__ > /* Test the 64-bit form */ > static void > ssse3_test_pabsd (int *i1, int *r) > @@ -62,7 +62,7 @@ TEST (void) >/* Manually compute the result */ >compute_correct_result([i + 0], ck); > > -#ifndef __AVX__ > +#if !defined __AVX__ || defined __x86_64__ >/* Run the 64-bit tests */ >ssse3_test_pabsd ([i + 0], [0]); >ssse3_test_pabsd ([i + 2], [2]); > diff --git a/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c > b/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c > index 67e4721b8e6..dd0caa9783f 100644 > --- a/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c > +++ b/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c > @@ -16,7 +16,7 @@ > > #include > > -#ifndef __AVX__ > +#if !defined __AVX__ || defined __x86_64__ > /* Test the 64-bit form */ > static void > ssse3_test_pabsw (int *i1, int *r) > @@ -64,7 +64,7 @@ TEST (void) >/* Manually compute the result */ >compute_correct_result ([i + 0], ck); > > -#ifndef __AVX__ > +#if !defined __AVX__ || defined __x86_64__ >/* Run the 64-bit tests */ >ssse3_test_pabsw ([i + 0], [0]); >ssse3_test_pabsw ([i + 2], [2]); > diff --git a/gcc/testsuite/gcc.target/i386/ssse3-palignr.c > b/gcc/testsuite/gcc.target/i386/ssse3-palignr.c > index dbee9bee4aa..f266f7805b8 100644 > --- a/gcc/testsuite/gcc.target/i386/ssse3-palignr.c > +++ b/gcc/testsuite/gcc.target/i386/ssse3-palignr.c > @@ -17,7 +17,7 @@ > #include > #include > > -#ifndef __AVX__ > +#if !defined __AVX__ || defined __x86_64__ > /* Test the 64-bit form */ > static void > ssse3_test_palignr (int *i1, int *i2, unsigned int imm,
Re: Go patch committed: Compile thunks with -Os
On Thu, Feb 14, 2019 at 1:41 AM Richard Biener
wrote:
>
> On Thu, Feb 14, 2019 at 2:21 AM Ian Lance Taylor wrote:
> >
> > Nikhil Benesch noticed that changes in the GCC backend were making the
> > use of defer functions that call recover less efficient. A defer
> > thunk is a generated function that looks like this (this is the entire
> > function body):
> >
> > if !runtime.setdeferretaddr() {
> > deferredFunction()
> > }
> > L:
> >
> > The idea is that the address of the label passed to setdeferretaddr is
> > the address to which deferredFunction returns. The code in canrecover
> > compares the return address of the function to this saved address to
> > see whether the recover function can return non-nil. This is
> > explained in marginally more detail at
> > https://www.airs.com/blog/archives/376 .
> >
> > When the return address does not match, the canrecover code does a
> > more costly check that requires unwinding the stack. What Nikhil
> > Benesch noticed is that we were always taking that fallback.
> >
> > It turned out that the label address passed to setdeferretaddr was not
> > the label to which the deferred function would return. And that was
> > because the epilogue was being duplicated by the bb-reorder pass, and
> > the label was moved to one copy of the epilogue while the deferred
> > function returned to the other epilogue.
> >
> > Of course there is no reason to duplicate the epilogue in such a small
> > function. One easy way to disable that epilogue duplication is to
> > compile the function with -Os. That is what this patch does. This
> > patch compiles all thunks, not just defer thunks, with -Os, but since
> > they are all small that does no harm.
> >
> > Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
> > to mainline.
>
> I think an easier way would have been to mark it with the cold attribute?
Maybe. The thunks aren't actually cold, though. It wouldn't make
sense to move the thunks to a cold part of the executable.
Ian
Backports for GCC 8
I backported my fixes for PR85805 (combine), PR88892 (rs6000), PR86684 and the first part of PR87149 (rs6000) to the GCC 8 branch. Segher 2019-02-14 Segher Boessenkool Backport from trunk 2018-08-31 Segher Boessenkool PR target/86684 PR target/87149 * config/rs6000/rs6000.md (lrounddi2): Gate on TARGET_FPRND. 2019-02-14 Segher Boessenkool Backport from trunk 2019-01-18 Segher Boessenkool PR target/88892 * config/rs6000/rs6000.md (*movsi_from_df): Allow only register operands. 2019-02-14 Segher Boessenkool Backport from trunk 2018-07-26 Segher Boessenkool PR rtl-optimization/85805 * combine.c (reg_nonzero_bits_for_combine): Only use the last set value for hard registers if that was written in the same mode.
Re: [PATCH 37/40] i386: Allow MMX intrinsic emulation with SSE
On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu wrote: > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA > by default with TARGET_MMX_WITH_SSE. > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit > mode since MMX intrinsics can be emulated wit SSE. > > gcc/ > > PR target/89021 > * config/i386/i386-builtin.def: Enable MMX intrinsics with > SSE/SSE2/SSSE3. > * config/i386/i386.c (ix86_option_override_internal): Don't > enable MMX ISA with TARGET_MMX_WITH_SSE by default. > (ix86_init_mmx_sse_builtins): Enable MMX intrinsics with > SSE/SSE2/SSSE3. > (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX > intrinsics with TARGET_MMX_WITH_SSE. > * config/i386/mmintrin.h: Don't require MMX in 64-bit mode. > > gcc/testsuite/ > > PR target/89021 > * gcc.target/i386/pr82483-1.c: Error only on ia32. > * gcc.target/i386/pr82483-2.c: Likewise. > --- > gcc/config/i386/i386-builtin.def | 126 +++--- > gcc/config/i386/i386.c| 46 ++-- > gcc/config/i386/mmintrin.h| 10 +- > gcc/testsuite/gcc.target/i386/pr82483-1.c | 2 +- > gcc/testsuite/gcc.target/i386/pr82483-2.c | 2 +- > 5 files changed, 110 insertions(+), 76 deletions(-) > > diff --git a/gcc/config/i386/i386-builtin.def > b/gcc/config/i386/i386-builtin.def > index 88005f4687f..10a9d631f29 100644 > --- a/gcc/config/i386/i386-builtin.def > +++ b/gcc/config/i386/i386-builtin.def > @@ -100,7 +100,7 @@ BDESC (0, 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", > IX86_BUILTIN_FNSTSW, UNKN > BDESC (0, 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, > UNKNOWN, (int) VOID_FTYPE_VOID) > > /* MMX */ > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", > IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID) > +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_emms, > "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID) > > /* 3DNow! */ > BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_femms, "__builtin_ia32_femms", > IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID) > @@ -442,68 +442,68 @@ BDESC (0, 0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", > IX86_BUILTIN_RORQI, UNKNO > BDESC (0, 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, > UNKNOWN, (int) UINT16_FTYPE_UINT16_INT) > > /* MMX */ > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv8qi3, > "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) > V8QI_FTYPE_V8QI_V8QI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv4hi3, > "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv2si3, > "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) > V2SI_FTYPE_V2SI_V2SI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv8qi3, > "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) > V8QI_FTYPE_V8QI_V8QI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv4hi3, > "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv2si3, > "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) > V2SI_FTYPE_V2SI_V2SI) > - > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv8qi3, > "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) > V8QI_FTYPE_V8QI_V8QI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv4hi3, > "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv8qi3, > "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) > V8QI_FTYPE_V8QI_V8QI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv4hi3, > "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv8qi3, > "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) > V8QI_FTYPE_V8QI_V8QI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv4hi3, > "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv8qi3, > "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) > V8QI_FTYPE_V8QI_V8QI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv4hi3, > "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > - > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_mulv4hi3, > "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_smulv4hi3_highpart, > "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) > V4HI_FTYPE_V4HI_V4HI) > - > -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", > IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) > -BDESC
Contents of PO file 'cpplib-9.1-b20190203.da.po'
cpplib-9.1-b20190203.da.po.gz Description: Binary data The Translation Project robot, in the name of your translation coordinator.
New Danish PO file for 'cpplib' (version 9.1-b20190203)
Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'cpplib' has been submitted by the Danish team of translators. The file is available at: https://translationproject.org/latest/cpplib/da.po (This file, 'cpplib-9.1-b20190203.da.po', has just now been sent to you in a separate email.) All other PO files for your package are available in: https://translationproject.org/latest/cpplib/ Please consider including all of these in your next release, whether official or a pretest. Whenever you have a new distribution with a new version number ready, containing a newer POT file, please send the URL of that distribution tarball to the address below. The tarball may be just a pretest or a snapshot, it does not even have to compile. It is just used by the translators when they need some extra translation context. The following HTML page has been updated: https://translationproject.org/domain/cpplib.html If any question arises, please contact the translation coordinator. Thank you for all your work, The Translation Project robot, in the name of your translation coordinator.
Go patch committed: Error for duplicate map string keys in composite literal
This Go frontend patch by Ben Shi gives an error for duplicate string
keys in a map composite literal. This is a step toward fixing
https://golang.org/issue/28104. Bootstrapped and ran Go testsuite on
x86_64-pc-linux-gnu. Committed to mainline.
Ian
Index: gcc/go/gofrontend/MERGE
===
--- gcc/go/gofrontend/MERGE (revision 268828)
+++ gcc/go/gofrontend/MERGE (working copy)
@@ -1,4 +1,4 @@
-6d03c4c8ca320042bd550d44c0f25575c5311ac2
+a487c86418488f6a17dab4f9945e2a5d495e3ddb
The first line of this file holds the git revision number of the last
merge done from the gofrontend repository.
Index: gcc/go/gofrontend/expressions.cc
===
--- gcc/go/gofrontend/expressions.cc(revision 268554)
+++ gcc/go/gofrontend/expressions.cc(working copy)
@@ -673,7 +673,7 @@ Type_expression : public Expression
{ go_unreachable(); }
void do_dump_expression(Ast_dump_context*) const;
-
+
private:
// The type which we are representing as an expression.
Type* type_;
@@ -2950,7 +2950,7 @@ Const_expression::do_numeric_constant_va
return false;
Expression* e = this->constant_->const_value()->expr();
-
+
this->seen_ = true;
bool r = e->numeric_constant_value(nc);
@@ -3298,10 +3298,10 @@ class Iota_expression : public Parser_ex
Expression*
do_copy()
{ go_unreachable(); }
-
+
void
do_dump_expression(Ast_dump_context* ast_dump_context) const
- { ast_dump_context->ostream() << "iota"; }
+ { ast_dump_context->ostream() << "iota"; }
};
// Make an iota expression. This is only called for one case: the
@@ -4174,7 +4174,7 @@ Unary_expression::base_is_static_initial
// know the address of this expression is being taken, we must always
// check for nil.
Unary_expression::Nil_check_classification
-Unary_expression::requires_nil_check(Gogo* gogo)
+Unary_expression::requires_nil_check(Gogo* gogo)
{
go_assert(this->op_ == OPERATOR_MULT);
go_assert(this->expr_->type()->points_to() != NULL);
@@ -7311,14 +7311,14 @@ Bound_method_expression::do_dump_express
{
if (this->expr_type_ != NULL)
ast_dump_context->ostream() << "(";
- ast_dump_context->dump_expression(this->expr_);
- if (this->expr_type_ != NULL)
+ ast_dump_context->dump_expression(this->expr_);
+ if (this->expr_type_ != NULL)
{
ast_dump_context->ostream() << ":";
ast_dump_context->dump_type(this->expr_type_);
ast_dump_context->ostream() << ")";
}
-
+
ast_dump_context->ostream() << "." << this->function_->name();
}
@@ -7461,7 +7461,7 @@ Builtin_call_expression::do_lower(Gogo*,
farg = farg->expr()->field_reference_expression();
}
}
-
+
if (this->is_constant())
{
Numeric_constant nc;
@@ -10812,7 +10812,7 @@ void
Call_result_expression::do_dump_expression(Ast_dump_context* ast_dump_context)
const
{
- // FIXME: Wouldn't it be better if the call is assigned to a temporary
+ // FIXME: Wouldn't it be better if the call is assigned to a temporary
// (struct) and the fields are referenced instead.
ast_dump_context->ostream() << this->index_ << "@(";
ast_dump_context->dump_expression(this->call_);
@@ -10930,8 +10930,8 @@ Index_expression::do_lower(Gogo*, Named_
// (expr[expr:expr:expr], expr[expr:expr] or expr[expr]) to a dump context.
void
-Index_expression::dump_index_expression(Ast_dump_context* ast_dump_context,
- const Expression* expr,
+Index_expression::dump_index_expression(Ast_dump_context* ast_dump_context,
+ const Expression* expr,
const Expression* start,
const Expression* end,
const Expression* cap)
@@ -10955,10 +10955,10 @@ Index_expression::dump_index_expression(
// Dump ast representation for an index expression.
void
-Index_expression::do_dump_expression(Ast_dump_context* ast_dump_context)
+Index_expression::do_dump_expression(Ast_dump_context* ast_dump_context)
const
{
- Index_expression::dump_index_expression(ast_dump_context, this->left_,
+ Index_expression::dump_index_expression(ast_dump_context, this->left_,
this->start_, this->end_,
this->cap_);
}
@@ -11471,10 +11471,10 @@ Array_index_expression::do_get_backend(T
// Dump ast representation for an array index expression.
void
-Array_index_expression::do_dump_expression(Ast_dump_context* ast_dump_context)
+Array_index_expression::do_dump_expression(Ast_dump_context* ast_dump_context)
const
{
- Index_expression::dump_index_expression(ast_dump_context, this->array_,
+ Index_expression::dump_index_expression(ast_dump_context, this->array_,
this->start_, this->end_,
this->cap_);
}
@@ -11697,7
New Danish PO file for 'gcc' (version 9.1-b20190203)
Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the Danish team of translators. The file is available at: https://translationproject.org/latest/gcc/da.po (This file, 'gcc-9.1-b20190203.da.po', has just now been sent to you in a separate email.) All other PO files for your package are available in: https://translationproject.org/latest/gcc/ Please consider including all of these in your next release, whether official or a pretest. Whenever you have a new distribution with a new version number ready, containing a newer POT file, please send the URL of that distribution tarball to the address below. The tarball may be just a pretest or a snapshot, it does not even have to compile. It is just used by the translators when they need some extra translation context. The following HTML page has been updated: https://translationproject.org/domain/gcc.html If any question arises, please contact the translation coordinator. Thank you for all your work, The Translation Project robot, in the name of your translation coordinator.
Re: Fortran vector math header
On Tue, 5 Feb 2019, Martin Liška wrote: > #ifdef NATIVE_SYSTEM_HEADER_DIR >/* Then search: /usr/include/finclude/ */ >add_sysrooted_hdrs_prefix (, NATIVE_SYSTEM_HEADER_DIR > "/finclude/", > - NULL, 0, 0, false); > + NULL, 0, 0, 0); > #endif The comment needs updating to reflect that the search no longer uses multilib suffixes. The driver changes are OK with that change. -- Joseph S. Myers jos...@codesourcery.com
[Committed][PATCH][GCC][Arm] Fix test directive
Hi All,
This patch fixes a failing testcase due to a use of dg-options instead of
dg-additional-options.
Committed under the GCC obvious
Bootstrapped Regtested on arm-none-eabi and no issues.
Ok for trunk?
Thanks,
Tamar
gcc/testsuite/ChangeLog:
2019-02-14 Tamar Christina
* gcc.target/arm/pr88850.c: change options to additional option.
--
diff --git a/gcc/testsuite/gcc.target/arm/pr88850.c b/gcc/testsuite/gcc.target/arm/pr88850.c
index 66d0e9e620aef4f092a33ead79521901b5d89636..6edd6bcee54dbc843b539ff67399ee7a30a707e4 100644
--- a/gcc/testsuite/gcc.target/arm/pr88850.c
+++ b/gcc/testsuite/gcc.target/arm/pr88850.c
@@ -1,6 +1,6 @@
/* PR target/88850 */
/* { dg-do compile } */
-/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fdump-rtl-final" } */
+/* { dg-additional-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fdump-rtl-final" } */
/* { dg-require-effective-target arm_neon_ok } */
typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8)));
[PATCH 41/40] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE
You will also need the following (untested) patch that prevents
allocation of MMX registers with TARGET_MMX_WITH_SSE in several insn
patterns.
2019-02-14 Uroš Bizjak
PR target/89021
* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
* config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto.
(*vec_concatv2sf_sse): Ditto.
(*vec_concatv2si_sse4_1): Ditto.
(*vec_concatv2si): Ditto.
(*vec_concatv4si_0): Ditto.
(*vec_concatv2di_0): Ditto.
Uros.
Index: config/i386/i386.md
===
--- config/i386/i386.md (revision 268854)
+++ config/i386/i386.md (working copy)
@@ -3855,6 +3855,10 @@
(const_string "avx512bw")
]
(const_string "*")))
+ (set (attr "mmx_isa")
+ (if_then_else (eq_attr "alternative" "5,6")
+ (const_string "native")
+ (const_string "*")))
(set (attr "type")
(cond [(eq_attr "alternative" "0,1,2,4")
(const_string "multi")
Index: config/i386/sse.md
===
--- config/i386/sse.md (revision 268855)
+++ config/i386/sse.md (working copy)
@@ -7241,6 +7241,10 @@
(const_string "mmxmov")
]
(const_string "sselog")))
+ (set (attr "mmx_isa")
+ (if_then_else (eq_attr "alternative" "7,8")
+ (const_string "native")
+ (const_string "*")))
(set (attr "prefix_data16")
(if_then_else (eq_attr "alternative" "3,4")
(const_string "1")
@@ -7276,7 +7280,8 @@
movss\t{%1, %0|%0, %1}
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
+ [(set_attr "mmx_isa" "*,*,native,native")
+ (set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
(set_attr "mode" "V4SF,SF,DI,DI")])
(define_insn "*vec_concatv4sf"
@@ -14549,6 +14554,10 @@
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,noavx,avx,avx512dq,noavx,noavx,avx,*,*,*")
+ (set (attr "mmx_isa")
+ (if_then_else (eq_attr "alternative" "8,9")
+ (const_string "native")
+ (const_string "*")))
(set (attr "type")
(cond [(eq_attr "alternative" "7")
(const_string "ssemov")
@@ -14586,6 +14595,7 @@
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
[(set_attr "isa" "sse2,sse2,*,*,*,*")
+ (set_attr "mmx_isa" "*,*,*,*,native,native")
(set_attr "type" "sselog,ssemov,sselog,ssemov,mmxcvt,mmxmov")
(set_attr "mode" "TI,TI,V4SF,SF,DI,DI")])
@@ -14615,7 +14625,8 @@
"@
%vmovq\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
+ [(set_attr "mmx_isa" "*,native")
+ (set_attr "type" "ssemov")
(set_attr "prefix" "maybe_vex,orig")
(set_attr "mode" "TI")])
@@ -14690,6 +14701,7 @@
%vmovq\t{%1, %0|%0, %1}
movq2dq\t{%1, %0|%0, %1}"
[(set_attr "isa" "x64,*,*")
+ (set_attr "mmx_isa" "*,*,native")
(set_attr "type" "ssemov")
(set_attr "prefix_rex" "1,*,*")
(set_attr "prefix" "maybe_vex,maybe_vex,orig")
Re: Provide __start_minfo/__stop_minfo for linkers that don't (PR d/87864)
On Thu, 14 Feb 2019 at 11:13, Rainer Orth wrote:
>
> Hi Iain,
>
> > On Tue, 29 Jan 2019 at 13:24, Rainer Orth
> > wrote:
> >>
> >> Solaris ld only gained support for section bracketing in Solaris 11.4.
> >> Fortunately, in gdc it is only used for the minfo section, so it's easy
> >> to provide a workaround by adding two additional startup files
> >> drt{begin,end}.o which define __start_minfo and __stop_minfo.
> >>
> >> This patch does just that.
> >>
> >> I've raised a couple of questions in the PR already:
> >>
> >> * I've introduced a new -dstartfiles option which triggers the use of
> >> libgphobos.spec even with -nophoboslib. Since it's effectively
> >> internal to the build system, I'm not currently documenting it.
> >>
> >> * I'm reading the spec file addition from a file: keeping it in a make
> >> variable would be extremely messy due to the necessary quoting.
> >>
> >> * I've chosen to use -Wc instead of -Xcompiler throughout: it's way
> >> shorter when more options need to be passed and it can take several
> >> comma-separated options at once.
> >>
> >> * libdruntime/gcc/drtstuff.c needs a copyright notice unless one wants
> >> to keep it in the public domain (also plausible). Effectively
> >> something for Iain to decide.
> >>
> >> Bootstrapped without regressions on i386-pc-solaris2.11 (Solaris 11.3),
> >> no regressions compared to Solaris 11.4 test results.
> >>
> >> Rainer
> >>
> >> --
> >> -
> >> Rainer Orth, Center for Biotechnology, Bielefeld University
> >>
> >>
> >> 2018-11-20 Rainer Orth
> >>
> >> libphobos:
> >> PR d/87864
> >> * configure.ac [!DCFG_MINFO_BRACKETING] (DRTSTUFF_SPEC): New
> >> variable.
> >> Substitute it.
> >> * libdruntime/m4/druntime/os.m4 (DRUNTIME_OS_MINFO_BRACKETING):
> >> New automake conditional.
> >> * configure: Regenerate.
> >> * libdruntime/gcc/drtstuff.c: New file.
> >> * libdruntime/Makefile.am [!DRUNTIME_OS_MINFO_BRACKETING]
> >> (DRTSTUFF, toolexeclib_DATA): New variables.
> >> (gcc/drtbegin.lo, gcc/drtend.lo): New rules.
> >> (libgdruntime_la_LDFLAGS): Add -dstartfiles -Bgcc -B../src.
> >> (libgdruntime_la_DEPENDENCIES): New variable.
> >> * src/Makefile.am (libgphobos_la_LDFLAGS): Add -dstartfiles
> >> -B../libdruntime/gcc.
> >> * libdruntime/Makefile.in, src/Makefile.in: Regenerate.
> >> * Makefile.in, testsuite/Makefile.in: Regenerate.
> >> * libdruntime/rt/sections_elf_shared.d (Minfo_Bracketing): Don't
> >> assert.
> >> * src/drtstuff.spec: New file.
> >> * src/libgphobos.spec.in (DRTSTUFF_SPEC): Substitute.
> >> (*lib): Only pass SPEC_PHOBOS_DEPS without -debuglib, -defaultlib,
> >> -nophoboslib.
> >> * testsuite/testsuite_flags.in <--gdcldflags> (GDCLDFLAGS): Add
> >> -B${BUILD_DIR}/libdruntime/gcc.
> >>
> >> * libdruntime/Makefile.am (unittest_static_LDFLAGS): Use -Wc
> >> instead of -Xcompiler.
> >> (libgdruntime_t_la_LDFLAGS): Likewise.
> >> (unittest_LDFLAGS): Likewise.
> >> * src/Makefile.am (unittest_static_LDFLAGS): Likewise.
> >> (libgphobos_t_la_LDFLAGS): Likewise.
> >> (unittest_LDFLAGS): Likewise.
> >>
> >> gcc/d:
> >> PR d/87864
> >> * lang.opt (dstartfiles): New option.
> >> * d-spec.cc (need_spec): New variable.
> >> (lang_specific_driver) : Enable need_spec.
> >> (lang_specific_pre_link): Also load libgphobos.spec if need_spec.
> >>
> >> gcc/testsuite:
> >> PR d/87864
> >> * lib/gdc.exp (gdc_link_flags): Add path to drtbegin.o/drtend.o if
> >> present.
> >>
> >
> > I'd say go for it. I see that there's a tab that found its way into
> > lib/gdc.exp, and there's a copyright notice that needs fixing up.
>
> that tab is both due the gcc convention (GCS actually) of using tabs
> instead of 8 spaces, unlike D, and Emacs' tcl mode that follows it.
> I've now fixed it up to be consistent with the rest of gdc.exp.
>
I didn't know that applied to dejagnu test scripts. Feel free to
re-tab the file so it's consistent, I only noticed because of the
mixed 8 spaces/tabs.
> For the drtstuff.c copyright notice, I've taken GPLv3+runtime exception,
> just like the libgcc/crtstuff.c one where this snippet effectively comes
> from. Since this file is gdc-only, I guess that's ok?
>
That's fine. There is no rationale for gdc-specific parts of the D
runtime library to be under any other non-GPL license.
> I'm running an i686-pc-linux-gnu bootstrap right now where this patch
> should be a no-op, just to make sure again that it doesn't break
> anything. Unless you see some error or there's a problem with the
> choice of license, I'm going to check it in afterwards.
>
OK, thanks.
--
Iain
Re: [PATCH] Update libstdc++ documentation for implementation status
On 14/02/19 15:12 +, Jonathan Wakely wrote: * doc/xml/manual/status_cxx2017.xml: Add P0063R3 to status table. * doc/html/*: Regenerate. And another update, thanks to Ulrich for pointing this out. Committed to trunk. commit 0fcc9bcdcb3923e50c6261bcdeb6f26694b3e245 Author: Jonathan Wakely Date: Thu Feb 14 17:44:28 2019 + Update libstdc++ documentation for C++2a implementation status * doc/xml/manual/status_cxx2020.xml: Update P0887R1 status. * doc/html/*: Regenerate. diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2020.xml b/libstdc++-v3/doc/xml/manual/status_cxx2020.xml index 0e56ebc6f01..e2c598190da 100644 --- a/libstdc++-v3/doc/xml/manual/status_cxx2020.xml +++ b/libstdc++-v3/doc/xml/manual/status_cxx2020.xml @@ -521,14 +521,13 @@ Feature-testing recommendations for C++. - The identity metafunction http://www.w3.org/1999/xlink; xlink:href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2018/p0887r1.pdf;> P0887R1 - + 9.1
Re: [PATCH][GCC][Arm] Add HF modes to ANY iterators
On 2/14/19 4:52 PM, Tamar Christina wrote:
Hi Kyrill,
I couldn't find a way to actually generate this case so I have instead removed
the entry from ANY128. New patch and changelog below.
--
The iterator ANY64 are used in various general split patterns and is supposed
to contain all 64 bit modes.
For some reason the pattern has HI but not HF. This adds HF so that general
64 bit splits are generated for these modes as well. These are required
by various split patterns that expect them to be there.
Bootstrapped Regtested on arm-none-gnueabihf and no issues.
Ok for trunk?
Ok.
Thanks,
Kyrill
Thanks,
Tamar
gcc/ChangeLog:
2019-02-14 Tamar Christina
PR target/88850
* config/arm/iterators.md (ANY64): Add V4HF.
gcc/testsuite/ChangeLog:
2019-02-14 Tamar Christina
PR target/88850
* gcc.target/arm/pr88850-2.c: New test.
* lib/target-supports.exp
(check_effective_target_arm_neon_softfp_fp16_ok_nocache,
check_effective_target_arm_neon_softfp_fp16_ok,
add_options_for_arm_neon_softfp_fp16): New.
The 02/13/2019 10:57, Kyrill Tkachov wrote:
Hi Tamar
On 2/13/19 10:33 AM, Tamar Christina wrote:
Hi All,
The iterators ANY64 and ANY128 are used in various general split
patterns and
are supposed to contain any 64 bit and 128 bit modes respectively.
For some reason these patterns had HI but not HF. This adds HF so
that general
64 and 128 bit splits are generated for these modes as well. These
are required
by various split patterns that expect them to be there.
Bootstrapped Regtested on aarch64-none-linux-gnu and issues.
Please do this on an arm-none-linux-gnueabihf target.
Though I suspect this is just a placeholder from a boilerplate ;)
Ok for trunk?
Thanks,
Tamar
gcc/ChangeLog:
2019-02-13 Tamar Christina
PR target/88850
* config/arm/iterators.md (ANY64): Add V4HF,
(ANY128): Add V8HF.
gcc/testsuite/ChangeLog:
2019-02-13 Tamar Christina
PR target/88850
* gcc.target/arm/pr88850-2.c: New test.
--
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index
c33e572c3e89c3dc5848bd6b825d618481247558..4ac048a0c609273691c264c97ccf6cd47b43943b
100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -24,11 +24,11 @@
;;
;; A list of modes that are exactly 64 bits in size. This is used to expand
-;; some splits that are the same for all modes when operating on ARM
+;; some splits that are the same for all modes when operating on ARM
;; registers.
-(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
+(define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF])
-(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
+(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V8HF V4SI V4SF])
I see ANY128 is used in the move_hi_quad_ and move_lo_quad_
expanders in neon.md.
Does the use of HF modes need guarding by TARGET_NEON_FP16INST there?
Would be good to see a test exercising this change...
;; A list of integer modes that are up to one word long
(define_mode_iterator QHSI [QI HI SI])
diff --git a/gcc/testsuite/gcc.target/arm/pr88850-2.c
b/gcc/testsuite/gcc.target/arm/pr88850-2.c
new file mode 100644
index
..fee2a0fe3a227ea4652bea2aa0e7335d20a7e9b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr88850-2.c
@@ -0,0 +1,19 @@
+/* PR target/88850. */
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -march=armv7-a -mfloat-abi=softfp
-fdump-rtl-final" } */
+/* { dg-add-options arm_neon_fp16 } */
+/* { dg-require-effective-target arm_soft_ok } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+
arm_soft_ok checks if it's okay to add -mfloat-abi=soft, but you're adding
softfp.
Is this right?
Thanks,
Kyrill
+#include
+
+extern void c (int, float16x4_t);
+
+void a (float16x4_t b)
+{
+ c (0, b);
+}
+
+
+/* Check that these 64-bit moves are done in SI. */
+/* { dg-final { scan-rtl-dump "_movsi_vfp" "final" } } *
Re: [PATCH][GCC][Arm] Add HF modes to ANY iterators
Hi Kyrill,
I couldn't find a way to actually generate this case so I have instead removed
the entry from ANY128. New patch and changelog below.
--
The iterator ANY64 are used in various general split patterns and is supposed
to contain all 64 bit modes.
For some reason the pattern has HI but not HF. This adds HF so that general
64 bit splits are generated for these modes as well. These are required
by various split patterns that expect them to be there.
Bootstrapped Regtested on arm-none-gnueabihf and no issues.
Ok for trunk?
Thanks,
Tamar
gcc/ChangeLog:
2019-02-14 Tamar Christina
PR target/88850
* config/arm/iterators.md (ANY64): Add V4HF.
gcc/testsuite/ChangeLog:
2019-02-14 Tamar Christina
PR target/88850
* gcc.target/arm/pr88850-2.c: New test.
* lib/target-supports.exp
(check_effective_target_arm_neon_softfp_fp16_ok_nocache,
check_effective_target_arm_neon_softfp_fp16_ok,
add_options_for_arm_neon_softfp_fp16): New.
The 02/13/2019 10:57, Kyrill Tkachov wrote:
> Hi Tamar
>
> On 2/13/19 10:33 AM, Tamar Christina wrote:
> > Hi All,
> >
> > The iterators ANY64 and ANY128 are used in various general split
> > patterns and
> > are supposed to contain any 64 bit and 128 bit modes respectively.
> >
> > For some reason these patterns had HI but not HF. This adds HF so
> > that general
> > 64 and 128 bit splits are generated for these modes as well. These
> > are required
> > by various split patterns that expect them to be there.
> >
> > Bootstrapped Regtested on aarch64-none-linux-gnu and > still running> issues.
> >
> Please do this on an arm-none-linux-gnueabihf target.
>
> Though I suspect this is just a placeholder from a boilerplate ;)
>
> > Ok for trunk?
> >
> > Thanks,
> > Tamar
> >
> > gcc/ChangeLog:
> >
> > 2019-02-13 Tamar Christina
> >
> > PR target/88850
> > * config/arm/iterators.md (ANY64): Add V4HF,
> > (ANY128): Add V8HF.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2019-02-13 Tamar Christina
> >
> > PR target/88850
> > * gcc.target/arm/pr88850-2.c: New test.
> >
> > --
>
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index
> c33e572c3e89c3dc5848bd6b825d618481247558..4ac048a0c609273691c264c97ccf6cd47b43943b
> 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -24,11 +24,11 @@
>
> ;;
>
> ;; A list of modes that are exactly 64 bits in size. This is used to expand
> -;; some splits that are the same for all modes when operating on ARM
> +;; some splits that are the same for all modes when operating on ARM
> ;; registers.
> -(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
> +(define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF])
>
> -(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
> +(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V8HF V4SI V4SF])
>
>
> I see ANY128 is used in the move_hi_quad_ and move_lo_quad_
> expanders in neon.md.
> Does the use of HF modes need guarding by TARGET_NEON_FP16INST there?
> Would be good to see a test exercising this change...
>
>
> ;; A list of integer modes that are up to one word long
> (define_mode_iterator QHSI [QI HI SI])
> diff --git a/gcc/testsuite/gcc.target/arm/pr88850-2.c
> b/gcc/testsuite/gcc.target/arm/pr88850-2.c
> new file mode 100644
> index
> ..fee2a0fe3a227ea4652bea2aa0e7335d20a7e9b5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/pr88850-2.c
> @@ -0,0 +1,19 @@
> +/* PR target/88850. */
> +/* { dg-do compile } */
> +/* { dg-additional-options "-O2 -march=armv7-a -mfloat-abi=softfp
> -fdump-rtl-final" } */
> +/* { dg-add-options arm_neon_fp16 } */
> +/* { dg-require-effective-target arm_soft_ok } */
> +/* { dg-require-effective-target arm_neon_fp16_ok } */
> +
>
> arm_soft_ok checks if it's okay to add -mfloat-abi=soft, but you're adding
> softfp.
> Is this right?
>
> Thanks,
> Kyrill
>
> +#include
> +
> +extern void c (int, float16x4_t);
> +
> +void a (float16x4_t b)
> +{
> + c (0, b);
> +}
> +
> +
> +/* Check that these 64-bit moves are done in SI. */
> +/* { dg-final { scan-rtl-dump "_movsi_vfp" "final" } } *
>
--
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index c33e572c3e89c3dc5848bd6b825d618481247558..eb07c5b90c1b1905d35d7b480bdbe7d7a45ab7ba 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -24,9 +24,9 @@
;;
;; A list of modes that are exactly 64 bits in size. This is used to expand
-;; some splits that are the same for all modes when operating on ARM
+;; some splits that are the same for all modes when operating on ARM
;; registers.
-(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
+(define_mode_iterator ANY64
Re: [PATCH] Fix excess warnings from -Wtype-limits with location wrappers (PR c++/88680)
On Thu, Feb 14, 2019 at 11:26:15AM -0500, David Malcolm wrote:
> There's an asymmetry in the warning; it's looking for a comparison of a
> LHS expression against an RHS constant 0, spelled as "0".
>
> If we fold_for_warn on the RHS, then that folding introduces a warning
> for expressions that aren't spelled as "0" but can be folded to 0,
> e.g., with:
>
> enum { FOO, BAR };
So, shouldn't it be made symmetric? Check if one argument is literal 0
before folding, and only if it is, fold_for_warn the other argument?
Jakub
Re: [rs6000] 64-bit integer loads/stores and FP instructions
> Yeah, something like that. It will need some serious testing, to make > sure we don't regress (including not regressing what that patch that took > them away was meant to do). I can arrange some testing, will you do the > patch though? I can do the patch and also (correctness) testing for 32-bit Linux. Another issue is the extent of the patch: practically speaking, putting back the '*' modifier before all the 'd' constraints would be sufficient, but the current setting is a bit inconsistent|*] so this could also be adjusted. [*] For example, in the *movdi_internal32 pattern, 2 'wi' constraints have it but not the other 2. Likewise for "wv'. -- Eric Botcazou
Re: [PATCH] Fix excess warnings from -Wtype-limits with location wrappers (PR c++/88680)
On Thu, 2019-02-14 at 10:38 -0500, Jason Merrill wrote:
> On 2/6/19 9:23 PM, David Malcolm wrote:
> > PR c++/88680 reports excess warnings from -Wtype-limits after the
> > C++
> > FE's use of location wrappers was extended in r267272 for cases
> > such as:
> >
> >const unsigned n = 8;
> >static_assert (n >= 0 && n % 2 == 0, "");
> >
> > t.C:3:18: warning: comparison of unsigned expression >= 0 is always
> > true
> >[-Wtype-limits]
> > 3 | static_assert (n >= 0 && n % 2 == 0, "");
> >|~~^~~~
> >
> > The root cause is that the location wrapper around "n" breaks the
> > suppression of the warning for the "if OP0 is a constant that is >=
> > 0"
> > case.
> >
> > This patch fixes it by calling fold_for_warn on OP0, extracting the
> > constant.
>
> Is there a reason not to do this for OP1 as well?
There's an asymmetry in the warning; it's looking for a comparison of a
LHS expression against an RHS constant 0, spelled as "0".
If we fold_for_warn on the RHS, then that folding introduces a warning
for expressions that aren't spelled as "0" but can be folded to 0,
e.g., with:
enum { FOO, BAR };
pr88680.C:34:9: warning: comparison of unsigned expression >= 0 is
always true [-Wtype-limits]
34 | if (n >= FOO)
| ~~^~
pr88680.C:36:9: warning: comparison of unsigned expression < 0 is
always false [-Wtype-limits]
36 | if (n < FOO)
| ~~^
which we didn't warn for before.
We need to fold the LHS so that we can look through wrapper nodes, and
around wrappers around enum values, to suppress the warning if the
folded version of the LHS is a constant that fits in the data type (for
the example given in the original message above).
Dave
Re: PR87689, PowerPC64 ELFv2 function parameter passing violation
On Thu, Feb 14, 2019 at 10:32:50AM +0100, Richard Biener wrote: > On Wed, Feb 13, 2019 at 7:59 AM Alan Modra wrote: > > > > Covers for a generic fortran bug. The effect is that we'll needlessly > > waste 64 bytes of stack space on some calls, but I don't see any > > simple and fully correct patch in generic code. Bootstrapped and > > regression tested powerpc64le-linux. OK mainline and branches? > > This looks very wrong to me ;) It won't work when compiling with -flto > for example. Yeah, that is a show-stopper. > The frontend needs to be properly fixed. Sure, but until that happens our target suffers while it seems to work for everyone else. This won't be the first or last time a target needs an ugly workaround, and this one is in target code even ;-) Segher
Re: [PATCH] Fix excess warnings from -Wtype-limits with location wrappers (PR c++/88680)
On 2/6/19 9:23 PM, David Malcolm wrote: PR c++/88680 reports excess warnings from -Wtype-limits after the C++ FE's use of location wrappers was extended in r267272 for cases such as: const unsigned n = 8; static_assert (n >= 0 && n % 2 == 0, ""); t.C:3:18: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits] 3 | static_assert (n >= 0 && n % 2 == 0, ""); |~~^~~~ The root cause is that the location wrapper around "n" breaks the suppression of the warning for the "if OP0 is a constant that is >= 0" case. This patch fixes it by calling fold_for_warn on OP0, extracting the constant. Is there a reason not to do this for OP1 as well? Jason
Re: [committed] Fix set_uids_in_ptset (PR middle-end/89303)
Hi Jakub, > The following testcase is miscompiled on x86_64-linux (-m32 and -m64) at > -O1, as a pointer has two vars in points-to set, the first one is escaped > heap var and the second one is escaped non-heap var, and in the end the last > var that sets vars_contains_escaped won and overwrote > vars_contains_escaped_heap rather than oring into it. > > Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, > preapproved by Richard on IRC, committed to trunk. > Will test 8.x backport tonight and commit to 8.3 if that succeeds. > > 2019-02-13 Jakub Jelinek > > PR middle-end/89303 > * tree-ssa-structalias.c (set_uids_in_ptset): Or in vi->is_heap_var > into pt->vars_contains_escaped_heap instead of setting > pt->vars_contains_escaped_heap to it. > > 2019-02-13 Jonathan Wakely > Jakub Jelinek > > PR middle-end/89303 > * g++.dg/torture/pr89303.C: New test. the new testcase FAILs on Solaris: +FAIL: g++.dg/torture/pr89303.C -O0 (test for excess errors) +FAIL: g++.dg/torture/pr89303.C -O1 (test for excess errors) +FAIL: g++.dg/torture/pr89303.C -O2 (test for excess errors) +FAIL: g++.dg/torture/pr89303.C -O2 -flto (test for excess errors) +FAIL: g++.dg/torture/pr89303.C -O2 -flto -flto-partition=none (test for excess errors) +FAIL: g++.dg/torture/pr89303.C -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions (test for excess errors) +FAIL: g++.dg/torture/pr89303.C -O3 -g (test for excess errors) +FAIL: g++.dg/torture/pr89303.C -Os (test for excess errors) Excess errors: ld: warning: symbol 'typeinfo for std::bad_weak_ptr' has differing sizes: (file /var/tmp//ccB1o8Ya.o value=0x8; file /var/gcc/regression/trunk/11-gcc/build/i386-pc-solaris2.11/./libstdc++-v3/src/.libs/libstdc++.so value=0xc); /var/tmp//ccB1o8Ya.o definition taken I suspect the class can just be renamed in pr89303.C to avoid the conflict with include/bits/shared_ptr_base.h? Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
[PATCH] Update libstdc++ documentation for implementation status
* doc/xml/manual/status_cxx2017.xml: Add P0063R3 to status table. * doc/html/*: Regenerate. Committed to trunk. I've also updated the LibstdcxxTodo wiki page: https://gcc.gnu.org/wiki/LibstdcxxTodo?action=diff=107=100 commit 5f7cebfc9de5a7c07c447d06b610002964065730 Author: Jonathan Wakely Date: Thu Feb 14 15:10:28 2019 + Update libstdc++ documentation for implementation status * doc/xml/manual/status_cxx2017.xml: Add P0063R3 to status table. * doc/html/*: Regenerate. diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2017.xml b/libstdc++-v3/doc/xml/manual/status_cxx2017.xml index c9913a9e3a7..bb82e34bba7 100644 --- a/libstdc++-v3/doc/xml/manual/status_cxx2017.xml +++ b/libstdc++-v3/doc/xml/manual/status_cxx2017.xml @@ -90,6 +90,17 @@ Feature-testing recommendations for C++. __cpp_lib_uncaught_exceptions >= 201411 + + C++17 should refer to C11 instead of C99 + + http://www.w3.org/1999/xlink; xlink:href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0063r3.html;> + P0063R3 + + + 9.1 + + + Variant: a type-safe union for C++17
[PATCH] DR 2586 fix value category in uses-allocator checks
Because uses-allocator construction is invariably done with a const lvalue the __uses_alloc helper should use a const lvalue for the is_constructible checks. Otherwise, it can detect that the type can be constructed from an rvalue, and then an error happens when a const lvalue is passed to the constructor instead. Prior to LWG DR 2586 scoped_allocator_adaptor incorrectly used an rvalue type in the is_constructible check and then used a non-const lvalue for the actual construction. The other components using uses-allocator construction (tuple and polymorphic_allocator) have always done so with a const lvalue allocator, although the use of __use_alloc in our implementation meant they behaved the same as scoped_allocator_adaptor and incorrectly used rvalues for the is_constructible checks. In C++20 the P0591R4 changes mean that all uses-allocator construction is defined in terms of the new uses_allocator_construction_args functions, which always use a const lvalue allocator. The changes in this patch ensure that the __use_alloc helper correctly matches the requirements in the standard, consistently using a const lvalue allocator for the is_constructible checks and the actual constructor arguments. * doc/xml/manual/intro.xml: Document LWG 2586 status. * include/bits/uses_allocator.h (__uses_alloc): Use const lvalue allocator type in is_constructible checks. * testsuite/20_util/scoped_allocator/69293_neg.cc: Adjust dg-error. * testsuite/20_util/scoped_allocator/dr2586.cc: New test. * testsuite/20_util/tuple/cons/allocators.cc: Add test using problematic type from LWG 2586 discussion. * testsuite/20_util/uses_allocator/69293_neg.cc: Adjust dg-error. * testsuite/20_util/uses_allocator/cons_neg.cc: Likewise. Tested powerpc64le-linux, committed to trunk. commit 4e3200491f4cde4ae884a28bb11ece782ca17997 Author: Jonathan Wakely Date: Thu Feb 14 11:17:22 2019 + DR 2586 fix value category in uses-allocator checks Because uses-allocator construction is invariably done with a const lvalue the __uses_alloc helper should use a const lvalue for the is_constructible checks. Otherwise, it can detect that the type can be constructed from an rvalue, and then an error happens when a const lvalue is passed to the constructor instead. Prior to LWG DR 2586 scoped_allocator_adaptor incorrectly used an rvalue type in the is_constructible check and then used a non-const lvalue for the actual construction. The other components using uses-allocator construction (tuple and polymorphic_allocator) have always done so with a const lvalue allocator, although the use of __use_alloc in our implementation meant they behaved the same as scoped_allocator_adaptor and incorrectly used rvalues for the is_constructible checks. In C++20 the P0591R4 changes mean that all uses-allocator construction is defined in terms of the new uses_allocator_construction_args functions, which always use a const lvalue allocator. The changes in this patch ensure that the __use_alloc helper correctly matches the requirements in the standard, consistently using a const lvalue allocator for the is_constructible checks and the actual constructor arguments. * doc/xml/manual/intro.xml: Document LWG 2586 status. * include/bits/uses_allocator.h (__uses_alloc): Use const lvalue allocator type in is_constructible checks. * testsuite/20_util/scoped_allocator/69293_neg.cc: Adjust dg-error. * testsuite/20_util/scoped_allocator/dr2586.cc: New test. * testsuite/20_util/tuple/cons/allocators.cc: Add test using problematic type from LWG 2586 discussion. * testsuite/20_util/uses_allocator/69293_neg.cc: Adjust dg-error. * testsuite/20_util/uses_allocator/cons_neg.cc: Likewise. diff --git a/libstdc++-v3/doc/xml/manual/intro.xml b/libstdc++-v3/doc/xml/manual/intro.xml index 656e32b00aa..9761b82fd65 100644 --- a/libstdc++-v3/doc/xml/manual/intro.xml +++ b/libstdc++-v3/doc/xml/manual/intro.xml @@ -1142,6 +1142,14 @@ requirements of the license of GCC. Add new constructor. +http://www.w3.org/1999/xlink; xlink:href="#2586">2586: + Wrong value category used in scoped_allocator_adaptor::construct() + + +Change internal helper for uses-allocator construction + to always check using const lvalue allocators. + + http://www.w3.org/1999/xlink; xlink:href="#2684">2684: priority_queue lacking comparator typedef diff --git a/libstdc++-v3/include/bits/uses_allocator.h b/libstdc++-v3/include/bits/uses_allocator.h index a118f695535..015828bee18 100644 --- a/libstdc++-v3/include/bits/uses_allocator.h +++ b/libstdc++-v3/include/bits/uses_allocator.h @@ -87,14 +87,17 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template struct __uses_alloc
[PATCH] i386: Check -mmanual-endbr in pass_insert_endbranch::gate
When -mmanual-endbr is used with -fcf-protection, only functions marked
with cf_check attribute should be instrumented with ENDBR. We should
skip rest_of_insert_endbranch on functions without cf_check attribute.
OK for trunk?
Thanks.
H.J.
---
gcc/
PR target/89353
* config/i386/i386.c (rest_of_insert_endbranch): Move the
-mmanual-endbr and cf_check attribute check to ..
(pass_insert_endbranch::gate): Here.
gcc/testsuite/
PR target/89353
* gcc.target/i386/cf_check-6.c: New test.
---
gcc/config/i386/i386.c | 10 +-
gcc/testsuite/gcc.target/i386/cf_check-6.c | 22 ++
2 files changed, 27 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/cf_check-6.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index fd05873ba39..a99ca23fffa 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2640,9 +2640,6 @@ rest_of_insert_endbranch (void)
if (!lookup_attribute ("nocf_check",
TYPE_ATTRIBUTES (TREE_TYPE (cfun->decl)))
- && (!flag_manual_endbr
- || lookup_attribute ("cf_check",
- DECL_ATTRIBUTES (cfun->decl)))
&& !cgraph_node::get (cfun->decl)->only_called_directly_p ())
{
/* Queue ENDBR insertion to x86_function_profiler. */
@@ -2773,9 +2770,12 @@ public:
{}
/* opt_pass methods: */
- virtual bool gate (function *)
+ virtual bool gate (function *fun)
{
- return ((flag_cf_protection & CF_BRANCH));
+ return ((flag_cf_protection & CF_BRANCH)
+ && (!flag_manual_endbr
+ || lookup_attribute ("cf_check",
+ DECL_ATTRIBUTES (fun->decl;
}
virtual unsigned int execute (function *)
diff --git a/gcc/testsuite/gcc.target/i386/cf_check-6.c
b/gcc/testsuite/gcc.target/i386/cf_check-6.c
new file mode 100644
index 000..292b964238d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/cf_check-6.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fcf-protection -mmanual-endbr" } */
+/* { dg-final { scan-assembler-not {\mendbr} } } */
+
+int
+bar (int* val)
+{
+ int status = 99;
+
+ if((val == 0))
+{
+ status = 22;
+ goto end;
+}
+
+ extern int x;
+ *val = x;
+
+ status = 0;
+end:
+ return status;
+}
--
2.20.1
Re: [Patch] [arm] Fix 88714, Arm LDRD/STRD peepholes
On 2/11/19 2:35 PM, Matthew Malcomson wrote:
On 10/02/19 09:42, Christophe Lyon wrote:
>
> Both this simple patch or the previous fix all the ICEs I reported,
thanks.
>
> Of course, the scan-assembler failures remain to be fixed.
>
In the testcase I failed to account for targets that don't support arm
mode or
targets that do not support the ldrd/strd instructions.
This patch accounts for both of these by adding some
dg-require-effective-target lines to the testcase.
This patch also adds a new effective-target procedure to check a target
supports arm ldrd/strd.
This check uses the 'r' constraint to ensure SP is not used so that it
will
work for thumb mode code generation as well as arm mode.
Tested by running this testcase with cross compilers using
"-march=armv5t",
"-mcpu=cortex-m3", "-mcpu-arm7tdmi", "-mcpu=cortex-a9 -march=armv5t" for
both
arm-none-eabi and arm-none-linux-gnueabihf.
Also ran this testcase with `make check` natively.
Ok for trunk?
Ok.
Thanks,
Kyrill
gcc/testsuite/ChangeLog:
2019-02-11 Matthew Malcomson
* gcc.dg/rtl/arm/ldrd-peepholes.c: Restrict testcase.
* lib/target-supports.exp: Add procedure to check for ldrd.
diff --git a/gcc/testsuite/gcc.dg/rtl/arm/ldrd-peepholes.c
b/gcc/testsuite/gcc.dg/rtl/arm/ldrd-peepholes.c
index
4c3949c0963b8482545df670c31db2d9ec0f26b3..cbb64a770f5d796250601cafe481d7c2ea13f2eb
100644
--- a/gcc/testsuite/gcc.dg/rtl/arm/ldrd-peepholes.c
+++ b/gcc/testsuite/gcc.dg/rtl/arm/ldrd-peepholes.c
@@ -1,4 +1,6 @@
/* { dg-do compile { target arm*-*-* } } */
+/* { dg-require-effective-target arm_arm_ok } */
+/* { dg-require-effective-target arm_ldrd_strd_ok } */
/* { dg-skip-if "Ensure only targetting arm with TARGET_LDRD" { *-*-*
} { "-mthumb" } { "" } } */
/* { dg-options "-O3 -marm -fdump-rtl-peephole2" } */
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index
a0b4b99067f9ae225bde3b6bc719e89e1ea8e0e1..16dd018e8020fdf8e104690fed6a4e8919aa4aa1
100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4918,6 +4918,27 @@ proc check_effective_target_arm_prefer_ldrd_strd
{ } {
} "-O2 -mthumb" ]
}
+# Return true if LDRD/STRD instructions are available on this target.
+proc check_effective_target_arm_ldrd_strd_ok { } {
+ if { ![check_effective_target_arm32] } {
+ return 0;
+ }
+
+ return [check_no_compiler_messages arm_ldrd_strd_ok object {
+ int main(void)
+ {
+ __UINT64_TYPE__ a = 1, b = 10;
+ __UINT64_TYPE__ *c =
+ // `a` will be in a valid register since it's a DImode quantity.
+ asm ("ldrd %0, %1"
+ : "=r" (a)
+ : "m" (c));
+ return a == 10;
+ }
+ }]
+}
+
# Return 1 if this is a PowerPC target supporting -meabi.
proc check_effective_target_powerpc_eabi_ok { } {
Re: Move -Wmaybe-uninitialized to -Wextra
> "Marc" == Marc Glisse writes: >> Lastly, in the case of uninitialized variables, the usual solution >> of initializing them is trivial and always safe (some coding styles >> even require it). Marc> Here it shows that we don't work with the same type of code at all. If Marc> I am using a boost::optional, i.e. a class with a buffer and a boolean Marc> that says if the buffer is initialized, how do I initialize the Marc> (private) buffer? Or should boost itself zero out the buffer whenever Marc> the boolean is set to false? This is https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80635 (I know you know, but maybe others on the thread don't). I think in this specific case (std::optional and similar classes), GCC should provide a way for the class to indicate that -Wmaybe-uninitialized should not apply to the payload. >> A shared definition of a false positive should be one of the very >> first steps to coming closer to a consensus. Real world (as opposed >> to anecdotal) data on the rates of actual rates of false positives >> and negatives vs true positives would be also most helpful, as would >> some consensus of the severity of the bugs the true positives >> expose, as well as some objective measure of the ease of >> suppression. There probably are others but these would be a start. Marc> This data is going to be super hard to get. Most projects have been Marc> compiling for years and tweaking their code to avoid some warnings. We Marc> do not get to see the code that people originally write, we can only Marc> see what they commit. gdb has gone through this over the years -- it turns on many warnings and sometimes false positives show up. Most of the time there's a comment, for -Wmaybe-uninitialized grep for "init.*gcc" in the source. Unfortunately the comment isn't standardized; but I only get ~20 hits for this in gdb, so it isn't really so bad in practice. Tom
Re: [PATCH 31/40] i386: Emulate MMX pshufb with SSE version
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX version of pshufb with SSE version by masking out the bit 3
> of the shuffle control byte. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/sse.md (ssse3_pshufbv8qi3): Renamed to ...
> (ssse3_pshufbv8qi3_mmx): This.
> (ssse3_pshufbv8qi3): New.
> (ssse3_pshufbv8qi3_sse): Likewise.
These insns can also be merged together using
(clobber (match_scratch:V4SI 3 "=X,x,Yv"))
Uros.
> ---
> gcc/config/i386/sse.md | 56 --
> 1 file changed, 54 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index cc7dbe79fa7..a92505c54a1 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -15722,18 +15722,70 @@
> (set_attr "btver2_decode" "vector")
> (set_attr "mode" "")])
>
> -(define_insn "ssse3_pshufbv8qi3"
> +(define_expand "ssse3_pshufbv8qi3"
> + [(set (match_operand:V8QI 0 "register_operand")
> + (unspec:V8QI [(match_operand:V8QI 1 "register_operand")
> + (match_operand:V8QI 2 "nonimmediate_operand")]
> +UNSPEC_PSHUFB))]
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
> +{
> + if (TARGET_MMX_WITH_SSE)
> +{
> + rtx op2 = force_reg (V8QImode, operands[2]);
> + emit_insn (gen_ssse3_pshufbv8qi3_sse (operands[0], operands[1],
> + op2));
> + DONE;
> +}
> +})
> +
> +(define_insn "ssse3_pshufbv8qi3_mmx"
>[(set (match_operand:V8QI 0 "register_operand" "=y")
> (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
> (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
> UNSPEC_PSHUFB))]
> - "TARGET_SSSE3"
> + "TARGET_SSSE3 && !TARGET_MMX_WITH_SSE"
>"pshufb\t{%2, %0|%0, %2}";
>[(set_attr "type" "sselog1")
> (set_attr "prefix_extra" "1")
> (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p
> (insn)"))
> (set_attr "mode" "DI")])
>
> +(define_insn_and_split "ssse3_pshufbv8qi3_sse"
> + [(set (match_operand:V8QI 0 "register_operand" "=x,Yv")
> + (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,Yv")
> + (match_operand:V8QI 2 "register_operand" "x,Yv")]
> +UNSPEC_PSHUFB))
> + (clobber (match_scratch:V4SI 3 "=x,Yv"))]
> + "TARGET_SSSE3 && TARGET_MMX_WITH_SSE"
> + "#"
> + "reload_completed"
> + [(set (match_dup 3) (match_dup 5))
> + (set (match_dup 3)
> + (and:V4SI (match_dup 3) (match_dup 2)))
> + (set (match_dup 0)
> + (unspec:V16QI [(match_dup 1) (match_dup 4)] UNSPEC_PSHUFB))]
> +{
> + /* Emulate MMX version of pshufb with SSE version by masking out the
> + bit 3 of the shuffle control byte. */
> + operands[0] = lowpart_subreg (V16QImode, operands[0],
> + GET_MODE (operands[0]));
> + operands[1] = lowpart_subreg (V16QImode, operands[1],
> + GET_MODE (operands[1]));
> + operands[2] = lowpart_subreg (V4SImode, operands[2],
> + GET_MODE (operands[2]));
> + operands[4] = lowpart_subreg (V16QImode, operands[3],
> + GET_MODE (operands[3]));
> + rtvec par = gen_rtvec (4, GEN_INT (0xf7f7f7f7),
> +GEN_INT (0xf7f7f7f7),
> +GEN_INT (0xf7f7f7f7),
> +GEN_INT (0xf7f7f7f7));
> + rtx vec_const = gen_rtx_CONST_VECTOR (V4SImode, par);
> + operands[5] = force_const_mem (V4SImode, vec_const);
> +}
> + [(set_attr "mmx_isa" "x64_noavx,x64_avx")
> + (set_attr "type" "sselog1")
> + (set_attr "mode" "TI,TI")])
> +
> (define_insn "_psign3"
>[(set (match_operand:VI124_AVX2 0 "register_operand" "=x,x")
> (unspec:VI124_AVX2
> --
> 2.20.1
>
Re: [PATCH 25/40] i386: Emulate MMX movntq with SSE2 movntidi
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX movntq with SSE2 movntidi. Only SSE register source operand
> is allowed.
There is no SSE register source operand. Probably "Only register
source operand is allowed."
Uros.
>
> PR target/89021
> * config/i386/mmx.md (sse_movntq): Add SSE2 emulation.
> ---
> gcc/config/i386/mmx.md | 14 +-
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index 0c08aebb071..274e895f51e 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -214,12 +214,16 @@
> })
>
> (define_insn "sse_movntq"
> - [(set (match_operand:DI 0 "memory_operand" "=m")
> - (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
> + [(set (match_operand:DI 0 "memory_operand" "=m,m")
> + (unspec:DI [(match_operand:DI 1 "register_operand" "y,r")]
>UNSPEC_MOVNTQ))]
> - "TARGET_SSE || TARGET_3DNOW_A"
> - "movntq\t{%1, %0|%0, %1}"
> - [(set_attr "type" "mmxmov")
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE)
> + && (TARGET_SSE || TARGET_3DNOW_A)"
> + "@
> + movntq\t{%1, %0|%0, %1}
> + movnti\t{%1, %0|%0, %1}"
> + [(set_attr "mmx_isa" "native,x64")
> + (set_attr "type" "mmxmov,ssemov")
> (set_attr "mode" "DI")])
>
> ;
> --
> 2.20.1
>
[PATCH] Add testcases for multiple -fsanitize=, -fno-sanitize= or -fno-sanitize-recover= options (take 2)
On Thu, Feb 14, 2019 at 05:48:29AM -0800, H.J. Lu wrote:
> I got
>
> UNRESOLVED: c-c++-common/ubsan/opts-1.c -O2 -flto
> -fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
> optimized "__ubsan_handle_divrem_overflow" 2
Ah, yes, UNRESOLVED doesn't show up visible when running tests by hand,
rather than doing test_summary. Here is an updated patch that adds the
needed dg-skip-if directives. Ok for trunk?
2019-02-14 Jakub Jelinek
* c-c++-common/ubsan/opts-1.c: New test.
* c-c++-common/ubsan/opts-2.c: New test.
* c-c++-common/ubsan/opts-3.c: New test.
* c-c++-common/ubsan/opts-4.c: New test.
--- gcc/testsuite/c-c++-common/ubsan/opts-1.c.jj2019-02-14
11:31:33.144895232 +0100
+++ gcc/testsuite/c-c++-common/ubsan/opts-1.c 2019-02-14 11:33:23.049077585
+0100
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=undefined -fsanitize=shift
-fsanitize=float-divide-by-zero -fdump-tree-optimized" } */
+/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
+/* { dg-final { scan-tree-dump-times "__ubsan_handle_divrem_overflow" 2
"optimized" } } */
+/* { dg-final { scan-tree-dump-times "__ubsan_handle_shift_out_of_bounds" 1
"optimized" } } */
+
+int
+foo (int x, int y)
+{
+ return x / y;
+}
+
+int
+bar (int x, int y)
+{
+ return x << y;
+}
+
+float
+baz (float x, float y)
+{
+ return x / y;
+}
--- gcc/testsuite/c-c++-common/ubsan/opts-2.c.jj2019-02-14
11:33:29.806965829 +0100
+++ gcc/testsuite/c-c++-common/ubsan/opts-2.c 2019-02-14 11:34:03.169414166
+0100
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=undefined -fno-sanitize=shift
-fsanitize=float-divide-by-zero -fdump-tree-optimized" } */
+/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
+/* { dg-final { scan-tree-dump-times "__ubsan_handle_divrem_overflow" 2
"optimized" } } */
+/* { dg-final { scan-tree-dump-not "__ubsan_handle_shift_out_of_bounds"
"optimized" } } */
+
+int
+foo (int x, int y)
+{
+ return x / y;
+}
+
+int
+bar (int x, int y)
+{
+ return x << y;
+}
+
+float
+baz (float x, float y)
+{
+ return x / y;
+}
--- gcc/testsuite/c-c++-common/ubsan/opts-3.c.jj2019-02-14
11:34:10.538292322 +0100
+++ gcc/testsuite/c-c++-common/ubsan/opts-3.c 2019-02-14 11:34:35.512879358
+0100
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=undefined -fno-sanitize=shift
-fno-sanitize=float-divide-by-zero -fdump-tree-optimized" } */
+/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
+/* { dg-final { scan-tree-dump-times "__ubsan_handle_divrem_overflow" 1
"optimized" } } */
+/* { dg-final { scan-tree-dump-not "__ubsan_handle_shift_out_of_bounds"
"optimized" } } */
+
+int
+foo (int x, int y)
+{
+ return x / y;
+}
+
+int
+bar (int x, int y)
+{
+ return x << y;
+}
+
+float
+baz (float x, float y)
+{
+ return x / y;
+}
--- gcc/testsuite/c-c++-common/ubsan/opts-4.c.jj2019-02-14
11:40:35.771922337 +0100
+++ gcc/testsuite/c-c++-common/ubsan/opts-4.c 2019-02-14 11:40:29.220030674
+0100
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=undefined
-fno-sanitize-recover=integer-divide-by-zero -fno-sanitize-recover=shift
-fdump-tree-optimized" } */
+/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
+/* { dg-final { scan-tree-dump-times "__ubsan_handle_divrem_overflow_abort" 1
"optimized" } } */
+/* { dg-final { scan-tree-dump-times
"__ubsan_handle_shift_out_of_bounds_abort" 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "__ubsan_handle_type_mismatch_v1" 1
"optimized" } } */
+/* { dg-final { scan-tree-dump-not "__ubsan_handle_type_mismatch_v1_abort"
"optimized" } } */
+
+int
+foo (int x, int y)
+{
+ return x / y;
+}
+
+int
+bar (int x, int y)
+{
+ return x << y;
+}
+
+enum E { E0, E1, E2, E3 };
+
+enum E
+baz (enum E *x)
+{
+ return *x;
+}
Jakub
Re: [PATCH 15/40] i386: Emulate MMX sse_cvtpi2ps with SSE
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
> destination XMM register. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (sse_cvtpi2ps): Renamed to ...
> (*mmx_cvtpi2ps): This. Disabled for TARGET_MMX_WITH_SSE.
> (sse_cvtpi2ps): New.
> (mmx_cvtpi2ps_sse): Likewise.
Now you can merge both instructions together using:
(clobber (match_scratch:V4SF 3 "=X,x,Yv"))
Please note "X" for the original case where scratch is not needed.
Uros.
> ---
> gcc/config/i386/sse.md | 77 --
> 1 file changed, 75 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 083f9ef0f44..b1bab15af41 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -4561,14 +4561,87 @@
> ;;
> ;
>
> -(define_insn "sse_cvtpi2ps"
> +(define_expand "sse_cvtpi2ps"
> + [(set (match_operand:V4SF 0 "register_operand")
> + (vec_merge:V4SF
> + (vec_duplicate:V4SF
> + (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand")))
> + (match_operand:V4SF 1 "register_operand")
> + (const_int 3)))]
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
> +{
> + if (TARGET_MMX_WITH_SSE)
> +{
> + rtx op2 = force_reg (V2SImode, operands[2]);
> + emit_insn (gen_mmx_cvtpi2ps_sse (operands[0], operands[1], op2));
> + DONE;
> +}
> +})
> +
> +(define_insn_and_split "mmx_cvtpi2ps_sse"
> + [(set (match_operand:V4SF 0 "register_operand" "=x,Yv")
> + (vec_merge:V4SF
> + (vec_duplicate:V4SF
> + (float:V2SF (match_operand:V2SI 2 "register_operand" "x,Yv")))
> + (match_operand:V4SF 1 "register_operand" "0,Yv")
> + (const_int 3)))
> + (clobber (match_scratch:V4SF 3 "=x,Yv"))]
> + "TARGET_MMX_WITH_SSE"
> + "#"
> + "&& reload_completed"
> + [(const_int 0)]
> +{
> + rtx op2 = lowpart_subreg (V4SImode, operands[2],
> + GET_MODE (operands[2]));
> + /* Generate SSE2 cvtdq2ps. */
> + rtx insn = gen_floatv4siv4sf2 (operands[3], op2);
> + emit_insn (insn);
> +
> + /* Merge operands[3] with operands[0]. */
> + rtx mask, op1;
> + if (TARGET_AVX)
> +{
> + mask = gen_rtx_PARALLEL (VOIDmode,
> + gen_rtvec (4, GEN_INT (0), GEN_INT (1),
> + GEN_INT (6), GEN_INT (7)));
> + op1 = gen_rtx_VEC_CONCAT (V8SFmode, operands[3], operands[1]);
> + op2 = gen_rtx_VEC_SELECT (V4SFmode, op1, mask);
> + insn = gen_rtx_SET (operands[0], op2);
> +}
> + else
> +{
> + /* NB: SSE can only concatenate OP0 and OP3 to OP0. */
> + mask = gen_rtx_PARALLEL (VOIDmode,
> + gen_rtvec (4, GEN_INT (2), GEN_INT (3),
> + GEN_INT (4), GEN_INT (5)));
> + op1 = gen_rtx_VEC_CONCAT (V8SFmode, operands[0], operands[3]);
> + op2 = gen_rtx_VEC_SELECT (V4SFmode, op1, mask);
> + insn = gen_rtx_SET (operands[0], op2);
> + emit_insn (insn);
> +
> + /* Swap bits 0:63 with bits 64:127. */
> + mask = gen_rtx_PARALLEL (VOIDmode,
> + gen_rtvec (4, GEN_INT (2), GEN_INT (3),
> + GEN_INT (0), GEN_INT (1)));
> + rtx dest = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> + op1 = gen_rtx_VEC_SELECT (V4SImode, dest, mask);
> + insn = gen_rtx_SET (dest, op1);
> +}
> + emit_insn (insn);
> + DONE;
> +}
> + [(set_attr "isa" "noavx,avx")
> + (set_attr "type" "ssecvt")
> + (set_attr "mode" "V4SF")])
> +
> +(define_insn "*mmx_cvtpi2ps"
>[(set (match_operand:V4SF 0 "register_operand" "=x")
> (vec_merge:V4SF
> (vec_duplicate:V4SF
> (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
> (match_operand:V4SF 1 "register_operand" "0")
> (const_int 3)))]
> - "TARGET_SSE"
> + "TARGET_SSE && !TARGET_MMX_WITH_SSE"
>"cvtpi2ps\t{%2, %0|%0, %2}"
>[(set_attr "type" "ssecvt")
> (set_attr "mode" "V4SF")])
> --
> 2.20.1
>
[PATCH] Add std::timespec and std::timespec_get for C++17
* configure.ac: Check for C11 timespec_get function.
* crossconfig.m4 (freebsd, linux, gnu, cygwin, solaris, netbsd)
(openbsd): Likewise
* config.h.in: Regenerate.
* configure: Regenerate.
* include/c_global/ctime (timespec, timespec_get): Add to namespace
std for C++17 and up.
Tested powerpc64le-linux (and bootstrapped on aarch64-linux-gnu cross
compiler), committed to trunk.
commit 9c433c582ce9ca7a12a61a1e674ca7b3885318d8
Author: Jonathan Wakely
Date: Thu Feb 14 11:06:46 2019 +
Add std::timespec and std::timespec_get for C++17
* configure.ac: Check for C11 timespec_get function.
* crossconfig.m4 (freebsd, linux, gnu, cygwin, solaris, netbsd)
(openbsd): Likewise
* config.h.in: Regenerate.
* configure: Regenerate.
* include/c_global/ctime (timespec, timespec_get): Add to namespace
std for C++17 and up.
diff --git a/libstdc++-v3/configure.ac b/libstdc++-v3/configure.ac
index ad5b4117cfd..6c98f270441 100644
--- a/libstdc++-v3/configure.ac
+++ b/libstdc++-v3/configure.ac
@@ -265,6 +265,9 @@ if $GLIBCXX_IS_NATIVE; then
AC_CHECK_FUNCS(aligned_alloc posix_memalign memalign _aligned_malloc)
AC_CHECK_FUNCS(_wfopen)
+ # C11 functions for C++17 library
+ AC_CHECK_FUNCS(timespec_get)
+
# For iconv support.
AM_ICONV
diff --git a/libstdc++-v3/crossconfig.m4 b/libstdc++-v3/crossconfig.m4
index 3de40dc138b..4a303008053 100644
--- a/libstdc++-v3/crossconfig.m4
+++ b/libstdc++-v3/crossconfig.m4
@@ -135,6 +135,7 @@ case "${host}" in
fi
AC_CHECK_FUNCS(__cxa_thread_atexit)
AC_CHECK_FUNCS(aligned_alloc posix_memalign memalign _aligned_malloc)
+AC_CHECK_FUNCS(timespec_get)
;;
*-fuchsia*)
@@ -194,6 +195,7 @@ case "${host}" in
GCC_CHECK_TLS
AC_CHECK_FUNCS(__cxa_thread_atexit_impl)
AC_CHECK_FUNCS(aligned_alloc posix_memalign memalign _aligned_malloc)
+AC_CHECK_FUNCS(timespec_get)
AM_ICONV
;;
*-mingw32*)
@@ -221,6 +223,7 @@ case "${host}" in
AC_DEFINE(HAVE_ISNANL)
fi
AC_CHECK_FUNCS(aligned_alloc posix_memalign memalign _aligned_malloc)
+AC_CHECK_FUNCS(timespec_get)
;;
*-qnx6.1* | *-qnx6.2*)
SECTION_FLAGS='-ffunction-sections -fdata-sections'
diff --git a/libstdc++-v3/include/c_global/ctime
b/libstdc++-v3/include/c_global/ctime
index cdd3d8d7171..685c821b577 100644
--- a/libstdc++-v3/include/c_global/ctime
+++ b/libstdc++-v3/include/c_global/ctime
@@ -72,4 +72,13 @@ namespace std
using ::strftime;
} // namespace
+#if __cplusplus >= 201703L && defined(_GLIBCXX_HAVE_TIMESPEC_GET)
+#undef timespec_get
+namespace std
+{
+ using ::timespec;
+ using ::timespec_get;
+} // namespace std
+#endif
+
#endif
[PATCH] LWG 2537 fix priority_queue constructors to establish invariant
This change is safe to make now (in stage 4), because the constructors
are currently incorrect and unusable (unless the supplied container
already contains a heap, in which case the new make_heap calls are
redundant but harmless).
* doc/xml/manual/intro.xml: Document LWG 2537 status.
* include/bits/stl_queue.h
(priority_queue(const Compare&, const Container&, const Alloc&))
(priority_queue(const Compare&, Container&&, const Alloc&)): Call
make_heap.
* testsuite/23_containers/priority_queue/dr2537.cc: New test.
Tested powerpc64le-linux, committed to trunk.
commit 00eb831064ca6c6cfff48b2f3f8b1217b0c5d527
Author: Jonathan Wakely
Date: Thu Feb 14 10:52:56 2019 +
LWG 2537 fix priority_queue constructors to establish invariant
This change is safe to make now (in stage 4), because the constructors
are currently incorrect and unusable (unless the supplied container
already contains a heap, in which case the new make_heap calls are
redundant but harmless).
* doc/xml/manual/intro.xml: Document LWG 2537 status.
* include/bits/stl_queue.h
(priority_queue(const Compare&, const Container&, const Alloc&))
(priority_queue(const Compare&, Container&&, const Alloc&)): Call
make_heap.
* testsuite/23_containers/priority_queue/dr2537.cc: New test.
diff --git a/libstdc++-v3/doc/xml/manual/intro.xml
b/libstdc++-v3/doc/xml/manual/intro.xml
index 2a3231f4eb4..656e32b00aa 100644
--- a/libstdc++-v3/doc/xml/manual/intro.xml
+++ b/libstdc++-v3/doc/xml/manual/intro.xml
@@ -1127,6 +1127,14 @@ requirements of the license of GCC.
Add static assertions to enforce the requirement.
+http://www.w3.org/1999/xlink; xlink:href="#2566">2566:
+ Constructors for priority_queue taking allocators
+should call make_heap
+
+
+Call make_heap.
+
+
http://www.w3.org/1999/xlink; xlink:href="#2583">2583:
There is no way to supply an allocator for
basic_string(str, pos)
diff --git a/libstdc++-v3/include/bits/stl_queue.h
b/libstdc++-v3/include/bits/stl_queue.h
index 1eb56810edc..dd1d5d9727a 100644
--- a/libstdc++-v3/include/bits/stl_queue.h
+++ b/libstdc++-v3/include/bits/stl_queue.h
@@ -520,14 +520,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
priority_queue(const _Compare& __x, const _Alloc& __a)
: c(__a), comp(__x) { }
+ // _GLIBCXX_RESOLVE_LIB_DEFECTS
+ // 2537. Constructors [...] taking allocators should call make_heap
template>
priority_queue(const _Compare& __x, const _Sequence& __c,
const _Alloc& __a)
- : c(__c, __a), comp(__x) { }
+ : c(__c, __a), comp(__x)
+ { std::make_heap(c.begin(), c.end(), comp); }
template>
priority_queue(const _Compare& __x, _Sequence&& __c, const _Alloc& __a)
- : c(std::move(__c), __a), comp(__x) { }
+ : c(std::move(__c), __a), comp(__x)
+ { std::make_heap(c.begin(), c.end(), comp); }
template>
priority_queue(const priority_queue& __q, const _Alloc& __a)
diff --git a/libstdc++-v3/testsuite/23_containers/priority_queue/dr2537.cc
b/libstdc++-v3/testsuite/23_containers/priority_queue/dr2537.cc
new file mode 100644
index 000..ecb51780ee5
--- /dev/null
+++ b/libstdc++-v3/testsuite/23_containers/priority_queue/dr2537.cc
@@ -0,0 +1,50 @@
+// Copyright (C) 2019 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+//
[PATCH] Enforce LWG DR 2566 requirement for container adaptors
Although there is no good use for stack> or similar types with a mismatched value_type, it's possible somebody is doing that and getting away with it currently. This patch only enforces the new requirement for C++17 and later. During stage 1 we should consider enforcing it for C++11 and C++14. * doc/xml/manual/intro.xml: Document LWG 2566 status. * include/bits/stl_queue.h (queue, priority_queue): Add static assertions to enforce LWG 2566 requirement on value_type. * include/bits/stl_stack.h (stack): Likewise. Tested powerpc64le-linux, committed to trunk. commit 69e8bd2a9cbae0b3e19abcd36615fc9e662db947 Author: Jonathan Wakely Date: Thu Feb 14 09:58:17 2019 + Enforce LWG DR 2566 requirement for container adaptors Although there is no good use for stack> or similar types with a mismatched value_type, it's possible somebody is doing that and getting away with it currently. This patch only enforces the new requirement for C++17 and later. During stage 1 we should consider enforcing it for C++11 and C++14. * doc/xml/manual/intro.xml: Document LWG 2566 status. * include/bits/stl_queue.h (queue, priority_queue): Add static assertions to enforce LWG 2566 requirement on value_type. * include/bits/stl_stack.h (stack): Likewise. diff --git a/libstdc++-v3/doc/xml/manual/intro.xml b/libstdc++-v3/doc/xml/manual/intro.xml index 71050a0cebc..2a3231f4eb4 100644 --- a/libstdc++-v3/doc/xml/manual/intro.xml +++ b/libstdc++-v3/doc/xml/manual/intro.xml @@ -1120,11 +1120,18 @@ requirements of the license of GCC. ill-formed. +http://www.w3.org/1999/xlink; xlink:href="#2537">2537: + Requirements on the first template parameter of container adaptors + + +Add static assertions to enforce the requirement. + + http://www.w3.org/1999/xlink; xlink:href="#2583">2583: There is no way to supply an allocator for basic_string(str, pos) -Add new constructor +Add new constructor. http://www.w3.org/1999/xlink; xlink:href="#2684">2684: diff --git a/libstdc++-v3/include/bits/stl_queue.h b/libstdc++-v3/include/bits/stl_queue.h index 6d092c9bbfe..1eb56810edc 100644 --- a/libstdc++-v3/include/bits/stl_queue.h +++ b/libstdc++-v3/include/bits/stl_queue.h @@ -118,7 +118,15 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template using _Uses = typename enable_if::value>::type; -#endif + +#if __cplusplus >= 201703L + // _GLIBCXX_RESOLVE_LIB_DEFECTS + // 2566. Requirements on the first template parameter of container + // adaptors + static_assert(is_same<_Tp, typename _Sequence::value_type>::value, + "value_type must be the same as the underlying container"); +#endif // C++17 +#endif // C++11 public: typedef typename _Sequence::value_type value_type; @@ -451,17 +459,25 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template using _Uses = typename enable_if::value>::type; -#endif + +#if __cplusplus >= 201703L + // _GLIBCXX_RESOLVE_LIB_DEFECTS + // 2566. Requirements on the first template parameter of container + // adaptors + static_assert(is_same<_Tp, typename _Sequence::value_type>::value, + "value_type must be the same as the underlying container"); +#endif // C++17 +#endif // C++11 public: typedef typename _Sequence::value_type value_type; - typedef typename _Sequence::reference reference; - typedef typename _Sequence::const_reference const_reference; - typedef typename _Sequence::size_type size_type; - typedef _Sequence container_type; + typedef typename _Sequence::referencereference; + typedef typename _Sequence::const_reference const_reference; + typedef typename _Sequence::size_typesize_type; + typedef _Sequence container_type; // _GLIBCXX_RESOLVE_LIB_DEFECTS // DR 2684. priority_queue lacking comparator typedef - typedef _Compare value_compare; + typedef _Compare value_compare; protected: // See queue::c for notes on these names. diff --git a/libstdc++-v3/include/bits/stl_stack.h b/libstdc++-v3/include/bits/stl_stack.h index e8443a78a05..28faab2e871 100644 --- a/libstdc++-v3/include/bits/stl_stack.h +++ b/libstdc++-v3/include/bits/stl_stack.h @@ -120,7 +120,15 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template using _Uses = typename enable_if::value>::type; -#endif + +#if __cplusplus >= 201703L + // _GLIBCXX_RESOLVE_LIB_DEFECTS + // 2566. Requirements on the first template parameter of container + // adaptors + static_assert(is_same<_Tp, typename _Sequence::value_type>::value, +
Re: [PATCH 08/40] i386: Emulate MMX ashr3/3 with SSE
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX ashr3/3 with SSE. Only SSE register
> source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_ashr3): Changed to define_expand.
> Disallow TARGET_MMX_WITH_SSE.
> (mmx_3): Likewise.
> (ashr3): New.
> (*ashr3): Likewise.
> (3): Likewise.
> (*3): Likewise.
Please add "|| TARGET_MMX_WITH_SSE" with new constraints to
mmx_*3 insn instead and don't introduce unnecessary mmx_*
expander.
Uros.
> ---
> gcc/config/i386/mmx.md | 68 --
> 1 file changed, 52 insertions(+), 16 deletions(-)
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index 23c10dffc38..4738d6b428e 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -958,33 +958,69 @@
>[(set_attr "type" "mmxadd")
> (set_attr "mode" "DI")])
>
> -(define_insn "mmx_ashr3"
> - [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
> +(define_expand "mmx_ashr3"
> + [(set (match_operand:MMXMODE24 0 "register_operand")
> (ashiftrt:MMXMODE24
> - (match_operand:MMXMODE24 1 "register_operand" "0")
> - (match_operand:DI 2 "nonmemory_operand" "yN")))]
> - "TARGET_MMX"
> - "psra\t{%2, %0|%0, %2}"
> - [(set_attr "type" "mmxshft")
> + (match_operand:MMXMODE24 1 "register_operand")
> + (match_operand:DI 2 "nonmemory_operand")))]
> + "TARGET_MMX || TARGET_MMX_WITH_SSE")
> +
> +(define_expand "ashr3"
> + [(set (match_operand:MMXMODE24 0 "register_operand")
> +(ashiftrt:MMXMODE24
> + (match_operand:MMXMODE24 1 "register_operand")
> + (match_operand:DI 2 "nonmemory_operand")))]
> + "TARGET_MMX_WITH_SSE")
> +
> +(define_insn "*ashr3"
> + [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv")
> +(ashiftrt:MMXMODE24
> + (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv")
> + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]
> + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> + "@
> + psra\t{%2, %0|%0, %2}
> + psra\t{%2, %0|%0, %2}
> + vpsra\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "mmxshft,sseishft,sseishft")
> (set (attr "length_immediate")
> (if_then_else (match_operand 2 "const_int_operand")
> (const_string "1")
> (const_string "0")))
> - (set_attr "mode" "DI")])
> + (set_attr "mode" "DI,TI,TI")])
>
> -(define_insn "mmx_3"
> - [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
> +(define_expand "mmx_3"
> + [(set (match_operand:MMXMODE248 0 "register_operand")
> (any_lshift:MMXMODE248
> - (match_operand:MMXMODE248 1 "register_operand" "0")
> - (match_operand:DI 2 "nonmemory_operand" "yN")))]
> - "TARGET_MMX"
> - "p\t{%2, %0|%0, %2}"
> - [(set_attr "type" "mmxshft")
> + (match_operand:MMXMODE248 1 "register_operand")
> + (match_operand:DI 2 "nonmemory_operand")))]
> + "TARGET_MMX || TARGET_MMX_WITH_SSE")
> +
> +(define_expand "3"
> + [(set (match_operand:MMXMODE248 0 "register_operand")
> +(any_lshift:MMXMODE248
> + (match_operand:MMXMODE248 1 "register_operand")
> + (match_operand:DI 2 "nonmemory_operand")))]
> + "TARGET_MMX_WITH_SSE")
> +
> +(define_insn "*3"
> + [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv")
> +(any_lshift:MMXMODE248
> + (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv")
> + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]
> + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> + "@
> + p\t{%2, %0|%0, %2}
> + p\t{%2, %0|%0, %2}
> + vp\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "mmxshft,sseishft,sseishft")
> (set (attr "length_immediate")
> (if_then_else (match_operand 2 "const_int_operand")
> (const_string "1")
> (const_string "0")))
> - (set_attr "mode" "DI")])
> + (set_attr "mode" "DI,TI,TI")])
>
> ;
> ;;
> --
> 2.20.1
>
Re: GCC 8 backports
On 2/14/19 12:23 PM, Martin Liška wrote:
> On 11/20/18 11:58 AM, Martin Liška wrote:
>> On 10/3/18 11:23 AM, Martin Liška wrote:
>>> On 9/25/18 8:48 AM, Martin Liška wrote:
Hi.
One more tested patch.
Martin
>>>
>>> One more tested patch.
>>>
>>> Martin
>>>
>>
>> Hi.
>>
>> One another tested patch that I'm going to install.
>>
>> Martin
>>
>
> Hi.
>
> Another 2 patches that I've just tested and will install.
>
> Martin
>
One more patch.
Martin
>From a434c00b2d9a540152ea149244fa8df97f64def4 Mon Sep 17 00:00:00 2001
From: marxin
Date: Thu, 14 Feb 2019 14:25:48 +0100
Subject: [PATCH] Backport r268873
gcc/ChangeLog:
2019-02-14 Martin Liska
PR rtl-optimization/89242
* dce.c (delete_unmarked_insns): Call free_dominance_info we
process a transformation.
gcc/testsuite/ChangeLog:
2019-02-14 Martin Liska
PR rtl-optimization/89242
* g++.dg/pr89242.C: New test.
---
gcc/dce.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/gcc/dce.c b/gcc/dce.c
index 2ef4dd7bd3b..ce2edc43efb 100644
--- a/gcc/dce.c
+++ b/gcc/dce.c
@@ -642,7 +642,10 @@ delete_unmarked_insns (void)
/* Deleted a pure or const call. */
if (must_clean)
-delete_unreachable_blocks ();
+{
+ delete_unreachable_blocks ();
+ free_dominance_info (CDI_DOMINATORS);
+}
}
--
2.20.1
Fix PR72715 "ICE in gfc_trans_omp_do, at fortran/trans-openmp.c:3164"
Hi!
PR72715 "ICE in gfc_trans_omp_do, at fortran/trans-openmp.c:3164" is the
OpenACC variant of the OpenMP PR60127 "ICE with OpenMP and DO CONCURRENT"
(trunk r210331) changes.
On Mon, 29 Aug 2016 14:33:07 -0700, Cesar Philippidis
wrote:
> It looks like the fortran FE has some preliminary support for do
> concurrent loops, however it was not well tested, nor is do concurrent
> supported by the OpenACC spec.
(Tobias Burnus has written up in some further PRs and emails what the
issues are.)
> This patch teaches the fortran FE to
> error when an acc loop directive is applied to a do concurrent loop.
>
> The reason why the existing do concurrent wasn't detected earlier is
> because the only tests that utilized do concurrent loops contained other
> expected failures, therefore the FE never successfully left the resolver
> stage. And this ICE occurred as the loop was being translated into gimple.
>
> There's one other questionably use of EXEC_DO_CONCURRENT that involves
> the OpenACC cache directive. I've decided to leave gfc_exec_oacc_cache
> alone for the time being because the OpenACC spec does not explicitly
> define what it means by 'loop'. Then again, the user isn't required to
> explicitly mark acc loops inside acc kernels regions, so perhaps it
> would be better to leave the end user with more flexibility. On the
> other hand, it's debatable whether do concurrent loops should even be
> permitted inside acc offloaded regions.
>
> I've applied this patch to gomp-4_0-branch. Is this OK for trunk, gcc-6
> and gcc-5?
Thanks. As attached committed to trunk in r268875, and will backport to
release branches later.
Grüße
Thomas
>From dac1fbf62c5293c4b6b2788a6d9677c73088df5d Mon Sep 17 00:00:00 2001
From: tschwinge
Date: Thu, 14 Feb 2019 13:44:19 +
Subject: [PATCH] Fix PR72715 "ICE in gfc_trans_omp_do, at
fortran/trans-openmp.c:3164"
The OpenACC 'resolve_oacc_nested_loops' function duplicates most code of the
OpenMP 'resolve_omp_do', but didn't include the PR60127 "ICE with OpenMP and DO
CONCURRENT" (trunk r210331) changes. (Probably the two functions should be
unified?)
The Fortran DO CONCURRENT construct is a way to tell the compiler that loop
iterations don't have any interdependencies -- which is information that would
very well be suitable for OpenACC/OpenMP loops. There are some "details"
however, see the discussion/references in PR60127, so for the time being, make
this a compile-time error instead of an ICE.
gcc/fortran/
* openmp.c (resolve_oacc_nested_loops): Error on do concurrent
loops.
gcc/testsuite/
* gfortran.dg/goacc/loop-3-2.f95: Error on do concurrent loops.
* gfortran.dg/goacc/loop-3.f95: Likewise.
* gfortran.dg/goacc/pr72715.f90: New test.
Reviewed-by: Thomas Schwinge
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@268875 138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/fortran/ChangeLog| 6 ++
gcc/fortran/openmp.c | 8 +++-
gcc/testsuite/ChangeLog | 7 +++
gcc/testsuite/gfortran.dg/goacc/loop-3-2.f95 | 4 ++--
gcc/testsuite/gfortran.dg/goacc/loop-3.f95 | 4 ++--
gcc/testsuite/gfortran.dg/goacc/pr72715.f90 | 6 ++
6 files changed, 30 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr72715.f90
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index c573f77410c..71cef4f1884 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2019-02-14 Cesar Philippidis
+
+ PR fortran/72715
+ * openmp.c (resolve_oacc_nested_loops): Error on do concurrent
+ loops.
+
2019-02-13 Martin Liska
PR fortran/88649
diff --git a/gcc/fortran/openmp.c b/gcc/fortran/openmp.c
index 15c5842dea4..8651afaee4f 100644
--- a/gcc/fortran/openmp.c
+++ b/gcc/fortran/openmp.c
@@ -5760,7 +5760,13 @@ resolve_oacc_nested_loops (gfc_code *code, gfc_code* do_code, int collapse,
"at %L", _code->loc);
break;
}
- gcc_assert (do_code->op == EXEC_DO || do_code->op == EXEC_DO_CONCURRENT);
+ if (do_code->op == EXEC_DO_CONCURRENT)
+ {
+ gfc_error ("!$ACC LOOP cannot be a DO CONCURRENT loop at %L",
+ _code->loc);
+ break;
+ }
+ gcc_assert (do_code->op == EXEC_DO);
if (do_code->ext.iterator->var->ts.type != BT_INTEGER)
gfc_error ("!$ACC LOOP iteration variable must be of type integer at %L",
_code->loc);
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index def998a14ee..6a649831c94 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2019-02-14 Cesar Philippidis
+
+ PR fortran/72715
+ * gfortran.dg/goacc/loop-3-2.f95: Error on do concurrent loops.
+ * gfortran.dg/goacc/loop-3.f95: Likewise.
+ * gfortran.dg/goacc/pr72715.f90: New test.
+
2019-02-14 Martin Liska
PR rtl-optimization/89242
diff --git a/gcc/testsuite/gfortran.dg/goacc/loop-3-2.f95 b/gcc/testsuite/gfortran.dg/goacc/loop-3-2.f95
index 9be74a85919..c091084a4f5 100644
---
Re: V2 [PATCH] driver: Also prune joined switches with negation
On Thu, Feb 14, 2019 at 12:03:30PM +0100, Jakub Jelinek wrote:
> On Wed, Feb 13, 2019 at 06:27:51PM -0800, H.J. Lu wrote:
> > --- a/gcc/doc/options.texi
> > +++ b/gcc/doc/options.texi
> > @@ -227,7 +227,10 @@ options, their @code{Negative} properties should form
> > a circular chain.
> > For example, if options @option{-@var{a}}, @option{-@var{b}} and
> > @option{-@var{c}} are mutually exclusive, their respective @code{Negative}
> > properties should be @samp{Negative(@var{b})}, @samp{Negative(@var{c})}
> > -and @samp{Negative(@var{a})}.
> > +and @samp{Negative(@var{a})}. @code{Negative} can be used together
> > +with @code{Joined} if there is no @code{RejectNegative} property.
> > +@code{Negative} is ignored if there is @code{Joined} without
> > +@code{RejectNegative}.
>
> I think this doesn't describe what is implemented.
>
> Something like:
> the option name with the leading ``-'' removed. This chain action will
> propagate through the @code{Negative} property of the option to be
> -turned off.
> +turned off. The driver will prune options, removing those that are
> +turned off by some later option. This pruning is not done for options
> +with @code{Joined} or @code{JoinedOrMissing} properties, unless the
> +options have either @code{RejectNegative} property or the @code{Negative}
> +property mentions an option other than itself.
>
> As a consequence, if you have a group of mutually-exclusive
> options, their @code{Negative} properties should form a circular chain.
>
> ?
>
> Otherwise LGTM, but Joseph is the options machinery maintainer, so I'll
> defer to him here.
>
Here is the updated patch with a "-march=native -march=knl" testcase.
Thanks.
H.J.
---
When -march=native is passed to host_detect_local_cpu to the backend,
it overrides all command lines after it. That means
$ gcc -march=native -march=skylake-avx512
is the treated as
$ gcc -march=skylake-avx512 -march=native
Prune joined switches with Negative and RejectNegative to allow
-march=skylake-avx512 to override previous -march=native on command-line.
gcc/
PR driver/69471
* opts-common.c (prune_options): Also prune joined switches
with Negative and RejectNegative.
* config/i386/i386.opt (march=): Add Negative(march=).
(mtune=): Add Negative(mtune=).
* doc/options.texi: Document Negative used together with Joined
and RejectNegative.
gcc/testsuite/
PR driver/69471
* gcc.dg/pr69471-1.c: New test.
* gcc.dg/pr69471-2.c: Likewise.
* gcc.target/i386/pr69471-3.c: Likewise.
---
gcc/config/i386/i386.opt | 4 ++--
gcc/doc/options.texi | 6 +-
gcc/opts-common.c | 11 ---
gcc/testsuite/gcc.dg/pr69471-1.c | 9 +
gcc/testsuite/gcc.dg/pr69471-2.c | 8
gcc/testsuite/gcc.target/i386/pr69471-3.c | 11 +++
6 files changed, 43 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/pr69471-1.c
create mode 100644 gcc/testsuite/gcc.dg/pr69471-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr69471-3.c
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 9b93241f790..b7998ee7363 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -253,7 +253,7 @@ EnumValue
Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
march=
-Target RejectNegative Joined Var(ix86_arch_string)
+Target RejectNegative Negative(march=) Joined Var(ix86_arch_string)
Generate code for given CPU.
masm=
@@ -510,7 +510,7 @@ Target Report Mask(TLS_DIRECT_SEG_REFS)
Use direct references against %gs when accessing tls data.
mtune=
-Target RejectNegative Joined Var(ix86_tune_string)
+Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string)
Schedule code for given CPU.
mtune-ctrl=
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index 0081243acab..1c83d241488 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -220,7 +220,11 @@ property is used.
The option will turn off another option @var{othername}, which is
the option name with the leading ``-'' removed. This chain action will
propagate through the @code{Negative} property of the option to be
-turned off.
+turned off. The driver will prune options, removing those that are
+turned off by some later option. This pruning is not done for options
+with @code{Joined} or @code{JoinedOrMissing} properties, unless the
+options have either @code{RejectNegative} property or the @code{Negative}
+property mentions an option other than itself.
As a consequence, if you have a group of mutually-exclusive
options, their @code{Negative} properties should form a circular chain.
diff --git a/gcc/opts-common.c b/gcc/opts-common.c
index ee8898b22ec..edbb3ac9b6d 100644
--- a/gcc/opts-common.c
+++ b/gcc/opts-common.c
@@ -1015,7 +1015,9 @@ prune_options (struct cl_decoded_option **decoded_options,
Re: [PATCH] Add testcases for multiple -fsanitize=, -fno-sanitize= or -fno-sanitize-recover= options
On Thu, Feb 14, 2019 at 3:09 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following patch adds testcase coverage to make sure
> -f{,no-}sanitize{,-recover}= options are all passed to the compiler backend
> from the driver.
>
> All these tests were broken by the earlier option handling patch from H.J.:
> https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00492.html
> and as nothing in the testsuite revealed the patch broke this, I think we
> want to cover this in the testsuite.
>
> Tested on x86_64-linux with
> make check-gcc check-c++-all RUNTESTFLAGS='--target_board=unix\{-m32,-m64\}
> ubsan.exp=opts*'
> with current trunk (all tests PASS) and with trunk patched with the above
> patch (all tests FAIL). Ok for trunk?
>
> 2019-02-14 Jakub Jelinek
>
> * c-c++-common/ubsan/opts-1.c: New test.
> * c-c++-common/ubsan/opts-2.c: New test.
> * c-c++-common/ubsan/opts-3.c: New test.
> * c-c++-common/ubsan/opts-4.c: New test.
I got
UNRESOLVED: c-c++-common/ubsan/opts-1.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow" 2
UNRESOLVED: c-c++-common/ubsan/opts-1.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_shift_out_of_bounds" 1
UNRESOLVED: c-c++-common/ubsan/opts-2.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow" 2
UNRESOLVED: c-c++-common/ubsan/opts-2.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-not
optimized "__ubsan_handle_shift_out_of_bounds"
UNRESOLVED: c-c++-common/ubsan/opts-3.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow" 1
UNRESOLVED: c-c++-common/ubsan/opts-3.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-not
optimized "__ubsan_handle_shift_out_of_bounds"
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow_abort" 1
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_shift_out_of_bounds_abort" 1
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_type_mismatch_v1" 1
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-not
optimized "__ubsan_handle_type_mismatch_v1_abort"
UNRESOLVED: c-c++-common/ubsan/opts-1.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow" 2
UNRESOLVED: c-c++-common/ubsan/opts-1.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_shift_out_of_bounds" 1
UNRESOLVED: c-c++-common/ubsan/opts-2.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow" 2
UNRESOLVED: c-c++-common/ubsan/opts-2.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-not
optimized "__ubsan_handle_shift_out_of_bounds"
UNRESOLVED: c-c++-common/ubsan/opts-3.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow" 1
UNRESOLVED: c-c++-common/ubsan/opts-3.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-not
optimized "__ubsan_handle_shift_out_of_bounds"
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_divrem_overflow_abort" 1
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_shift_out_of_bounds_abort" 1
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
optimized "__ubsan_handle_type_mismatch_v1" 1
UNRESOLVED: c-c++-common/ubsan/opts-4.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-not
optimized "__ubsan_handle_type_mismatch_v1_abort"
since -flto suppresses -fdump-tree-optimized.
H.J.
> --- gcc/testsuite/c-c++-common/ubsan/opts-1.c.jj2019-02-14
> 11:31:33.144895232 +0100
> +++ gcc/testsuite/c-c++-common/ubsan/opts-1.c 2019-02-14 11:33:23.049077585
> +0100
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-fsanitize=undefined -fsanitize=shift
> -fsanitize=float-divide-by-zero -fdump-tree-optimized" } */
> +/* { dg-final { scan-tree-dump-times "__ubsan_handle_divrem_overflow" 2
> "optimized" } } */
> +/* { dg-final { scan-tree-dump-times "__ubsan_handle_shift_out_of_bounds" 1
> "optimized" } } */
> +
> +int
> +foo (int x, int y)
> +{
> + return x / y;
> +}
> +
> +int
> +bar (int x, int y)
> +{
> + return x << y;
> +}
> +
> +float
> +baz (float x,
[PR fortran/89348, patch] Fortran Command Options documentation fixes
Enabling of -fdec-include is missing from list of options enabled by
-fdec. When rendered as a PDF some lines are too long in the list of
options controlling Fortran dialect and in the list of options to
request or suppress errors and warnings.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89348
gcc/fortran/ChangeLog:
2019-02-14 Mark Eggleston
PR fortran/89348
* invoke.texi: Lines too long for PDF in option lists. Add
-fdec-include to list of options enabled by -fdec.
OK for trunk? I do not have commit access.
regards, Mark
--
https://www.codethink.co.uk/privacy.html
>From 876b91cfa9aaed30a621fc80d98a9d2820170ad7 Mon Sep 17 00:00:00 2001
From: Mark Eggleston
Date: Tue, 12 Feb 2019 15:52:47 +
Subject: [PATCH] Fortran Command Options documentation fixes.
Enabling of -fdec-include missing from list of options enabled by -fdec.
Some lines were too long in the list of options controlling Fortran dialect
and in the list of options to request or suppress errors and warnings.
---
gcc/fortran/invoke.texi | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/gcc/fortran/invoke.texi b/gcc/fortran/invoke.texi
index 80804993522..27ad0721a7d 100644
--- a/gcc/fortran/invoke.texi
+++ b/gcc/fortran/invoke.texi
@@ -144,14 +144,15 @@ by type. Explanations are in the following sections.
@item Error and Warning Options
@xref{Error and Warning Options,,Options to request or suppress errors
and warnings}.
-@gccoptlist{-Waliasing -Wall -Wampersand -Wargument-mismatch -Warray-bounds
--Wc-binding-type -Wcharacter-truncation -Wconversion @gol
+@gccoptlist{-Waliasing -Wall -Wampersand -Wargument-mismatch @gol
+-Warray-bounds -Wc-binding-type -Wcharacter-truncation -Wconversion @gol
-Wdo-subscript -Wfunction-elimination -Wimplicit-interface @gol
--Wimplicit-procedure -Wintrinsic-shadow -Wuse-without-only -Wintrinsics-std @gol
--Wline-truncation -Wno-align-commons -Wno-tabs -Wreal-q-constant @gol
--Wsurprising -Wunderflow -Wunused-parameter -Wrealloc-lhs @gol
--Wrealloc-lhs-all -Wfrontend-loop-interchange -Wtarget-lifetime @gol
--fmax-errors=@var{n} -fsyntax-only -pedantic -pedantic-errors @gol
+-Wimplicit-procedure -Wintrinsic-shadow -Wuse-without-only @gol
+-Wintrinsics-std -Wline-truncation -Wno-align-commons -Wno-tabs @gol
+-Wreal-q-constant -Wsurprising -Wunderflow -Wunused-parameter @gol
+-Wrealloc-lhs -Wrealloc-lhs-all -Wfrontend-loop-interchange @gol
+-Wtarget-lifetime -fmax-errors=@var{n} -fsyntax-only -pedantic @gol
+-pedantic-errors
}
@item Debugging Options
@@ -183,15 +184,15 @@ and warnings}.
@gccoptlist{-faggressive-function-elimination -fblas-matmul-limit=@var{n} @gol
-fbounds-check -fcheck-array-temporaries @gol
-fcheck=@var{} @gol
--fcoarray=@var{} -fexternal-blas -ff2c
+-fcoarray=@var{} -fexternal-blas -ff2c @gol
-ffrontend-loop-interchange @gol
-ffrontend-optimize @gol
-finit-character=@var{n} -finit-integer=@var{n} -finit-local-zero @gol
-finit-derived @gol
--finit-logical=@var{}
+-finit-logical=@var{} @gol
-finit-real=@var{} @gol
-finline-matmul-limit=@var{n} @gol
--fmax-array-constructor=@var{n} -fmax-stack-var-size=@var{n}
+-fmax-array-constructor=@var{n} -fmax-stack-var-size=@var{n} @gol
-fno-align-commons @gol
-fno-automatic -fno-protect-parens -fno-underscoring @gol
-fsecond-underscore -fpack-derived -frealloc-lhs -frecursive @gol
@@ -251,6 +252,7 @@ full documentation.
Other flags enabled by this switch are:
@option{-fdollar-ok} @option{-fcray-pointer} @option{-fdec-structure}
@option{-fdec-intrinsic-ints} @option{-fdec-static} @option{-fdec-math}
+@option{-fdec-include}
If @option{-fd-lines-as-code}/@option{-fd-lines-as-comments} are unset, then
@option{-fdec} also sets @option{-fd-lines-as-comments}.
--
2.11.0
Re: [PR fortran/89348, patch] Fortran Command Options documentation fixes
Mark, > Patch and change log attached to PR. Could you please submit this the normal way, with the ChangeLog in the text and the patch ad attachment? Regards, Thomas
Re: PR87689, PowerPC64 ELFv2 function parameter passing violation
On Thu, Feb 14, 2019 at 10:32:50AM +0100, Richard Biener wrote: > On Wed, Feb 13, 2019 at 7:59 AM Alan Modra wrote: > > > > Covers for a generic fortran bug. The effect is that we'll needlessly > > waste 64 bytes of stack space on some calls, but I don't see any > > simple and fully correct patch in generic code. Bootstrapped and > > regression tested powerpc64le-linux. OK mainline and branches? > > This looks very wrong to me ;) It won't work when compiling with -flto > for example. Blah. Nothing looks right to me. :) That patch was really me giving up on the bug (and hoping I'd found a suitable hack that could be applied to gcc-8 and gcc-7). > The frontend needs to be properly fixed. You'll notice I didn't assign myself to the bug.. -- Alan Modra Australia Development Lab, IBM
[PATCH 38/40] i386: Enable TM MMX intrinsics with SSE2
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1d417e08734..20219983462 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31075,13 +31075,13 @@ static const struct builtin_description
bdesc_##kind[] = \
we're lazy. Add casts to make them fit. */
static const struct builtin_description bdesc_tm[] =
{
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum
ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum
ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum
ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum
ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum
ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum
ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum
ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN,
VOID_FTYPE_PV2SI_V2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64,
UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64,
UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN,
V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64,
UNKNOWN, V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64,
UNKNOWN, V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64,
UNKNOWN, V2SI_FTYPE_PCV2SI },
{ OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum
ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
{ OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum
ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
@@ -31099,7 +31099,7 @@ static const struct builtin_description bdesc_tm[] =
{ OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum
ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
{ OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum
ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum
ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
"__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN,
VOID_FTYPE_PCVOID },
{ OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum
ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
{ OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum
ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
};
--
2.20.1
[PATCH 32/40] i386: Emulate MMX ssse3_psign3 with SSE
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a92505c54a1..f235fe36a2d 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15804,17 +15804,21 @@
(set_attr "mode" "")])
(define_insn "ssse3_psign3"
- [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
+ [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv")
(unspec:MMXMODEI
- [(match_operand:MMXMODEI 1 "register_operand" "0")
- (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
+ [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv")
+ (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym,x,Yv")]
UNSPEC_PSIGN))]
- "TARGET_SSSE3"
- "psign\t{%2, %0|%0, %2}";
- [(set_attr "type" "sselog1")
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+ "@
+ psign\t{%2, %0|%0, %2}
+ psign\t{%2, %0|%0, %2}
+ vpsign\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "DI,TI,TI")])
(define_insn "_palignr_mask"
[(set (match_operand:VI1_AVX512 0 "register_operand" "=v")
--
2.20.1
[PATCH 26/40] i386: Emulate MMX umulv1siv1di3 with SSE2
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 274e895f51e..a618a620eb1 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -911,24 +911,30 @@
(vec_select:V1SI
(match_operand:V2SI 2 "nonimmediate_operand")
(parallel [(const_int 0)])]
- "TARGET_SSE2"
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
(define_insn "*sse2_umulv1siv1di3"
- [(set (match_operand:V1DI 0 "register_operand" "=y")
+ [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
(mult:V1DI
(zero_extend:V1DI
(vec_select:V1SI
- (match_operand:V2SI 1 "nonimmediate_operand" "%0")
+ (match_operand:V2SI 1 "nonimmediate_operand" "%0,0,Yv")
(parallel [(const_int 0)])))
(zero_extend:V1DI
(vec_select:V1SI
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+ (match_operand:V2SI 2 "nonimmediate_operand" "ym,x,Yv")
(parallel [(const_int 0)])]
- "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
- "pmuludq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "DI")])
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+ && TARGET_SSE2
+ && ix86_binary_operator_ok (MULT, V2SImode, operands)"
+ "@
+ pmuludq\t{%2, %0|%0, %2}
+ pmuludq\t{%2, %0|%0, %2}
+ vpmuludq\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "mmxmul,ssemul,ssemul")
+ (set_attr "mode" "DI,TI,TI")])
(define_expand "mmx_v4hi3"
[(set (match_operand:V4HI 0 "register_operand")
--
2.20.1
[PATCH 28/40] i386: Emulate MMX ssse3_phdv2si3 with SSE
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.md | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 97cbd250dd4..af6a305d63e 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15381,26 +15381,44 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "ssse3_phdv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
+(define_insn_and_split "ssse3_phdv2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
(vec_concat:V2SI
(plusminus:SI
(vec_select:SI
- (match_operand:V2SI 1 "register_operand" "0")
+ (match_operand:V2SI 1 "register_operand" "0,0,Yv")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(plusminus:SI
(vec_select:SI
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+ (match_operand:V2SI 2 "nonimmediate_operand" "ym,x,Yv")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])]
- "TARGET_SSSE3"
- "phd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+ "@
+ phd\t{%2, %0|%0, %2}
+ #
+ #"
+ "TARGET_MMX_WITH_SSE && reload_completed"
+ [(const_int 0)]
+{
+ /* Generate SSE version of the operation. */
+ rtx op0 = lowpart_subreg (V4SImode, operands[0],
+ GET_MODE (operands[0]));
+ rtx op1 = lowpart_subreg (V4SImode, operands[1],
+ GET_MODE (operands[1]));
+ rtx op2 = lowpart_subreg (V4SImode, operands[2],
+ GET_MODE (operands[2]));
+ emit_insn (gen_ssse3_phdv4si3 (op0, op1, op2));
+ ix86_move_vector_high_sse_to_mmx (op0);
+ DONE;
+}
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "DI,TI,TI")])
(define_insn "avx2_pmaddubsw256"
[(set (match_operand:V16HI 0 "register_operand" "=x,v")
--
2.20.1
[PATCH 21/40] i386: Emulate MMX maskmovq with SSE2 maskmovdqu
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/xmmintrin.h: Emulate MMX maskmovq with SSE2
maskmovdqu for __MMX_WITH_SSE__.
---
gcc/config/i386/i386-c.c| 2 ++
gcc/config/i386/xmmintrin.h | 61 +
2 files changed, 63 insertions(+)
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 5e7e46fcebe..213e1b56c6b 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -548,6 +548,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__CLDEMOTE__");
if (isa_flag2 & OPTION_MASK_ISA_PTWRITE)
def_or_undef (parse_in, "__PTWRITE__");
+ if (TARGET_MMX_WITH_SSE)
+def_or_undef (parse_in, "__MMX_WITH_SSE__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h
index 58284378514..a915f6c87d7 100644
--- a/gcc/config/i386/xmmintrin.h
+++ b/gcc/config/i386/xmmintrin.h
@@ -1165,7 +1165,68 @@ _m_pshufw (__m64 __A, int const __N)
extern __inline void __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
{
+#ifdef __MMX_WITH_SSE__
+ /* Emulate MMX maskmovq with SSE2 maskmovdqu and handle unmapped bits
+ 64:127 at address __P. */
+ typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+ typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+ /* Zero-extend __A and __N to 128 bits. */
+ __v2di __A128 = __extension__ (__v2di) { ((__v1di) __A)[0], 0 };
+ __v2di __N128 = __extension__ (__v2di) { ((__v1di) __N)[0], 0 };
+
+ /* Check the alignment of __P. */
+ __SIZE_TYPE__ offset = ((__SIZE_TYPE__) __P) & 0xf;
+ if (offset)
+{
+ /* If the misalignment of __P > 8, subtract __P by 8 bytes.
+Otherwise, subtract __P by the misalignment. */
+ if (offset > 8)
+ offset = 8;
+ __P = (char *) (((__SIZE_TYPE__) __P) - offset);
+
+ /* Shift __A128 and __N128 to the left by the adjustment. */
+ switch (offset)
+ {
+ case 1:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 8);
+ break;
+ case 2:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 2 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 2 * 8);
+ break;
+ case 3:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 3 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 3 * 8);
+ break;
+ case 4:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 4 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 4 * 8);
+ break;
+ case 5:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 5 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 5 * 8);
+ break;
+ case 6:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 6 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 6 * 8);
+ break;
+ case 7:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 7 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 7 * 8);
+ break;
+ case 8:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 8 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 8 * 8);
+ break;
+ default:
+ break;
+ }
+}
+ __builtin_ia32_maskmovdqu ((__v16qi)__A128, (__v16qi)__N128, __P);
+#else
__builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P);
+#endif
}
extern __inline void __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
--
2.20.1
[PATCH 27/40] i386: Emulate MMX ssse3_phwv4hi3 with SSE
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.md | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b1bab15af41..97cbd250dd4 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15257,13 +15257,13 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "ssse3_phwv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
+(define_insn_and_split "ssse3_phwv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
(vec_concat:V4HI
(vec_concat:V2HI
(ssse3_plusminus:HI
(vec_select:HI
- (match_operand:V4HI 1 "register_operand" "0")
+ (match_operand:V4HI 1 "register_operand" "0,0,Yv")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ssse3_plusminus:HI
@@ -15272,19 +15272,37 @@
(vec_concat:V2HI
(ssse3_plusminus:HI
(vec_select:HI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")
+ (match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))]
- "TARGET_SSSE3"
- "phw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+ "@
+ phw\t{%2, %0|%0, %2}
+ #
+ #"
+ "TARGET_MMX_WITH_SSE && reload_completed"
+ [(const_int 0)]
+{
+ /* Generate SSE version of the operation. */
+ rtx op0 = lowpart_subreg (V8HImode, operands[0],
+ GET_MODE (operands[0]));
+ rtx op1 = lowpart_subreg (V8HImode, operands[1],
+ GET_MODE (operands[1]));
+ rtx op2 = lowpart_subreg (V8HImode, operands[2],
+ GET_MODE (operands[2]));
+ emit_insn (gen_ssse3_phwv8hi3 (op0, op1, op2));
+ ix86_move_vector_high_sse_to_mmx (op0);
+ DONE;
+}
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "DI,TI,TI")])
(define_insn "avx2_phdv8si3"
[(set (match_operand:V8SI 0 "register_operand" "=x")
--
2.20.1
[PATCH 29/40] i386: Emulate MMX ssse3_pmaddubsw with SSE
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index af6a305d63e..a7d0889f3e1 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15569,17 +15569,17 @@
(set_attr "mode" "TI")])
(define_insn "ssse3_pmaddubsw"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
+ [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
(ss_plus:V4HI
(mult:V4HI
(zero_extend:V4HI
(vec_select:V4QI
- (match_operand:V8QI 1 "register_operand" "0")
+ (match_operand:V8QI 1 "register_operand" "0,0,Yv")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))
(sign_extend:V4HI
(vec_select:V4QI
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")
+ (match_operand:V8QI 2 "nonimmediate_operand" "ym,x,Yv")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)]
(mult:V4HI
@@ -15591,13 +15591,17 @@
(vec_select:V4QI (match_dup 2)
(parallel [(const_int 1) (const_int 3)
(const_int 5) (const_int 7)]))]
- "TARGET_SSSE3"
- "pmaddubsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+ "@
+ pmaddubsw\t{%2, %0|%0, %2}
+ pmaddubsw\t{%2, %0|%0, %2}
+ vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "DI,TI,TI")])
(define_mode_iterator PMULHRSW
[V4HI V8HI (V16HI "TARGET_AVX2")])
--
2.20.1
[PATCH 19/40] i386: Emulate MMX mmx_pmovmskb with SSE
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
gcc/config/i386/mmx.md | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index dcc1bd1becf..9ff0db9c2ed 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1774,14 +1774,30 @@
[(set_attr "type" "mmxshft")
(set_attr "mode" "DI")])
-(define_insn "mmx_pmovmskb"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
+(define_insn_and_split "mmx_pmovmskb"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x")]
UNSPEC_MOVMSK))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pmovmskb\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+ && (TARGET_SSE || TARGET_3DNOW_A)"
+ "@
+ pmovmskb\t{%1, %0|%0, %1}
+ #"
+ "TARGET_MMX_WITH_SSE && reload_completed"
+ [(set (match_dup 0)
+(unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
+ (set (match_dup 0)
+ (zero_extend:SI (match_dup 2)))]
+{
+ /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */
+ operands[1] = lowpart_subreg (V16QImode, operands[1],
+ GET_MODE (operands[1]));
+ operands[2] = lowpart_subreg (QImode, operands[0],
+ GET_MODE (operands[0]));
+}
+ [(set_attr "mmx_isa" "native,x64")
+ (set_attr "type" "mmxcvt,ssemov")
+ (set_attr "mode" "DI,TI")])
(define_expand "mmx_maskmovq"
[(set (match_operand:V8QI 0 "memory_operand")
--
2.20.1
