Re: [PATCH 2/4 GCC11] Add target hook stride_dform_valid_p
Hi, I'd like to ping this patch as well as its sblings. Thanks in advance. 1/4 v3 https://gcc.gnu.org/pipermail/gcc-patches/2020-February/540171.html 2/4 v3 https://gcc.gnu.org/pipermail/gcc-patches/2020-March/541387.html 3/4 v3 https://gcc.gnu.org/pipermail/gcc-patches/2020-May/545643.html BR, Kewen on 2020/3/3 下午8:25, Kewen.Lin wrote: > Hi Richard, > > Thanks for your comments! It's a good idea to use param due to the > flexibility. And yes, it sounds good to have more targets to try and > make it better. But I have a bit concern on turning it on by default. > Since it replies on unroll factor estimation, as part 1/4 shows, it > calls targetm.loop_unroll_adjust if target supports, which used to > work on RTL level. To avoid possible ICE, I'm intended to turn it > off for those targets (s390 & i386) with that hook, since without good > understanding on those targets, it's hard for me to extend them with > gimple level support. Does it make sense? > > The updated patch has been attached. > > BR, > Kewen > - > > gcc/ChangeLog > > 2020-03-03 Kewen Lin > > * doc/invoke.texi (iv-consider-reg-offset-for-unroll): Document new > option. > * params.opt (iv-consider-reg-offset-for-unroll): New. > * config/s390/s390.c (s390_option_override_internal): Disable parameter > iv-consider-reg-offset-for-unroll by default. > * config/i386/i386-options.c (ix86_option_override_internal): Likewise. >
[PATCH 3/4 V3 GCC11] IVOPTs Consider cost_step on different forms during unrolling
Hi,
Updated to v3 according to 2/4's param change.
BR,
Kewen
---
gcc/ChangeLog
2020-MM-DD Kewen Lin
* tree-ssa-loop-ivopts.c (struct iv_group): New field reg_offset_p.
(struct iv_cand): New field reg_offset_p.
(struct ivopts_data): New field consider_reg_offset_for_unroll_p.
(dump_groups): Dump group with reg_offset_p.
(record_group): Initialize reg_offset_p.
(mark_reg_offset_groups): New function.
(find_interesting_uses): Call mark_reg_offset_groups.
(add_candidate_1): Update reg_offset_p if derived from reg_offset_p
group.
(set_group_iv_cost): Scale up group cost with estimate_unroll_factor if
consider_reg_offset_for_unroll_p.
(determine_iv_cost): Increase step cost with estimate_unroll_factor if
consider_reg_offset_for_unroll_p.
(tree_ssa_iv_optimize_loop): Call estimate_unroll_factor, update
consider_reg_offset_for_unroll_p.
on 2020/2/25 下午5:48, Kewen.Lin wrote:
> Hi,
>
> As the proposed hook changes, updated this with main changes:
> 1) Check with addr_offset_valid_p instead.
> 2) Check the 1st and the last use for the whole address group.
> 3) Scale up group costs accordingly.
>
> Bootstrapped/regtested on powerpc64le-linux-gnu (LE).
>
> BR,
> Kewen
> ---
>
> gcc/ChangeLog
>
> 2020-02-25 Kewen Lin
>
> * tree-ssa-loop-ivopts.c (struct iv_group): New field reg_offset_p.
> (struct iv_cand): New field reg_offset_p.
> (struct ivopts_data): New field consider_reg_offset_for_unroll_p.
> (dump_groups): Dump group with reg_offset_p.
> (record_group): Initialize reg_offset_p.
> (mark_reg_offset_groups): New function.
> (find_interesting_uses): Call mark_reg_offset_groups.
> (add_candidate_1): Update reg_offset_p if derived from reg_offset_p
> group.
> (set_group_iv_cost): Scale up group cost with estimate_unroll_factor if
> consider_reg_offset_for_unroll_p.
> (determine_iv_cost): Increase step cost with estimate_unroll_factor if
> consider_reg_offset_for_unroll_p.
> (tree_ssa_iv_optimize_loop): Call estimate_unroll_factor, update
> consider_reg_offset_for_unroll_p.
>
diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c
index 1d2697ae1ba..1b7e4621f37 100644
--- a/gcc/tree-ssa-loop-ivopts.c
+++ b/gcc/tree-ssa-loop-ivopts.c
@@ -432,6 +432,8 @@ struct iv_group
struct iv_cand *selected;
/* To indicate this is a doloop use group. */
bool doloop_p;
+ /* To indicate this group is reg_offset valid. */
+ bool reg_offset_p;
/* Uses in the group. */
vec vuses;
};
@@ -473,6 +475,7 @@ struct iv_cand
struct iv *orig_iv; /* The original iv if this cand is added from biv with
smaller type. */
bool doloop_p; /* Whether this is a doloop candidate. */
+ bool reg_offset_p;/* Derived from one reg_offset valid group. */
};
/* Hashtable entry for common candidate derived from iv uses. */
@@ -653,6 +656,10 @@ struct ivopts_data
/* Whether the loop has doloop comparison use. */
bool doloop_use_p;
+
+ /* Whether need to consider register offset addressing mode for the loop with
+ upcoming unrolling by estimated unroll factor. */
+ bool consider_reg_offset_for_unroll_p;
};
/* An assignment of iv candidates to uses. */
@@ -840,6 +847,11 @@ dump_groups (FILE *file, struct ivopts_data *data)
gcc_assert (group->type == USE_COMPARE);
fprintf (file, " Type:\tCOMPARE\n");
}
+ if (group->reg_offset_p)
+ {
+ gcc_assert (address_p (group->type));
+ fprintf (file, " reg_offset_p: true\n");
+ }
for (j = 0; j < group->vuses.length (); j++)
dump_use (file, group->vuses[j]);
}
@@ -1582,6 +1594,7 @@ record_group (struct ivopts_data *data, enum use_type
type)
group->related_cands = BITMAP_ALLOC (NULL);
group->vuses.create (1);
group->doloop_p = false;
+ group->reg_offset_p = false;
data->vgroups.safe_push (group);
return group;
@@ -2731,6 +2744,60 @@ split_address_groups (struct ivopts_data *data)
}
}
+/* Go through all address type groups, check and mark reg_offset addressing
mode
+ valid groups. */
+
+static void
+mark_reg_offset_groups (struct ivopts_data *data)
+{
+ class loop *loop = data->current_loop;
+ gcc_assert (data->current_loop->estimated_unroll > 1);
+ bool any_reg_offset_p = false;
+
+ for (unsigned i = 0; i < data->vgroups.length (); i++)
+{
+ struct iv_group *group = data->vgroups[i];
+ if (address_p (group->type))
+ {
+ struct iv_use *head_use = group->vuses[0];
+ if (!tree_fits_poly_int64_p (head_use->iv->step))
+ continue;
+
+ bool found = true;
+ poly_int64 step = tree_to_poly_int64 (head_use->iv->step);
+ /* Max extra offset to fill for head of group. */
+ poly_int64 max_increase =
[PATCH] c++: SFINAE for invalid delete-expression [PR79706]
This fixes SFINAE when substitution yields an invalid delete-expression
due to the pertinent deallocation function being marked deleted or
otherwise inaccessible.
We need to check for an erroneous result from build_op_delete_call and
exit early in that case, so that we don't build a COND_EXPR around the
erroneous call which finish_decltype_type would then quietly accept.
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK to
commit?
gcc/cp/ChangeLog:
PR c++/79706
* init.c (build_vec_delete_1): Return error_mark_node if
deallocate_expr is error_mark_node.
(build_delete): Return error_mark_node if do_delete is
error_mark_node.
gcc/testsuite/ChangeLog:
PR c++/79706
* g++.dg/template/sfinae30.C: New test.
---
gcc/cp/init.c| 8 ++--
gcc/testsuite/g++.dg/template/sfinae30.C | 21 +
2 files changed, 27 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/template/sfinae30.C
diff --git a/gcc/cp/init.c b/gcc/cp/init.c
index e2e547afd96..c1047dbb1cc 100644
--- a/gcc/cp/init.c
+++ b/gcc/cp/init.c
@@ -4076,7 +4076,9 @@ build_vec_delete_1 (location_t loc, tree base, tree
maxindex, tree type,
}
body = loop;
- if (!deallocate_expr)
+ if (deallocate_expr == error_mark_node)
+return error_mark_node;
+ else if (!deallocate_expr)
;
else if (!body)
body = deallocate_expr;
@@ -4993,7 +4995,9 @@ build_delete (location_t loc, tree otype, tree addr,
return expr;
}
- if (do_delete)
+ if (do_delete == error_mark_node)
+return error_mark_node;
+ else if (do_delete)
{
tree do_delete_call_expr = extract_call_expr (do_delete);
if (TREE_CODE (do_delete_call_expr) == CALL_EXPR)
diff --git a/gcc/testsuite/g++.dg/template/sfinae30.C
b/gcc/testsuite/g++.dg/template/sfinae30.C
new file mode 100644
index 000..82f31aaa625
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/sfinae30.C
@@ -0,0 +1,21 @@
+// PR c++/79706
+// { dg-do compile { target c++11 } }
+
+struct A {
+ void operator delete(void*) = delete;
+private:
+ void operator delete[](void*);
+};
+
+extern A *p;
+
+template
+auto foo(T *t) -> decltype(delete t); // { dg-error "use of deleted function" }
+
+template
+auto bar(T *t) -> decltype(delete[] t); // { dg-error "private within this
context" }
+
+void baz() {
+ foo(p); // { dg-error "no match" }
+ bar(p); // { dg-error "no match" }
+}
--
2.26.2.561.g07d8ea56f2
Re: [PATCH] Refactor tree-vrp.c
Hi. On 05/11, Richard Biener wrote: > On Fri, May 8, 2020 at 7:11 PM Jeff Law via Gcc-patches > wrote: > > > > On Fri, 2020-05-08 at 13:06 -0300, Giuliano Belinassi via Gcc-patches wrote: > > > Hi, > > > > > > This patch Refactors tree-vrp.c to eliminate all global variables except > > > 'x_vrp_values', which will require that 'thread_outgoing_edges' to > > > accept an extra argument and pass it to the 'simplify' callback. > > > > > > It also removes every access to 'cfun', retrieving the function being > > > compiled from the pass engine. > > > > > > Bootstrapped and ran the testsuite on Linux x86_64. > > > > > > gcc/ChangeLog > > > 2020-05-08 Giuliano Belinassi > > > > > > * tree-vrp.c (class liveness): New. > > > (insert_range_assertions): Move to class liveness. > > > (dump_all_asserts): Same as above. > > > (dump_asserts_for): Same as above. > > > (live): Same as above. > > > (need_assert_for): Same as above. > > > (live_on_edge): Same as above. > > > (finish_register_edge_assert_for): Same as above. > > > (find_switch_asserts): Same as above. > > > (find_assert_locations): Same as above. > > > (find_assert_locations_1): Same as above. > > > (find_conditional_asserts): Same as above. > > > (process_assert_insertions): Same as above. > > > (register_new_assert_for): Same as above. > > > (vrp_prop): New variable fun. > > > (vrp_initialize): New parameter. > > > (identify_jump_threads): Same as above. > > > (execute_vrp): Same as above. > > Just a note. While the old VRP implementation in tree-vrp.c is on the > > chopping > > block, but it'll likely be the end of summer before we know if further work > > in > > the new Ranger based implementation will be needed to totally replace > > tree-vrp > > w/o introducing any performance regressions. > > > > Thus, IMHO, we should go forward with the review. > > Agreed, so I went ahead and reviewed it. The only comment I have is > that 'liveness' is not a good match for the machinery which is about > insertion of ASSERT_EXPR stmts for VRP. I suggest to use > vrp_insert or vrp_asserts instead. Renamed to vrp_insert, bootstrapped, and commited to master as trivial. Giuliano. > > OK with that change. > Richard. > > > > > Jeff > > > > > >
Re: [PR 95013] EOF location is at end of file
On Tue, May 12, 2020 at 2:24 PM Nathan Sidwell wrote:
>
> My recent C++ parser change to pay attention to EOF location uncovered a
> separate bug. The preprocesor's EOF logic would set the EOF location to
> be the beginning of the last line of text in the file -- not the 'line'
> after that, which contains no characters. Mostly. This fixes things so
> that when we attempt to read the last line of the main file, we don't
> pop the buffer until the tokenizer has a chance to create an EOF token
> with the correct location information. It is then responsible for
> popping the buffer. As it happens, raw string literal tokenizing
> contained a bug -- it would increment the line number prematurely,
> because it cached buffer->cur in a local variable, but checked
> buffer->cur before updating it to figure out if it was at end of file.
> We fix up that too.
>
> The EOF token intentionally doesn't have a column number -- it's not a
> position on a line, it's a non-existant line.
>
> The testsuite churn is just correcting the EOF location diagnostics.
> This time I've made sure to check all testsuites, sorry obj-c++ folks.
>
> pushed to master.
>
> nathan
>
> --
> Nathan Sidwell
I got
ERROR: gcc.dg/unclosed-init.c: syntax error in target selector ".+1"
for " dg-error 3 "-: expected '.' at end of input" { target *-*-* }
.+1 "
ERROR: gcc.dg/unclosed-init.c: syntax error in target selector ".+1"
for " dg-error 3 "-: expected '.' at end of input" { target *-*-* }
.+1 "
ERROR: gcc.dg/unclosed-init.c: syntax error in target selector ".+1"
for " dg-error 3 "-: expected '.' at end of input" { target *-*-* }
.+1 "
ERROR: gcc.dg/unclosed-init.c: syntax error in target selector ".+1"
for " dg-error 3 "-: expected '.' at end of input" { target *-*-* }
.+1 "
ERROR: gcc.dg/unclosed-init.c: syntax error in target selector ".+1"
for " dg-error 3 "-: expected '.' at end of input" { target *-*-* }
.+1 "
ERROR: gcc.dg/unclosed-init.c: syntax error in target selector ".+1"
for " dg-error 3 "-: expected '.' at end of input" { target *-*-* }
.+1 "
on Linux/x86:
https://gcc.gnu.org/pipermail/gcc-regression/2020-May/072573.html
--
H.J.
[PATCH] RISC-V: Make unique SECCAT_SRODATA names start with .srodata
This fixes a bug reported to the RISC-V sw-dev mailing list late last year.
https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/JV5Jdh4UjVw
Keith Packard wote the obvious patch to fix it. I tested it with cross builds
for riscv32-newlib and riscv64-linux. There were no regressions. Checking
toolchain libraries with objdump shows that there are no longer sdata2 sections
in the libraries.
Committed.
Jim
2020-05-12 Keith Packard
* config/riscv/riscv.c (riscv_unique_section): New.
(TARGET_ASM_UNIQUE_SECTION): New.
default_unique_section uses ".sdata2" as a prefix for SECCAT_SRODATA
unique sections, but RISC-V uses ".srodata" instead. Override the
TARGET_ASM_UNIQUE_SECTION function to catch this case, allowing the
default to be used for all other sections.
Signed-off-by: Keith Packard
---
gcc/config/riscv/riscv.c | 40
1 file changed, 40 insertions(+)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index e4c08d780db..1ad9799fce4 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3492,6 +3492,43 @@ riscv_select_section (tree decl, int reloc,
}
}
+/* Switch to the appropriate section for output of DECL. */
+
+static void
+riscv_unique_section (tree decl, int reloc)
+{
+ const char *prefix = NULL;
+ bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
+
+ switch (categorize_decl_for_section (decl, reloc))
+{
+case SECCAT_SRODATA:
+ prefix = one_only ? ".sr" : ".srodata";
+ break;
+
+default:
+ break;
+}
+ if (prefix)
+{
+ const char *name, *linkonce;
+ char *string;
+
+ name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
+ name = targetm.strip_name_encoding (name);
+
+ /* If we're using one_only, then there needs to be a .gnu.linkonce
+prefix to the section name. */
+ linkonce = one_only ? ".gnu.linkonce" : "";
+
+ string = ACONCAT ((linkonce, prefix, ".", name, NULL));
+
+ set_decl_section_name (decl, string);
+ return;
+}
+ default_unique_section (decl, reloc);
+}
+
/* Return a section for X, handling small data. */
static section *
@@ -5254,6 +5291,9 @@ riscv_new_address_profitable_p (rtx memref, rtx_insn
*insn, rtx new_addr)
#undef TARGET_ASM_SELECT_SECTION
#define TARGET_ASM_SELECT_SECTION riscv_select_section
+#undef TARGET_ASM_UNIQUE_SECTION
+#define TARGET_ASM_UNIQUE_SECTION riscv_unique_section
+
#undef TARGET_ASM_SELECT_RTX_SECTION
#define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
--
2.17.1
[PATCH] Add -fsplit-dwarf
-fsplit-dwarf is similar to -gsplit-dwarf, but does not enable debugging
information by itself. This makes it easier to be plugged into a build
system without worrying that unnecessary debugging information may be
generated.
2020-05-12 Fangrui Song
PR debug/95096
* common.opt: Add -fsplit-dwarf.
* doc/invoke.texi: Document it.
---
gcc/common.opt | 4
gcc/doc/invoke.texi | 8
2 files changed, 12 insertions(+)
diff --git a/gcc/common.opt b/gcc/common.opt
index 4464049fc1f..07aa9f28002 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -2515,6 +2515,10 @@ fsingle-precision-constant
Common Report Var(flag_single_precision_constant) Optimization
Convert floating point constants to single precision constants.
+fsplit-dwarf
+Common Driver Var(dwarf_split_debug_info) Init(0)
+If debug information is enabled, generate debug information in separate .dwo
files.
+
fsplit-ivs-in-unroller
Common Report Var(flag_split_ivs_in_unroller) Init(1) Optimization
Split lifetimes of induction variables when loops are unrolled.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 850aeac033d..6590e60f5b3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -448,6 +448,7 @@ Objective-C and Objective-C++ Dialects}.
-femit-struct-debug-detailed@r{[}=@var{spec-list}@r{]} @gol
-fno-eliminate-unused-debug-symbols -femit-class-debug-always @gol
-fno-merge-debug-strings -fno-dwarf2-cfi-asm @gol
+-fsplit-dwarf @gol
-fvar-tracking -fvar-tracking-assignments}
@item Optimization Options
@@ -8771,6 +8772,13 @@ also be used to change an absolute path to a relative
path by using
are location independent, but may require an extra command to tell GDB
where to find the source files. See also @option{-ffile-prefix-map}.
+@item -fsplit-dwarf
+@opindex fsplit-dwarf
+If DWARF debugging information is enabled, separate as much debugging
+information as possible into a separate output file with the extension
+@file{.dwo}. This is similar to @option{-gsplit-dwarf}, but this option
+does not enable debugging information by itself.
+
@item -fvar-tracking
@opindex fvar-tracking
Run variable tracking pass. It computes where variables are stored at each
--
2.26.2.645.ge9eca65c58-goog
Re: [PATCH v2 2/2] RISC-V: Handle implied extension for -march parser.
On Sun, Apr 12, 2020 at 7:54 PM Kito Cheng wrote: > On Sat, Apr 11, 2020 at 1:48 AM Jim Wilson wrote: > > Do we really need this now? It is a new feature not a bug fix, so it > > might be better to wait until we reach stage1. We have limited time > > to test this before the gcc-10 release. > > Yeah, agree, there is no urgency to merge this in gcc-10, so let it > delay committing those two patches until stage 1. The tree is open for development work again. You can commit this now. Jim
Re: [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass
On Mon, Apr 27, 2020 at 10:08 AM Craig Blackmore wrote: > Thanks for the review. I have updated the following patch with those changes. This looks good, and the tree is open for development work again, so I committed both parts 1 and 2 and pushed it. One weird thing is that while the patch program accepted the patch fine, git am would not, and kept giving me an error that didn't make any sense, pointing at a line that didn't have any visible problem. So I had to commit it by hand and then use git commit --amend to fix the authorship before pushing it. The end result looks OK to me though. Jim
[PR 95013] EOF location is at end of file
My recent C++ parser change to pay attention to EOF location uncovered a
separate bug. The preprocesor's EOF logic would set the EOF location to
be the beginning of the last line of text in the file -- not the 'line'
after that, which contains no characters. Mostly. This fixes things so
that when we attempt to read the last line of the main file, we don't
pop the buffer until the tokenizer has a chance to create an EOF token
with the correct location information. It is then responsible for
popping the buffer. As it happens, raw string literal tokenizing
contained a bug -- it would increment the line number prematurely,
because it cached buffer->cur in a local variable, but checked
buffer->cur before updating it to figure out if it was at end of file.
We fix up that too.
The EOF token intentionally doesn't have a column number -- it's not a
position on a line, it's a non-existant line.
The testsuite churn is just correcting the EOF location diagnostics.
This time I've made sure to check all testsuites, sorry obj-c++ folks.
pushed to master.
nathan
--
Nathan Sidwell
2020-05-12 Nathan Sidwell
libcpp/
EOF location is at end of file
PR preprocessor/95013
* lex.c (lex_raw_string): Process line notes before incrementing.
Correct incrementing condition. Adjust for new
_cpp_get_fresh_line EOF behaviour.
(_cpp_get_fresh_line): Do not pop buffer at EOF, increment line
instead.
(_cpp_lex_direct): Adjust for new _cpp_get_fresh_line behaviour.
(cpp_directive_only_process): Assert we got a fresh line.
* traditional.c (_cpp_read_logical_line_trad): Adjust for new
_cpp_get_fresh_line behaviour.
gcc/testsuite/
* c-c++-common/goacc/pr79428-1.c: Adjust EOF diagnostic location.
* c-c++-common/gomp/pr79428-2.c: Likewise.
* g++.dg/cpp0x/decltype63.C: Likewise.
* g++.dg/cpp0x/gen-attrs-64.C: Likewise.
* g++.dg/cpp0x/pr68726.C: Likewise.
* g++.dg/cpp0x/pr78341.C: Likewise.
* g++.dg/cpp1y/pr65202.C: Likewise.
* g++.dg/cpp1y/pr65340.C: Likewise.
* g++.dg/cpp1y/pr68578.C: Likewise.
* g++.dg/cpp1z/class-deduction44.C: Likewise.
* g++.dg/diagnostic/unclosed-extern-c.C: Likewise.
* g++.dg/diagnostic/unclosed-function.C: Likewise.
* g++.dg/diagnostic/unclosed-namespace.C: Likewise.
* g++.dg/diagnostic/unclosed-struct.C: Likewise.
* g++.dg/ext/pr84598.C: Likewise.
* g++.dg/other/switch4.C: Likewise.
* g++.dg/parse/attr4.C: Likewise.
* g++.dg/parse/cond4.C: Likewise.
* g++.dg/parse/crash10.C: Likewise.
* g++.dg/parse/crash18.C: Likewise.
* g++.dg/parse/crash27.C: Likewise.
* g++.dg/parse/crash34.C: Likewise.
* g++.dg/parse/crash35.C: Likewise.
* g++.dg/parse/crash52.C: Likewise.
* g++.dg/parse/crash59.C: Likewise.
* g++.dg/parse/crash61.C: Likewise.
* g++.dg/parse/crash67.C: Likewise.
* g++.dg/parse/error14.C: Likewise.
* g++.dg/parse/error56.C: Likewise.
* g++.dg/parse/invalid1.C: Likewise.
* g++.dg/parse/parameter-declaration-1.C: Likewise.
* g++.dg/parse/parser-pr28152-2.C: Likewise.
* g++.dg/parse/parser-pr28152.C: Likewise.
* g++.dg/parse/pr68722.C: Likewise.
* g++.dg/pr46852.C: Likewise.
* g++.dg/pr46868.C: Likewise.
* g++.dg/template/crash115.C: Likewise.
* g++.dg/template/crash43.C: Likewise.
* g++.dg/template/crash90.C: Likewise.
* g++.dg/template/error-recovery1.C: Likewise.
* g++.dg/template/error57.C: Likewise.
* g++.old-deja/g++.other/crash31.C: Likewise.
* gcc.dg/empty-source-2.c: Likewise.
* gcc.dg/empty-source-3.c: Likewise.
* gcc.dg/noncompile/pr30552-3.c: Likewise.
* gcc.dg/noncompile/pr35447-1.c: Likewise.
* gcc.dg/pr20245-1.c: Likewise.
* gcc.dg/pr28419.c: Likewise.
* gcc.dg/rtl/truncated-rtl-file.c: Likewise.
* gcc.dg/unclosed-init.c: Likewise.
* obj-c++.dg/property/property-neg-6.mm: Likewise.
* obj-c++.dg/syntax-error-10.mm: Likewise.
* obj-c++.dg/syntax-error-8.mm: Likewise.
* obj-c++.dg/syntax-error-9.mm: Likewise.
diff --git i/libcpp/lex.c w/libcpp/lex.c
index 3bcf073710e..043852d14e2 100644
--- i/libcpp/lex.c
+++ w/libcpp/lex.c
@@ -1897,12 +1897,13 @@ lex_raw_string (cpp_reader *pfile, cpp_token *token, const uchar *base,
BUF_APPEND (base, cur - base);
- if (pfile->buffer->cur < pfile->buffer->rlimit)
+ pfile->buffer->cur = cur-1;
+ _cpp_process_line_notes (pfile, false);
+
+ if (pfile->buffer->next_line < pfile->buffer->rlimit)
CPP_INCREMENT_LINE (pfile, 0);
pfile->buffer->need_line = true;
- pfile->buffer->cur = cur-1;
- _cpp_process_line_notes (pfile, false);
if (!_cpp_get_fresh_line (pfile))
{
location_t src_loc = token->src_loc;
@@ -1914,6 +1915,8 @@ lex_raw_string (cpp_reader *pfile, cpp_token *token, const uchar *base,
_cpp_release_buff (pfile, first_buff);
cpp_error_with_line (pfile, CPP_DL_ERROR, src_loc, 0,
"unterminated raw string");
+ /* Now pop the buffer that _cpp_get_fresh_line did not. */
+ _cpp_pop_buffer (pfile);
return;
}
@@ -2651,8 +2654,6 @@ _cpp_lex_token (cpp_reader *pfile)
bool
[Ada] Suppress warning for Interfaces.C with -fdump-ada-spec
The C/C++ bindings generated by means of -fdump-ada-spec always contain with
and use clauses for Interfaces.C, but they can be unused in some cases so make
sure to avoid warning about that.
Tested on x86-64/Linux, applied on the mainline.
2020-05-12 Eric Botcazou
c-family/
* c-ada-spec.c (dump_ads): Output pragma Warnings ("U"); on entry.
--
Eric Botcazoudiff --git a/gcc/c-family/c-ada-spec.c b/gcc/c-family/c-ada-spec.c
index 6d9192f2a26..c75b173eec3 100644
--- a/gcc/c-family/c-ada-spec.c
+++ b/gcc/c-family/c-ada-spec.c
@@ -3412,9 +3412,12 @@ dump_ads (const char *source_file,
cpp_check = check;
dump_ada_nodes (, source_file);
- /* We require Ada 2012 syntax, so generate corresponding pragma.
- Also, disable style checks since this file is auto-generated. */
- fprintf (f, "pragma Ada_2012;\npragma Style_Checks (Off);\n\n");
+ /* We require Ada 2012 syntax, so generate corresponding pragma. */
+ fputs ("pragma Ada_2012;\n", f);
+
+ /* Disable style checks and warnings on unused entities since this file
+ is auto-generated and always has a with clause for Interfaces.C. */
+ fputs ("pragma Style_Checks (Off);\npragma Warnings (\"U\");\n\n", f);
/* Dump withs. */
dump_ada_withs (f);
[Ada] Be prepared for more aggregates in gigi
This makes sure that gigi is prepared to handle more aggregates in the special memset code path. Tested on x86-64/Linux, applied on the mainline. 2020-05-12 Eric Botcazou * sem_aggr.ads (Is_Single_Aggregate): New function. * sem_aggr.adb (Is_Others_Aggregate): Use local variable. (Is_Single_Aggregate): New function to recognize an aggregate with a single association containing a single choice. * fe.h (Is_Others_Aggregate): Delete. (Is_Single_Aggregate): New declaration. * gcc-interface/trans.c (gnat_to_gnu) : Call Is_Single_Aggregate instead of Is_Others_Aggregate. -- Eric Botcazoudiff --git a/gcc/ada/fe.h b/gcc/ada/fe.h index 6b3f300301c..99613282213 100644 --- a/gcc/ada/fe.h +++ b/gcc/ada/fe.h @@ -253,9 +253,9 @@ extern Boolean No_Exception_Handlers_Set (void); /* sem_aggr: */ -#define Is_Others_Aggregate sem_aggr__is_others_aggregate +#define Is_Single_Aggregate sem_aggr__is_single_aggregate -extern Boolean Is_Others_Aggregate (Node_Id); +extern Boolean Is_Single_Aggregate (Node_Id); /* sem_aux: */ diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index cddeae3081a..b7a4cadb7e6 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -7887,7 +7887,7 @@ gnat_to_gnu (Node_Id gnat_node) const bool use_memset_p = regular_array_type_p && Nkind (gnat_inner) == N_Aggregate - && Is_Others_Aggregate (gnat_inner); + && Is_Single_Aggregate (gnat_inner); /* If we use memset, we need to find the innermost expression. */ if (use_memset_p) @@ -7897,7 +7897,7 @@ gnat_to_gnu (Node_Id gnat_node) gnat_temp = Expression (First (Component_Associations (gnat_temp))); } while (Nkind (gnat_temp) == N_Aggregate - && Is_Others_Aggregate (gnat_temp)); + && Is_Single_Aggregate (gnat_temp)); gnu_rhs = gnat_to_gnu (gnat_temp); } else diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb index e41fcdb6cc0..5a26cf9c7fd 100644 --- a/gcc/ada/sem_aggr.adb +++ b/gcc/ada/sem_aggr.adb @@ -832,13 +832,26 @@ package body Sem_Aggr is - function Is_Others_Aggregate (Aggr : Node_Id) return Boolean is + Assoc : constant List_Id := Component_Associations (Aggr); + begin return No (Expressions (Aggr)) -and then - Nkind (First (Choice_List (First (Component_Associations (Aggr) = -N_Others_Choice; +and then Nkind (First (Choice_List (First (Assoc = N_Others_Choice; end Is_Others_Aggregate; + - + -- Is_Single_Aggregate -- + - + + function Is_Single_Aggregate (Aggr : Node_Id) return Boolean is + Assoc : constant List_Id := Component_Associations (Aggr); + + begin + return No (Expressions (Aggr)) +and then No (Next (First (Assoc))) +and then No (Next (First (Choice_List (First (Assoc); + end Is_Single_Aggregate; + -- Is_Top_Level_Aggregate -- diff --git a/gcc/ada/sem_aggr.ads b/gcc/ada/sem_aggr.ads index 1d4f3489d78..13519a25742 100644 --- a/gcc/ada/sem_aggr.ads +++ b/gcc/ada/sem_aggr.ads @@ -37,6 +37,9 @@ package Sem_Aggr is function Is_Others_Aggregate (Aggr : Node_Id) return Boolean; -- Returns True is aggregate Aggr consists of a single OTHERS choice + function Is_Single_Aggregate (Aggr : Node_Id) return Boolean; + -- Returns True is aggregate Aggr consists of a single choice + -- WARNING: There is a matching C declaration of this subprogram in fe.h end Sem_Aggr;
Re: [PATCH] c++: Function found via ADL when it should not [PR95074]
On 5/12/20 4:18 PM, Marek Polacek wrote: I noticed that we don't implement [basic.lookup.argdep]/3: quite correctly; it says "If X (the lookup set produced by unqualified lookup) contains -- a block-scope function declaration that is not a using-declaration [...] then Y (the lookup set produced by ADL) is empty." but we were still performing ADL in fn1 in the attached test. The problem was that we were only looking at the first function in the overload set which in this case happened to be a using-declaration, and those don't suppress ADL. We have to look through the whole set to find out if unqualified lookup found a block-scope function declaration, or a member function declaration. Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? PR c++/95074 * parser.c (cp_parser_postfix_expression) : When looking for a block-scope function declaration, look through the whole set, not just the first function in the overload set. ok, thanks! -- Nathan Sidwell
[PATCH] c++: Function found via ADL when it should not [PR95074]
I noticed that we don't implement [basic.lookup.argdep]/3: quite correctly;
it says "If X (the lookup set produced by unqualified lookup) contains
-- a block-scope function declaration that is not a using-declaration
[...]
then Y (the lookup set produced by ADL) is empty."
but we were still performing ADL in fn1 in the attached test. The
problem was that we were only looking at the first function in the
overload set which in this case happened to be a using-declaration, and
those don't suppress ADL. We have to look through the whole set to find
out if unqualified lookup found a block-scope function declaration, or
a member function declaration.
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
PR c++/95074
* parser.c (cp_parser_postfix_expression) : When
looking for a block-scope function declaration, look through the whole
set, not just the first function in the overload set.
* g++.dg/lookup/koenig15.C: New test.
---
gcc/cp/parser.c| 26 +--
gcc/testsuite/g++.dg/lookup/koenig15.C | 45 ++
2 files changed, 61 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/lookup/koenig15.C
diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 10627cb1c92..f1ddef220fe 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -7385,19 +7385,25 @@ cp_parser_postfix_expression (cp_parser *parser, bool
address_p, bool cast_p,
else if (!args->is_empty ()
&& is_overloaded_fn (postfix_expression))
{
- /* We only need to look at the first function,
- because all the fns share the attribute we're
- concerned with (all member fns or all local
- fns). */
- tree fn = get_first_fn (postfix_expression);
- fn = STRIP_TEMPLATE (fn);
-
/* Do not do argument dependent lookup if regular
lookup finds a member function or a block-scope
function declaration. [basic.lookup.argdep]/3 */
- if (!((TREE_CODE (fn) == USING_DECL && DECL_DEPENDENT_P
(fn))
- || DECL_FUNCTION_MEMBER_P (fn)
- || DECL_LOCAL_FUNCTION_P (fn)))
+ bool do_adl_p = true;
+ tree fns = get_fns (postfix_expression);
+ for (lkp_iterator iter (fns); iter; ++iter)
+ {
+ tree fn = STRIP_TEMPLATE (*iter);
+ if ((TREE_CODE (fn) == USING_DECL
+&& DECL_DEPENDENT_P (fn))
+ || DECL_FUNCTION_MEMBER_P (fn)
+ || DECL_LOCAL_FUNCTION_P (fn))
+ {
+ do_adl_p = false;
+ break;
+ }
+ }
+
+ if (do_adl_p)
{
koenig_p = true;
if (!any_type_dependent_arguments_p (args))
diff --git a/gcc/testsuite/g++.dg/lookup/koenig15.C
b/gcc/testsuite/g++.dg/lookup/koenig15.C
new file mode 100644
index 000..f317c010dde
--- /dev/null
+++ b/gcc/testsuite/g++.dg/lookup/koenig15.C
@@ -0,0 +1,45 @@
+// PR c++/95074 - Function found via ADL when it should not.
+// { dg-do compile }
+
+namespace N {
+ struct S { };
+ void f(S);
+}
+
+namespace M {
+ void f(int);
+}
+
+void
+fn0 ()
+{
+ N::S s;
+ using M::f;
+ f (s);
+}
+
+void
+fn1 ()
+{
+ N::S s;
+ extern void f(char);
+ using M::f;
+ f (s); // { dg-error "no matching function" }
+}
+
+void
+fn2 ()
+{
+ N::S s;
+ using M::f;
+ extern void f(char);
+ f (s); // { dg-error "no matching function" }
+}
+
+void
+fn3 ()
+{
+ N::S s;
+ extern void (*f)(char);
+ f (s); // { dg-error "cannot convert" }
+}
base-commit: f0de5d83eecd4902e4a0447bfa4863014b6b2eaf
--
Marek Polacek • Red Hat, Inc. • 300 A St, Boston, MA
[PATCH] x86: Properly count cost of XMM register push
Update STV pass to properly count cost of XMM register push. In 32-bit
mode, to convert XMM register push in DImode, we do an XMM store in
DImode, followed by 2 memory pushes in SImode, instead of 2 integer
register pushes in SImode. To convert XM register push in SImode, we
do an XMM register to integer register move in SImode, followed an
integer register push in SImode, instead of an integer register push in
SImode. In 64-bit mode, we do an XMM register to integer register move
in SImode or DImode, followed an integer register push in SImode or
DImode, instead of an integer register push SImode or DImode.
Tested on Linux/x86 and Linux/x86-64.
OK for master?
Thanks.
H.J.
--
gcc/
PR target/95021
* config/i386/i386-features.c
(general_scalar_chain::general_scalar_chain): Initialize
n_sse_push.
(general_scalar_chain::mark_dual_mode_def): Add a df_ref
argument for reference. Increment n_sse_push for XMM register
push.
(timode_scalar_chain::mark_dual_mode_def): Add a dummy df_ref
argument.
(scalar_chain::analyze_register_chain): Pass chain->ref
to mark_dual_mode_def.
(general_scalar_chain::compute_convert_gain): Count cost of
XMM register push.
* config/i386/i386-features.h (scalar_chain::mark_dual_mode_def):
Add a df_ref argument.
(general_scalar_chain): Add n_sse_push.
(general_scalar_chain::mark_dual_mode_def): Add a df_ref
argument.
(timode_scalar_chain::mark_dual_mode_def): Add a df_ref
argument.
gcc/testsuite/
PR target/95021
* gcc.target/i386/pr95021-1.c: New test.
* gcc.target/i386/pr95021-2.c: Likewise.
---
gcc/config/i386/i386-features.c | 33 ---
gcc/config/i386/i386-features.h | 7 ++---
gcc/testsuite/gcc.target/i386/pr95021-1.c | 25 +
gcc/testsuite/gcc.target/i386/pr95021-2.c | 25 +
4 files changed, 83 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr95021-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr95021-2.c
diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c
index 78fb373db6e..c85ab41350c 100644
--- a/gcc/config/i386/i386-features.c
+++ b/gcc/config/i386/i386-features.c
@@ -326,6 +326,7 @@ general_scalar_chain::general_scalar_chain (enum
machine_mode smode_,
insns_conv = BITMAP_ALLOC (NULL);
n_sse_to_integer = 0;
n_integer_to_sse = 0;
+ n_sse_push = 0;
}
general_scalar_chain::~general_scalar_chain ()
@@ -337,7 +338,7 @@ general_scalar_chain::~general_scalar_chain ()
conversion. */
void
-general_scalar_chain::mark_dual_mode_def (df_ref def)
+general_scalar_chain::mark_dual_mode_def (df_ref def, df_ref ref)
{
gcc_assert (DF_REF_REG_DEF_P (def));
@@ -356,6 +357,12 @@ general_scalar_chain::mark_dual_mode_def (df_ref def)
if (!reg_new)
return;
n_sse_to_integer++;
+ rtx_insn *insn = DF_REF_INSN (ref);
+ rtx set = single_set (insn);
+ /* Count XMM register push. */
+ if (set
+ && push_operand (SET_DEST (set), GET_MODE (SET_DEST (set
+ n_sse_push++;
}
if (dump_file)
@@ -367,7 +374,7 @@ general_scalar_chain::mark_dual_mode_def (df_ref def)
/* For TImode conversion, it is unused. */
void
-timode_scalar_chain::mark_dual_mode_def (df_ref)
+timode_scalar_chain::mark_dual_mode_def (df_ref, df_ref)
{
gcc_unreachable ();
}
@@ -408,14 +415,14 @@ scalar_chain::analyze_register_chain (bitmap candidates,
df_ref ref)
if (dump_file)
fprintf (dump_file, " r%d def in insn %d isn't convertible\n",
DF_REF_REGNO (chain->ref), uid);
- mark_dual_mode_def (chain->ref);
+ mark_dual_mode_def (chain->ref, chain->ref);
}
else
{
if (dump_file)
fprintf (dump_file, " r%d use in insn %d isn't convertible\n",
DF_REF_REGNO (chain->ref), uid);
- mark_dual_mode_def (ref);
+ mark_dual_mode_def (ref, chain->ref);
}
}
}
@@ -627,6 +634,24 @@ general_scalar_chain::compute_convert_gain ()
are at the moment. */
cost += n_integer_to_sse * ix86_cost->sse_to_integer;
+ /* In 32-bit mode, to convert XMM register push in DImode, we do
+ an XMM store in DImode, followed by 2 memory pushes in SImode,
+ instead of 2 integer register pushes in SImode. To convert XM
+ register push in SImode, we do an XMM register to integer register
+ move in SImode, followed an integer register push in SImode,
+ instead of an integer register push in SImode. In 64-bit mode,
+ we do an XMM register to integer register move in SImode or DImode,
+ followed an integer register push in SImode or DImode, instead of
+ an integer register push SImode or DImode. */
+ if (n_sse_push)
+{
+ if (TARGET_64BIT || m == 1)
+
testsuite: Fix up gcc.dg/asan/pr95051.c testcase [PR95051]
Hi!
On Tue, May 12, 2020 at 12:06:25PM -0700, H.J. Lu wrote:
> Excess errors:
> cc1: error: '-fsanitize=address' is incompatible with
> '-fsanitize=kernel-address'
asan.exp adds -fsanitize=address which is incompatible with
-fsanitize=kernel-address,
so we need to disable it first.
Tested on x86_64-linux -m32/-m64, committed to trunk as obvious.
2020-05-12 Jakub Jelinek
PR sanitizer/95051
* gcc.dg/asan/pr95051.c: Add -fno-sanitize=all to dg-options.
--- gcc/testsuite/gcc.dg/asan/pr95051.c.jj 2020-05-12 11:25:46.209148953
+0200
+++ gcc/testsuite/gcc.dg/asan/pr95051.c 2020-05-12 21:12:28.170118274 +0200
@@ -1,6 +1,6 @@
/* PR sanitizer/95051 */
/* { dg-do compile } */
-/* { dg-options "-fsanitize=kernel-address --param=asan-stack=1 -O2" } */
+/* { dg-options "-fno-sanitize=all -fsanitize=kernel-address
--param=asan-stack=1 -O2" } */
struct a {
struct {
Jakub
[committed] wwwdocs: Update link to IBM Journal of Research and Development.
I really don't get it why so many corporate webmasters do not put redirects in place at least for a while. Luckily we've got Google. Pushed. Gerald --- htdocs/readings.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/htdocs/readings.html b/htdocs/readings.html index 086baaa1..09420335 100644 --- a/htdocs/readings.html +++ b/htdocs/readings.html @@ -610,7 +610,7 @@ names. https://en.wikipedia.org/wiki/IEEE_754r;>IEEE 754r, an ongoing revision to the IEEE 754 floating point standard. - http://researchweb.watson.ibm.com/journal/;>IBM Journal of Research and Development + https://www.research.ibm.com/journal/;>IBM Journal of Research and Development http://refspecs.linux-foundation.org/elf/elfspec_ppc.pdf;>System V PowerPC ABI -- 2.26.2
Re: [PATCH] ASAN: do not rewrite param for DECL_NOT_GIMPLE_REG_P.
On Tue, May 12, 2020 at 11:57 AM H.J. Lu wrote: > > On Tue, May 12, 2020 at 1:12 AM Richard Biener via Gcc-patches > wrote: > > > > On Tue, May 12, 2020 at 9:04 AM Martin Liška wrote: > > > > > > On 5/11/20 2:44 PM, Richard Biener wrote: > > > > Hmm, I think the fix is to clear DECL_NOT_GIMPLE_REG_P instead > > > > where the code clears TREE_ADDRESSABLE of 'arg' > > > > > > Ah, you are right. There's a patch that I've just tested. > > > > > > Patch can bootstrap on x86_64-linux-gnu and survives regression tests. > > > > > > Ready to be installed? > > > > OK. > > > > I got > > FAIL: gcc.dg/asan/pr95051.c -O0 (test for excess errors) > FAIL: gcc.dg/asan/pr95051.c -O1 (test for excess errors) > FAIL: gcc.dg/asan/pr95051.c -O2 -flto -fno-use-linker-plugin > -flto-partition=none (test for excess errors) > FAIL: gcc.dg/asan/pr95051.c -O2 -flto -fuse-linker-plugin > -fno-fat-lto-objects (test for excess errors) > FAIL: gcc.dg/asan/pr95051.c -O2 (test for excess errors) > FAIL: gcc.dg/asan/pr95051.c -O3 -g (test for excess errors) > FAIL: gcc.dg/asan/pr95051.c -Os (test for excess errors) > > on Linux/x86. > Excess errors: cc1: error: '-fsanitize=address' is incompatible with '-fsanitize=kernel-address' -- H.J.
Re: [PATCH] ASAN: do not rewrite param for DECL_NOT_GIMPLE_REG_P.
On Tue, May 12, 2020 at 1:12 AM Richard Biener via Gcc-patches wrote: > > On Tue, May 12, 2020 at 9:04 AM Martin Liška wrote: > > > > On 5/11/20 2:44 PM, Richard Biener wrote: > > > Hmm, I think the fix is to clear DECL_NOT_GIMPLE_REG_P instead > > > where the code clears TREE_ADDRESSABLE of 'arg' > > > > Ah, you are right. There's a patch that I've just tested. > > > > Patch can bootstrap on x86_64-linux-gnu and survives regression tests. > > > > Ready to be installed? > > OK. > I got FAIL: gcc.dg/asan/pr95051.c -O0 (test for excess errors) FAIL: gcc.dg/asan/pr95051.c -O1 (test for excess errors) FAIL: gcc.dg/asan/pr95051.c -O2 -flto -fno-use-linker-plugin -flto-partition=none (test for excess errors) FAIL: gcc.dg/asan/pr95051.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects (test for excess errors) FAIL: gcc.dg/asan/pr95051.c -O2 (test for excess errors) FAIL: gcc.dg/asan/pr95051.c -O3 -g (test for excess errors) FAIL: gcc.dg/asan/pr95051.c -Os (test for excess errors) on Linux/x86. -- H.J.
Re: [PATCH] rs6000: Add vec_extracth and vec_extractl
On 5/12/20 1:21 PM, Segher Boessenkool wrote:
Hi!
On Mon, May 11, 2020 at 09:56:14PM -0500, Bill Schmidt wrote:
On 5/11/20 9:48 AM, David Edelsohn wrote:
On Sun, May 10, 2020 at 9:14 AM Bill Schmidt
wrote:
* config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
(UNSPEC_EXTRACTR): Likewise.
(VEXTRACT_LR): New int iterator.
Well now the previous VSTRIR/VSTRIL patch is inconsistent. If we're
going to use an iterator for "LR", that's fine, but it needs to be
used consistently for similar situations. The approach for the two,
similar instructions and issues need to match.
I see your point. I don't really like the way this was done very much,
since the attributes are tied to the unspecs for extract-{low,high}.
Simple attribute names like LR, lr, rl shouldn't be scoped so narrowly.
Yeah... The point was to make the resulting code readable. xx is
readable, but xx is not.
I don't like any of the alternatives very well, either. I could either
(1) change the names of the int iterators in this patch to incorporate
part of the word "extract", and create similar iterators for the
vstril/vstrir patterns; or (2) remove the iterators from this patch and
just create two expansions and two insns instead of one of each. I have
a slight preference for (2) since the longer iterator names will make
things ugly.
Do you or Segher have a preference?
Two patterns is the best idea I think.
And all of this will be less code if you can move the decision making
part to the builtin code?
OK, thanks! The vector string isolation patch went upstream already
after David's first review, but I will go back and rewrite that code in
a subsequent patch.
And I will work on fixing this one and ask for re-review when it's ready.
Thanks to both of you!
Bill
Segher
Re: [PATCH v2] Fold (add -1; zero_ext; add +1) operations to zero_ext when not overflow (PR37451, part of PR61837)
luoxhu writes:
> + /* Fold (add -1; zero_ext; add +1) operations to zero_ext. i.e:
> +
> + 73: r145:SI=r123:DI#0-0x1
> + 74: r144:DI=zero_extend (r145:SI)
> + 75: r143:DI=r144:DI+0x1
> + ...
> + 31: r135:CC=cmp (r123:DI,0)
> + 72: {pc={(r143:DI!=0x1)?L70:pc};r143:DI=r143:DI-0x1;clobber
> + scratch;clobber scratch;}
Minor, but it might be worth stubbing out the clobbers, since they're
not really necessary to understand the comment:
72: {pc={(r143:DI!=0x1)?L70:pc};r143:DI=r143:DI-0x1;...}
> +
> + r123:DI#0-0x1 is param count derived from loop->niter_expr equal to the
> + loop iterations, if loop iterations expression doesn't overflow, then
> + (zero_extend (r123:DI#0-1))+1 could be simplified to zero_extend only.
> + */
> + bool simplify_zext = false;
I think it'd be easier to follow if this was split out into
a subroutine, rather than having the simplify_zext variable.
> + rtx extop0 = XEXP (count, 0);
> + if (GET_CODE (count) == ZERO_EXTEND && GET_CODE (extop0) == PLUS)
This isn't valid: we can only do XEXP (count, 0) *after* checking
for a ZERO_EXTEND. (It'd be good to test the patch with
--enable-checking=yes,extra,rtl , which hopefully would have
caught this.)
> + {
> + rtx addop0 = XEXP (extop0, 0);
> + rtx addop1 = XEXP (extop0, 1);
> +
> + int nonoverflow = 0;
> + unsigned int_mode
> + = GET_MODE_PRECISION (as_a GET_MODE (addop0));
Heh. I wondered at first how on earth this compiled. It looked like
there was a missing "(...)" around the GET_MODE. But of course,
GET_MODE adds its own parentheses, so it all works out. :-)
Please add the "(...)" anyway though. We shouldn't rely on that.
"int_mode" seems a bit of a confusing name, since it's actually a precision
in bits rather than a mode.
> + unsigned HOST_WIDE_INT int_mode_max
> + = (HOST_WIDE_INT_1U << (int_mode - 1) << 1) - 1;
> + if (get_max_loop_iterations (loop, )
> + && wi::ltu_p (iterations, int_mode_max))
You could use GET_MODE_MASK instead of int_mode_max here.
For extra safety, it would be good to add a HWI_COMPUTABLE_P test,
to make sure that using HWIs is valid.
> + nonoverflow = 1;
> +
> + if (nonoverflow
Having the nonoverflow variable doesn't seem necessary. We could
just fuse the two "if" conditions together.
> + && CONST_SCALAR_INT_P (addop1)
> + && GET_MODE_PRECISION (mode) == int_mode * 2
This GET_MODE_PRECISION condition also shouldn't be necessary.
If we can prove that the subtraction doesn't wrap, we can extend
to any wider mode, not just to double the width.
> + && addop1 == GEN_INT (-1))
This can just be:
addop1 == constm1_rtx
There's then no need for the CONST_SCALAR_INT_P check.
Thanks,
Richard
Re: [PATCH] rs6000: Add vec_extracth and vec_extractl
Hi!
On Mon, May 11, 2020 at 09:56:14PM -0500, Bill Schmidt wrote:
> On 5/11/20 9:48 AM, David Edelsohn wrote:
> >On Sun, May 10, 2020 at 9:14 AM Bill Schmidt
> >wrote:
> >> * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
> >> (UNSPEC_EXTRACTR): Likewise.
> >> (VEXTRACT_LR): New int iterator.
> >Well now the previous VSTRIR/VSTRIL patch is inconsistent. If we're
> >going to use an iterator for "LR", that's fine, but it needs to be
> >used consistently for similar situations. The approach for the two,
> >similar instructions and issues need to match.
>
> I see your point. I don't really like the way this was done very much,
> since the attributes are tied to the unspecs for extract-{low,high}.
> Simple attribute names like LR, lr, rl shouldn't be scoped so narrowly.
Yeah... The point was to make the resulting code readable. xx is
readable, but xx is not.
> I don't like any of the alternatives very well, either. I could either
> (1) change the names of the int iterators in this patch to incorporate
> part of the word "extract", and create similar iterators for the
> vstril/vstrir patterns; or (2) remove the iterators from this patch and
> just create two expansions and two insns instead of one of each. I have
> a slight preference for (2) since the longer iterator names will make
> things ugly.
>
> Do you or Segher have a preference?
Two patterns is the best idea I think.
And all of this will be less code if you can move the decision making
part to the builtin code?
Segher
Re: [PATCH 1/1] Make anti_adjust_stack_and_probe_stack_clash extern and use it for Z
On Fri, 2020-05-08 at 19:51 +0200, Andreas Krebbel via Gcc-patches wrote:
> When compiling with -mbackchain -fstack-clash-protection currently no
> probes are emitted. This patch adjusts the "allocate_stack" expander
> to call anti_adjust_stack_and_probe_stack_clash when needed. In order
> to do this I had to export that function from explow.c.
>
> Ok for mainline?
>
> 2020-05-08 Andreas Krebbel
>
> * explow.c (anti_adjust_stack_and_probe_stack_clash): Remove
> prototype. Remove static.
> * explow.h (anti_adjust_stack_and_probe_stack_clash): Add
> prototype.
> * config/s390/s390.md ("allocate_stack"): Call
> anti_adjust_stack_and_probe_stack_clash when stack clash
> protection is enabled.
>
> gcc/testsuite/ChangeLog:
>
> 2020-05-08 Andreas Krebbel
>
> * gcc.target/s390/stack-clash-3.c: New test.
OK. Not sure how I missed the allocate_stack pattern in the s390 backend and
the
fact that it needed stack-clash handling. THanks for taking care of it.
jeff
>
[committed] i386: Add V2SFmode copysign, xorsign and signbit expanders [PR95046]
gcc/ChangeLog:
2020-05-12 Uroš Bizjak
PR target/95046
* config/i386/mmx.md (copysignv2sf3): New expander.
(xorsignv2sf3): Ditto.
(signbitv2sf3): Ditto.
testsuite/ChangeLog:
2020-05-12 Uroš Bizjak
PR target/95046
* gcc.target/i386/pr95046-4.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index f6f302eb7ff..d159134e0fb 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -660,6 +660,47 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
+(define_expand "copysignv2sf3"
+ [(set (match_dup 4)
+ (and:V2SF
+ (not:V2SF (match_dup 3))
+ (match_operand:V2SF 1 "register_operand")))
+ (set (match_dup 5)
+ (and:V2SF (match_dup 3)
+ (match_operand:V2SF 2 "register_operand")))
+ (set (match_operand:V2SF 0 "register_operand")
+ (ior:V2SF (match_dup 4) (match_dup 5)))]
+ "TARGET_MMX_WITH_SSE"
+{
+ operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
+
+ operands[4] = gen_reg_rtx (V2SFmode);
+ operands[5] = gen_reg_rtx (V2SFmode);
+})
+
+(define_expand "xorsignv2sf3"
+ [(set (match_dup 4)
+ (and:V2SF (match_dup 3)
+ (match_operand:V2SF 2 "register_operand")))
+ (set (match_operand:V2SF 0 "register_operand")
+ (xor:V2SF (match_dup 4)
+ (match_operand:V2SF 1 "register_operand")))]
+ "TARGET_MMX_WITH_SSE"
+{
+ operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
+
+ operands[4] = gen_reg_rtx (V2SFmode);
+})
+
+(define_expand "signbitv2sf2"
+ [(set (match_operand:V2SI 0 "register_operand")
+ (lshiftrt:V2SI
+ (subreg:V2SI
+ (match_operand:V2SF 1 "register_operand") 0)
+ (match_dup 2)))]
+ "TARGET_MMX_WITH_SSE"
+ "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);")
+
;
;;
;; Parallel single-precision FMA multiply/accumulate instructions.
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-4.c
b/gcc/testsuite/gcc.target/i386/pr95046-4.c
new file mode 100644
index 000..5a85045b095
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-4.c
@@ -0,0 +1,39 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -msse2" } */
+
+
+float r[2], a[2], b[2];
+
+float copysignf (float, float);
+
+void
+test_copysign (void)
+{
+ for (int i = 0; i < 2; i++)
+r[i] = copysignf (a[i], b[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?andnps" } } */
+
+void
+test_xorsign (void)
+{
+ for (int i = 0; i < 2; i++)
+r[i] = a[i] * copysignf (1.0f, b[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?xorps" } } */
+
+int s[2];
+
+int signbitf (float);
+
+void
+test_signbitf (void)
+{
+ for (int i = 0; i < 2; i++)
+s[i] = signbitf (a[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?psrld" } } */
Re: [PATCH] Enable CET in cross compiler if possible
On Fri, 2020-05-08 at 06:11 -0700, H.J. Lu via Gcc-patches wrote: > Don't perform CET run-time check for host when cross compiling. Instead, > enable CET in cross compiler if possible so that it will run on both CET > and non-CET hosts. > > config/ > > PR bootstrap/94998 > * cet.m4 (GCC_CET_HOST_FLAGS): Enable CET in cross compiler if > possible. > > libiberty/ > > PR bootstrap/94998 > * configure: Regenerated. > > lto-plugin/ > > PR bootstrap/94998 > * configure: Regenerated. OK jeff >
[committed] i386: Add V2SFmode FMA insn patterns [PR95046]
gcc/ChangeLog:
2020-05-12 Uroš Bizjak
PR target/95046
* config/i386/mmx.md (fmav2sf4): New insn pattern.
(fmsv2sf4): Ditto.
(fnmav2sf4): Ditto.
(fnmsv2sf4): Ditto.
testsuite/ChangeLog:
2020-05-12 Uroš Bizjak
PR target/95046
* gcc.target/i386/pr95046-3.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 0ec80c06d35..f6f302eb7ff 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -660,6 +660,76 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "V4SF")])
+;
+;;
+;; Parallel single-precision FMA multiply/accumulate instructions.
+;;
+;
+
+(define_insn "fmav2sf4"
+ [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+ (fma:V2SF
+ (match_operand:V2SF 1 "register_operand" "%0,v,x")
+ (match_operand:V2SF 2 "register_operand" "v,v,x")
+ (match_operand:V2SF 3 "register_operand" "v,0,x")))]
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+ "@
+ vfmadd132ps\t{%2, %3, %0|%0, %3, %2}
+ vfmadd231ps\t{%2, %1, %0|%0, %1, %2}
+ vfmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "fma,fma,fma4")
+ (set_attr "type" "ssemuladd")
+ (set_attr "mode" "V4SF")])
+
+(define_insn "fmsv2sf4"
+ [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+ (fma:V2SF
+ (match_operand:V2SF 1 "register_operand" "%0,v,x")
+ (match_operand:V2SF 2 "register_operand" "v,v,x")
+ (neg:V2SF
+ (match_operand:V2SF 3 "register_operand" "v,0,x"]
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+ "@
+ vfmsub132ps\t{%2, %3, %0|%0, %3, %2}
+ vfmsub231ps\t{%2, %1, %0|%0, %1, %2}
+ vfmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "fma,fma,fma4")
+ (set_attr "type" "ssemuladd")
+ (set_attr "mode" "V4SF")])
+
+(define_insn "fnmav2sf4"
+ [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+ (fma:V2SF
+ (neg:V2SF
+ (match_operand:V2SF 1 "register_operand" "%0,v,x"))
+ (match_operand:V2SF 2 "register_operand" "v,v,x")
+ (match_operand:V2SF 3 "register_operand" "v,0,x")))]
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+ "@
+ vfnmadd132ps\t{%2, %3, %0|%0, %3, %2}
+ vfnmadd231ps\t{%2, %1, %0|%0, %1, %2}
+ vfnmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "fma,fma,fma4")
+ (set_attr "type" "ssemuladd")
+ (set_attr "mode" "V4SF")])
+
+(define_insn "fnmsv2sf4"
+ [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
+ (fma:V2SF
+ (neg:V2SF
+ (match_operand:V2SF 1 "register_operand" "%0,v,x"))
+ (match_operand:V2SF 2 "register_operand" "v,v,x")
+ (neg:V2SF
+ (match_operand:V2SF 3 "register_operand" "v,0,x"]
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE"
+ "@
+ vfnmsub132ps\t{%2, %3, %0|%0, %3, %2}
+ vfnmsub231ps\t{%2, %1, %0|%0, %1, %2}
+ vfnmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "isa" "fma,fma,fma4")
+ (set_attr "type" "ssemuladd")
+ (set_attr "mode" "V4SF")])
+
;
;;
;; Parallel single-precision floating point conversion operations
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-3.c
b/gcc/testsuite/gcc.target/i386/pr95046-3.c
new file mode 100644
index 000..7d15b39e5af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-3.c
@@ -0,0 +1,42 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -mfma" } */
+
+
+float r[2], a[2], b[2], c[2];
+
+void
+test_fma (void)
+{
+ for (int i = 0; i < 2; i++)
+r[i] = a[i] * b[i] + c[i];
+}
+
+/* { dg-final { scan-assembler "\tvfmadd\[123\]+ps" } } */
+
+void
+test_fms (void)
+{
+ for (int i = 0; i < 2; i++)
+r[i] = a[i] * b[i] - c[i];
+}
+
+/* { dg-final { scan-assembler "\tvfmsub\[123\]+ps" } } */
+
+void
+test_fnma (void)
+{
+ for (int i = 0; i < 2; i++)
+r[i] = -(a[i] * b[i]) + c[i];
+}
+
+/* { dg-final { scan-assembler "\tvfnmadd\[123\]+ps" } } */
+
+void
+test_fnms (void)
+{
+ for (int i = 0; i < 2; i++)
+r[i] = -(a[i] * b[i]) - c[i];
+}
+
+/* { dg-final { scan-assembler "\tvfnmsub\[123\]+ps" } } */
[committed] c++: Add abbreviated fn template test for [PR78752]
This adds an abbreviated function template version of the testcase in
PR78752, which seems to already be fixed.
gcc/testsuite/ChangeLog:
PR c++/78752
* g++.dg/cpp2a/concepts-pr78752-2.C: New test.
---
.../g++.dg/cpp2a/concepts-pr78752-2.C | 21 +++
2 files changed, 21 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-pr78752-2.C
diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-pr78752-2.C
b/gcc/testsuite/g++.dg/cpp2a/concepts-pr78752-2.C
new file mode 100644
index 000..6777054285d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/concepts-pr78752-2.C
@@ -0,0 +1,21 @@
+// { dg-do compile { target c++2a } }
+// { dg-additional-options "-fconcepts-ts" }
+
+template
+concept bool Same = __is_same(T, U);
+
+struct test {
+ void func(Same... ints) {}
+};
+
+void func(Same... ints) {}
+
+int main()
+{
+ test t;
+ t.func(1, 2, 3);
+ func(1, 2, 3);
+
+ t.func(1, 2, ""); // { dg-error "no match" }
+ func(1, 2, ""); // { dg-error "unsatisfied constraints" }
+}
--
2.26.2.561.g07d8ea56f2
Re: [PATCH] handle initialized flexible array members in __builtin_object_size [PR92815]
On Thu, 2020-04-23 at 16:05 -0600, Martin Sebor wrote: > On 4/23/20 9:42 AM, Jeff Law wrote: > > On Wed, 2020-04-22 at 15:36 -0600, Martin Sebor via Gcc-patches wrote: > > > When computing the size of an object with a flexible array member > > > the object size pass doesn't consider that the initializer of such > > > an object can result in its size being in excess of the size of > > > the enclosing type. As a result, stores into such objects by > > > string functions causes false positive warnings and can abort > > > at runtime. > > > > > > The warnings are an old regression but as more of them make use > > > of the object size results more of them are affected by the bug. > > > The abort goes back to when support for _FORTIFY_SOURCE was added. > > > > > > The same problem has already been independently fixed in GCC 10 > > > for -Warray-bounds which doesn't use the object size checking pass, > > > but the object size bug still remains. The attached patch corrects > > > it as well. > > > > > > Tested on x86_64-linux. > > Do you need to change guarding condition to use decl_init_size instead of > > DECL_SIZE_UNIT as well? > > > > else if (pt_var > > && DECL_P (pt_var) > > && tree_fits_uhwi_p (DECL_SIZE_UNIT (pt_var)) > > ^^ > > && tree_to_uhwi (DECL_SIZE_UNIT (pt_var)) < offset_limit) > > ^^ > > It doesn't see that changing it is strictly necessary. If the tests > above pass and the result doesn't satisfy the conditions because it's > either null or doesn't fit in UHWI it's handled later by returning > false. With offset_limit set to SIZE_MAX / 2, I don't think the result > can as big as that or bigger: it would imply the whole object, including > its initializer, is bigger than half the address space and GCC rejects > such objects with an error. I've added another test in the patch to > to verify this. > > I do agree it would be better to validate the final result the same > way. That makes the change a little more intrusive to avoid validating > the size multiple times, but I think it also improves the readability > of the code, so the updated patch does that. It passes testing on > x86_64-linux. > > Let me know which one of the two you prefer, or if you'd rather hold > off until stage 1. So we're in stage1, so you're good to go with the patch as-is or revamped per the discussion above. jeff >
Re: [PATCH 1/3] zlib: Add --enable-cet to configure
On Fri, 2020-05-08 at 13:10 -0700, H.J. Lu wrote: > When --enable-cet is used to configure GCC, enable Intel CET in target > zlib. > > * Makefile.am (AM_CFLAGS): New. > * configure.ac (CET_FLAGS): Add GCC_CET_FLAGS and AC_SUBST. > * Makefile.in: Regenerated. > * aclocal.m4: Likewise. > * configure.ac: Likewise. OK jeff >
Re: [libitm] eh specifications are lax
On Tue, 2020-05-05 at 16:08 -0400, Nathan Sidwell wrote: > I discovered that libitm: > (a) declares __cxa_allocate_exception and friends directly, > (b) doesn't mark them as 'throw()' > (c) doesn't mark the replacment fns _ITM_$foo as nothrow either > > We happen to get away with it because of code in the compiler that, > although it checks the parameter types, doesn't check the exception > specification. (One reason being they used to not be part of the > language's type system, but now they are.) I suspect this can lead us > to generate pessimal code later, if we've seen one of these decls > earlier. Anyway, with modules it becomes trickier[*], so I'm trying to > clean it up and not be a problem. I see Jakub fixed part of the problem > (https://gcc.gnu.org/pipermail/gcc-patches/2018-December/513302.html) > AFAICT, he did fix libitm's decls, but left the lax parm-type checking > in the compiler. > > libitm.h is not very informative about specification: >in version 1 of http://www.intel.com/some/path/here.pdf. */ > > Anyway, it was too fiddly to have libitm pick up the declarations from > libsupc++. Besides it makes them weak declarations, and then provides > definitions for non-elf systems. So this patch adds the expected 'throw()' > > While I can't be sure, I suspect the _ITM entry points are supposed to > have the same exception specification as the original entry points. So > those are also made 'throw ()'. libstdc++'s _GLIBCXX_NOTHROW didn't > seem available, so I make use of a new _ITM_NOTHROW macro, suitably defined. > > Because of the lax checking in the compiler, and old compiler with a > patched libitm.h will be ok... Until I change the compiler :) > > booted & tested on x86_64-linux, ok? > > nathan > > [*] modules make it harder to have ODR violations, that's why it finds > ODR violations in existing code. > > > 2020-05-05 Nathan Sidwell > > > > Fix throw specifiers on interface. > > * libitm/libitm.h (_ITM_NOTHROW): Define. > > (_ITM_cxa_allocate_exception, _ITM_cxa_free_exception) > > (_ITM_cxa_begin_catch): Use it. > > * eh_cpp.cc: Add throw() to __cxa_allocate_exception, > > __cxa_free_exception, __cxa_begin_catch, __cxa_tm_cleanup, > > __cxa_get_globals. > > (_ITM_cxa_allocate_exception, _ITM_cxa_free_exception) > > (_ITM_cxa_begin_catch): Likewise. > > OK jeff
Re: [PATCH 3/5] libcpp: Enable Intel CET on Intel CET enabled host for jit
On Sat, 2020-05-09 at 08:43 -0700, H.J. Lu wrote: > Since on Intel CET enabled host, dlopen in Intel CET enabled applications > fails on shared libraries which aren't Intel CET enabled, compile with > -fcf-protection on Intel CET enabled host when jit is enabled to enable > Intel CET on libgccjit. > > * Makefile.in (CET_HOST_FLAGS): New. > (COMPILER): Add $(CET_HOST_FLAGS). > * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and > AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't > enabled. > * aclocal.m4: Regenerated. > * configure: Likewise. OK jeff >
Re: [PATCH 5/5] libbacktrace: Enable Intel CET on Intel CET enabled host for jit
On Sat, 2020-05-09 at 08:43 -0700, H.J. Lu wrote: > Since on Intel CET enabled host, dlopen in Intel CET enabled applications > fails on shared libraries which aren't Intel CET enabled, compile with > -fcf-protection on Intel CET enabled host when jit is enabled to enable > Intel CET on libgccjit. > > * Makefile.am (AM_CFLAGS): Add $(CET_HOST_FLAGS). > * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and > AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't > enabled. > * Makefile.in: Regenerated. > * configure: Likewise. OK jeff >
Re: [PATCH 4/5] libdecnumber: Enable Intel CET on Intel CET enabled host for jit
On Sat, 2020-05-09 at 08:43 -0700, H.J. Lu wrote: > Since on Intel CET enabled host, dlopen in Intel CET enabled applications > fails on shared libraries which aren't Intel CET enabled, compile with > -fcf-protection on Intel CET enabled host when jit is enabled to enable > Intel CET on libgccjit. > > * Makefile.in (CET_HOST_FLAGS): New. > (COMPILER): Add $(CET_HOST_FLAGS). > * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and > AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't > enabled. > * aclocal.m4: Regenerated. > * configure: Likewise. OK jeff >
Re: [PATCH 2/5] gcc: Enable Intel CET on Intel CET enabled host for jit
On Sat, 2020-05-09 at 08:43 -0700, H.J. Lu wrote: > Since on Intel CET enabled host, dlopen in Intel CET enabled applications > fails on shared libraries which aren't Intel CET enabled, compile with > -fcf-protection on Intel CET enabled host when jit is enabled to enable > Intel CET on libgccjit. > > * Makefile.in (CET_HOST_FLAGS): New. > (COMPILER): Add $(CET_HOST_FLAGS). > * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and > AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't > enabled. > * aclocal.m4: Regenerated. > * configure: Likewise. OK jeff >
Re: [PATCH 1/5] libcc1: Enable Intel CET on Intel CET enabled host
On Sat, 2020-05-09 at 08:43 -0700, H.J. Lu wrote: > Since on Intel CET enabled host, dlopen in Intel CET enabled applications > fails on shared libraries which aren't Intel CET enabled, enable Intel > CET in libcc1 on Intel CET enabled host. > > * Makefile.am (AM_CXXFLAGS): Add $(CET_HOST_FLAGS). > * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and > AC_SUBST(CET_HOST_FLAGS). > * Makefile.in: Regenerated. > * aclocal.m4: Likewise. > * configure: Likewise. OK jeff >
[committed] i386: Add V2SFmode NEG, ABS and logic insn patterns [PR95046]
gcc/ChangeLog:
2020-05-12 Uroš Bizjak
PR target/95046
* config/i386/mmx.md (v2sf2): New insn pattern.
(*mmx_v2sf2): New insn_and_split pattern.
(*mmx_nabsv2sf2): Ditto.
(*mmx_andnotv2sf3): New insn pattern.
(*mmx_v2sf3): Ditto.
* config/i386/i386.md (absneg_op): New code attribute.
* config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
(ix86_build_signbit_mask): Ditto.
testsuite/ChangeLog:
2020-05-12 Uroš Bizjak
PR target/95046
* gcc.target/i386/pr95046-2.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d1c0e354162..17883ffd131 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -15091,6 +15091,7 @@ ix86_build_const_vector (machine_mode mode, bool vect,
rtx value)
case E_V16SFmode:
case E_V8SFmode:
case E_V4SFmode:
+case E_V2SFmode:
case E_V8DFmode:
case E_V4DFmode:
case E_V2DFmode:
@@ -15131,6 +15132,7 @@ ix86_build_signbit_mask (machine_mode mode, bool vect,
bool invert)
case E_V4SImode:
case E_V8SFmode:
case E_V4SFmode:
+case E_V2SFmode:
vec_mode = mode;
imode = SImode;
break;
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8bfc9cb0b71..722eb9b5ec8 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -954,6 +954,9 @@
;; Mapping of abs neg operators
(define_code_iterator absneg [abs neg])
+;; Mapping of abs neg operators to logic operation
+(define_code_attr absneg_op [(abs "and") (neg "xor")])
+
;; Base name for x87 insn mnemonic.
(define_code_attr absneg_mnemonic [(abs "fabs") (neg "fchs")])
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index a8f603b94f8..0ec80c06d35 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -238,6 +238,40 @@
;;
;
+(define_expand "v2sf2"
+ [(set (match_operand:V2SF 0 "register_operand")
+ (absneg:V2SF
+ (match_operand:V2SF 1 "register_operand")))]
+ "TARGET_MMX_WITH_SSE"
+ "ix86_expand_fp_absneg_operator (, V2SFmode, operands); DONE;")
+
+(define_insn_and_split "*mmx_v2sf2"
+ [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+ (absneg:V2SF
+ (match_operand:V2SF 1 "register_operand" "%0,x")))
+ (use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
+ "TARGET_MMX_WITH_SSE"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (:V2SF (match_dup 1) (match_dup 2)))]
+ ""
+ [(set_attr "isa" "noavx,avx")])
+
+(define_insn_and_split "*mmx_nabsv2sf2"
+ [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+ (neg:V2SF
+ (abs:V2SF
+ (match_operand:V2SF 1 "register_operand" "%0,x"
+ (use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
+ "TARGET_MMX_WITH_SSE"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (ior:V2SF (match_dup 1) (match_dup 2)))]
+ ""
+ [(set_attr "isa" "noavx,avx")])
+
(define_expand "mmx_addv2sf3"
[(set (match_operand:V2SF 0 "register_operand")
(plus:V2SF
@@ -591,6 +625,41 @@
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
+;
+;;
+;; Parallel single-precision floating point logical operations
+;;
+;
+
+(define_insn "*mmx_andnotv2sf3"
+ [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+ (and:V2SF
+ (not:V2SF
+ (match_operand:V2SF 1 "register_operand" "0,x"))
+ (match_operand:V2SF 2 "register_operand" "x,x")))]
+ "TARGET_MMX_WITH_SSE"
+ "@
+ andps\t{%2, %0|%0, %2}
+ vandps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V4SF")])
+
+(define_insn "*mmx_v2sf3"
+ [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+ (any_logic:V2SF
+ (match_operand:V2SF 1 "register_operand" "%0,x")
+ (match_operand:V2SF 2 "register_operand" "x,x")))]
+ "TARGET_MMX_WITH_SSE"
+ "@
+ ps\t{%2, %0|%0, %2}
+ vps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "V4SF")])
+
;
;;
;; Parallel single-precision floating point conversion operations
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-2.c
b/gcc/testsuite/gcc.target/i386/pr95046-2.c
new file mode 100644
index 000..277cc2d2e58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-2.c
@@ -0,0 +1,35 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -msse2" } */
+
+
+float r[2], a[2];
+
+float fabsf (float);
+
+void
+test_abs (void)
+{
+ for (int i = 0; i < 2; i++)
+r[i] =
[PATCH, FORTRAN] ICE in gfc_conv_array_constructor_expr PR93497
Please find attached for PR93497. This patch was posted as a comment to
the PR, I've checked it added a test case. It has the side affect of
changing the errors for three other test cases which have modified
accordingly.
The commit message is as follows:
fortran : ICE in gfc_conv_array_constructor_expr PR93497
Invalid expressions, such as those involving array constructors,
used for the length of character types will cause an ICE.
2020-05-12 Steven G. Kargl
gcc/fortran/
PR fortran/93497
* decl.c (char_len_param_value) : Check whether character
length expression is of type EXPR_OP and if so simplify it.
* resolve.c (resolve_charlen) : Reject length if it has a
rank.
2020-05-12 Mark Eggleston
gcc/testsuite/
PR fortran/93497
* gfortran.dg/pr88025.f90: Change in wording of error.
* gfortran.dg/pr93497.f90: New test.
* gfortran.dg/pr93714_1.f90: Change in wording of errors.
* gfortran.dg/pr93714_2.f90: Change in wording of errors.
Note: the dates will be updated as necessary when the patch is committed.
Tested using make check-fortran on x86_64 for branches master,
releases/gcc-8, releases/gcc-9 and releases/gcc-10.
OK to commit to master and to backport to releases/gcc-8, releases/gcc-9
and releases/gcc-10?
--
https://www.codethink.co.uk/privacy.html
>From 143b9911a9c8420c9906a41b7a96376bad1753c4 Mon Sep 17 00:00:00 2001
From: Mark Eggleston
Date: Thu, 7 May 2020 08:29:14 +0100
Subject: [PATCH] fortran : ICE in gfc_conv_array_constructor_expr PR93497
Invalid expressions, such as those involving array constructors,
used for the length of character types will cause an ICE.
2020-05-12 Steven G. Kargl
gcc/fortran/
PR fortran/93497
* decl.c (char_len_param_value) : Check whether character
length expression is of type EXPR_OP and if so simplify it.
* resolve.c (resolve_charlen) : Reject length if it has a
rank.
2020-05-12 Mark Eggleston
gcc/testsuite/
PR fortran/93497
* gfortran.dg/pr88025.f90: Change in wording of error.
* gfortran.dg/pr93497.f90: New test.
* gfortran.dg/pr93714_1.f90: Change in wording of errors.
* gfortran.dg/pr93714_2.f90: Change in wording of errors.
---
gcc/fortran/decl.c | 5 +
gcc/fortran/resolve.c | 2 +-
gcc/testsuite/gfortran.dg/pr88025.f90 | 2 +-
gcc/testsuite/gfortran.dg/pr93497.f90 | 8
gcc/testsuite/gfortran.dg/pr93714_1.f90 | 4 ++--
gcc/testsuite/gfortran.dg/pr93714_2.f90 | 4 ++--
6 files changed, 19 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/pr93497.f90
diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index d650407da41..9cc81361f43 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -1077,6 +1077,11 @@ char_len_param_value (gfc_expr **expr, bool *deferred)
if (!gfc_expr_check_typed (*expr, gfc_current_ns, false))
return MATCH_ERROR;
+ /* If gfortran gets an EXPR_OP, try to simplifiy it. This catches things
+ like CHARACTER(([1])). */
+ if ((*expr)->expr_type == EXPR_OP)
+gfc_simplify_expr (*expr, 1);
+
if ((*expr)->expr_type == EXPR_FUNCTION)
{
if ((*expr)->ts.type == BT_INTEGER
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index fd3b025a84f..ed1705f62ba 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -12356,7 +12356,7 @@ resolve_charlen (gfc_charlen *cl)
}
/* cl->length has been resolved. It should have an integer type. */
- if (cl->length->ts.type != BT_INTEGER)
+ if (cl->length->ts.type != BT_INTEGER || cl->length->rank != 0)
{
gfc_error ("Scalar INTEGER expression expected at %L",
>length->where);
diff --git a/gcc/testsuite/gfortran.dg/pr88025.f90 b/gcc/testsuite/gfortran.dg/pr88025.f90
index 96172fae76a..c51390f1434 100644
--- a/gcc/testsuite/gfortran.dg/pr88025.f90
+++ b/gcc/testsuite/gfortran.dg/pr88025.f90
@@ -2,6 +2,6 @@
! PR fortran/88025
program p
type t
- character(('')) :: c = 'c'! { dg-error "must be of INTEGER type" }
+ character(('')) :: c = 'c' ! { dg-error "Scalar INTEGER expression expected" }
end type
end
diff --git a/gcc/testsuite/gfortran.dg/pr93497.f90 b/gcc/testsuite/gfortran.dg/pr93497.f90
new file mode 100644
index 000..612b41cd8ca
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr93497.f90
@@ -0,0 +1,8 @@
+! { dg-do compile }
+
+program p
+ print *, [character(((/1/))) :: 'a','b'] ! { dg-error "Scalar INTEGER expression expected" }
+ print *, [character(([1])) :: 'a','b'] ! { dg-error "Scalar INTEGER expression expected" }
+ print *, [character(1+[1]) :: 'a','b'] ! { dg-error "Scalar INTEGER expression expected" }
+end
+
diff --git a/gcc/testsuite/gfortran.dg/pr93714_1.f90 b/gcc/testsuite/gfortran.dg/pr93714_1.f90
index 40f4a4bf89f..e55812c76de 100644
--- a/gcc/testsuite/gfortran.dg/pr93714_1.f90
+++ b/gcc/testsuite/gfortran.dg/pr93714_1.f90
@@ -7,5 +7,5 @@ program test
character, pointer :: b => a
end program
Re: [PATCH v2] Fold (add -1; zero_ext; add +1) operations to zero_ext when not overflow (PR37451, part of PR61837)
Hi!
On Tue, May 12, 2020 at 02:48:40PM +0800, luoxhu wrote:
> diff --git a/gcc/testsuite/gcc.target/powerpc/doloop-2.c
> b/gcc/testsuite/gcc.target/powerpc/doloop-2.c
> new file mode 100644
> index 000..dc8516bb0ab
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/doloop-2.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile { target powerpc*-*-* } } */
Just { dg-do compiler } please, *everything* that runs this testsuite
is powerpc*-*-*; but compile is the default as well, so you can leave
that line completely out as well, if you want.
> +/* { dg-final { scan-assembler-not "-1" } } */
This will fail the test for the string "-1" anywhere in the file. Like,
if it was called "doloop-1.c" it would fail, or "doloop-12345.c". \m
and \M can help for that last case, but you probably want to make the
regex a bit more selective ;-) (And, document what it doesn't want to
see, if it isn't really obvious?)
Segher
Re: [pushed] c++: Make references to __cxa_pure_virtual weak.
On Tue, 12 May 2020 at 10:28, Andreas Schwab wrote: > > On Mai 11 2020, Jason Merrill via Gcc-patches wrote: > > > If a program has no other dependencies on libstdc++, we shouldn't require it > > just for __cxa_pure_virtual, which is only there to give a prettier > > diagnostic before crashing the program; resolving the reference to NULL will > > also crash, just without the diagnostic. > > That doesn't work on ia64: > > pure-virtual1.o:(.data.rel.ro._ZTV1A[_ZTV1A]+0x10): undefined reference to > `__cxa_pure_virtual' > collect2: error: ld returned 1 exit status > $ nm -u pure-virtual1.o > U __cxa_pure_virtual > This doesn't work on aarch64-elf either: I'm using newlib/libgloss' -specs=aem-ve.specs, which has: *lib: cpu-init/rdimon-aem-el3.o%s --start-group %(libc) %(libgloss) --end-group Since the testcase uses -nodefaultlibs, this also removes libgloss from the link, leading to: /aarch64-none-elf/lib/rdimon-crt0.o: in function `_mainCRTStartup': /newlib/libgloss/aarch64/crt0.S:113: undefined reference to `__heap_limit' /newlib/libgloss/aarch64/crt0.S:114: undefined reference to `__heap_limit' /newlib/libgloss/aarch64/crt0.S:165: undefined reference to `initialise_monitor_handles' [...] Christophe > Andreas. > > -- > Andreas Schwab, sch...@linux-m68k.org > GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 > "And now for something completely different."
Re: [PATCH] rs6000: Vector string isolate instructions
On 5/12/20 4:54 AM, Segher Boessenkool wrote:
Hi!
Looks fine to me... Just the same generic things as before, things we
can improve later, not even limited to this series:
On Sat, May 09, 2020 at 08:16:26AM -0500, Bill Schmidt wrote:
* config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
(UNSPEC_VSTRIL): Likewise.
Names for these could perhaps be better. Or maybe not, they are short
now, there's something to say for that as well :-)
(vstrir_): New expansion.
(vstrir_code_): New insn.
Could you make this vstrir and vstrir_internal, like the
rest?
(vstrir_p_): New expansion.
(vstrir_p_code_): New insn.
But, not sure what to do with those. "Something to improve later" then
I guess, for all of it :-)
+(define_expand "vstrir_"
+ [(set (match_operand:VIshort 0 "altivec_register_operand")
+ (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
+ UNSPEC_VSTRIR))]
+ "TARGET_FUTURE"
+{
+ if (BYTES_BIG_ENDIAN)
+emit_insn (gen_vstrir_code_ (operands[0], operands[1]));
+ else
+emit_insn (gen_vstril_code_ (operands[0], operands[1]));
+ DONE;
+})
So the reason this pattern is special at all is that left and right are
swapped for LE. Maybe that could/should be done in the code for the
builtin, instead?
+;; This expands into same code as vstrir_ followed by condition logic
+;; so that a single vstribr. or vstrihr. or vstribl. or vstrihl. instruction
+;; can, for example, satisfy the needs of a vec_strir () function paired
+;; with a vec_strir_p () function if both take the same incoming arguments.
+(define_expand "vstrir_p_"
+ [(match_operand:SI 0 "gpc_reg_operand")
+ (match_operand:VIshort 1 "altivec_register_operand")]
+ "TARGET_FUTURE"
+{
+ rtx scratch = gen_reg_rtx (mode);
+ if (BYTES_BIG_ENDIAN)
+emit_insn (gen_vstrir_p_code_ (scratch, operands[1]));
+ else
+emit_insn (gen_vstril_p_code_ (scratch, operands[1]));
+ emit_insn (gen_cr6_test_for_zero (operands[0]));
+ DONE;
+})
And the code for the builtin can do this then, as well.
Not sure how easy that is to fit in with the current code, or after your
work on it. Either way, it looks fine to me :-)
Thanks, lots of good cleanups here. I've committed this patch, but will
open an internal issue to track the cleanups from this series of patches
and try to get them cleaned up later in the release. Thanks for the review!
Bill
Segher
Re: [PATCH] remove dead debug-bind resets
On Tue, 12 May 2020, Richard Biener wrote:
>
> This removes debug-bind resets aka
>
> # DEBUG b = NULL
>
> when the reset variable is otherwise unused. I've gathered statistics
> for a single TU, fold-const.ii which at -O2 -g shows
>
> 28 ssa "dead debug bind reset" 1
> 34 einline "dead debug bind reset" 340
> 54 release_ssa "dead debug bind reset" 176
> 54 release_ssa "live debug bind reset of dead var" 4
> 86 inline "dead debug bind reset" 5131
> 86 inline "live debug bind reset of dead var" 61
> 241 optimized "dead debug bind reset" 970
> 241 optimized "live debug bind reset of dead var" 287
>
> where "live debug bind reset of dead var" means the variable is unused
> but there were debug binds with a value for them and
> "dead debug bind reset" means the variable is unused and there were
> only debug bind resets (each reset of the same variable is counted
> for both counters). This shows A considerable amount of dead stmts
> removed esp. after IPA inlining.
>
> Bootstrap and regtest running on x86_64-unknown-linux-gnu.
This is what I have applied after consulting with Jakub.
Richard.
>From 6657b248e2c1978862ae81bf589c555b0465ae82 Mon Sep 17 00:00:00 2001
From: Richard Biener
Date: Tue, 14 Jan 2020 15:31:18 +0100
Subject: [PATCH] remove dead debug-bind resets
This removes debug-bind resets aka
# DEBUG b = NULL
when the reset variable is otherwise unused. I've gathered statistics
for a single TU, fold-const.ii which at -O2 -g shows
28 ssa "dead debug bind reset" 1
34 einline "dead debug bind reset" 340
54 release_ssa "dead debug bind reset" 176
54 release_ssa "live debug bind reset of dead var" 4
86 inline "dead debug bind reset" 5131
86 inline "live debug bind reset of dead var" 61
241 optimized "dead debug bind reset" 970
241 optimized "live debug bind reset of dead var" 287
where "live debug bind reset of dead var" means the variable is unused
but there were debug binds with a value for them and
"dead debug bind reset" means the variable is unused and there were
only debug bind resets (each reset of the same variable is counted
for both counters). This shows A considerable amount of dead stmts
removed esp. after IPA inlining.
2020-05-12 Richard Biener
* tree-ssa-live.c (remove_unused_locals): Remove dead debug
bind resets.
---
gcc/tree-ssa-live.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/tree-ssa-live.c b/gcc/tree-ssa-live.c
index f3975320e8c..21a9ee43e6b 100644
--- a/gcc/tree-ssa-live.c
+++ b/gcc/tree-ssa-live.c
@@ -743,6 +743,7 @@ remove_unused_locals (void)
mark_scope_block_unused (DECL_INITIAL (current_function_decl));
usedvars = BITMAP_ALLOC (NULL);
+ auto_bitmap useddebug;
/* Walk the CFG marking all referenced symbols. */
FOR_EACH_BB_FN (bb, cfun)
@@ -763,7 +764,21 @@ remove_unused_locals (void)
do it. If the block is not otherwise used, the stmt will
be cleaned up in clean_unused_block_pointer. */
if (is_gimple_debug (stmt))
- continue;
+ {
+ if (gimple_debug_bind_p (stmt))
+ {
+ tree var = gimple_debug_bind_get_var (stmt);
+ if (VAR_P (var))
+ {
+ if (!gimple_debug_bind_get_value (stmt))
+ /* Run the 2nd phase. */
+ have_local_clobbers = true;
+ else
+ bitmap_set_bit (useddebug, DECL_UID (var));
+ }
+ }
+ continue;
+ }
if (gimple_clobber_p (stmt))
{
@@ -846,6 +861,20 @@ remove_unused_locals (void)
if (b)
TREE_USED (b) = true;
}
+ else if (gimple_debug_bind_p (stmt))
+ {
+ tree var = gimple_debug_bind_get_var (stmt);
+ if (VAR_P (var)
+ && !bitmap_bit_p (useddebug, DECL_UID (var))
+ && !is_used_p (var))
+ {
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ fprintf (dump_file, "Dead debug bind reset to %u\n",
+ DECL_UID (var));
+ gsi_remove (, true);
+ continue;
+ }
+ }
gsi_next ();
}
}
--
2.25.1
PING: [PATCH] Enable CET in cross compiler if possible
On Fri, May 8, 2020 at 6:11 AM H.J. Lu wrote:
>
> Don't perform CET run-time check for host when cross compiling. Instead,
> enable CET in cross compiler if possible so that it will run on both CET
> and non-CET hosts.
>
> config/
>
> PR bootstrap/94998
> * cet.m4 (GCC_CET_HOST_FLAGS): Enable CET in cross compiler if
> possible.
>
> libiberty/
>
> PR bootstrap/94998
> * configure: Regenerated.
>
> lto-plugin/
>
> PR bootstrap/94998
> * configure: Regenerated.
> ---
> config/cet.m4| 18 --
> libiberty/configure | 12 +---
> lto-plugin/configure | 16 +++-
> 3 files changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/config/cet.m4 b/config/cet.m4
> index ea616b728a9..d9608699cd5 100644
> --- a/config/cet.m4
> +++ b/config/cet.m4
> @@ -111,7 +111,8 @@ if test x$may_have_cet = xyes; then
> fi
>
> if test x$may_have_cet = xyes; then
> - AC_TRY_RUN([
> + if test x$cross_compiling = xno; then
> +AC_TRY_RUN([
> static void
> foo (void)
> {
> @@ -137,12 +138,17 @@ main ()
>bar ();
>return 0;
> }
> - ],
> - [have_cet=no],
> - [have_cet=yes])
> - if test x$enable_cet = xno -a x$have_cet = xyes; then
> -AC_MSG_ERROR([Intel CET must be enabled on Intel CET enabled host])
> +],
> +[have_cet=no],
> +[have_cet=yes])
> +if test x$enable_cet = xno -a x$have_cet = xyes; then
> + AC_MSG_ERROR([Intel CET must be enabled on Intel CET enabled host])
> +fi
>fi
> +else
> + # Enable CET in cross compiler if possible so that it will run on both
> + # CET and non-CET hosts.
> + have_cet=yes
> fi
> if test x$enable_cet = xyes; then
>$1="-fcf-protection"
> diff --git a/libiberty/configure b/libiberty/configure
> index bb76cf1b823..3f82c5bb865 100755
> --- a/libiberty/configure
> +++ b/libiberty/configure
> @@ -5375,7 +5375,8 @@ rm -f core conftest.err conftest.$ac_objext \
> fi
>
> if test x$may_have_cet = xyes; then
> - if test "$cross_compiling" = yes; then :
> + if test x$cross_compiling = xno; then
> +if test "$cross_compiling" = yes; then :
>{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
> $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
> as_fn_error $? "cannot run test program while cross compiling
> @@ -5420,9 +5421,14 @@ rm -f core *.core core.conftest.* gmon.out bb.out
> conftest$ac_exeext \
>conftest.$ac_objext conftest.beam conftest.$ac_ext
> fi
>
> - if test x$enable_cet = xno -a x$have_cet = xyes; then
> -as_fn_error $? "Intel CET must be enabled on Intel CET enabled host"
> "$LINENO" 5
> +if test x$enable_cet = xno -a x$have_cet = xyes; then
> + as_fn_error $? "Intel CET must be enabled on Intel CET enabled host"
> "$LINENO" 5
> +fi
>fi
> +else
> + # Enable CET in cross compiler if possible so that it will run on both
> + # CET and non-CET hosts.
> + have_cet=yes
> fi
> if test x$enable_cet = xyes; then
>CET_HOST_FLAGS="-fcf-protection"
> diff --git a/lto-plugin/configure b/lto-plugin/configure
> index 1baf6cc70b8..36c6ecc5875 100755
> --- a/lto-plugin/configure
> +++ b/lto-plugin/configure
> @@ -5768,7 +5768,8 @@ rm -f core conftest.err conftest.$ac_objext \
> fi
>
> if test x$may_have_cet = xyes; then
> - if test "$cross_compiling" = yes; then :
> + if test x$cross_compiling = xno; then
> +if test "$cross_compiling" = yes; then :
>{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
> $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
> as_fn_error $? "cannot run test program while cross compiling
> @@ -5813,9 +5814,14 @@ rm -f core *.core core.conftest.* gmon.out bb.out
> conftest$ac_exeext \
>conftest.$ac_objext conftest.beam conftest.$ac_ext
> fi
>
> - if test x$enable_cet = xno -a x$have_cet = xyes; then
> -as_fn_error $? "Intel CET must be enabled on Intel CET enabled host"
> "$LINENO" 5
> +if test x$enable_cet = xno -a x$have_cet = xyes; then
> + as_fn_error $? "Intel CET must be enabled on Intel CET enabled host"
> "$LINENO" 5
> +fi
>fi
> +else
> + # Enable CET in cross compiler if possible so that it will run on both
> + # CET and non-CET hosts.
> + have_cet=yes
> fi
> if test x$enable_cet = xyes; then
>CET_HOST_FLAGS="-fcf-protection"
> @@ -11941,7 +11947,7 @@ else
>lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
>lt_status=$lt_dlunknown
>cat > conftest.$ac_ext <<_LT_EOF
> -#line 11944 "configure"
> +#line 11950 "configure"
> #include "confdefs.h"
>
> #if HAVE_DLFCN_H
> @@ -12047,7 +12053,7 @@ else
>lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
>lt_status=$lt_dlunknown
>cat > conftest.$ac_ext <<_LT_EOF
> -#line 12050 "configure"
> +#line 12056 "configure"
> #include "confdefs.h"
>
> #if HAVE_DLFCN_H
> --
> 2.26.2
>
PING.
This fixes a regression on master and GCC 10 branch.
--
H.J.
Re: [PATCH] rs6000: Add cntlzdm and cnttzdm
On Mon, May 11, 2020 at 11:45:09AM -0500, Bill Schmidt wrote: > On 5/8/20 6:51 PM, Segher Boessenkool wrote: > >On Fri, May 08, 2020 at 08:17:18AM -0500, Bill Schmidt wrote: > >>From: Kelvin Nilsen > >> > >>Add support for new scalar instructions for counting leading or > >>trailing zeros under control of a bitmask. > >> > >>Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no > >>regressions. Is this okay for master? > >Ooh, I found problems! > > Thanks for catching these! Okay with them fixed? Erm yes, sorry I forgot to say -- I don't see any othger problems. Segher
Re: [PATCH] rs6000: Add vec_extracth and vec_extractl
On Mon, May 11, 2020 at 10:56 PM Bill Schmidt wrote:
>
> On 5/11/20 9:48 AM, David Edelsohn wrote:
> > On Sun, May 10, 2020 at 9:14 AM Bill Schmidt wrote:
> >> From: Kelvin Nilsen
> >>
> >> Add new insns vextdu[bhw]vlx, vextddvlx, vextdu[bhw]vhx, and
> >> vextddvhx, along with built-in access and overloaded built-in
> >> access to these insns.
> >>
> >> Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
> >> regressions, using a Power9 configuration. Is this okay for
> >> master?
> >>
> >> Thanks,
> >> Bill
> >>
> >> [gcc]
> >>
> >> 2020-05-10 Kelvin Nilsen
> >>
> >> * config/rs6000/altivec.h (vec_extractl): New #define.
> >> (vec_extracth): Likewise.
> >> * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
> >> (UNSPEC_EXTRACTR): Likewise.
> >> (VEXTRACT_LR): New int iterator.
> > Well now the previous VSTRIR/VSTRIL patch is inconsistent. If we're
> > going to use an iterator for "LR", that's fine, but it needs to be
> > used consistently for similar situations. The approach for the two,
> > similar instructions and issues need to match.
>
>
> I see your point. I don't really like the way this was done very much,
> since the attributes are tied to the unspecs for extract-{low,high}.
> Simple attribute names like LR, lr, rl shouldn't be scoped so narrowly.
>
> I don't like any of the alternatives very well, either. I could either
> (1) change the names of the int iterators in this patch to incorporate
> part of the word "extract", and create similar iterators for the
> vstril/vstrir patterns; or (2) remove the iterators from this patch and
> just create two expansions and two insns instead of one of each. I have
> a slight preference for (2) since the longer iterator names will make
> things ugly.
>
> Do you or Segher have a preference?
Hi, Bill
I don't have a particular preference. Maybe Segher sees more future
implications from one choice or the other.
It's easy enough to create a more generic iterator name (LEFTRIGHT_ITERATOR).
Some of the earlier even/odd patterns with endian fixes required more
adjustment to one or the other, so it couldn't use a simple iterator,
which means we can't be completely consistent. I would prefer that if
an endian fixup pattern can use an iterator, we either always use one
or never use one, not this mix and match. It should be a consistent
style and implementation in the rs6000 port.
Thanks, David
[PATCH] middle-end/94988 fix testcase for big-endian
The testcase only works for little-endian, mark it so.
2020-05-12 Richard Biener
* gcc.dg/torture/pr94988.c: Disable runtime test for
* non-little-endian.
---
gcc/testsuite/gcc.dg/torture/pr94988.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/torture/pr94988.c
b/gcc/testsuite/gcc.dg/torture/pr94988.c
index 1ee99fea5ce..dd523b81d99 100644
--- a/gcc/testsuite/gcc.dg/torture/pr94988.c
+++ b/gcc/testsuite/gcc.dg/torture/pr94988.c
@@ -14,7 +14,9 @@ main()
{
b = (short *)
bar (0, 1);
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
if ((short)(__UINTPTR_TYPE__)b != 0)
__builtin_abort ();
+#endif
return 0;
}
--
2.12.3
[committed] MSP430: Define ASM_OUTPUT_ALIGNED_DECL_LOCAL
The attached patch implements ASM_OUTPUT_ALIGNED_DECL_LOCAL for msp430. The
default handler needs to be overridden so local common symbols which need
their own section (e.g. variables with the "noinit" attribute) will be placed
in that section rather than the common block.
This fixes "gcc.c-torture/execute/noinit-attribute.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects execution test", which was failing
because the global noinit variable would get optimized into a local common
variable by LTO and placed in the common block, which always get initialized to
0.
The attached patch also skips the noinit-attribute test for msp430 when -mlarge
is being tested. The simulator linker script for -mlarge simulates the copying
of data from ROM to RAM at startup, so a variable in the test which is supposed
to check if this is the first or second time round the test, is always reset to
its initial value, causing the test to loop forever and eventually timeout.
Successfully regtested for msp430-elf in the default, -mcpu=msp430 and -mlarge
configurations.
Committed as obvious.
>From e8fb1a3892f4e2f8268ac2649776a7bd0a967643 Mon Sep 17 00:00:00 2001
From: Jozef Lawrynowicz
Date: Fri, 8 May 2020 14:45:20 +0100
Subject: [PATCH] MSP430: Define ASM_OUTPUT_ALIGNED_DECL_LOCAL
gcc/ChangeLog:
2020-05-12 Jozef Lawrynowicz
* config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
Update prototype to include "local" argument.
* config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
"local" argument. Handle local common decls.
* config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
msp430_output_aligned_decl_common call with 0 for "local" argument.
(ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
gcc/testsuite/ChangeLog:
2020-05-12 Jozef Lawrynowicz
* gcc.c-torture/execute/noinit-attribute.c: Skip for msp430
in the large memory model.
---
gcc/ChangeLog | 10 ++
gcc/config/msp430/msp430-protos.h | 3 ++-
gcc/config/msp430/msp430.c| 19 +++
gcc/config/msp430/msp430.h| 8 +++-
gcc/testsuite/ChangeLog | 5 +
.../gcc.c-torture/execute/noinit-attribute.c | 6 +-
6 files changed, 44 insertions(+), 7 deletions(-)
diff --git gcc/ChangeLog gcc/ChangeLog
index b0a9212688a..e2b01aaae27 100644
--- gcc/ChangeLog
+++ gcc/ChangeLog
@@ -1,3 +1,13 @@
+2020-05-12 Jozef Lawrynowicz
+
+ * config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
+ Update prototype to include "local" argument.
+ * config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
+ "local" argument. Handle local common decls.
+ * config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
+ msp430_output_aligned_decl_common call with 0 for "local" argument.
+ (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
+
2020-05-12 Richard Biener
* cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
diff --git gcc/config/msp430/msp430-protos.h gcc/config/msp430/msp430-protos.h
index 657af4c7075..29ce9babc4a 100644
--- gcc/config/msp430/msp430-protos.h
+++ gcc/config/msp430/msp430-protos.h
@@ -39,7 +39,8 @@ boolmsp430_is_interrupt_func (void);
const char * msp430x_logical_shift_right (rtx);
const char * msp430_mcu_name (void);
voidmsp430_output_aligned_decl_common (FILE *, const tree, const char *,
- unsigned HOST_WIDE_INT, unsigned);
+ unsigned HOST_WIDE_INT, unsigned,
+ int);
void msp430_output_labelref (FILE *, const char *);
void msp430_register_pragmas (void);
rtx msp430_return_addr_rtx (int);
diff --git gcc/config/msp430/msp430.c gcc/config/msp430/msp430.c
index e77ca101599..6bb1714f465 100644
--- gcc/config/msp430/msp430.c
+++ gcc/config/msp430/msp430.c
@@ -2019,13 +2019,15 @@ msp430_unique_section (tree decl, int reloc)
/* Emit a declaration of a common symbol.
If a data region is in use then put the symbol into the
- equivalent .bss section instead. */
+ equivalent .bss section instead.
+ If LOCAL is 1, then DECL is for a local common variable. */
void
msp430_output_aligned_decl_common (FILE * stream,
const tree decl,
const char * name,
unsigned HOST_WIDE_INT size,
- unsigned int align)
+ unsigned int align,
+ int local)
{
/* Only emit a common symbol if the variable does not have a specific section
assigned. */
@@ -2039,6 +2041,12 @@ msp430_output_aligned_decl_common (FILE * stream,
&& !has_attr (ATTR_PERSIST, decl)
&& !has_attr (ATTR_NOINIT, decl))
{
+ if (local)
+ {
+ fprintf (stream, LOCAL_ASM_OP);
+ assemble_name (stream, name);
+ fprintf (stream, "\n");
+ }
fprintf (stream, COMMON_ASM_OP);
assemble_name (stream, name);
fprintf (stream, "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
@@ -2069,8 +2077,11 @@ msp430_output_aligned_decl_common (FILE * stream,
switch_to_section
[committed] MSP430: Allow .bss section to be created in region-attribute-misuse test
Uninitialized global variables are put in the .bss section since the -fno-common
change, the attached patch prevents region-attribute-misuse.c failing if a .bss
section is in the assembler output.
Committed as obvious.
>From 89aa37dc3c71666d0ff05e96ea84e195d049a226 Mon Sep 17 00:00:00 2001
From: Jozef Lawrynowicz
Date: Mon, 11 May 2020 16:58:11 +0100
Subject: [PATCH] MSP430: Allow .bss section to be created in
region-attribute-misuse test
2020-05-12 Jozef Lawrynowicz
* gcc.target/msp430/region-attribute-misuse.c: Allow a .bss section to
be created.
---
gcc/testsuite/ChangeLog | 5 +
gcc/testsuite/gcc.target/msp430/region-attribute-misuse.c | 1 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git gcc/testsuite/ChangeLog gcc/testsuite/ChangeLog
index 05952acab92..da776417bd5 100644
--- gcc/testsuite/ChangeLog
+++ gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-12 Jozef Lawrynowicz
+
+ * gcc.target/msp430/region-attribute-misuse.c: Allow a .bss section to
+ be created.
+
2020-05-12 Martin Liska
PR sanitizer/95033
diff --git gcc/testsuite/gcc.target/msp430/region-attribute-misuse.c gcc/testsuite/gcc.target/msp430/region-attribute-misuse.c
index a108e274123..2b5107f0b8c 100644
--- gcc/testsuite/gcc.target/msp430/region-attribute-misuse.c
+++ gcc/testsuite/gcc.target/msp430/region-attribute-misuse.c
@@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-mcpu=msp430" "-mlarge" "-mcode-region=*" "-mdata-region=*" } { "" } } */
-/* { dg-final { scan-assembler-not ".section.*bss" } } */
/* { dg-final { scan-assembler ".section.*upper.data" } } */
/* { dg-final { scan-assembler ".section.*lower.data" } } */
/* { dg-final { scan-assembler ".section.*either.data" } } */
--
2.17.1
[Ada] Fix PR ada/95035
This fixes an oversight in the new canonicalization code for packable types: it does not take into account the scalar storage order. Tested on x86-64/Linux and SPARC/Solaris, applied on the mainline. 2020-05-12 Eric Botcazou PR ada/95035 * gcc-interface/utils.c (packable_type_hasher::equal): Also compare the scalar storage order. (hash_packable_type): Also hash the scalar storage order. (hash_pad_type): Likewise. -- Eric Botcazoudiff --git a/gcc/ada/gcc-interface/utils.c b/gcc/ada/gcc-interface/utils.c index 391b6827a5e..1527be4f6d1 100644 --- a/gcc/ada/gcc-interface/utils.c +++ b/gcc/ada/gcc-interface/utils.c @@ -1026,14 +1026,15 @@ packable_type_hasher::equal (packable_type_hash *t1, packable_type_hash *t2) type1 = t1->type; type2 = t2->type; - /* We consider that packable types are equivalent if they have the same - name, size, alignment and RM size. Taking the mode into account is - redundant since it is determined by the others. */ + /* We consider that packable types are equivalent if they have the same name, + size, alignment, RM size and storage order. Taking the mode into account + is redundant since it is determined by the others. */ return TYPE_NAME (type1) == TYPE_NAME (type2) && TYPE_SIZE (type1) == TYPE_SIZE (type2) && TYPE_ALIGN (type1) == TYPE_ALIGN (type2) -&& TYPE_ADA_SIZE (type1) == TYPE_ADA_SIZE (type2); +&& TYPE_ADA_SIZE (type1) == TYPE_ADA_SIZE (type2) +&& TYPE_REVERSE_STORAGE_ORDER (type1) == TYPE_REVERSE_STORAGE_ORDER (type2); } /* Compute the hash value for the packable TYPE. */ @@ -1047,6 +1048,8 @@ hash_packable_type (tree type) hashcode = iterative_hash_expr (TYPE_SIZE (type), hashcode); hashcode = iterative_hash_hashval_t (TYPE_ALIGN (type), hashcode); hashcode = iterative_hash_expr (TYPE_ADA_SIZE (type), hashcode); + hashcode += iterative_hash_hashval_t (TYPE_REVERSE_STORAGE_ORDER (type), hashcode); return hashcode; } @@ -1402,7 +1405,7 @@ pad_type_hasher::equal (pad_type_hash *t1, pad_type_hash *t2) type1 = t1->type; type2 = t2->type; - /* We consider that the padded types are equivalent if they pad the same type + /* We consider that padded types are equivalent if they pad the same type and have the same size, alignment, RM size and storage order. Taking the mode into account is redundant since it is determined by the others. */ return @@ -1425,6 +1428,8 @@ hash_pad_type (tree type) hashcode = iterative_hash_expr (TYPE_SIZE (type), hashcode); hashcode = iterative_hash_hashval_t (TYPE_ALIGN (type), hashcode); hashcode = iterative_hash_expr (TYPE_ADA_SIZE (type), hashcode); + hashcode += iterative_hash_hashval_t (TYPE_REVERSE_STORAGE_ORDER (type), hashcode); return hashcode; }
Re: [Patch][Fortran] OpenMP - permit lastprivate in distribute + SIMD fixes (PR94690)
On Thu, Apr 23, 2020 at 08:52:39AM +0200, Tobias Burnus wrote: > [Fortran] OpenMP - permit lastprivate in distribute + SIMD fixes (PR94690) > > PR fortran/94690 > * openmp.c (OMP_DISTRIBUTE_CLAUSES): Add OMP_CLAUSE_LASTPRIVATE. > * trans-openmp.c (gfc_trans_omp_do): Don't add private/lastprivate > for dovar_found == 0, unless !simple. > * openmp.c (gfc_resolve_do_iterator): Skip the private handling > for SIMD as that is handled by ME code. Ok, thanks. But can you please put the two openmp.c changes together under the same * openmp.c (OMP_DISTRIBUTE_CLAUSES): ... (gfc_resolve_do_iterator): ... ? > > PR fortran/94690 > * libgomp.fortran/pr66199-3.f90: New. > * libgomp.fortran/pr66199-4.f90: New. > * libgomp.fortran/pr66199-5.f90: New. > * libgomp.fortran/pr66199-6.f90: New. > * libgomp.fortran/pr66199-7.f90: New. > * libgomp.fortran/pr66199-8.f90: New. > * libgomp.fortran/pr66199-9.f90: New. Jakub
[PATCH] remove dead debug-bind resets
This removes debug-bind resets aka
# DEBUG b = NULL
when the reset variable is otherwise unused. I've gathered statistics
for a single TU, fold-const.ii which at -O2 -g shows
28 ssa "dead debug bind reset" 1
34 einline "dead debug bind reset" 340
54 release_ssa "dead debug bind reset" 176
54 release_ssa "live debug bind reset of dead var" 4
86 inline "dead debug bind reset" 5131
86 inline "live debug bind reset of dead var" 61
241 optimized "dead debug bind reset" 970
241 optimized "live debug bind reset of dead var" 287
where "live debug bind reset of dead var" means the variable is unused
but there were debug binds with a value for them and
"dead debug bind reset" means the variable is unused and there were
only debug bind resets (each reset of the same variable is counted
for both counters). This shows A considerable amount of dead stmts
removed esp. after IPA inlining.
Bootstrap and regtest running on x86_64-unknown-linux-gnu.
Richard.
2020-05-12 Richard Biener
* tree-ssa-live.c (remove_unused_locals): Remove dead debug
bind resets.
---
gcc/tree-ssa-live.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/gcc/tree-ssa-live.c b/gcc/tree-ssa-live.c
index f3975320e8c..c2e3787f99a 100644
--- a/gcc/tree-ssa-live.c
+++ b/gcc/tree-ssa-live.c
@@ -743,6 +743,7 @@ remove_unused_locals (void)
mark_scope_block_unused (DECL_INITIAL (current_function_decl));
usedvars = BITMAP_ALLOC (NULL);
+ auto_bitmap useddebug;
/* Walk the CFG marking all referenced symbols. */
FOR_EACH_BB_FN (bb, cfun)
@@ -763,7 +764,21 @@ remove_unused_locals (void)
do it. If the block is not otherwise used, the stmt will
be cleaned up in clean_unused_block_pointer. */
if (is_gimple_debug (stmt))
- continue;
+ {
+ if (gimple_debug_bind_p (stmt))
+ {
+ tree var = gimple_debug_bind_get_var (stmt);
+ if (TREE_CODE (var) != DEBUG_EXPR_DECL)
+ {
+ if (!gimple_debug_bind_get_value (stmt))
+ /* Run the 2nd phase. */
+ have_local_clobbers = true;
+ else
+ bitmap_set_bit (useddebug, DECL_UID (var));
+ }
+ }
+ continue;
+ }
if (gimple_clobber_p (stmt))
{
@@ -846,6 +861,20 @@ remove_unused_locals (void)
if (b)
TREE_USED (b) = true;
}
+ else if (gimple_debug_bind_p (stmt))
+ {
+ tree var = gimple_debug_bind_get_var (stmt);
+ if (TREE_CODE (var) != DEBUG_EXPR_DECL
+ && !bitmap_bit_p (useddebug, DECL_UID (var))
+ && !bitmap_bit_p (usedvars, DECL_UID (var)))
+ {
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ fprintf (dump_file, "Dead debug bind reset to %u\n",
+ DECL_UID (var));
+ gsi_remove (, true);
+ continue;
+ }
+ }
gsi_next ();
}
}
--
2.16.4
Re: [Patch][OpenMP] Fix mapping of artificial variables (PR94874)
On Fri, May 08, 2020 at 05:09:07PM +0200, Tobias Burnus wrote:
> I was thinking of simply marking them as
> "nflags |= GOVD_FIRSTPRIVATE" but I am not sure whether
> that would always make sense, either. In any case, a
> simple usage would bypass the
> "implicit mapping of assumed size array"
> diagnostic in gfc_omp_finish_clause.
>
> One could also use a value returned by the hook,
> but currently it is tailored for shared memory
> use only. A fix would be either a new argument
> ("bool for_mapping") plus special handling or
> a new hook. In any case, the current hook has:
I think we want a new hook, the clear cases (mostly DECL_ARTIFICIAL ones,
if it is really something compiler created and not something under user's
control) handle the way we find best for them (perhaps firstprivate
in some cases, though e.g. for typeinfo and vtables I think we want to make
them declare target to), but for user-visible stuff best file a github
OpenMP/spec issue (can you please do that) and discuss there?
I mean, if something is predetermined firstprivate, then one could in some
reading assume it then can't be specified and must be firstprivatized on
target (or as an exception may be specified but still default to being
firstprivatized), but if the spec says that e.g. static data members are
predetermined shared, then I don't see how that makes any difference to
how it should be mapped or not. So, it is unclear what
void bar (const char *);
#pragma omp declare target to (bar)
void foo ()
{
#pragma omp target defaultmap(none)
bar (__FUNCTION__);
}
should be doing, etc.; target really doesn't have shared clauses and nothing
says that variables that have predetermined data sharing of shared are say
mapped(tofrom:) implicitly.
Jakub
Re: Follow-up Patch – Re: [Patch][OpenMP] Fix 'omp exit data' for Fortran arrays (PR 94635)
On Thu, Apr 23, 2020 at 03:43:47PM +0200, Tobias Burnus wrote: > On 4/20/20 11:33 PM, Thomas Schwinge wrote: > > Really 'GOMP_MAP_DELETE', or should that rather be 'GOMP_MAP_RELEASE'? > > Depends on the previous item, i.e. 'delete:' vs. 'release:/from:/…' > > Rather obvious – OK? > > Tobias > > - > Mentor Graphics (Deutschland) GmbH, Arnulfstraße 201, 80634 München / Germany > Registergericht München HRB 106955, Geschäftsführer: Thomas Heurung, > Alexander Walter > [OpenMP] Fix 'omp exit data' for Fortran arrays (PR 94635) > > PR middle-end/94635 > * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with > OMP_TARGET_EXIT_DATA, use 'release:' unless the associated > item is 'delete:'. > > PR middle-end/94635 > * gfortran.dg/gomp/target-exit-data.f90: New. Ok, thanks. Jakub
Re: [PATCH] [PR94118]] Update documentation for x86 operand modifier.
On Tue, May 12, 2020 at 7:27 AM Hongtao Liu wrote: > > Documents operand modifiers which are available in asm stmt but > missing in document. > > | Modifier | Description | Available in asm stmt | Existed in documentation | > | --- | --- | --- | - | > | L,W,B,Q,S,T | print the opcode suffix for specified size of > operand. | Available | Not | > | C | print opcode suffix for set/cmov insn. | Not | - | > | c | like C, but print reversed condition | Not | - | > | F,f | likewise, but for floating-point. | Not | - | > | O | if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.", > otherwise nothing | Not | - | > | R | print embedded rounding and sae. | Available | Not | > | r | print only sae. | Available | Not | > | z | print the opcode suffix for the size of the current operand. | > Available | Existed | > | Z | likewise, with special suffixes for x87 instructions. | Availble | Not > | > | * | print a star (in certain assembler syntax) | Not | - | > | A | print an absolute memory reference. | Available | Existed | > | E | print address with DImode register names if TARGET_64BIT. | > Available | Existed | > | w | print the operand as if it's a "word" (HImode) even if it > isn't. | Available | Existed | > | s | print a shift double count, followed by the assemblers argument > delimiter. | Available | Not | > | b | print the QImode name of the register for the indicated operand > %b0 would print %al if operands[0] is reg 0. | Available | Existed | > | w | likewise, print the HImode name of the register. | Available | Existed > | > | k | likewise, print the SImode name of the register. | Available | Existed > | > | q | likewise, print the DImode name of the register. | Available | Existed > | > | x | likewise, print the V4SFmode name of the register. | Available | Not | > | t | likewise, print the V8SFmode name of the register. | Available | Not | > | g | likewise, print the V16SFmode name of the register. | Avaliable | Not | > | h | print the QImode name for a "high" register, either ah, bh, ch > or dh. | Available | Existed | > | y | print "st(0)" instead of "st" as a register. | Available | Not | > | d | print duplicated register operand for AVX instruction. | > Available | Not | > | D | print condition for SSE cmp instruction. | Not | - | > | P | if PIC, print an @PLT suffix. | Available | Existed | > | p | print raw symbol name. | Available | Existed | > | X | don't print any sort of PIC '@' suffix for a symbol. | Not | - | > | & | print some in-use local-dynamic symbol name. | Not | - | > | H | print a memory address offset by 8; used for sse high-parts | > Available | Existed | > | Y | print condition for XOP pcom* instruction. | Not | - | > | V | print naked full integer register name without %. | Available | > Existed | > | + | print a branch hint as 'cs' or 'ds' prefix | Not | - | > | ; | print a semicolon (after prefixes due to bug in older gas). | Not | - | > | ~ | print "i" if TARGET_AVX2, "f" otherwise. | Not | - | > | ^ | print addr32 prefix if TARGET_64BIT and Pmode != word_mode | Not | - | > | M | print addr32 prefix for TARGET_X32 with VSIB address. | Not | - | > | ! | print NOTRACK prefix for jxx/call/ret instructions if required. > | Not | - | > | N | print maskz if it's constant 0 operand. | Available | Not | > | I | print comparision predicate operand for sse cmp condition. | Not | - | > > Bootstrap is ok. > > gcc/ChangeLog > > PR target/94118 > * doc/extend.texi (x86Operandmodifiers): Document more x86 > operand modifier. > * gcc/config/i386/i386.c: Add comment for operand modifier N > and I. Although some of modifiers are considered for internal use, they won't go away, so they could be documented as well. LGTM. Thanks, Uros.
Re: [PATCH] rs6000: Vector string isolate instructions
Hi!
Looks fine to me... Just the same generic things as before, things we
can improve later, not even limited to this series:
On Sat, May 09, 2020 at 08:16:26AM -0500, Bill Schmidt wrote:
> * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
> (UNSPEC_VSTRIL): Likewise.
Names for these could perhaps be better. Or maybe not, they are short
now, there's something to say for that as well :-)
> (vstrir_): New expansion.
> (vstrir_code_): New insn.
Could you make this vstrir and vstrir_internal, like the
rest?
> (vstrir_p_): New expansion.
> (vstrir_p_code_): New insn.
But, not sure what to do with those. "Something to improve later" then
I guess, for all of it :-)
> +(define_expand "vstrir_"
> + [(set (match_operand:VIshort 0 "altivec_register_operand")
> + (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")]
> + UNSPEC_VSTRIR))]
> + "TARGET_FUTURE"
> +{
> + if (BYTES_BIG_ENDIAN)
> +emit_insn (gen_vstrir_code_ (operands[0], operands[1]));
> + else
> +emit_insn (gen_vstril_code_ (operands[0], operands[1]));
> + DONE;
> +})
So the reason this pattern is special at all is that left and right are
swapped for LE. Maybe that could/should be done in the code for the
builtin, instead?
> +;; This expands into same code as vstrir_ followed by condition logic
> +;; so that a single vstribr. or vstrihr. or vstribl. or vstrihl. instruction
> +;; can, for example, satisfy the needs of a vec_strir () function paired
> +;; with a vec_strir_p () function if both take the same incoming arguments.
> +(define_expand "vstrir_p_"
> + [(match_operand:SI 0 "gpc_reg_operand")
> + (match_operand:VIshort 1 "altivec_register_operand")]
> + "TARGET_FUTURE"
> +{
> + rtx scratch = gen_reg_rtx (mode);
> + if (BYTES_BIG_ENDIAN)
> +emit_insn (gen_vstrir_p_code_ (scratch, operands[1]));
> + else
> +emit_insn (gen_vstril_p_code_ (scratch, operands[1]));
> + emit_insn (gen_cr6_test_for_zero (operands[0]));
> + DONE;
> +})
And the code for the builtin can do this then, as well.
Not sure how easy that is to fit in with the current code, or after your
work on it. Either way, it looks fine to me :-)
Segher
Re: Automatically generated ChangeLog files - PHASE 1
I'm also CCing gcc-patches and fortran ML. Martin On 5/12/20 11:05 AM, Martin Liška wrote: Hi. Thanks to Jakub, we finally set up an experimental environment: gcc.gnu.org/home/gccadmin/gcc-reposurgeon-8.git The repository now contains a new pre-commit hook that validates the git commit format ([1]) and provides a reasonable error message when violated. The hook is based on [2] and the page also contains a fuzzy definition of what is supported. Cloning [2], one can also check what will be added to ChangeLog entries by: $ ./git_changelog.py /home/marxin/Programming/gcc-reposurgeon-8 8a37df5e5cb2de8302f9412173103593ec53961e -- gcc/ChangeLog -- 2020-01-13 Martin Jambor PR ipa/93223 * ipa-cp.c (devirtualization_time_bonus): Check whether isummary is NULL. -- gcc/testsuite/ChangeLog -- 2020-01-13 Martin Jambor PR ipa/93223 testsuite/ * g++.dg/ipa/pr93223.C: New test. (one needs [3] Python package for that) We encourage people to test both the hook and the script. We hope we'll cover majority of the used formats. I also support _not_ using DATESTAMP and committer name, these can be automatically deduced from a commit. That will simplify workflow as people won't have to adjust a message before pushing. Unresolved questions: - format of reverted patches - what to do with backports Here I suggest to use native 'git revert XYZ' and 'git cherry-pick -x XYZ'. Doing that the commit messages will provide link to original commit and the script can later append corresponding 'Backported ..' or 'Reverted' line. For the possible issues or questions, please open a Github issue at [4]. Thoughts? Martin [1] https://github.com/marxin/git-hooks/tree/gcc-changelog [2] https://github.com/marxin/gcc-changelog [3] https://gitpython.readthedocs.io/en/stable/intro.html [4] https://github.com/marxin/gcc-changelog/issues
Re: [pushed] c++: Make references to __cxa_pure_virtual weak.
On Mai 11 2020, Jason Merrill via Gcc-patches wrote: > If a program has no other dependencies on libstdc++, we shouldn't require it > just for __cxa_pure_virtual, which is only there to give a prettier > diagnostic before crashing the program; resolving the reference to NULL will > also crash, just without the diagnostic. That doesn't work on ia64: pure-virtual1.o:(.data.rel.ro._ZTV1A[_ZTV1A]+0x10): undefined reference to `__cxa_pure_virtual' collect2: error: ld returned 1 exit status $ nm -u pure-virtual1.o U __cxa_pure_virtual Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different."
Re: [PATCH] make minmax detection work with FMIN/FMAX IFNs
On Mon, 11 May 2020, Joseph Myers wrote:
> On Fri, 8 May 2020, Richard Biener wrote:
>
> > The IFNs are supposed to match fmin and fmax from the C standard which
> > IIRC have IEEE semantics.
>
> fmin and fmax have IEEE (2008) semantics (where an sNaN operand results in
> a qNaN result with "invalid" raised", but a quiet NaN results in the other
> operand, if not sNaN, being returned). Not to be confused with any of the
> new minimum/maximum operations in IEEE (2019) (both variants that treat
> all NaNs like other arithmetic operations, and variants that can raise
> "invalid" for sNaN without returning a NaN), for which C bindings under
> different names are proposed.
Uh, ok - that makes the situation even more messy in the future
(exact rules how to combine maximumX (fmin (X, Y), X) or so...).
In the mean time I'm considering the following for my immediate
needs which are PR88540 not basic-block vectorizing FP min/max w/o
-ffast-math and testcase breakage in gcc.target/i386/pr54855-[89].c
where conditional move handling on RTL no longer happens when
GIMPLE starts to be more clever.
The patch below makes phiopt if-convert min/max-like operations
for floating-point types regardless of HONOR_NANS/HONOR_SIGNED_ZEROS
because targets likely implement instructions for C conditional
operator-style min/max-like operations.
Now x86 does so for d1[n] < d2[n] ? d1[n] : d2[n] but not
d1[n] <= d2[n] ? d1[n] : d2[n] which is a subtle difference but
the patch below still if-converts those.
I've chosen not to try to combine with existing min/max operations
(nor try detecting the COND_EXPR form as such) but instead give up.
I could have given up for <= and >= operations as well (and not
if-convert), if there's reasons to believe no targets implement
single instructions for those.
Note I specifically do not want general if-conversion to
COND_EXPRs applied here (so that's a bit of conflicting interest).
But there's no standard pattern names for those conditional
min/max-like operations (and I'm not sure we need them).
Thanks,
Richard.
[PATCH] tree-optimization/88540 - apply phiopt to min/max-like operation
This applies if conversion in phiopt to a < b ? a : b like computations
which are not MIN or MAX_EXPR or fmin or fmax due to NaNs and
signed zeros. Instead of giving up this makes phiopt emit
a COND_EXPR. This helps vectorization of straight-line code and
avoids messing up the pattern by PRE.
2020-05-12 Richard Biener
PR tree-optimization/88540
* tree-ssa-phiopt.c (minmax_replacement): When honoring
NaNs or signed zeros instead emit a COND_EXPR.
* gcc.target/i386/pr88540-1.c: New testcase.
---
gcc/testsuite/gcc.target/i386/pr88540-1.c | 21 +
gcc/tree-ssa-phiopt.c | 25 ++---
2 files changed, 39 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr88540-1.c
diff --git a/gcc/testsuite/gcc.target/i386/pr88540-1.c
b/gcc/testsuite/gcc.target/i386/pr88540-1.c
new file mode 100644
index 000..a66b89ef66c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr88540-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+void test1(double* __restrict d1, double* __restrict d2, double* __restrict d3)
+{
+ for (int n = 0; n < 2; ++n)
+{
+ d3[n] = d1[n] < d2[n] ? d1[n] : d2[n];
+}
+}
+
+void test2(double* __restrict d1, double* __restrict d2, double* __restrict d3)
+{
+ for (int n = 0; n < 2; ++n)
+{
+ d3[n] = d1[n] > d2[n] ? d1[n] : d2[n];
+}
+}
+
+/* { dg-final { scan-assembler "minpd" } } */
+/* { dg-final { scan-assembler "maxpd" } } */
diff --git a/gcc/tree-ssa-phiopt.c b/gcc/tree-ssa-phiopt.c
index b1e0dce93d8..eac8dcdd696 100644
--- a/gcc/tree-ssa-phiopt.c
+++ b/gcc/tree-ssa-phiopt.c
@@ -1369,13 +1369,10 @@ minmax_replacement (basic_block cond_bb, basic_block
middle_bb,
enum tree_code cmp, minmax, ass_code;
tree smaller, alt_smaller, larger, alt_larger, arg_true, arg_false;
gimple_stmt_iterator gsi, gsi_from;
+ bool ieee_fp;
type = TREE_TYPE (PHI_RESULT (phi));
-
- /* The optimization may be unsafe due to NaNs. */
- if (HONOR_NANS (type) || HONOR_SIGNED_ZEROS (type))
-return false;
-
+ ieee_fp = (HONOR_NANS (type) || HONOR_SIGNED_ZEROS (type));
cond = as_a (last_stmt (cond_bb));
cmp = gimple_cond_code (cond);
rhs = gimple_cond_rhs (cond);
@@ -1527,6 +1524,10 @@ minmax_replacement (basic_block cond_bb, basic_block
middle_bb,
b = MAX (a, d);
x = MIN (b, u); */
+ /* But not when we have to care bout NaNs or singed zeros. */
+ if (ieee_fp)
+ return false;
+
gimple *assign = last_and_only_stmt (middle_bb);
tree lhs, op0, op1, bound;
@@ -1697,8 +1698,18 @@ minmax_replacement (basic_block cond_bb, basic_block
middle_bb,
else
result = make_ssa_name (TREE_TYPE (result));
- /* Emit the statement to compute
Re: [C++] EOF has a location
Hi Jakub,
> On Fri, May 08, 2020 at 11:48:34AM -0400, Nathan Sidwell wrote:
>> 2020-05-08 Nathan Sidwell
>>
>> gcc/cp/
>> * parser.c (cp_lexer_set_source_position_from_token): EOF has a
>> location too.
>
> This change:
>
>> --- c/gcc/cp/parser.c
>> +++ w/gcc/cp/parser.c
>> @@ -895,10 +895,7 @@ cp_lexer_get_preprocessor_token (cp_lexer *lexer,
>> cp_token *token)
>> static inline void
>> cp_lexer_set_source_position_from_token (cp_token *token)
>> {
>> - if (token->type != CPP_EOF)
>> -{
>> - input_location = token->location;
>> -}
>> + input_location = token->location;
>> }
>>
>> /* Update the globals input_location and the input file stack from LEXER.
>> */
>
> seems to have regressed:
> +FAIL: obj-c++.dg/syntax-error-10.mm -fgnu-runtime (test for errors, line 1)
> +FAIL: obj-c++.dg/syntax-error-10.mm -fgnu-runtime (test for excess errors)
> +FAIL: obj-c++.dg/syntax-error-8.mm -fgnu-runtime (test for errors, line 1)
> +FAIL: obj-c++.dg/syntax-error-8.mm -fgnu-runtime (test for excess errors)
> +FAIL: obj-c++.dg/syntax-error-9.mm -fgnu-runtime (test for errors, line 2)
> +FAIL: obj-c++.dg/syntax-error-9.mm -fgnu-runtime (test for excess errors)
> +FAIL: obj-c++.dg/property/property-neg-6.mm -fgnu-runtime (test for
> errors, line 8)
> +FAIL: obj-c++.dg/property/property-neg-6.mm -fgnu-runtime (test for excess
> errors)
>
> E.g. on syntax-error-8.mm, cc1objplus used to emit:
> syntax-error-8.mm:1:12: error: expected ‘@end’ at end of input
> 1 | @interface A /* { dg-error "expected ..end." } */
> |^
> and now it emits:
> syntax-error-8.mm:1: error: expected ‘@end’ at end of input
> 1 | @interface A /* { dg-error "expected ..end." } */
> |
> instead (no column at all).
this is PR objc++/95013. Nathan is working on it already.
Rainer
--
-
Rainer Orth, Center for Biotechnology, Bielefeld University
[PATCH] Optimize store_expr from STRING_CST [PR95052]
Hi!
In the following testcase, store_expr of e.g. 97 bytes long string literal
into 1MB long array is implemented by copying the 97 bytes from .rodata
section, followed by clearing the remaining bytes. But, as the STRING_CST
has type char[1024*1024], we actually allocate whole 1MB in .rodata section
for it, even when we only use the first 97 bytes from that.
The following patch tweaks it so that if we are going to initialize only the
small part from it, we don't emit all the zeros that we never use after it.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2020-05-12 Jakub Jelinek
PR middle-end/95052
* expr.c (store_expr): If expr_size is constant and significantly
larger than TREE_STRING_LENGTH, set temp to just the
TREE_STRING_LENGTH portion of the STRING_CST.
* gcc.target/i386/pr95052.c: New test.
--- gcc/expr.c.jj 2020-04-16 12:57:16.584912448 +0200
+++ gcc/expr.c 2020-05-11 20:58:46.436785403 +0200
@@ -5749,7 +5749,31 @@ store_expr (tree exp, rtx target, int ca
/* If we want to use a nontemporal or a reverse order store, force the
value into a register first. */
tmp_target = nontemporal || reverse ? NULL_RTX : target;
- temp = expand_expr_real (exp, tmp_target, GET_MODE (target),
+ tree rexp = exp;
+ if (TREE_CODE (exp) == STRING_CST
+ && tmp_target == target
+ && GET_MODE (target) == BLKmode
+ && TYPE_MODE (TREE_TYPE (exp)) == BLKmode)
+ {
+ rtx size = expr_size (exp);
+ if (CONST_INT_P (size)
+ && size != const0_rtx
+ && (UINTVAL (size)
+ > ((unsigned HOST_WIDE_INT) TREE_STRING_LENGTH (exp) + 32)))
+ {
+ /* If the STRING_CST has much larger array type than
+TREE_STRING_LENGTH, only emit the TREE_STRING_LENGTH part of
+it into the rodata section as the code later on will use
+memset zero for the remainder anyway. See PR95052. */
+ tmp_target = NULL_RTX;
+ rexp = copy_node (exp);
+ tree index
+ = build_index_type (size_int (TREE_STRING_LENGTH (exp) - 1));
+ TREE_TYPE (rexp) = build_array_type (TREE_TYPE (TREE_TYPE (exp)),
+ index);
+ }
+ }
+ temp = expand_expr_real (rexp, tmp_target, GET_MODE (target),
(call_param_p
? EXPAND_STACK_PARM : EXPAND_NORMAL),
_rtl, false);
--- gcc/testsuite/gcc.target/i386/pr95052.c.jj 2020-05-11 21:03:05.635238485
+0200
+++ gcc/testsuite/gcc.target/i386/pr95052.c 2020-05-11 21:02:47.473487020
+0200
@@ -0,0 +1,20 @@
+/* PR middle-end/95052 */
+/* { dg-do compile } */
+/* { dg-options "-Os -mtune=skylake" } */
+/* Verify we don't waste almost 2 megabytes of .rodata. */
+/* { dg-final { scan-assembler-not "\.zero\t1048\[0-9]\[0-9]\[0-9]" } } */
+extern void foo (char *, unsigned);
+
+int
+main ()
+{
+ char str[1024 * 1024] =
+
"fooiuhluhpiuhliuhliyfyukyfklyugkiuhpoipoipoipoipoipoipoipoipoipoipoipoipoimipoipiuhoulouihnliuhl";
+ char arr[1024 * 1024] =
+{ 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 6, 2, 3,
+ 4, 5, 6, 7, 8, 9, 0, 3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6,
+ 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0 };
+ foo (str, sizeof (str));
+ foo (arr, sizeof (arr));
+ return 0;
+}
Jakub
[committed] openmp: Fix up handling of DECL_OMP_PRIVATIZED_MEMBER for bit-fields [PR95063]
Hi!
The r11-15 change broke this testcase, as it now asserts type is equal to
the type of the DECL_VALUE_EXPR, but for DECL_OMP_PRIVATIZED_MEMBER artificial
vars mapping to bitfields it wasn't. Fixed by changing the
DECL_OMP_PRIVATIZED_MEMBER var type in that case.
Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk.
2020-05-12 Jakub Jelinek
PR c++/95063
* pt.c (tsubst_decl): Deal with DECL_OMP_PRIVATIZED_MEMBER for
a bit-field.
* g++.dg/gomp/pr95063.C: New test.
--- gcc/cp/pt.c.jj 2020-05-07 11:10:25.644548337 +0200
+++ gcc/cp/pt.c 2020-05-11 23:16:31.070378604 +0200
@@ -14627,6 +14627,12 @@ tsubst_decl (tree t, tree args, tsubst_f
}
if (nop)
ve = build_nop (type, ve);
+ else if (DECL_LANG_SPECIFIC (t)
+&& DECL_OMP_PRIVATIZED_MEMBER (t)
+&& TREE_CODE (ve) == COMPONENT_REF
+&& TREE_CODE (TREE_OPERAND (ve, 1)) == FIELD_DECL
+&& DECL_BIT_FIELD_TYPE (TREE_OPERAND (ve, 1)) == type)
+ type = TREE_TYPE (ve);
else
gcc_checking_assert (TREE_TYPE (ve) == type);
SET_DECL_VALUE_EXPR (r, ve);
--- gcc/testsuite/g++.dg/gomp/pr95063.C.jj 2020-05-11 19:35:30.680174343
+0200
+++ gcc/testsuite/g++.dg/gomp/pr95063.C 2020-05-11 19:34:53.138731112 +0200
@@ -0,0 +1,24 @@
+// PR c++/95063
+
+template
+struct S {
+ T a : 12;
+ S () : a(0)
+ {
+#pragma omp for linear(a)
+for (int k = 0; k < 64; ++k)
+ a++;
+ }
+};
+struct U {
+ int a : 12;
+ U () : a(0)
+ {
+#pragma omp for linear(a)
+for (int k = 0; k < 64; ++k)
+ a++;
+ }
+};
+
+S s;
+U u;
Jakub
[committed] openmp: Implement discovery of implicit declare target to clauses
Hi!
This attempts to implement what the OpenMP 5.0 spec in declare target section
says as ammended by the 5.1 changes so far (related to device_type(host)),
except
that it doesn't have the device(ancestor: ...) handling yet because we do not
support it yet, and I've left so far out the except lambda note, because I need
that clarified.
Bootstrapped/regtested on x86_64-linux and i686-linux and also tested with
x86_64-linux -> nvptx-none offloading, committed to trunk.
2020-05-12 Jakub Jelinek
* omp-offload.h (omp_discover_implicit_declare_target): Declare.
* omp-offload.c: Include context.h.
(omp_declare_target_fn_p, omp_declare_target_var_p,
omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
omp_discover_implicit_declare_target): New functions.
* cgraphunit.c (analyze_functions): Call
omp_discover_implicit_declare_target.
* testsuite/libgomp.c/target-39.c: New test.
--- gcc/omp-offload.h.jj2020-01-15 11:05:19.315140331 +0100
+++ gcc/omp-offload.h 2020-05-11 19:45:04.752660397 +0200
@@ -30,5 +30,6 @@ extern GTY(()) vec *offload
extern GTY(()) vec *offload_vars;
extern void omp_finish_file (void);
+extern void omp_discover_implicit_declare_target (void);
#endif /* GCC_OMP_DEVICE_H */
--- gcc/omp-offload.c.jj2020-05-11 18:33:23.032680781 +0200
+++ gcc/omp-offload.c 2020-05-11 20:04:19.473126701 +0200
@@ -52,6 +52,7 @@ along with GCC; see the file COPYING3.
#include "stringpool.h"
#include "attribs.h"
#include "cfgloop.h"
+#include "context.h"
/* Describe the OpenACC looping structure of a function. The entire
function is held in a 'NULL' loop. */
@@ -158,6 +159,138 @@ add_decls_addresses_to_decl_constructor
}
}
+/* Return true if DECL is a function for which its references should be
+ analyzed. */
+
+static bool
+omp_declare_target_fn_p (tree decl)
+{
+ return (TREE_CODE (decl) == FUNCTION_DECL
+ && lookup_attribute ("omp declare target", DECL_ATTRIBUTES (decl))
+ && !lookup_attribute ("omp declare target host",
+ DECL_ATTRIBUTES (decl))
+ && (!flag_openacc
+ || oacc_get_fn_attrib (decl) == NULL_TREE));
+}
+
+/* Return true if DECL Is a variable for which its initializer references
+ should be analyzed. */
+
+static bool
+omp_declare_target_var_p (tree decl)
+{
+ return (VAR_P (decl)
+ && lookup_attribute ("omp declare target", DECL_ATTRIBUTES (decl))
+ && !lookup_attribute ("omp declare target link",
+ DECL_ATTRIBUTES (decl)));
+}
+
+/* Helper function for omp_discover_implicit_declare_target, called through
+ walk_tree. Mark referenced FUNCTION_DECLs implicitly as
+ declare target to. */
+
+static tree
+omp_discover_declare_target_fn_r (tree *tp, int *walk_subtrees, void *data)
+{
+ if (TREE_CODE (*tp) == FUNCTION_DECL
+ && !omp_declare_target_fn_p (*tp)
+ && !lookup_attribute ("omp declare target host", DECL_ATTRIBUTES (*tp)))
+{
+ tree id = get_identifier ("omp declare target");
+ if (!DECL_EXTERNAL (*tp) && DECL_SAVED_TREE (*tp))
+ ((vec *) data)->safe_push (*tp);
+ DECL_ATTRIBUTES (*tp) = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (*tp));
+ symtab_node *node = symtab_node::get (*tp);
+ if (node != NULL)
+ {
+ node->offloadable = 1;
+ if (ENABLE_OFFLOADING)
+ g->have_offload = true;
+ }
+}
+ else if (TYPE_P (*tp))
+*walk_subtrees = 0;
+ /* else if (TREE_CODE (*tp) == OMP_TARGET)
+ {
+if (tree dev = omp_find_clause (OMP_TARGET_CLAUSES (*tp)))
+ if (OMP_DEVICE_ANCESTOR (dev))
+*walk_subtrees = 0;
+ } */
+ return NULL_TREE;
+}
+
+/* Helper function for omp_discover_implicit_declare_target, called through
+ walk_tree. Mark referenced FUNCTION_DECLs implicitly as
+ declare target to. */
+
+static tree
+omp_discover_declare_target_var_r (tree *tp, int *walk_subtrees, void *data)
+{
+ if (TREE_CODE (*tp) == FUNCTION_DECL)
+return omp_discover_declare_target_fn_r (tp, walk_subtrees, data);
+ else if (VAR_P (*tp)
+ && is_global_var (*tp)
+ && !omp_declare_target_var_p (*tp))
+{
+ tree id = get_identifier ("omp declare target");
+ if (lookup_attribute ("omp declare target link", DECL_ATTRIBUTES (*tp)))
+ {
+ error_at (DECL_SOURCE_LOCATION (*tp),
+ "%qD specified both in declare target % and "
+ "implicitly in % clauses", *tp);
+ DECL_ATTRIBUTES (*tp)
+ = remove_attribute ("omp declare target link", DECL_ATTRIBUTES
(*tp));
+ }
+ if (TREE_STATIC (*tp) && DECL_INITIAL (*tp))
+ ((vec *) data)->safe_push (*tp);
+ DECL_ATTRIBUTES (*tp) = tree_cons (id, NULL_TREE, DECL_ATTRIBUTES (*tp));
+ symtab_node *node = symtab_node::get (*tp);
+ if (node != NULL && !node->offloadable)
+ {
+
Re: [PATCH] ASAN: do not rewrite param for DECL_NOT_GIMPLE_REG_P.
On Tue, May 12, 2020 at 9:04 AM Martin Liška wrote: > > On 5/11/20 2:44 PM, Richard Biener wrote: > > Hmm, I think the fix is to clear DECL_NOT_GIMPLE_REG_P instead > > where the code clears TREE_ADDRESSABLE of 'arg' > > Ah, you are right. There's a patch that I've just tested. > > Patch can bootstrap on x86_64-linux-gnu and survives regression tests. > > Ready to be installed? OK. Richard. > Thanks, > Martin
Re: [C++] EOF has a location
On Fri, May 08, 2020 at 11:48:34AM -0400, Nathan Sidwell wrote:
> 2020-05-08 Nathan Sidwell
>
> gcc/cp/
> * parser.c (cp_lexer_set_source_position_from_token): EOF has a
> location too.
This change:
> --- c/gcc/cp/parser.c
> +++ w/gcc/cp/parser.c
> @@ -895,10 +895,7 @@ cp_lexer_get_preprocessor_token (cp_lexer *lexer,
> cp_token *token)
> static inline void
> cp_lexer_set_source_position_from_token (cp_token *token)
> {
> - if (token->type != CPP_EOF)
> -{
> - input_location = token->location;
> -}
> + input_location = token->location;
> }
>
> /* Update the globals input_location and the input file stack from LEXER. */
seems to have regressed:
+FAIL: obj-c++.dg/syntax-error-10.mm -fgnu-runtime (test for errors, line 1)
+FAIL: obj-c++.dg/syntax-error-10.mm -fgnu-runtime (test for excess errors)
+FAIL: obj-c++.dg/syntax-error-8.mm -fgnu-runtime (test for errors, line 1)
+FAIL: obj-c++.dg/syntax-error-8.mm -fgnu-runtime (test for excess errors)
+FAIL: obj-c++.dg/syntax-error-9.mm -fgnu-runtime (test for errors, line 2)
+FAIL: obj-c++.dg/syntax-error-9.mm -fgnu-runtime (test for excess errors)
+FAIL: obj-c++.dg/property/property-neg-6.mm -fgnu-runtime (test for errors,
line 8)
+FAIL: obj-c++.dg/property/property-neg-6.mm -fgnu-runtime (test for excess
errors)
E.g. on syntax-error-8.mm, cc1objplus used to emit:
syntax-error-8.mm:1:12: error: expected ‘@end’ at end of input
1 | @interface A /* { dg-error "expected ..end." } */
|^
and now it emits:
syntax-error-8.mm:1: error: expected ‘@end’ at end of input
1 | @interface A /* { dg-error "expected ..end." } */
|
instead (no column at all).
Jakub
Re: [PATCH] ASAN: do not rewrite param for DECL_NOT_GIMPLE_REG_P.
On 5/11/20 2:44 PM, Richard Biener wrote:
Hmm, I think the fix is to clear DECL_NOT_GIMPLE_REG_P instead
where the code clears TREE_ADDRESSABLE of 'arg'
Ah, you are right. There's a patch that I've just tested.
Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
Ready to be installed?
Thanks,
Martin
>From d321e69665a930ef8f10d27db16a8e1200326a1c Mon Sep 17 00:00:00 2001
From: Martin Liska
Date: Mon, 11 May 2020 11:11:17 +0200
Subject: [PATCH] ASAN: clear DECL_NOT_GIMPLE_REG_P.
gcc/ChangeLog:
2020-05-11 Martin Liska
PR sanitizer/95033
PR sanitizer/95051
* sanopt.c (sanitize_rewrite_addressable_params):
Clear DECL_NOT_GIMPLE_REG_P for argument.
gcc/testsuite/ChangeLog:
2020-05-11 Martin Liska
PR sanitizer/95033
PR sanitizer/95051
* g++.dg/asan/function-argument-4.C: New test.
* gcc.dg/asan/pr95033.c: New test.
* gcc.dg/asan/pr95051.c: New test.
---
gcc/sanopt.c | 1 +
.../g++.dg/asan/function-argument-4.C | 26 +++
gcc/testsuite/gcc.dg/asan/pr95033.c | 13 ++
gcc/testsuite/gcc.dg/asan/pr95051.c | 22
4 files changed, 62 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/asan/function-argument-4.C
create mode 100644 gcc/testsuite/gcc.dg/asan/pr95033.c
create mode 100644 gcc/testsuite/gcc.dg/asan/pr95051.c
diff --git a/gcc/sanopt.c b/gcc/sanopt.c
index 86180e32c7e..6c3bce92378 100644
--- a/gcc/sanopt.c
+++ b/gcc/sanopt.c
@@ -1158,6 +1158,7 @@ sanitize_rewrite_addressable_params (function *fun)
&& TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
{
TREE_ADDRESSABLE (arg) = 0;
+ DECL_NOT_GIMPLE_REG_P (arg) = 0;
/* The parameter is no longer addressable. */
has_any_addressable_param = true;
diff --git a/gcc/testsuite/g++.dg/asan/function-argument-4.C b/gcc/testsuite/g++.dg/asan/function-argument-4.C
new file mode 100644
index 000..cec1f1d788f
--- /dev/null
+++ b/gcc/testsuite/g++.dg/asan/function-argument-4.C
@@ -0,0 +1,26 @@
+// { dg-do run }
+// { dg-shouldfail "asan" }
+
+#include
+
+static __attribute__ ((noinline)) long double
+goo (long double _Complex *a)
+{
+ return crealf(*(volatile _Complex long double *)a);
+}
+
+__attribute__ ((noinline)) float
+foo (float _Complex arg)
+{
+ return goo ((long double _Complex *));
+}
+
+int
+main ()
+{
+ return foo (3 + 2 * I);
+}
+
+// { dg-output "ERROR: AddressSanitizer: stack-buffer-overflow on address.*(\n|\r\n|\r)" }
+// { dg-output "READ of size \[0-9\]* at.*" }
+// { dg-output ".*'arg' \\(line 13\\) <== Memory access at offset \[0-9\]* partially overflows this variable.*" }
diff --git a/gcc/testsuite/gcc.dg/asan/pr95033.c b/gcc/testsuite/gcc.dg/asan/pr95033.c
new file mode 100644
index 000..1228b7edcdb
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/asan/pr95033.c
@@ -0,0 +1,13 @@
+/* PR sanitizer/95033 */
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=address" } */
+
+struct a
+{
+ int b;
+};
+
+struct a c(_Complex d)
+{
+ return *(struct a *)
+}
diff --git a/gcc/testsuite/gcc.dg/asan/pr95051.c b/gcc/testsuite/gcc.dg/asan/pr95051.c
new file mode 100644
index 000..ec41a831299
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/asan/pr95051.c
@@ -0,0 +1,22 @@
+/* PR sanitizer/95051 */
+/* { dg-do compile } */
+/* { dg-options "-fsanitize=kernel-address --param=asan-stack=1 -O2" } */
+
+struct a {
+ struct {
+struct {
+ int b;
+} c;
+ };
+};
+struct d {
+ struct {
+int e;
+ } f;
+}
+
+g(int h) {
+ struct a *i;
+ struct d *j = (struct d*)
+ i->c.b = j->f.e;
+}
--
2.26.2
[PATCH v2] Fold (add -1; zero_ext; add +1) operations to zero_ext when not overflow (PR37451, part of PR61837)
Minor refine of checking iterations nonoverflow and a testcase for stage 1.
This "subtract/extend/add" existed for a long time and still annoying us
(PR37451, part of PR61837) when converting from 32bits to 64bits, as the ctr
register is used as 64bits on powerpc64, Andraw Pinski had a patch but
caused some issue and reverted by Joseph S. Myers(PR37451, PR37782).
Andraw:
http://gcc.gnu.org/ml/gcc-patches/2008-09/msg01070.html
http://gcc.gnu.org/ml/gcc-patches/2008-10/msg01321.html
Joseph:
https://gcc.gnu.org/legacy-ml/gcc-patches/2011-11/msg02405.html
We can do the simplification from "subtract/extend/add" to only extend
when loop iterations is known to be LT than MODE_MAX-1(NOT do simplify
when counter+0x1 overflow).
Bootstrap and regression tested pass on Power8-LE.
gcc/ChangeLog
2020-05-12 Xiong Hu Luo
PR rtl-optimization/37451, part of PR target/61837
* loop-doloop.c (doloop_modify): Simplify (add -1; zero_ext; add +1)
to zero_ext when not wrapping overflow.
gcc/testsuite/ChangeLog
2020-05-12 Xiong Hu Luo
PR rtl-optimization/37451, part of PR target/61837
* gcc.target/powerpc/doloop-2.c: New test.
---
gcc/loop-doloop.c | 46 -
gcc/testsuite/gcc.target/powerpc/doloop-2.c | 14 +++
2 files changed, 59 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/doloop-2.c
diff --git a/gcc/loop-doloop.c b/gcc/loop-doloop.c
index db6a014e43d..16372382a22 100644
--- a/gcc/loop-doloop.c
+++ b/gcc/loop-doloop.c
@@ -477,7 +477,51 @@ doloop_modify (class loop *loop, class niter_desc *desc,
}
if (increment_count)
-count = simplify_gen_binary (PLUS, mode, count, const1_rtx);
+{
+ /* Fold (add -1; zero_ext; add +1) operations to zero_ext. i.e:
+
+73: r145:SI=r123:DI#0-0x1
+74: r144:DI=zero_extend (r145:SI)
+75: r143:DI=r144:DI+0x1
+...
+31: r135:CC=cmp (r123:DI,0)
+72: {pc={(r143:DI!=0x1)?L70:pc};r143:DI=r143:DI-0x1;clobber
+scratch;clobber scratch;}
+
+r123:DI#0-0x1 is param count derived from loop->niter_expr equal to the
+loop iterations, if loop iterations expression doesn't overflow, then
+(zero_extend (r123:DI#0-1))+1 could be simplified to zero_extend only.
+ */
+ bool simplify_zext = false;
+ rtx extop0 = XEXP (count, 0);
+ if (GET_CODE (count) == ZERO_EXTEND && GET_CODE (extop0) == PLUS)
+ {
+ rtx addop0 = XEXP (extop0, 0);
+ rtx addop1 = XEXP (extop0, 1);
+
+ int nonoverflow = 0;
+ unsigned int_mode
+ = GET_MODE_PRECISION (as_a GET_MODE (addop0));
+ unsigned HOST_WIDE_INT int_mode_max
+ = (HOST_WIDE_INT_1U << (int_mode - 1) << 1) - 1;
+ if (get_max_loop_iterations (loop, )
+ && wi::ltu_p (iterations, int_mode_max))
+ nonoverflow = 1;
+
+ if (nonoverflow
+ && CONST_SCALAR_INT_P (addop1)
+ && GET_MODE_PRECISION (mode) == int_mode * 2
+ && addop1 == GEN_INT (-1))
+ {
+ count = simplify_gen_unary (ZERO_EXTEND, mode, addop0,
+ GET_MODE (addop0));
+ simplify_zext = true;
+ }
+ }
+
+ if (!simplify_zext)
+ count = simplify_gen_binary (PLUS, mode, count, const1_rtx);
+}
/* Insert initialization of the count register into the loop header. */
start_sequence ();
diff --git a/gcc/testsuite/gcc.target/powerpc/doloop-2.c
b/gcc/testsuite/gcc.target/powerpc/doloop-2.c
new file mode 100644
index 000..dc8516bb0ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/doloop-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2 -fno-unroll-loops" } */
+
+int f(int l, int *a)
+{
+int i;
+ for(i = 0;i < l; i++)
+ a[i] = i;
+return l;
+}
+
+/* { dg-final { scan-assembler-not "-1" } } */
+/* { dg-final { scan-assembler "bdnz" } } */
+/* { dg-final { scan-assembler-times "mtctr" 1 } } */
--
2.21.0.777.g83232e3864
[PATCH] preserve EDGE_DFS_BACK across split_edge
This moves EDGE_DFS_BACK to the appropriate edge when the split
edge had it set.
Bootstrap & regtest running on x86_64-unknown-linux-gnu.
2020-05-12 Richard Biener
* cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
---
gcc/cfghooks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/gcc/cfghooks.c b/gcc/cfghooks.c
index ea558b46947..71c6b63ad3b 100644
--- a/gcc/cfghooks.c
+++ b/gcc/cfghooks.c
@@ -640,6 +640,7 @@ split_edge (edge e)
profile_count count = e->count ();
edge f;
bool irr = (e->flags & EDGE_IRREDUCIBLE_LOOP) != 0;
+ bool back = (e->flags & EDGE_DFS_BACK) != 0;
class loop *loop;
basic_block src = e->src, dest = e->dest;
@@ -659,6 +660,11 @@ split_edge (edge e)
single_pred_edge (ret)->flags |= EDGE_IRREDUCIBLE_LOOP;
single_succ_edge (ret)->flags |= EDGE_IRREDUCIBLE_LOOP;
}
+ if (back)
+{
+ single_pred_edge (ret)->flags &= ~EDGE_DFS_BACK;
+ single_succ_edge (ret)->flags |= EDGE_DFS_BACK;
+}
if (dom_info_available_p (CDI_DOMINATORS))
set_immediate_dominator (CDI_DOMINATORS, ret, single_pred (ret));
--
2.16.4
[PATCH] tree-optimization/95045 - fix SM with exit exiting multiple loops
Since we apply SM to an edge which exits multiple loops we have
to make sure to commit insertions on it immediately since otherwise
store order is not preserved.
The testcase was committed with yesterdays fix, the bug was still
latent (with careful -fdbgcnt=lim you could still trigger it).
Bootstrapped / tested on x86_64-unknown-linux-gnu, applied.
Richard.
2020-05-11 Richard Biener
PR tree-optimization/95045
* dbgcnt.def (lim): Add debug-counter.
* tree-ssa-loop-im.c: Include dbgcnt.h.
(find_refs_for_sm): Use lim debug counter for store motion
candidates.
(do_store_motion): Rename form store_motion. Commit edge
insertions...
(store_motion_loop): ... here.
(tree_ssa_lim): Adjust.
---
gcc/dbgcnt.def | 1 +
gcc/tree-ssa-loop-im.c | 15 ++-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/gcc/dbgcnt.def b/gcc/dbgcnt.def
index 232b1928983..3998c9636aa 100644
--- a/gcc/dbgcnt.def
+++ b/gcc/dbgcnt.def
@@ -174,6 +174,7 @@ DEBUG_COUNTER (ipa_sra_params)
DEBUG_COUNTER (ipa_sra_retvalues)
DEBUG_COUNTER (ira_move)
DEBUG_COUNTER (ivopts_loop)
+DEBUG_COUNTER (lim)
DEBUG_COUNTER (local_alloc_for_sched)
DEBUG_COUNTER (match)
DEBUG_COUNTER (merged_ipa_icf)
diff --git a/gcc/tree-ssa-loop-im.c b/gcc/tree-ssa-loop-im.c
index bb78dfb2ce8..0d77aaa08a5 100644
--- a/gcc/tree-ssa-loop-im.c
+++ b/gcc/tree-ssa-loop-im.c
@@ -47,6 +47,7 @@ along with GCC; see the file COPYING3. If not see
#include "alias.h"
#include "builtins.h"
#include "tree-dfa.h"
+#include "dbgcnt.h"
/* TODO: Support for predicated code motion. I.e.
@@ -2862,7 +2863,7 @@ find_refs_for_sm (class loop *loop, bitmap sm_executed,
bitmap refs_to_sm)
EXECUTE_IF_AND_COMPL_IN_BITMAP (refs, sm_executed, 0, i, bi)
{
ref = memory_accesses.refs_list[i];
- if (can_sm_ref_p (loop, ref))
+ if (can_sm_ref_p (loop, ref) && dbg_cnt (lim))
bitmap_set_bit (refs_to_sm, i);
}
}
@@ -2900,7 +2901,12 @@ store_motion_loop (class loop *loop, bitmap sm_executed)
{
find_refs_for_sm (loop, sm_executed, sm_in_loop);
if (!bitmap_empty_p (sm_in_loop))
- hoist_memory_references (loop, sm_in_loop, exits);
+ {
+ hoist_memory_references (loop, sm_in_loop, exits);
+ /* Commit edge inserts here to preserve the order of stores
+when an exit exits multiple loops. */
+ gsi_commit_edge_inserts ();
+ }
}
exits.release ();
@@ -2915,7 +2921,7 @@ store_motion_loop (class loop *loop, bitmap sm_executed)
loops. */
static void
-store_motion (void)
+do_store_motion (void)
{
class loop *loop;
bitmap sm_executed = BITMAP_ALLOC (_bitmap_obstack);
@@ -2924,7 +2930,6 @@ store_motion (void)
store_motion_loop (loop, sm_executed);
BITMAP_FREE (sm_executed);
- gsi_commit_edge_inserts ();
}
/* Fills ALWAYS_EXECUTED_IN information for basic blocks of LOOP, i.e.
@@ -3141,7 +3146,7 @@ tree_ssa_lim (void)
/* Execute store motion. Force the necessary invariants to be moved
out of the loops as well. */
- store_motion ();
+ do_store_motion ();
/* Move the expressions that are expensive enough. */
todo = move_computations ();
--
2.25.1
Re: [RFC PATCH] i386: Add V2SFmode FMA insn patterns [PR95046]
On Tue, May 12, 2020 at 7:57 AM Richard Biener wrote: > > On Mon, 11 May 2020, Uros Bizjak wrote: > > > Attached patch implements V2SFmode FMA insn patterns. Patched compiler > > vectorizes FMA, FMS and FNMA instructions, but for some reason fails > > to vectorize FNMS. > > > > I have double checked that the insn pattern is correct, and now I'm > > all out of ideas what could be wrong with the pattern, still ignored > > by the vectorizer. -fno-vect-cost-model does not help so it's time to > > ask the experts... > > Do you have negate patterns for V2SFmode? The vectorizer sees > decomposed ops and only the vectorized operations are later formed > into FMAs. No, not yet. I'll add V2SF absneg next; they require some surgery in ix86_expand_fp_absneg_operator, so I left them for "later. Thanks, Uros.
