[PATCH] Objective-C: fix protocol list count type (pertinent to non-LP64)

[Matt Jacobson via Gcc-patches]

Fix protocol list layout for non-LP64.  clang and objc4 both give the `count` 
field as `long`, not `intptr_t`.  Those are the same on LP64, but not 
everywhere.  For non-LP64, this fixes binary compatibility with clang-built 
classes.

This was more complicated than I anticipated, because the relevant frontend 
code in fact had no AST type for `protocol_list_t`, instead emitting protocol 
lists as `protocol_t[]`, with the zeroth element actually being the integer 
count.  That made it nontrivial to change the count to `long`.  With this 
change, there is now a true `protocol_list_t` type in the AST.

Tested multiple ways.  On x86_64/Darwin, I confirmed with a test program that 
protocol conformances by classes, categories, and protocols works.  On AVR, I 
manually inspected the generated assembly to confirm that protocol lists gain 
an extra two bytes of `count`, matching clang.

Thank you for your time.




gcc/objc/ChangeLog:

2021-09-26  Matt Jacobson  

* objc-next-runtime-abi-02.c (enum objc_v2_tree_index): Add new global 
tree.
(static void next_runtime_02_initialize): Initialize protocol list type 
tree.
(struct class_ro_t): Fix type misspelling.
(build_v2_class_templates): Correct type in field declaration.
(build_v2_protocol_templates): Create actual protocol list type tree.
(build_v2_category_template): Correct type in field declaration.
(generate_v2_protocol_list): Emit protocol list count as `long`.
(generate_v2_protocols): Use correct type.
(build_v2_category_initializer): Use correct type.
(build_v2_class_ro_t_initializer): Use correct type.


diff --git a/gcc/objc/objc-next-runtime-abi-02.c 
b/gcc/objc/objc-next-runtime-abi-02.c
index c3af369ff0d..aadf1741676 100644
--- a/gcc/objc/objc-next-runtime-abi-02.c
+++ b/gcc/objc/objc-next-runtime-abi-02.c
@@ -92,6 +92,7 @@ enum objc_v2_tree_index
   OCTI_V2_CAT_TEMPL,
   OCTI_V2_CLS_RO_TEMPL,
   OCTI_V2_PROTO_TEMPL,
+  OCTI_V2_PROTO_LIST_TEMPL,
   OCTI_V2_IVAR_TEMPL,
   OCTI_V2_IVAR_LIST_TEMPL,
   OCTI_V2_MESSAGE_REF_TEMPL,
@@ -130,6 +131,8 @@ enum objc_v2_tree_index
objc_v2_global_trees[OCTI_V2_CAT_TEMPL]
 #define objc_v2_protocol_template \
objc_v2_global_trees[OCTI_V2_PROTO_TEMPL]
+#define objc_v2_protocol_list_template \
+   objc_v2_global_trees[OCTI_V2_PROTO_LIST_TEMPL]
 
 /* struct message_ref_t */
 #define objc_v2_message_ref_template \
@@ -196,7 +199,7 @@ static void build_v2_message_ref_templates (void);
 static void build_v2_class_templates (void);
 static void build_v2_super_template (void);
 static void build_v2_category_template (void);
-static void build_v2_protocol_template (void);
+static void build_v2_protocol_templates (void);
 
 static tree next_runtime_abi_02_super_superclassfield_id (void);
 
@@ -394,9 +397,9 @@ static void next_runtime_02_initialize (void)
build_pointer_type (xref_tag (RECORD_TYPE,
get_identifier ("_prop_list_t")));
 
+  build_v2_protocol_templates ();
   build_v2_class_templates ();
   build_v2_super_template ();
-  build_v2_protocol_template ();
   build_v2_category_template ();
 
   bool fixup_p = flag_next_runtime < USE_FIXUP_BEFORE;
@@ -636,7 +639,7 @@ struct class_ro_t
 const uint8_t * const ivarLayout;
 const char *const name;
 const struct method_list_t * const baseMethods;
-const struct objc_protocol_list *const baseProtocols;
+const struct protocol_list_t *const baseProtocols;
 const struct ivar_list_t *const ivars;
 const uint8_t * const weakIvarLayout;
 const struct _prop_list_t * const properties;
@@ -685,11 +688,9 @@ build_v2_class_templates (void)
   /* const struct method_list_t * const baseMethods; */
   add_field_decl (objc_method_list_ptr, "baseMethods", );
 
-  /* const struct objc_protocol_list *const baseProtocols; */
-  add_field_decl (build_pointer_type
-   (xref_tag (RECORD_TYPE,
-  get_identifier (UTAG_V2_PROTOCOL_LIST))),
- "baseProtocols", );
+  /* const struct protocol_list_t *const baseProtocols; */
+  add_field_decl (build_pointer_type (objc_v2_protocol_list_template),
+ "baseProtocols", );
 
   /* const struct ivar_list_t *const ivars; */
   add_field_decl (objc_v2_ivar_list_ptr, "ivars", );
@@ -763,25 +764,33 @@ build_v2_super_template (void)
  const char ** extended_method_types;
  const char * demangled_name;
  const struct _prop_list_t * class_properties;
-   }
+  };
+
+  struct protocol_list_t
+  {
+long count;
+struct protocol_t protocols[];
+  };
 */
 static void
-build_v2_protocol_template (void)
+build_v2_protocol_templates (void)
 {
-  tree decls, *chain = NULL;
+  tree decls, protolist_pointer_type, 

Re: *PING* [PATCH] c++: fix cases of core1001/1322 by not dropping cv-qualifier of function parameter of type of typename or decltype[PR101402,PR102033,PR102034,PR102039,PR102044]

[nick huang via Gcc-patches]

>>template 
>>struct A
>>{
>>   void f(T);
>>};
>>
>>template 
>>void A::f(const T)
>>{ }
>>
>>which is certainly questionable code, but is currently also accepted by 
>>clang and EDG compilers.

I just found out that clang actually correctly reject this code during 
specialization. 
(https://www.godbolt.org/z/evjvhqqoo)
It all depends on explicit argument which may turn "const" into 
top-level-cv-qualifier
or not.
For example, when argument is "int[3]", the function signature of 
specialization 
will have to keep the const because it is no longer top-level cv qualifier.

template<>
void A::f(const int*){} // not matching declaration "void(int*)"

Obviously when explicit argument is "int", the const would be dropped and 
specialization matches
declaration. i.e.
template<>
void A::f(int){} // this matches declaration "void(int)"

So, clang is correct to NOT reject template definition when there is no 
specialization yet.

As a comparison, GCC is not able to reject  incorrect specialization. Should we 
file this bug? Or just add this 
as test case to original 1001 core issue?

Again, my patch cannot deal this case as it is not "typename". We may have to 
fix "tsubst_function_decl" to see any workaround of line 
"SET_DECL_IMPLICIT_INSTANTIATION (r);" 
(See my previous email 
https://gcc.gnu.org/pipermail/gcc-patches/2021-September/580260.html)
This macro "DECL_USE_TEMPLATE" is set to 1. However, the comment says "1" is 
for "implicit specialization", but we are actually dealing with "partial or 
explicit specialization" which is "2".

Here I quote comment from cp-tree.h

/* Nonzero iff NODE is a specialization of a template.  The value
   indicates the type of specializations:

 1=implicit instantiation

 2=partial or explicit specialization, e.g.:

template <> int min (int, int),

 3=explicit instantiation, e.g.:

template int min (int, int);

   Note that NODE will be marked as a specialization even if the
   template it is instantiating is not a primary template.  For
   example, given:

 template  struct O {
   void f();
   struct I {};
 };

   both O::f and O::I will be marked as instantiations.

   If DECL_USE_TEMPLATE is nonzero, then DECL_TEMPLATE_INFO will also
   be non-NULL.  */

Re: [PATCH] c++: Suppress error when cv-qualified reference is introduced by typedef [PR101783]

[nick huang via Gcc-patches]

Hi Jason,

1. Thank you very much for your detailed comments for my patch and I really 
appreciate it! Here is my revised patch:

The root cause of this bug is that it considers reference with
cv-qualifiers as an error by generating value for variable "bad_quals".
However, this is not correct for case of typedef. Here I quote spec:
"Cv-qualified references are ill-formed except when the cv-qualifiers
are introduced through the use of a typedef-name ([dcl.typedef],
[temp.param]) or decltype-specifier ([dcl.type.decltype]),
in which case the cv-qualifiers are ignored."

2021-09-25  qingzhe huang  

gcc/cp/
PR c++/101783
* tree.c (cp_build_qualified_type_real):

gcc/testsuite/
PR c++/101783
* g++.dg/parse/pr101783.C: New test.
-- next part --
diff --git a/gcc/cp/tree.c b/gcc/cp/tree.c
index 8840932dba2..d5c8daeb340 100644
--- a/gcc/cp/tree.c
+++ b/gcc/cp/tree.c
@@ -1356,11 +1356,18 @@ cp_build_qualified_type_real (tree type,
   /* A reference or method type shall not be cv-qualified.
  [dcl.ref], [dcl.fct].  This used to be an error, but as of DR 295
  (in CD1) we always ignore extra cv-quals on functions.  */
+
+  /* Cv-qualified references are ill-formed except when the cv-qualifiers
+ are introduced through the use of a typedef-name ([dcl.typedef],
+ [temp.param]) or decltype-specifier ([dcl.type.decltype]),
+ in which case the cv-qualifiers are ignored.
+   */
   if (type_quals & (TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE)
   && (TYPE_REF_P (type)
  || FUNC_OR_METHOD_TYPE_P (type)))
 {
-  if (TYPE_REF_P (type))
+  if (TYPE_REF_P (type)
+ && (!typedef_variant_p (type) || FUNC_OR_METHOD_TYPE_P (type)))
bad_quals |= type_quals & (TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE);
   type_quals &= ~(TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE);
 }
diff --git a/gcc/testsuite/g++.dg/parse/pr101783.C 
b/gcc/testsuite/g++.dg/parse/pr101783.C
new file mode 100644
index 000..4e0a435dd0b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/pr101783.C
@@ -0,0 +1,5 @@
+template struct A{
+typedef T& Type;
+};
+template void f(const typename A::Type){}
+template <> void f(const typename A::Type){}



2. 
> In Jonathan's earlier reply he asked how you tested the patch; this
> message still doesn't say anything about that.
I communicated with Mr. Jonathan in private email, worrying my naive question 
might pollute the public maillist. The following is major part of this 
communication and I attached original part in attachment. 

>>>How has this patch been tested? Have you bootstrapped the compiler and
>>>run the full testsuite?
Here is how I am doing:
a) build original 10.2.0 from scratch and make check to get both 
"testsuite/gcc/gcc.sum"
and "testsuite/g++/g++.sum".
b) apply my patch and build from scratch and make check to get both two files 
above.
c) compare two run's *.sum files to see if there is any difference. 

 (Later I realized there is tool  "contrib/compare_tests" is a good help of 
doing so.)

3. 
> What is the legal status of your contributions?
I thought small patch didn't require assignment. However, I just sent email to 
ass...@gnu.org to request assignment.
Alternatively, I am not sure if adding this "signoff" tag in submission will 
help?
Signed-off-by: qingzhe huang 


Thank you again!


> On 8/28/21 07:54, nick huang via Gcc-patches wrote:
> > Reference with cv-qualifiers should be ignored instead of causing an error
> > because standard accepts cv-qualified references introduced by typedef which
> > is ignored.
> > Therefore, the fix prevents GCC from reporting error by not setting variable
> > "bad_quals" in case the reference is introduced by typedef. Still the
> > cv-qualifier is silently ignored.
> > Here I quote spec (https://timsong-cpp.github.io/cppwp/dcl.ref#1):
> > "Cv-qualified references are ill-formed except when the cv-qualifiers
> > are introduced through the use of a typedef-name ([dcl.typedef],
> > [temp.param]) or decltype-specifier ([dcl.type.decltype]),
> > in which case the cv-qualifiers are ignored."
> >
> > PR c++/101783
> >
> > gcc/cp/ChangeLog:
> >
> > 2021-08-27  qingzhe huang  
> >
> > * tree.c (cp_build_qualified_type_real):
>
> The git commit verifier rejects this commit message with
>
> Checking 1fa0fbcdd15adf936ab4fae584f841beb35da1bb: FAILED ERR: missing
> description of a change:
> " * tree.c (cp_build_qualified_type_real):"
>
> (your initial patch had a description here, you just need to copy it over)
>
> ERR: PR 101783 in subject but not in changelog:
> "c++: Suppress error when cv-qualified reference is introduced by
> typedef [PR101783]"
>
> (the PR number needs to have a Tab before it)
>
> In Jonathan's earlier reply he asked how you tested the patch; this
> message still doesn't say anything about that.
>
> https://gcc.gnu.org/contribute.html#testing
>
> What is the legal status of your contributions?
>
> https://gcc.gnu.org/contribute.html#legal
>
> 

[PATCH] c-format: Add -Wformat-same-precision option [PR80060]

[Daniil Stas via Gcc-patches]

This option is enabled by default when -Wformat option is enabled. A
user can specify -Wno-format-same-precision to disable emitting
warnings about an argument passed to printf-like function having a
different type from the one specified in the format string if the
types precisions are the same.

Signed-off-by: Daniil Stas 

gcc/c-family/ChangeLog:

* c-format.c (check_format_types): Don't emit warnings about
type differences with the format string if
-Wno-format-same-precision is specified and the types have
the same precision.
* c.opt: Add -Wformat-same-precision option.

gcc/ChangeLog:

* doc/invoke.texi: Add -Wformat-same-precision option description.

gcc/testsuite/ChangeLog:

* c-c++-common/Wformat-same-precision-1.c: New test.
* c-c++-common/Wformat-same-precision-2.c: New test.
---
 gcc/c-family/c-format.c   | 2 +-
 gcc/c-family/c.opt| 5 +
 gcc/doc/invoke.texi   | 8 +++-
 gcc/testsuite/c-c++-common/Wformat-same-precision-1.c | 7 +++
 gcc/testsuite/c-c++-common/Wformat-same-precision-2.c | 7 +++
 5 files changed, 27 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/c-c++-common/Wformat-same-precision-1.c
 create mode 100644 gcc/testsuite/c-c++-common/Wformat-same-precision-2.c

diff --git a/gcc/c-family/c-format.c b/gcc/c-family/c-format.c
index b4cb765a9d3..07cdcefbef8 100644
--- a/gcc/c-family/c-format.c
+++ b/gcc/c-family/c-format.c
@@ -4243,7 +4243,7 @@ check_format_types (const substring_loc _loc,
  && (!pedantic || i < 2)
  && char_type_flag)
continue;
-  if (types->scalar_identity_flag
+  if ((types->scalar_identity_flag || !warn_format_same_precision)
  && (TREE_CODE (cur_type) == TREE_CODE (wanted_type)
  || (INTEGRAL_TYPE_P (cur_type)
  && INTEGRAL_TYPE_P (wanted_type)))
diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
index 9c151d19870..e7af7365c91 100644
--- a/gcc/c-family/c.opt
+++ b/gcc/c-family/c.opt
@@ -656,6 +656,11 @@ C ObjC C++ LTO ObjC++ Warning Alias(Wformat-overflow=, 1, 
0) IntegerRange(0, 2)
 Warn about function calls with format strings that write past the end
 of the destination region.  Same as -Wformat-overflow=1.
 
+Wformat-same-precision
+C ObjC C++ ObjC++ Var(warn_format_same_precision) Warning LangEnabledBy(C ObjC 
C++ ObjC++,Wformat=,warn_format >= 1, 0)
+Warn about type differences with the format string even if the types
+precision is the same.
+
 Wformat-security
 C ObjC C++ ObjC++ Var(warn_format_security) Warning LangEnabledBy(C ObjC C++ 
ObjC++,Wformat=, warn_format >= 2, 0)
 Warn about possible security problems with format functions.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ba98eab68a5..8833f257d75 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -347,7 +347,7 @@ Objective-C and Objective-C++ Dialects}.
 -Werror  -Werror=*  -Wexpansion-to-defined  -Wfatal-errors @gol
 -Wfloat-conversion  -Wfloat-equal  -Wformat  -Wformat=2 @gol
 -Wno-format-contains-nul  -Wno-format-extra-args  @gol
--Wformat-nonliteral  -Wformat-overflow=@var{n} @gol
+-Wformat-nonliteral  -Wformat-overflow=@var{n} -Wformat-same-precision @gol
 -Wformat-security  -Wformat-signedness  -Wformat-truncation=@var{n} @gol
 -Wformat-y2k  -Wframe-address @gol
 -Wframe-larger-than=@var{byte-size}  -Wno-free-nonheap-object @gol
@@ -6054,6 +6054,12 @@ If @option{-Wformat} is specified, also warn if the 
format string is not a
 string literal and so cannot be checked, unless the format function
 takes its format arguments as a @code{va_list}.
 
+@item -Wformat-same-precision
+@opindex Wformat-same-precision
+@opindex Wno-format-same-precision
+If @option{-Wformat} is specified, warn about type differences with the format
+string even if the types precision is the same.
+
 @item -Wformat-security
 @opindex Wformat-security
 @opindex Wno-format-security
diff --git a/gcc/testsuite/c-c++-common/Wformat-same-precision-1.c 
b/gcc/testsuite/c-c++-common/Wformat-same-precision-1.c
new file mode 100644
index 000..fbc11e4200a
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Wformat-same-precision-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-Wformat" } */
+
+void test ()
+{
+  __builtin_printf ("%lu\n", (long long) 1); /* { dg-warning "expects argument 
of type" } */
+}
diff --git a/gcc/testsuite/c-c++-common/Wformat-same-precision-2.c 
b/gcc/testsuite/c-c++-common/Wformat-same-precision-2.c
new file mode 100644
index 000..17e643e0441
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Wformat-same-precision-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-Wformat -Wno-format-same-precision" } */
+
+void test ()
+{
+  __builtin_printf ("%lu\n", (long long) 1); /* { ! dg-warning "expects 
argument of type" } */
+}
-- 
2.33.0

[RFC] Experimental __attribute__((saturating)) on integer types.

[Roger Sayle]

This patch is prototype proof-of-concept (and request for feedback)
that touches the front-end, middle-end and backend.  My recent patch to
perform RTL constant folding of saturating arithmetic revealed how
difficult it is to generate a (portable) test case for that functionality.
This patch experiments with adding an "saturating" attribute to the
C-family front-ends to set the TYPE_SATURATING flag on integer types,
initially as a debugging/testing tool for the middle-end.  GCC already
contains logic during RTL expansion to emit [us]s_plus and [us]s_minus
instructions via the standard named [us]ss{add,sub}3 optabs.

Disappointingly, although the documentation for ssplus3 patterns
implies this should work for arbitrary (i.e. integer) modes, the
optab querying infrastructure (based on optabs.def) is currently
limited to fixed-point modes.  Hence the patch below contains a
tweak to optabs.def.

With both of the above pieces in place, GCC can now generate an
ssaddsi3 instruction (such as the example provided for the nvptx
backend), or ICE if the required saturating operation doesn't exist,
as libgcc doesn't (yet) provide fall-back implementations for
saturating signed and unsigned arithmetic.

Sticking with the positive, the following code:

typedef int sat_int32 __attribute__ ((saturating));
int ssadd32(int x, int y) {
  sat_int32 t = (sat_int32)x + (sat_int32)y;
  return (int)t;
}

with this patch, now generates the following on nvptx-none:

mov.u32 %r23, %ar0;
mov.u32 %r24, %ar1;
add.sat.s32 %value, %r23, %r24;


Are any of the independent chunks below suitable for the compiler?
Tested on nvptx-none and x86_64-pc-linux-gnu, but nothing changes
unless __attribute__ ((saturating)) is explicitly added to the source
code [and I'd recommend against that except for testing purposes].

Eventually saturating arithmetic such as this might be useful for
kernel security (a hot topic of last week's Linux Plumbers' Conference)
but it would require a lot of polishing to clean-up the rough edges
(and ideally better hardware support).

Thoughts?  Even if a new C-family attribute is unsuitable, is my
logic/implementation in handle_saturating_attribute correct?


2021-09-26  Roger Sayle  

gcc/c-family/ChangeLog
* c-attribs (handle_saturating_attribute): New callback function
for a "saturating" attribute to set the TYPE_SATURATING flag on
an integer type.
(c_common_attribute_table): New entry for "saturating".

gcc/ChangeLog
* config/nvptx/nvptx.md (ssaddsi3, sssubsi3): New define_insn
patterns for SImode saturating addition/subtraction respectively.

* optabs.def (ssadd_optab, usadd_optab, ssub_optab, usub_optab):
Allow querying of integer modes in addition to fixed-point modes.

* print-tree.c (print_node): Output "saturating" when the
TYPE_SATURATING flag is set on integer types.

Roger
--

diff --git a/gcc/c-family/c-attribs.c b/gcc/c-family/c-attribs.c
index 007b928..cd58605 100644
--- a/gcc/c-family/c-attribs.c
+++ b/gcc/c-family/c-attribs.c
@@ -169,6 +169,7 @@ static tree handle_objc_nullability_attribute (tree *, 
tree, tree, int, bool *);
 static tree handle_signed_bool_precision_attribute (tree *, tree, tree, int,
bool *);
 static tree handle_retain_attribute (tree *, tree, tree, int, bool *);
+static tree handle_saturating_attribute (tree *, tree, tree, int, bool *);
 
 /* Helper to define attribute exclusions.  */
 #define ATTR_EXCL(name, function, type, variable)  \
@@ -536,6 +537,8 @@ const struct attribute_spec c_common_attribute_table[] =
  handle_special_var_sec_attribute, 
attr_section_exclusions },
   { "access",1, 3, false, true, true, false,
  handle_access_attribute, NULL },
+  { "saturating",0, 0, false, true, false, false,
+ handle_saturating_attribute, NULL },
   /* Attributes used by Objective-C.  */
   { "NSObject",  0, 0, true, false, false, false,
  handle_nsobject_attribute, NULL },
@@ -5761,6 +5764,27 @@ handle_objc_nullability_attribute (tree *node, tree 
name, tree args,
   return NULL_TREE;
 }
 
+/* Handle a "saturating" attribute.  */
+
+static tree
+handle_saturating_attribute (tree *node, tree name, tree ARG_UNUSED (args),
+int flags, bool *no_add_attrs)
+{
+  tree type = *node;
+
+  *no_add_attrs = true;
+
+  if (TREE_CODE (type) == INTEGER_TYPE)
+{
+  if (!(flags & (int) ATTR_FLAG_TYPE_IN_PLACE))
+   *node = type = build_duplicate_type (type);
+  TYPE_SATURATING (type) = 1;
+}
+  else
+warning (OPT_Wattributes,"saturating attribute on non-integer type");
+  return NULL_TREE;
+}
+
 /* Attempt to partially validate a single attribute ATTR as if
it were to be applied to an entity OPER.  */
 
diff --git a/gcc/config/nvptx/nvptx.md 

[RFC 6/7] Enable MIPS DSP rev3 ASE for nanoMIPS

[Dragan Mladjenovic via Gcc-patches]

gcc/ChangeLog:

* config/mips/mips-dsp.md (mips_bposge):
Output bposgec for TARGET_DSPR3.
* config/mips/mips.c (mips_output_move):
Use $ac0 for $lo if base isa doesn't have md registers.
(mips_option_override) [TARGET_DSPR3]:
Enable TARGET_DSP and TARGET_DSPR2.
(mips_conditional_register_usage) [ISA_HAS_DSP]:
Don't disable md registers.
* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS)
[TARGET_DSPR3]: Define __mips_dsp_rev=3 and __mips_dspr3.
(ASM_SPEC): Forward mdspr3 and mno-dspr3.
* config/mips/mips.md (mulsidi3_32bit):
Enable for ISA_HAS_DSP.
(mfhi_,
mthi_):
Use $ac0 for $lo if base isa doesn't have md registers.
* config/mips/mips.opt (mdspr3): New option.
Enabled for TARGET_NANOMIPS.
(mdspr2): Disabled for TARGET_NANOMIPS.

gcc/testsuite/ChangeLog:

* gcc.target/nanomips/dpaq_sa_l_w.c: New test.
* gcc.target/nanomips/dpsq_sa_l_w.c: New test.
* gcc.target/nanomips/dsp-ctrl.c: New test.
* gcc.target/nanomips/dsp-lhxs.c: New test.
* gcc.target/nanomips/dsp-no-lhx.c: New test.
* gcc.target/nanomips/fixed-scalar-type.c: New test.
* gcc.target/nanomips/fixed-vector-type.c: New test.
* gcc.target/nanomips/madd-4.c: New test.
* gcc.target/nanomips/maddu-3.c: New test.
* gcc.target/nanomips/maddu-4.c: New test.
* gcc.target/nanomips/mips-prepend-1.c: New test.
* gcc.target/nanomips/mips32-dsp-run.c: New test.
* gcc.target/nanomips/mips32-dspr2.c: New test.
* gcc.target/nanomips/msub-4.c: New test.
* gcc.target/nanomips/msubu-4.c: New test.
* gcc.target/nanomips/nanomips-dsp-accinit-2.c: New test.
* gcc.target/nanomips/nanomips-dsp.c: New test.
* gcc.target/nanomips/nanomips-dspr3-type-1.c: New test.
* gcc.target/nanomips/nanomips-dspr3-type-2.c: New test.
---
 gcc/config/mips/mips-dsp.md   |   17 +-
 gcc/config/mips/mips.c|   22 +-
 gcc/config/mips/mips.h|6 +
 gcc/config/mips/mips.md   |   12 +-
 gcc/config/mips/mips.opt  |6 +-
 .../gcc.target/nanomips/dpaq_sa_l_w.c (new)   |   51 +
 .../gcc.target/nanomips/dpsq_sa_l_w.c (new)   |   37 +
 .../gcc.target/nanomips/dsp-ctrl.c (new)  |   69 +
 .../gcc.target/nanomips/dsp-lhxs.c (new)  |   11 +
 .../gcc.target/nanomips/dsp-no-lhx.c (new)|   11 +
 .../nanomips/fixed-scalar-type.c (new)|  218 
 .../nanomips/fixed-vector-type.c (new)|  133 ++
 .../gcc.target/nanomips/madd-4.c (new)|   27 +
 .../gcc.target/nanomips/maddu-3.c (new)   |   30 +
 .../gcc.target/nanomips/maddu-4.c (new)   |   30 +
 .../nanomips/mips-prepend-1.c (new)   |8 +
 .../nanomips/mips32-dsp-run.c (new)   | 1063 +++
 .../gcc.target/nanomips/mips32-dspr2.c (new)  |  541 
 .../gcc.target/nanomips/msub-4.c (new)|   21 +
 .../gcc.target/nanomips/msubu-4.c (new)   |   24 +
 .../nanomips/nanomips-dsp-accinit-2.c (new)   |   23 +
 .../gcc.target/nanomips/nanomips-dsp.c (new)  | 1160 +
 .../nanomips/nanomips-dspr3-type-1.c (new)|   30 +
 .../nanomips/nanomips-dspr3-type-2.c (new)|   12 +
 24 files changed, 3552 insertions(+), 10 deletions(-)
 24 files changed, 3552 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dpaq_sa_l_w.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dpsq_sa_l_w.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dsp-ctrl.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dsp-lhxs.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dsp-no-lhx.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/fixed-scalar-type.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/fixed-vector-type.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/madd-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/maddu-3.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/maddu-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/mips-prepend-1.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/mips32-dsp-run.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/mips32-dspr2.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/msub-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/msubu-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dsp-accinit-2.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dsp.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dspr3-type-1.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dspr3-type-2.c

diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md
index 5a5694f3f9e..d71ad95aa40 100644
--- a/gcc/config/mips/mips-dsp.md
+++ b/gcc/config/mips/mips-dsp.md
@@ -1152,8 +1152,21 

[RFC 7/7] Add documentation for nanoMIPS

[Dragan Mladjenovic via Gcc-patches]

gcc/ChangeLog:

* doc/extend.texi: Add nanoMIPS Function Attributes,
nanoMIPS Built-in Functions and nanoMIPS DSP Built-in Functions.
* doc/invoke.texi: Add nanoMIPS Options.
* doc/md.texi: Add nanoMIPS constraints.
---
 gcc/doc/extend.texi | 124 +++
 gcc/doc/invoke.texi | 367 
 gcc/doc/md.texi |  71 +
 3 files changed, 562 insertions(+)
 3 files changed, 562 insertions(+)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 6d8b9856eea..5bfea4cd7b6 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -2484,6 +2484,7 @@ GCC plugins may provide their own attributes.
 * Microsoft Windows Function Attributes::
 * MIPS Function Attributes::
 * MSP430 Function Attributes::
+* nanoMIPS Function Attributes::
 * NDS32 Function Attributes::
 * Nios II Function Attributes::
 * Nvidia PTX Function Attributes::
@@ -5673,6 +5674,99 @@ options can help the packing, however, since they 
produce smaller,
 easier to pack regions.
 @end table
 
+@node nanoMIPS Function Attributes
+@subsection nanoMIPS Function Attributes
+
+These function attributes are supported by the nanoMIPS back end:
+
+@table @code
+@item cmodel ("@var{model}")
+@cindex @code{cmodel} function attribute, nanoMIPS
+Use this attribute to indicate what code should be generated for a particular
+code and data model for this function.  The behavior and permissible arguments
+are the same as for the command line option @option{-mcmodel=}.
+@end table
+
+@table @code
+@item interrupt
+@cindex @code{interrupt} function attribute, nanoMIPS
+Use this attribute to indicate that the specified function is an interrupt
+handler.  The compiler generates function entry and exit sequences suitable
+for use in an interrupt handler when this attribute is present.
+An optional argument is supported for the interrupt attribute which allows
+the interrupt mode to be described.  By default GCC assumes the external
+interrupt controller (EIC) mode is in use, this can be explicitly set using
+@code{eic}.  When interrupts are non-masked then the requested Interrupt
+Priority Level (IPL) is copied to the current IPL which has the effect of only
+enabling higher priority interrupts.  To use vectored interrupt mode use
+the argument @code{vector=[sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5]}, this will change
+the behavior of the non-masked interrupt support and GCC will arrange to mask
+all interrupts from sw0 up to and including the specified interrupt vector.
+
+You can use the following attributes to modify the behavior
+of an interrupt handler:
+@table @code
+@item use_shadow_register_set
+@cindex @code{use_shadow_register_set} function attribute, nanoMIPS
+Assume that the handler uses a shadow register set, instead of
+the main general-purpose registers.  An optional argument @code{intstack} is
+supported to indicate that the shadow register set contains a valid stack
+pointer.
+
+@item keep_interrupts_masked
+@cindex @code{keep_interrupts_masked} function attribute, nanoMIPS
+Keep interrupts masked for the whole function.  Without this attribute,
+GCC tries to reenable interrupts for as much of the function as it can.
+
+@item use_debug_exception_return
+@cindex @code{use_debug_exception_return} function attribute, nanoMIPS
+Return using the @code{deret} instruction.  Interrupt handlers that don't
+have this attribute return using @code{eret} instead.
+@end table
+
+You can use any combination of these attributes, as shown below:
+@smallexample
+void __attribute__ ((interrupt)) v0 ();
+void __attribute__ ((interrupt, use_shadow_register_set)) v1 ();
+void __attribute__ ((interrupt, keep_interrupts_masked)) v2 ();
+void __attribute__ ((interrupt, use_debug_exception_return)) v3 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ keep_interrupts_masked)) v4 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ use_debug_exception_return)) v5 ();
+void __attribute__ ((interrupt, keep_interrupts_masked,
+ use_debug_exception_return)) v6 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ keep_interrupts_masked,
+ use_debug_exception_return)) v7 ();
+void __attribute__ ((interrupt("eic"))) v8 ();
+void __attribute__ ((interrupt("vector=hw3"))) v9 ();
+@end smallexample
+
+@item long_call
+@itemx near
+@itemx far
+@cindex indirect calls, nanoMIPS
+@cindex @code{long_call} function attribute, nanoMIPS
+@cindex @code{near} function attribute, nanoMIPS
+@cindex @code{far} function attribute, nanoMIPS
+These attributes specify how a particular function is called on nanoMIPS@.
+The attributes override the @option{-mlong-calls} (@pxref{nanoMIPS Options})
+command-line switch.  The @code{long_call} and @code{far} attributes are
+synonyms, and cause the compiler to always call
+the function by first loading its address into a register, and then using

[RFC 5/7] Fix unhelpful messages for disabled options.

[Dragan Mladjenovic via Gcc-patches]

Firstly, the option handling was building suggestions without checking
if an option is disabled.  This could have caused other unhelpful
messages for other mistyped options.

Secondly, the key issue here appears to be the lack of CL_JOINED flag
for the false 'Condition' i.e. an option is disabled but other flags are
zeroed out too.  This caused find_opt() not to return the right index
to an option e.g. for -mabi= we would expect OPT_mabi_ rather than
OPT_SPECIAL_unknown, hence, the option did not appear to be correctly
marked as disabled.  The patch aims to retain the extra flag but to keep
an option as disabled.  I do not see any fallout with this, -m=
are now rejected on the command line and not printed with --target-help.

gcc/ChangeLog:

* opt-suggestions.c (option_proposer::build_option_suggestions):
Ignore disabled options.
* opts.c (print_filtered_help): Likewise.
* optc-gen.awk: Preserve flags in both cases.

gcc/testsuite/ChangeLog:

* gcc.target/nanomips/nanomips-err-mabi32.c: New test.
---
 gcc/opt-suggestions.c| 3 +++
 gcc/optc-gen.awk | 5 +++--
 gcc/opts.c   | 4 
 .../gcc.target/nanomips/nanomips-err-mabi32.c (new)  | 4 
 4 files changed, 14 insertions(+), 2 deletions(-)
 4 files changed, 14 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c

diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
index 5c36fc8cc8c..03bccd5379f 100644
--- a/gcc/opt-suggestions.c
+++ b/gcc/opt-suggestions.c
@@ -108,6 +108,9 @@ option_proposer::build_option_suggestions (const char 
*prefix)
   switch (i)
{
default:
+/* We don't want to suggest disabled options.  */
+if (option->cl_disabled)
+  continue;
  if (option->var_type == CLVC_ENUM)
{
  const struct cl_enum *e = _enums[option->var_enum];
diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
index 77e598efd60..eb725fdb8ce 100644
--- a/gcc/optc-gen.awk
+++ b/gcc/optc-gen.awk
@@ -412,10 +412,11 @@ for (i = 0; i < n_opts; i++) {
   "%s,\n" \
   "0, %s,\n" \
   "#else\n" \
-  "0,\n" \
+  "%s,\n" \
   "1 /* Disabled.  */, %s,\n" \
   "#endif\n",
-  condition, cl_flags, cl_bit_fields, cl_zero_bit_fields)
+  condition, cl_flags, cl_bit_fields,
+  cl_flags, cl_zero_bit_fields)
else
printf("%s,\n" \
   "0, %s,\n",
diff --git a/gcc/opts.c b/gcc/opts.c
index 1d2d22d7a3f..d85fc2adf8a 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1435,6 +1435,10 @@ print_filtered_help (unsigned int include_flags,
continue;
}
 
+  /* Skip disabled options.  */
+  if (option->cl_disabled)
+   continue;
+
   /* Skip unwanted switches.  */
   if ((option->flags & exclude_flags) != 0)
continue;
diff --git a/gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c 
b/gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c
new file mode 100644
index 000..1bf233a36e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c
@@ -0,0 +1,4 @@
+/* Verify that we get an error for unsupported -mabi=32 option.  */
+/* { dg-additional-options "-mabi=32" } */
+/* { dg-error "not supported by this configuration" "" { target *-*-* } 0 } */
+void foo (void) {}
-- 
2.17.1

[RFC 2/7] Make mips-classic.md entry point for mips*-*-* targets

[Dragan Mladjenovic via Gcc-patches]

Make parts of the code and options conditional on compile-time defines.

gcc/ChangeLog:

* config/mips/mips.h
(MIPS_SUPPORT_DSP, MIPS_SUPPORT_PS_3D,
MIPS_SUPPORT_MSA, MIPS_SUPPORT_LOONGSON
MIPS_SUPPORT_MICROMIPS, MIPS_SUPPORT_LEGACY
MIPS_SUPPORT_FRAME_HEADER_OPT): New defines.
* config/mips/mips.c (MIPS_BUILTIN_MOVF,
MIPS_BUILTIN_MOVT, mips_expand_vcondv2sf,
pll_ps, pul_ps, plu_ps, mips_expand_builtin_movtf,
mips_expand_builtin_compare):
Make conditional on MIPS_SUPPORT_PS_3D.
(MIPS_BUILTIN_BPOSGE32, mips_emit_compare,
dspalu_bypass_table, CODE_FOR_mips_sqrt_ps,
... CODE_FOR_mips_multu, addq_ph ...
dpsqx_sa_w_ph, mips_expand_builtin_bposge):
Make conditional on MIPS_SUPPORT_DSP.
(mips_split_move_p, mips_split_move,
CODE_FOR_msa_adds_s_b ... CODE_FOR_msa_ldi_d,
mips_builtin_vectorized_function,
mips_expand_builtin_insn,
mips_expand_msa_shuffle,
mips_msa_vec_parallel_const_half,
mips_expand_vector_init,
mips_expand_vec_reduc):
Make conditional on MIPS_SUPPORT_MSA.
(struct mips_ls2,
mips_ls2_init_dfa_post_cycle_insn,
mips_sched_init, mips_ls2_variable_issue,
mips_variable_issue,
CODE_FOR_loongson_packsswh ...
CODE_FOR_loongson_psubusb,
mips_expand_vpc_loongson_even_odd
mips_expand_vec_perm_const_1,
mips_expand_vi_broadcast,
mips_expand_vi_loongson_one_pinsrh,
mips_expand_vector_init,
TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN,
TARGET_SCHED_DFA_POST_ADVANCE_CYCLE):
Make conditional on MIPS_SUPPORT_LOONGSON.
(vr4130_reorder, mips_sched_init,
mips_sched_reorder_1, mips_variable_issue):
Make conditional on MIPS_SUPPORT_LEGACY.
(mips_expand_epilogue):
Make conditional on MIPS_SUPPORT_MICROMIPS.
(mips_compute_frame_info, mips_option_override):
Make conditional on MIPS_SUPPORT_FRAME_HEADER_OPT.
* config/mips/mips.md (processor):
(unspec): Move into ...
* config/mips/mips-classic.md: ... here.
* config.gcc [mips*-*-*]: Use mips-classic.md.
* config/mips/mips.opt: Conditionalize options.
---
 gcc/config.gcc|   1 +
 gcc/config/mips/mips-classic.md (new) | 142 
 gcc/config/mips/mips.c| 154 ++
 gcc/config/mips/mips.h|   8 ++
 gcc/config/mips/mips.md   | 117 ---
 gcc/config/mips/mips.opt  | 122 ++--
 6 files changed, 346 insertions(+), 198 deletions(-)
 6 files changed, 346 insertions(+), 198 deletions(-)
 create mode 100644 gcc/config/mips/mips-classic.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 498c51e619d..58e38f70aa6 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -448,6 +448,7 @@ microblaze*-*-*)
 ;;
 mips*-*-*)
cpu_type=mips
+   md_file=mips/mips-classic.md
d_target_objs="mips-d.o"
extra_headers="loongson.h loongson-mmiintrin.h msa.h"
extra_objs="frame-header-opt.o"
diff --git a/gcc/config/mips/mips-classic.md b/gcc/config/mips/mips-classic.md
new file mode 100644
index 000..0f7efc4d5d8
--- /dev/null
+++ b/gcc/config/mips/mips-classic.md
@@ -0,0 +1,142 @@
+;;  Mips.md Machine Description for MIPS based processors
+;;  Copyright (C) 1989-2021 Free Software Foundation, Inc.
+;;  Contributed by   A. Lichnewsky, l...@inria.inria.fr
+;;  Changes by   Michael Meissner, meiss...@osf.org
+;;  64-bit r4000 support by Ian Lance Taylor, i...@cygnus.com, and
+;;  Brendan Eich, bren...@microunity.com.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_enum "processor" [
+  r3000
+  4kc
+  4kp
+  5kc
+  5kf
+  20kc
+  24kc
+  24kf2_1
+  24kf1_1
+  74kc
+  74kf2_1
+  74kf1_1
+  74kf3_2
+  loongson_2e
+  loongson_2f
+  gs464
+  gs464e
+  gs264e
+  m4k
+  octeon
+  octeon2
+  octeon3
+  r3900
+  r6000
+  r4000
+  r4100
+  r4111
+  r4120
+  r4130
+  r4300
+  r4600
+  r4650
+  r4700
+  r5000
+  r5400
+  r5500
+  r5900
+  r7000
+  r8000
+  r9000
+  r1
+  sb1
+  sb1a
+  sr71000
+  xlr
+  xlp
+  p5600
+  m5100
+  i6400
+  p6600
+])
+
+(include "mips.md")
+
+(include "i6400.md")
+(include 

[RFC 1/7] Avoid references to register names in instruction output patterns.

[Dragan Mladjenovic via Gcc-patches]

This allows us to choose the different names if needed in the future.

gcc/ChangeLog:

* config/mips/mips.c (mips_print_operand_punctuation):
Handle '&' punctuation.
(mips_output_probe_stack_range): Use '%.' instead of $0.
* config/mips/mips.h (GLOBAL_POINTER_REGNUM): Move to ...
* config/mips/mips.md (GLOBAL_POINTER_REGNUM): ... here.
(trap, *conditional_trap_reg, *msac, *muls,
*muls_di, msubsidi4): Use '%.' instead of $0.
(clear_hazard_): Use '%&' instead of $31.
---
 gcc/config/mips/mips.c  |  9 +++--
 gcc/config/mips/mips.h  |  4 
 gcc/config/mips/mips.md | 17 +
 3 files changed, 16 insertions(+), 14 deletions(-)
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ce60c5500b7..ab63575eb26 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8816,6 +8816,7 @@ mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
'^' Print the name of the pic call-through register (t9 or $25).
'+' Print the name of the gp register (usually gp or $28).
'$' Print the name of the stack pointer register (sp or $29).
+   '&' Print the name of the return register (ra or $31).
':'  Print "c" to use the compact version if the delay slot is a nop.
'!'  Print "s" to use the short version if the delay slot contains a
16-bit instruction.
@@ -8902,6 +8903,10 @@ mips_print_operand_punctuation (FILE *file, int ch)
   fputs (reg_names[STACK_POINTER_REGNUM], file);
   break;
 
+case '&':
+  fputs (reg_names[RETURN_ADDR_REGNUM], file);
+  break;
+
 case ':':
   /* When final_sequence is 0, the delay slot will be a nop.  We can
 use the compact version where available.  The %: formatter will
@@ -12133,9 +12138,9 @@ mips_output_probe_stack_range (rtx reg1, rtx reg2)
   strcpy (tmp, "%(%"
@@ -1860,7 +1861,7 @@
   else if (TARGET_MIPS5500)
 return "msub\t%2,%3";
   else
-return "msac\t$0,%2,%3";
+return "msac\t%.,%2,%3";
 }
   [(set_attr "type" "imadd")
(set_attr "accum_in""1")
@@ -2060,7 +2061,7 @@
(clobber (match_scratch:SI 3 "=X,l"))]
   "ISA_HAS_MULS"
   "@
-   muls\t$0,%1,%2
+   muls\t%.,%1,%2
muls\t%0,%1,%2"
   [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
@@ -2243,7 +2244,7 @@
  (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
  (any_extend:DI (match_operand:SI 2 "register_operand" "d")]
   "!TARGET_64BIT && ISA_HAS_MULS"
-  "muls\t$0,%1,%2"
+  "muls\t%.,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
 
@@ -2268,7 +2269,7 @@
   else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
 return "msub\t%1,%2";
   else
-return "msac\t$0,%1,%2";
+return "msac\t%.,%1,%2";
 }
   [(set_attr "type" "imadd")
(set_attr "accum_in""3")
@@ -5622,8 +5623,8 @@
 {
   return "%(%addiu\t$31,$31,12\n"
- "\tjr.hb\t$31\n"
+ "1:\taddiu\t%&,%&,12\n"
+ "\tjr.hb\t%&\n"
  "\tnop%>%)";
 }

[RFC 0/7] nanoMIPS port

[Dragan Mladjenovic via Gcc-patches]

Hi all,


This is somewhat a continuation of the previous effort [1] to bring nanoMIPS 
support upstream.
We would like to move our toolchain releases [2] to something more closer to 
the upstream GCC.
As part of that, we are interested in feedback from the community if the 
current approach of
code sharing between nanoMIPS and MIPS backend is viable for future upstream 
inclusion?

The RFC presented here contains enough to produce the nanomips-elf toolchain 
when paired
with [3], [4], [5]. It targets a little-endian bare metal environment using p32 
ABI with soft-float.
Any feedback on it will be appreciated.

Best regards,

Dragan


References:

[1] https://gcc.gnu.org/legacy-ml/gcc/2018-05/msg00012.html
[2] 
https://github.com/MediaTek-Labs/nanomips-gnu-toolchain/releases/tag/nanoMIPS-2021.07-01
[3] https://github.com/MediaTek-Labs/newlib/tree/mtk/newlib250
[4] https://github.com/MediaTek-Labs/binutils-gdb/tree/mtk/binutils_v9
[5] https://github.com/MediaTek-Labs/binutils-gdb/tree/mtk/gold_v7


  (Robert Suchanek)
  (Toma Tabacu)
  (Matthew Fortune)
  (Zoran Jovanovic)
  (Prachi Godbole)
  (Faraz Shahbazker)
  (Steve Ellcey)
  (Jack Romo)
  (Stefan Markovic)
  (Sara Popadic)
  (Mihailo Stojanovic)
  (Dragan Mladjenovic)
  Avoid references to register names in instruction output patterns
  Make mips-classic.md entry point for mips*-*-* targets
  Add nanoMIPS support
  Add test cases for nanoMIPS
  Fix unhelpful messages for disabled options
  Enable MIPS DSP rev3 ASE for nanoMIPS
  Add documentation for nanoMIPS


 config.sub|3 +-
 config/mt-nanomips (new)  |6 +
 configure |9 +-
 configure.ac  |9 +-
 contrib/test_installed|3 +-
 gcc/config.gcc|   65 +
 gcc/config/mips/constraints.md|   57 +-
 gcc/config/mips/genopt-nanomips.sh (new +x)   |   74 +
 gcc/config/mips/i7200.md (new)|  142 +
 gcc/config/mips/micromips.md  |   12 +-
 gcc/config/mips/mips-classic.md (new) |  142 +
 gcc/config/mips/mips-dsp.md   |   17 +-
 gcc/config/mips/mips-ftypes.def   |1 +
 gcc/config/mips/mips-opts.h   |8 +
 gcc/config/mips/mips-protos.h |   81 +-
 gcc/config/mips/mips.c| 3697 +++--
 gcc/config/mips/mips.h|  456 +-
 gcc/config/mips/mips.md   | 1043 +++--
 gcc/config/mips/mips.opt  |  126 +-
 gcc/config/mips/nanomips-cpus.def (new)   |   41 +
 gcc/config/mips/nanomips-tables.opt (new) |   40 +
 gcc/config/mips/nanomips.h (new)  |  349 ++
 gcc/config/mips/nanomips.md (new) |  285 ++
 gcc/config/mips/nanomips.opt (new)|   60 +
 gcc/config/mips/predicates.md |  246 +-
 gcc/config/mips/t-nanomips (new)  |   23 +
 gcc/config/mips/t-nanomips-elf (new)  |   36 +
 gcc/configure |8 +
 gcc/configure.ac  |6 +
 gcc/doc/extend.texi   |  124 +
 gcc/doc/invoke.texi   |  367 ++
 gcc/doc/md.texi   |   71 +
 gcc/opt-suggestions.c |3 +
 gcc/optc-gen.awk  |5 +-
 gcc/opts.c|4 +
 .../gcc.target/nanomips/addiu48-1.c (new) |   12 +
 .../gcc.target/nanomips/addiu48-2.c (new) |   12 +
 .../gcc.target/nanomips/beqic-1.c (new)   |   13 +
 .../gcc.target/nanomips/bgeiuc-1.c (new)  |   31 +
 .../gcc.target/nanomips/bltc-1.c (new)|   28 +
 .../gcc.target/nanomips/bltic-1.c (new)   |   11 +
 .../gcc.target/nanomips/bltiuc-1.c (new)  |   19 +
 .../gcc.target/nanomips/bnec-1.c (new)|   11 +
 .../gcc.target/nanomips/bneic-1.c (new)   |   11 +
 .../gcc.target/nanomips/bnezc-1.c (new)   |   18 +
 .../gcc.target/nanomips/branch-2.c (new)  |   13 +
 .../gcc.target/nanomips/branch-3.c (new)  |   12 +
 .../gcc.target/nanomips/branch-4.c (new)  |   12 +
 .../gcc.target/nanomips/branch-5.c (new)  |   11 +
 .../gcc.target/nanomips/branch-helper.h (new) |  107 +
 .../gcc.target/nanomips/bswap-1.c (new)   |   10 +
 .../gcc.target/nanomips/bswap-2.c (new)   |9 +
 .../gcc.target/nanomips/bswap-3.c (new)   |   13 +
 .../gcc.target/nanomips/bswap-4.c (new)   |9 +
 .../gcc.target/nanomips/cache-1.c (new)   |   31 +
 .../gcc.target/nanomips/call-saved-1.c (new)  |   14 +
 .../gcc.target/nanomips/clear-cache-1.c (new) |   13 +
 .../gcc.target/nanomips/constraint-m.c (new)  |9 +
 .../gcc.target/nanomips/dpaq_sa_l_w.c (new)   |   51 +
 .../gcc.target/nanomips/dpsq_sa_l_w.c (new)   |   37 +
 .../gcc.target/nanomips/dsp-ctrl.c (new)  |   69 +
 

Re: [PATCH] Objective-C: fix class_ro layout for non-LP64

[Iain Sandoe]

Hi Matt

> On 26 Sep 2021, at 09:10, Matt Jacobson via Gcc-patches 
>  wrote:
> 

> Thanks for reviewing.  I’m happy to make the suggested changes.  One comment 
> inline.
> 
>> On Sep 22, 2021, at 2:49 PM, Iain Sandoe  wrote:
>> 
>> However, the behaviour is changed - the existing implementation is explicit 
>> about the fields and
>> clears the reserved ones (and, ISTR, that was based on what the gcc-4.2.1 
>> compiler did).
> 
> My original change does in fact clear the reserved bytes on LP64 platforms.  
> The padding space compiles down to a `.space` assembler directive, and GNU as 
> is documented to fill that space with zeros.  So the reserved bits are indeed 
> cleared.

Apologies for iterating here ..

So it does, indeed, seem that clang does:

target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128”

%struct._class_ro_t = type { i32, i32, i32, i8*, i8*, %struct.__method_list_t*, 
%struct._objc_protocol_list*, 

(for -m64 -fobjc-runtime=macosx -emit-llvm -S)

and,...

target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128”

%struct._class_ro_t = type { i32, i32, i32, i8*, i8*, %struct.__method_list_t*, 
%struct._objc_protocol_list*, 

(for -m32 -fobjc-runtime=macosx -emit-llvm -S), even if the target platform 
will fail to link that (at least macOS will).

So the padding is not explicit in this and will accommodate whatever the target 
uses.

Now - to change that such that the previously reserved field could be used on 
platforms which don’t have implicit padding would be an ABI break, so isn’t 
going to happen by accident (or at all, I imagine).

Since we produce .space for Darwin9 and Darwin10 (where the system compiler is 
GCC) I am no longer concerned about dropping the reserved field.

This is a long-winded way of saying that I now think your original approach is 
fine, and will put that patch into my testing queue (spot checks only so far) 
and apply if all goes without regression.

thanks for the patch,
Iain

[PATCH v3 3/3] reassoc: Test rank biasing

[Ilya Leoshkevich via Gcc-patches]

Add both positive and negative tests.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/reassoc-46.c: New test.
* gcc.dg/tree-ssa/reassoc-46.h: Common code for new tests.
* gcc.dg/tree-ssa/reassoc-47.c: New test.
* gcc.dg/tree-ssa/reassoc-48.c: New test.
* gcc.dg/tree-ssa/reassoc-49.c: New test.
* gcc.dg/tree-ssa/reassoc-50.c: New test.
* gcc.dg/tree-ssa/reassoc-51.c: New test.
---
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c |  7 +
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.h | 33 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-47.c |  9 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-48.c |  9 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-49.c | 11 
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-50.c | 10 +++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-51.c | 11 
 7 files changed, 90 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.h
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-47.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-48.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-49.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-50.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-51.c

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c 
b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c
new file mode 100644
index 000..97563dd929f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized -ftree-vectorize" } */
+
+#include "reassoc-46.h"
+
+/* Check that the loop accumulator is added last.  */
+/* { dg-final { scan-tree-dump-times {(?:vect_)?sum_[\d._]+ = 
(?:(?:vect_)?_[\d._]+ \+ (?:vect_)?sum_[\d._]+|(?:vect_)?sum_[\d._]+ \+ 
(?:vect_)?_[\d._]+)} 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.h 
b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.h
new file mode 100644
index 000..e60b490ea0d
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.h
@@ -0,0 +1,33 @@
+#define M 1024
+unsigned int arr1[M];
+unsigned int arr2[M];
+volatile unsigned int sink;
+
+unsigned int
+test (void)
+{
+  unsigned int sum = 0;
+  for (int i = 0; i < M; i++)
+{
+#ifdef MODIFY
+  /* Modify the loop accumulator using a chain of operations - this should
+ not affect its rank biasing.  */
+  sum |= 1;
+  sum ^= 2;
+#endif
+#ifdef STORE
+  /* Save the loop accumulator into a global variable - this should not
+ affect its rank biasing.  */
+  sink = sum;
+#endif
+#ifdef USE
+  /* Add a tricky use of the loop accumulator - this should prevent its
+ rank biasing.  */
+  i = (i + sum) % M;
+#endif
+  /* Use addends with different ranks.  */
+  sum += arr1[i];
+  sum += arr2[((i ^ 1) + 1) % M];
+}
+  return sum;
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-47.c 
b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-47.c
new file mode 100644
index 000..1b0f0fdabe1
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-47.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized -ftree-vectorize" } */
+
+#define MODIFY
+#include "reassoc-46.h"
+
+/* Check that if the loop accumulator is saved into a global variable, it's
+   still added last.  */
+/* { dg-final { scan-tree-dump-times {(?:vect_)?sum_[\d._]+ = 
(?:(?:vect_)?_[\d._]+ \+ (?:vect_)?sum_[\d._]+|(?:vect_)?sum_[\d._]+ \+ 
(?:vect_)?_[\d._]+)} 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-48.c 
b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-48.c
new file mode 100644
index 000..13836ebe8e6
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-48.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized -ftree-vectorize" } */
+
+#define STORE
+#include "reassoc-46.h"
+
+/* Check that if the loop accumulator is modified using a chain of operations
+   other than addition, its new value is still added last.  */
+/* { dg-final { scan-tree-dump-times {(?:vect_)?sum_[\d._]+ = 
(?:(?:vect_)?_[\d._]+ \+ (?:vect_)?sum_[\d._]+|(?:vect_)?sum_[\d._]+ \+ 
(?:vect_)?_[\d._]+)} 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-49.c 
b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-49.c
new file mode 100644
index 000..c1136a447a2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-49.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized -ftree-vectorize" } */
+
+#define MODIFY
+#define STORE
+#include "reassoc-46.h"
+
+/* Check that if the loop accumulator is both modified using a chain of
+   operations other than addition and stored into a global variable, its new
+   value is still added last.  */
+/* { dg-final { scan-tree-dump-times {(?:vect_)?sum_[\d._]+ = 
(?:(?:vect_)?_[\d._]+ \+ 

[PATCH v3 2/3] reassoc: Propagate PHI_LOOP_BIAS along single uses

[Ilya Leoshkevich via Gcc-patches]

PR tree-optimization/49749 introduced code that shortens dependency
chains containing loop accumulators by placing them last on operand
lists of associative operations.

456.hmmer benchmark on s390 could benefit from this, however, the code
that needs it modifies loop accumulator before using it, and since only
so-called loop-carried phis are are treated as loop accumulators, the
code in the present form doesn't really help.   According to Bill
Schmidt - the original author - such a conservative approach was chosen
so as to avoid unnecessarily swapping operands, which might cause
unpredictable effects.  However, giving special treatment to forms of
loop accumulators is acceptable.

The definition of loop-carried phi is: it's a single-use phi, which is
used in the same innermost loop it's defined in, at least one argument
of which is defined in the same innermost loop as the phi itself.
Given this, it seems natural to treat single uses of such phis as phis
themselves.

gcc/ChangeLog:

* tree-ssa-reassoc.c (biased_names): New global.
(propagate_bias_p): New function.
(loop_carried_phi): Remove.
(propagate_rank): Propagate bias along single uses.
(get_rank): Update biased_names when needed.
---
 gcc/tree-ssa-reassoc.c | 109 -
 1 file changed, 74 insertions(+), 35 deletions(-)

diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c
index 420c14e8cf5..db9fb4e1cac 100644
--- a/gcc/tree-ssa-reassoc.c
+++ b/gcc/tree-ssa-reassoc.c
@@ -211,6 +211,10 @@ static int64_t *bb_rank;
 /* Operand->rank hashtable.  */
 static hash_map *operand_rank;
 
+/* SSA_NAMEs that are forms of loop accumulators and whose ranks need to be
+   biased.  */
+static auto_bitmap biased_names;
+
 /* Vector of SSA_NAMEs on which after reassociate_bb is done with
all basic blocks the CFG should be adjusted - basic blocks
split right after that SSA_NAME's definition statement and before
@@ -256,6 +260,53 @@ reassoc_remove_stmt (gimple_stmt_iterator *gsi)
the rank difference between two blocks.  */
 #define PHI_LOOP_BIAS (1 << 15)
 
+/* Return TRUE iff PHI_LOOP_BIAS should be propagated from one of the STMT's
+   operands to the STMT's left-hand side.  The goal is to preserve bias in code
+   like this:
+
+ x_1 = phi(x_0, x_2)
+ a = x_1 | 1
+ b = a ^ 2
+ .MEM = b
+ c = b + d
+ x_2 = c + e
+
+   That is, we need to preserve bias along single-use chains originating from
+   loop-carried phis.  Only GIMPLE_ASSIGNs to SSA_NAMEs are considered to be
+   uses, because only they participate in rank propagation.  */
+static bool
+propagate_bias_p (gimple *stmt)
+{
+  use_operand_p use;
+  imm_use_iterator use_iter;
+  gimple *single_use_stmt = NULL;
+
+  if (TREE_CODE_CLASS (gimple_assign_rhs_code (stmt)) == tcc_reference)
+return false;
+
+  FOR_EACH_IMM_USE_FAST (use, use_iter, gimple_assign_lhs (stmt))
+{
+  gimple *current_use_stmt = USE_STMT (use);
+
+  if (is_gimple_assign (current_use_stmt)
+ && TREE_CODE (gimple_assign_lhs (current_use_stmt)) == SSA_NAME)
+   {
+ if (single_use_stmt != NULL && single_use_stmt != current_use_stmt)
+   return false;
+ single_use_stmt = current_use_stmt;
+   }
+}
+
+  if (single_use_stmt == NULL)
+return false;
+
+  if (gimple_bb (stmt)->loop_father
+  != gimple_bb (single_use_stmt)->loop_father)
+return false;
+
+  return true;
+}
+
 /* Rank assigned to a phi statement.  If STMT is a loop-carried phi of
an innermost loop, and the phi has only a single use which is inside
the loop, then the rank is the block rank of the loop latch plus an
@@ -313,49 +364,27 @@ phi_rank (gimple *stmt)
   return bb_rank[bb->index];
 }
 
-/* If EXP is an SSA_NAME defined by a PHI statement that represents a
-   loop-carried dependence of an innermost loop, return TRUE; else
-   return FALSE.  */
-static bool
-loop_carried_phi (tree exp)
-{
-  gimple *phi_stmt;
-  int64_t block_rank;
-
-  if (TREE_CODE (exp) != SSA_NAME
-  || SSA_NAME_IS_DEFAULT_DEF (exp))
-return false;
-
-  phi_stmt = SSA_NAME_DEF_STMT (exp);
-
-  if (gimple_code (SSA_NAME_DEF_STMT (exp)) != GIMPLE_PHI)
-return false;
-
-  /* Non-loop-carried phis have block rank.  Loop-carried phis have
- an additional bias added in.  If this phi doesn't have block rank,
- it's biased and should not be propagated.  */
-  block_rank = bb_rank[gimple_bb (phi_stmt)->index];
-
-  if (phi_rank (phi_stmt) != block_rank)
-return true;
-
-  return false;
-}
-
 /* Return the maximum of RANK and the rank that should be propagated
from expression OP.  For most operands, this is just the rank of OP.
For loop-carried phis, the value is zero to avoid undoing the bias
in favor of the phi.  */
 static int64_t
-propagate_rank (int64_t rank, tree op)
+propagate_rank (int64_t rank, tree op, bool *maybe_biased_p)
 {
   int64_t op_rank;
 
-  if (loop_carried_phi (op))
- 

[PATCH v3 1/3] reassoc: Do not bias loop-carried PHIs early

[Ilya Leoshkevich via Gcc-patches]

Biasing loop-carried PHIs during the 1st reassociation pass interferes
with reduction chains and does not bring measurable benefits, so do it
only during the 2nd reassociation pass.

gcc/ChangeLog:

* passes.def (pass_reassoc): Rename parameter to early_p.
* tree-ssa-reassoc.c (reassoc_bias_loop_carried_phi_ranks_p):
New variable.
(phi_rank): Don't bias loop-carried phi ranks
before vectorization pass.
(execute_reassoc): Add bias_loop_carried_phi_ranks_p parameter.
(pass_reassoc::pass_reassoc): Add bias_loop_carried_phi_ranks_p
initializer.
(pass_reassoc::set_param): Set bias_loop_carried_phi_ranks_p
value.
(pass_reassoc::execute): Pass bias_loop_carried_phi_ranks_p to
execute_reassoc.
(pass_reassoc::bias_loop_carried_phi_ranks_p): New member.
---
 gcc/passes.def |  4 ++--
 gcc/tree-ssa-reassoc.c | 16 ++--
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/gcc/passes.def b/gcc/passes.def
index d7a1f8c97a6..c5f915d04c6 100644
--- a/gcc/passes.def
+++ b/gcc/passes.def
@@ -242,7 +242,7 @@ along with GCC; see the file COPYING3.  If not see
   /* Identify paths that should never be executed in a conforming
 program and isolate those paths.  */
   NEXT_PASS (pass_isolate_erroneous_paths);
-  NEXT_PASS (pass_reassoc, true /* insert_powi_p */);
+  NEXT_PASS (pass_reassoc, true /* early_p */);
   NEXT_PASS (pass_dce);
   NEXT_PASS (pass_forwprop);
   NEXT_PASS (pass_phiopt, false /* early_p */);
@@ -325,7 +325,7 @@ along with GCC; see the file COPYING3.  If not see
   NEXT_PASS (pass_lower_vector_ssa);
   NEXT_PASS (pass_lower_switch);
   NEXT_PASS (pass_cse_reciprocals);
-  NEXT_PASS (pass_reassoc, false /* insert_powi_p */);
+  NEXT_PASS (pass_reassoc, false /* early_p */);
   NEXT_PASS (pass_strength_reduction);
   NEXT_PASS (pass_split_paths);
   NEXT_PASS (pass_tracer);
diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c
index 8498cfc7aa8..420c14e8cf5 100644
--- a/gcc/tree-ssa-reassoc.c
+++ b/gcc/tree-ssa-reassoc.c
@@ -180,6 +180,10 @@ along with GCC; see the file COPYING3.  If not see
point 3a in the pass header comment.  */
 static bool reassoc_insert_powi_p;
 
+/* Enable biasing ranks of loop accumulators.  We don't want this before
+   vectorization, since it interferes with reduction chains.  */
+static bool reassoc_bias_loop_carried_phi_ranks_p;
+
 /* Statistics */
 static struct
 {
@@ -269,6 +273,9 @@ phi_rank (gimple *stmt)
   use_operand_p use;
   gimple *use_stmt;
 
+  if (!reassoc_bias_loop_carried_phi_ranks_p)
+return bb_rank[bb->index];
+
   /* We only care about real loops (those with a latch).  */
   if (!father->latch)
 return bb_rank[bb->index];
@@ -6940,9 +6947,10 @@ fini_reassoc (void)
optimization of a gimple conditional.  Otherwise returns zero.  */
 
 static unsigned int
-execute_reassoc (bool insert_powi_p)
+execute_reassoc (bool insert_powi_p, bool bias_loop_carried_phi_ranks_p)
 {
   reassoc_insert_powi_p = insert_powi_p;
+  reassoc_bias_loop_carried_phi_ranks_p = bias_loop_carried_phi_ranks_p;
 
   init_reassoc ();
 
@@ -6983,15 +6991,19 @@ public:
 {
   gcc_assert (n == 0);
   insert_powi_p = param;
+  bias_loop_carried_phi_ranks_p = !param;
 }
   virtual bool gate (function *) { return flag_tree_reassoc != 0; }
   virtual unsigned int execute (function *)
-{ return execute_reassoc (insert_powi_p); }
+  {
+return execute_reassoc (insert_powi_p, bias_loop_carried_phi_ranks_p);
+  }
 
  private:
   /* Enable insertion of __builtin_powi calls during execute_reassoc.  See
  point 3a in the pass header comment.  */
   bool insert_powi_p;
+  bool bias_loop_carried_phi_ranks_p;
 }; // class pass_reassoc
 
 } // anon namespace
-- 
2.31.1

[PATCH v3 0/3] reassoc: Propagate PHI_LOOP_BIAS along single uses

[Ilya Leoshkevich via Gcc-patches]

v2: https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579976.html
Changes in v3:
* Do not propagate bias along tcc_references.
* Call get_rank () before checking biased_names.
* Add loop-carried phis to biased_names.
* Move the propagate_bias_p () call outside of the loop.
* Test with -ftree-vectorize, adjust expectations.

Ilya Leoshkevich (3):
  reassoc: Do not bias loop-carried PHIs early
  reassoc: Propagate PHI_LOOP_BIAS along single uses
  reassoc: Test rank biasing

 gcc/passes.def |   4 +-
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c |   7 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.h |  33 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-47.c |   9 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-48.c |   9 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-49.c |  11 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-50.c |  10 ++
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-51.c |  11 ++
 gcc/tree-ssa-reassoc.c | 125 +++--
 9 files changed, 180 insertions(+), 39 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.h
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-47.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-48.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-49.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-50.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/reassoc-51.c

-- 
2.31.1

[PATCH] Fix PR c/94726: ICE with __builtin_shuffle and changing of types

[apinski--- via Gcc-patches]

From: Andrew Pinski 

The problem here is __builtin_shuffle when called with two arguments
instead of 1, uses a SAVE_EXPR to put in for the 1st and 2nd operand
of VEC_PERM_EXPR and when we go and gimplify the SAVE_EXPR, the type
is now error_mark_node and that fails hard.
This fixes the problem by adding a simple check for type of operand
of SAVE_EXPR not to be error_mark_node.

OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

PR c/94726
* gimplify.c (gimplify_save_expr): Return early
if the type of val is error_mark_node.

gcc/testsuite/ChangeLog:

PR c/94726
* gcc.dg/pr94726.c: New test.
---
 gcc/gimplify.c |  3 +++
 gcc/testsuite/gcc.dg/pr94726.c | 11 +++
 2 files changed, 14 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/pr94726.c

diff --git a/gcc/gimplify.c b/gcc/gimplify.c
index 9163dcda438..943c5cb8f2d 100644
--- a/gcc/gimplify.c
+++ b/gcc/gimplify.c
@@ -6232,6 +6232,9 @@ gimplify_save_expr (tree *expr_p, gimple_seq *pre_p, 
gimple_seq *post_p)
   gcc_assert (TREE_CODE (*expr_p) == SAVE_EXPR);
   val = TREE_OPERAND (*expr_p, 0);
 
+  if (TREE_TYPE (val) == error_mark_node)
+return GS_ERROR;
+
   /* If the SAVE_EXPR has not been resolved, then evaluate it once.  */
   if (!SAVE_EXPR_RESOLVED_P (*expr_p))
 {
diff --git a/gcc/testsuite/gcc.dg/pr94726.c b/gcc/testsuite/gcc.dg/pr94726.c
new file mode 100644
index 000..d6911a644a4
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94726.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+typedef unsigned int type __attribute__ ( ( vector_size ( 2*sizeof(int) ) ) ) 
; 
+type a , b; 
+/* { dg-message "note: previous declaration" "previous declaration" { target 
*-*-* } .-1 } */
+void foo ( void ) { 
+   type var = { 2 , 2 } ; 
+   b = __builtin_shuffle ( a , var ) ;
+} 
+
+void * a [ ] = { } ; /* { dg-error "conflicting types" } */
-- 
2.17.1

Re: [PATCH] Objective-C: fix class_ro layout for non-LP64

[Matt Jacobson via Gcc-patches]

Hi Iain,

Thanks for reviewing.  I’m happy to make the suggested changes.  One comment 
inline.

> On Sep 22, 2021, at 2:49 PM, Iain Sandoe  wrote:
> 
> However, the behaviour is changed - the existing implementation is explicit 
> about the fields and
> clears the reserved ones (and, ISTR, that was based on what the gcc-4.2.1 
> compiler did).

My original change does in fact clear the reserved bytes on LP64 platforms.  
The padding space compiles down to a `.space` assembler directive, and GNU as 
is documented to fill that space with zeros.  So the reserved bits are indeed 
cleared.

However, I understand the argument that this is too implicit, in that the C 
standard makes no guarantee about the contents of padding bytes.  So future 
standard-conforming changes to GCC *could* cause that space to be filled with 
other values (however unlikely that may actually be).

(Of course, clang -- which also does not explicitly declare this field --
essentially faces this same theoretical peril...)

One problem with the proposed diff: `__LP64__` there refers to the host, not 
the target.  What's the right way to refer to the LP64-ness of the target?  I 
see `TARGET_LP64`, but it's only defined for Intel.  I'm using it below (and 
backstopping it to zero), but I'm not sure if that's correct.  Note that it's a 
run-time-of-compiler (not build-time-of-compiler) check.

===

Here's v2.




gcc/objc/ChangeLog:

2021-09-26  Matt Jacobson  

* objc-next-runtime-abi-02.c (build_v2_class_templates): Remove explicit
padding on non-LP64.
(build_v2_class_ro_t_initializer): Remove initialization of explicit 
padding on
non-LP64.


diff --git a/gcc/objc/objc-next-runtime-abi-02.c 
b/gcc/objc/objc-next-runtime-abi-02.c
index 42645e22316..22d5232614d 100644
--- a/gcc/objc/objc-next-runtime-abi-02.c
+++ b/gcc/objc/objc-next-runtime-abi-02.c
@@ -85,6 +85,10 @@ along with GCC; see the file COPYING3.  If not see
 
 #define OBJC2_CLS_HAS_CXX_STRUCTORS0x0004L
 
+#ifndef TARGET_LP64
+#define TARGET_LP64 0
+#endif
+
 enum objc_v2_tree_index
 {
   /* Templates.  */
@@ -677,10 +681,12 @@ build_v2_class_templates (void)
   /* uint32_t const instanceSize; */
   add_field_decl (integer_type_node, "instanceSize", );
 
-  /* This ABI is currently only used on m64 NeXT.  We always
- explicitly declare the alignment padding.  */
+  /* For compatibility with existing implementations of the 64-bit NeXT v2
+ ABI, explicitly declare reserved fields that otherwise would be filled
+ with alignment padding. */
   /* uint32_t const reserved; */
-  add_field_decl (integer_type_node, "reserved", );
+  if (TARGET_LP64)
+add_field_decl (integer_type_node, "reserved", );
 
   /* const uint8_t * const ivarLayout; */
   cnst_strg_type = build_pointer_type (unsigned_char_type_node);
@@ -3225,10 +3231,12 @@ build_v2_class_ro_t_initializer (tree type, tree name,
   CONSTRUCTOR_APPEND_ELT (initlist, NULL_TREE,
  build_int_cst (integer_type_node, instanceSize));
 
-  /* This ABI is currently only used on m64 NeXT.  We always
- explicitly declare the alignment padding.  */
-  /* reserved, pads alignment.  */
-  CONSTRUCTOR_APPEND_ELT (initlist, NULL_TREE,
+  /* For compatibility with existing implementations of the 64-bit NeXT v2
+ ABI, explicitly zero-fill reserved fields that otherwise would be filled
+ with alignment padding. */
+  /* reserved */
+  if (TARGET_LP64)
+CONSTRUCTOR_APPEND_ELT (initlist, NULL_TREE,
build_int_cst (integer_type_node, 0));
 
   /* ivarLayout */