[PATCH V2] Extend vectorizer to handle nonlinear induction for neg, mul/lshift/rshift with a constant.

[liuhongt via Gcc-patches]

>Looks good overall - a few comments inline.  Also can you please add
>SLP support?
>I've tried hard to fill in gaps where SLP support is missing since my
>goal is still to get
>rid of non-SLP.
For slp with different induction type, they need separate iv update and
an vector permutation. And if they are the same induction type, iv can
be updated with 1 instructions w/o permutation.
I'll add a incremental patch for that.

>gcc_assert (is_a  (loop_phi_node));
>is shorter
It looks like it doesn't support gphi*, just support gimple*. Since it's
already gphi* here, I've removed the assert.

>I think you should use
>init_expr = PHI_ARG_DEF_FROM_EDGE (loop_phi_node,loop_preheader_edge (loop));
>and loop_latch_edge (loop) for ev_expr, you can't rely on them being arg 0 / 1.
Changed.

>Likewise.  Use preheader/latch edge.
Changed.

>and those two should then go away.
Removed.

>is not vectorized?  I think it should be possible to relax
>this.
Relaxed.

>def is never NULL so a cheaper way to write this is
>|| ((def = SSA_NAME_DEF_STMT (ev_expr)), true)
Changed.

>not sure if we need to bother here - ideally vectorizable_live_operation would
>give up instead (but I suppose the regular IV / induction analysis gives up
>here as well?)
Removed.

>the above can at least go into the combined switch case
Changed.

>Seeing this - did you check whether you handle prologue peeling correctly?  The
>same issue might show up with a vectorized epilogue.  I think you can force a
>peeled prologue with storing unaligned and -fno-vect-cost-model (that IIRC will
>simply optimize for the larger number of aligned memory ops)
Update in vect_update_ivs_after_vectorizer, also support peel for unaligned 
cases.

>since you only handle inner loop nonlinear IVs you should probably
>swap the two checks?
Changed.

>There might be a more canonical way to build the series expr
build_vec_series doens't add stmt to sequence, so i'll still keep VEC_SERY_EXPR 
here?

>use types_compatible_p (...) instead of comparing TYPE_CANONICAL.
>A small enhancement would be to support different signedness
>(use tree_nop_conversion_p then).
Support different signedness.

>above you asserted that the conversion is only necessary for constants
>but then fold_convert will also generate a tree NOP_EXPR for
>some types_compatible_p types.  So maybe only do this for INTEGER_CST
>init_expr or use init_expr = gimple_convert (...) and insert required stmts
>on the preheader.
Changed.

>Alternatively you could perform the vector IV updates in an unsigned type?
Changed.

>why's that necessary?  can we do a MIN (vector_step, { prec-1, prec-1,
>prec-1 ... })
It's true for ashr, but not for ashl, lshr. For the later 2, when vector_step 
>= precision
The result should be zero instead of shift by prec - 1.

>> +  new_name = vect_create_nonlinear_iv_step (, step_expr,
>> +   nunits, induction_type);
>> +
>> +  vec_step = vect_create_nonlinear_iv_vec_step (loop_vinfo, stmt_info,
>> +   new_name, vectype,
>> +   induction_type);

>are these not the same as created above?are these not the same as created 
>above?

They are different, the first one is vf, this is nunits, vf could be multi copy 
of nunits which
is exact this code is handled and phi_latch is updated in the former vf place.


Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.


For neg, the patch create a vec_init as [ a, -a, a, -a, ...  ] and no
vec_step is needed to update vectorized iv since vf is always multiple
of 2(negative * negative is positive).

For shift, the patch create a vec_init as [ a, a >> c, a >> 2*c, ..]
as vec_step as [ c * nunits, c * nunits, c * nunits, ... ], vectorized iv is
updated as vec_def = vec_init >>/<< vec_step.

For mul, the patch create a vec_init as [ a, a * c, a * pow(c, 2), ..]
as vec_step as [ pow(c,nunits), pow(c,nunits),...] iv is updated as vec_def =
vec_init * vec_step.

The patch handles nonlinear iv for
1. Integer type only, floating point is not handled.
2. No slp_node.
3. iv_loop should be same as vector loop, not nested loop.
4. No UD is created, for mul, use unsigned mult to avoid UD, for
   shift, shift count should be less than type precision.

gcc/ChangeLog:

PR tree-optimization/103144
* tree-vect-loop.cc (vect_is_nonlinear_iv_evolution): New function.
(vect_analyze_scalar_cycles_1): Detect nonlinear iv by upper function.
(vect_create_nonlinear_iv_init): New function.
(vect_peel_nonlinear_iv_init): Ditto.
(vect_create_nonlinear_iv_step): Ditto
(vect_create_nonlinear_iv_vec_step): Ditto
(vect_update_nonlinear_iv): Ditto
(vectorizable_nonlinear_induction): Ditto.
(vectorizable_induction): Call
vectorizable_nonlinear_induction when induction_type is not
vect_step_op_add.
* tree-vect-loop-manip.cc 

Re: [PATCH V2]HIGH part of symbol ref is invalid for constant pool[PR106460]

[Jiufu Guo via Gcc-patches]

Jiufu Guo  writes:

New patch V6 is updated as:
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600475.html.

BR,
Jeff(Jiufu)

> Hi,
>
> As the issue in PR106460, a rtx 'high:DI (symbol_ref:DI ("var_48")' is tried
> to store into constant pool.  But actually, it indicates partial address,
> which to be forced to constant memory.
>
> In function rs6000_cannot_force_const_mem, we already return true for
> "HIGH with UNSPEC" rtx.  For this function if GET_CODE (X) is HIGH, the "X"
> represents the high part of a symbol ref, this function would also return
> true.  Below are some examples:
> (high:DI (const:DI (plus:DI (symbol_ref:DI ("xx") (const_int 12 [0xc])
> (high:DI (symbol_ref:DI ("var_1")..)))
>
> This patch updates rs6000_cannot_force_const_mem to return true for
> rtx with HIGH code.
>
>   PR target/106460
>
> gcc/ChangeLog:
>
>   * config/rs6000/rs6000.cc (rs6000_cannot_force_const_mem): Return true
>   for HIGH code rtx.
>
> gcc/testsuite/ChangeLog:
>
>   * gcc.target/powerpc/pr106460.c: New test.
>
> ---
>  gcc/config/rs6000/rs6000.cc   |  7 +--
>  gcc/testsuite/gcc.target/powerpc/pr106460.c | 11 +++
>  2 files changed, 16 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106460.c
>
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index 0af2085adc0..d56832ebbfc 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -9704,8 +9704,11 @@ rs6000_init_stack_protect_guard (void)
>  static bool
>  rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
>  {
> -  if (GET_CODE (x) == HIGH
> -  && GET_CODE (XEXP (x, 0)) == UNSPEC)
> +  /* If GET_CODE (x) is HIGH, the 'X' represets the high part of a 
> symbol_ref.
> + It indicates partial address,  which can not be put into a constant 
> pool.
> + e.g.  (high:DI (unspec:DI [(symbol_ref/u:DI ("*.LC0")..)
> + (high:DI (symbol_ref:DI ("var")..)).  */
> +  if (GET_CODE (x) == HIGH)
>  return true;
>  
>/* A TLS symbol in the TOC cannot contain a sum.  */
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106460.c 
> b/gcc/testsuite/gcc.target/powerpc/pr106460.c
> new file mode 100644
> index 000..ed7a994827b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106460.c
> @@ -0,0 +1,11 @@
> +/* { dg-options "-O1 -mdejagnu-cpu=power10" } */
> +
> +/* (high:DI (symbol_ref:DI ("var_48")..))) should not cause ICE. */
> +extern short var_48;
> +void
> +foo (double *r)
> +{
> +  if (var_48)
> +*r = 1234.5678;
> +}
> +

[PATCH V6] rs6000: Optimize cmp on rotated 16bits constant

[Jiufu Guo via Gcc-patches]

Hi,

When checking eq/ne with a constant which has only 16bits, it can be
optimized to check the rotated data.  By this, the constant building
is optimized.

As the example in PR103743:
For "in == 0x8000LL", this patch generates:
rotldi %r3,%r3,16
cmpldi %cr0,%r3,32768
instead:
li %r9,-1
rldicr %r9,%r9,0,0
cmpd %cr0,%r3,%r9

Compare with previous patchs:
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600385.html
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600198.html

This patch releases the condition on can_create_pseudo_p and adds
clobbers to allow the splitter can be run both before and after RA.

This is updated patch based on previous patch and comments:
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600315.html

This patch pass bootstrap and regtest on ppc64 and ppc64le.
Is it ok for trunk?  Thanks for comments!

BR,
Jeff(Jiufu)


PR target/103743

gcc/ChangeLog:

* config/rs6000/rs6000-protos.h (rotate_from_leading_zeros_const): New.
(compare_rotate_immediate_p): New.
* config/rs6000/rs6000.cc (rotate_from_leading_zeros_const): New
definition.
(compare_rotate_immediate_p): New definition.
* config/rs6000/rs6000.md (EQNE): New code_attr.
(*rotate_on_cmpdi): New define_insn_and_split.

gcc/testsuite/ChangeLog:

* gcc.target/powerpc/pr103743.c: New test.
* gcc.target/powerpc/pr103743_1.c: New test.

---
 gcc/config/rs6000/rs6000-protos.h |  2 +
 gcc/config/rs6000/rs6000.cc   | 41 
 gcc/config/rs6000/rs6000.md   | 62 +++-
 gcc/testsuite/gcc.target/powerpc/pr103743.c   | 52 ++
 gcc/testsuite/gcc.target/powerpc/pr103743_1.c | 95 +++
 5 files changed, 251 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103743.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103743_1.c

diff --git a/gcc/config/rs6000/rs6000-protos.h 
b/gcc/config/rs6000/rs6000-protos.h
index b3c16e7448d..78847e6b3db 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -35,6 +35,8 @@ extern bool xxspltib_constant_p (rtx, machine_mode, int *, 
int *);
 extern int vspltis_shifted (rtx);
 extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
 extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
+extern int rotate_from_leading_zeros_const (unsigned HOST_WIDE_INT, int);
+extern bool compare_rotate_immediate_p (unsigned HOST_WIDE_INT);
 extern int num_insns_constant (rtx, machine_mode);
 extern int small_data_operand (rtx, machine_mode);
 extern bool mem_operand_gpr (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index df491bee2ea..a548db42660 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -14797,6 +14797,47 @@ rs6000_reverse_condition (machine_mode mode, enum 
rtx_code code)
 return reverse_condition (code);
 }
 
+/* Check if C can be rotated from an immediate which starts (as 64bit integer)
+   with at least CLZ bits zero.
+
+   Return the number by which C can be rotated from the immediate.
+   Return -1 if C can not be rotated as from.  */
+
+int
+rotate_from_leading_zeros_const (unsigned HOST_WIDE_INT c, int clz)
+{
+  /* case a. 0..0xxx: already at least clz zeros.  */
+  int lz = clz_hwi (c);
+  if (lz >= clz)
+return 0;
+
+  /* case b. 0..0xxx0..0: at least clz zeros.  */
+  int tz = ctz_hwi (c);
+  if (lz + tz >= clz)
+return tz;
+
+  /* case c. xx10.0xx: rotate 'clz + 1' bits firstly, then check case b.
+  ^bit -> Vbit
+00...00xxx100, 'clz + 1' >= bits of .  */
+  const int rot_bits = HOST_BITS_PER_WIDE_INT - clz + 1;
+  unsigned HOST_WIDE_INT rc = (c >> rot_bits) | (c << (clz - 1));
+  tz = ctz_hwi (rc);
+  if (clz_hwi (rc) + tz >= clz)
+return tz + rot_bits;
+
+  return -1;
+}
+
+/* Check if C can be rotated from an immediate operand of cmpdi or cmpldi.  */
+
+bool
+compare_rotate_immediate_p (unsigned HOST_WIDE_INT c)
+{
+  /* leading 48 zeros (cmpldi), or leading 49 ones (cmpdi).  */
+  return rotate_from_leading_zeros_const (~c, 49) > 0
+|| rotate_from_leading_zeros_const (c, 48) > 0;
+}
+
 /* Generate a compare for CODE.  Return a brand-new rtx that
represents the result of the compare.  */
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e9e5cd1e54d..cad3cfc98cd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7766,6 +7766,67 @@ (define_insn "*movsi_from_df"
   "xscvdpsp %x0,%x1"
   [(set_attr "type" "fp")])
 
+
+(define_code_iterator eqne [eq ne])
+(define_code_attr EQNE [(eq "EQ") (ne "NE")])
+
+;; "i == C" ==> "rotl(i,N) == rotl(C,N)"
+(define_insn_and_split "*rotate_on_cmpdi"
+  [(set (pc)
+   (if_then_else (eqne (match_operand:DI 1 "gpc_reg_operand" "r")
+   

Re: [PATCH] LoongArch: testsuite: refine __tls_get_addr tests with tls_native

[Lulu Cheng]

LGTM!

Thanks.

在 2022/8/24 下午10:09, Xi Ruoyao 写道:

If GCC is not built with a working linker for the target (developers
occansionally build such a "minimal" GCC for testing and debugging),
TLS will be emulated and __tls_get_addr won't be used.  Refine those
tests depending on __tls_get_addr with tls_native to avoid test
failures.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/func-call-medium-1.c: Refine test
depending on __tls_get_addr with { target tls_native }.
* gcc.target/loongarch/func-call-medium-2.c: Likewise.
* gcc.target/loongarch/func-call-medium-3.c: Likewise.
* gcc.target/loongarch/func-call-medium-4.c: Likewise.
* gcc.target/loongarch/func-call-medium-5.c: Likewise.
* gcc.target/loongarch/func-call-medium-6.c: Likewise.
* gcc.target/loongarch/func-call-medium-7.c: Likewise.
* gcc.target/loongarch/func-call-medium-8.c: Likewise.
* gcc.target/loongarch/tls-gd-noplt.c: Likewise.
---
  gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c | 2 +-
  gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c | 2 +-
  gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c | 2 +-
  gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c | 2 +-
  gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c | 2 +-
  gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c | 2 +-
  gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c | 2 +-
  gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c | 3 ++-
  gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c   | 2 +-
  9 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c 
b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c
index 276d73e5ee8..6339e832fe5 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c
@@ -3,7 +3,7 @@
  /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
  /* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */
  /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } 
*/
+/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { 
target tls_native } } } */
  
  extern void g (void);

  void
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c 
b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c
index 237821c066b..a53e75e0bf9 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c
@@ -3,7 +3,7 @@
  /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
  /* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */
  /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } 
*/
+/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { 
target tls_native } } } */
  
  extern void g (void);

  void
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c 
b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c
index 9a6e16103bc..0da7bf98e3c 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c
@@ -3,7 +3,7 @@
  /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
  /* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */
  /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } 
*/
+/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { 
target tls_native } } } */
  
  extern void g (void);

  void
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c 
b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c
index 2577e345239..0219688ae80 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c
@@ -3,7 +3,7 @@
  /* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
  /* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */
  /* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
-/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" } } 
*/
+/* { dg-final { scan-assembler "test3:.*la\.global\t.*\_\_tls\_get\_addr" { 
target tls_native } } } */
  
  extern void g (void);

  void
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c 
b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c
index d70b6ea4663..8a47b5afcba 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c
@@ -3,7 +3,7 @@
  /* { dg-final { scan-assembler 

[PATCH V0] RISC-V: Fix a redefinition bug for the fd-4.c

[shiyulong]

From: yulong 

This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the 
definition in stdio.h.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.

---
 gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-4.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
index 842a26b4364..db342feb6ee 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
@@ -12,11 +12,6 @@ int read (int fd, void *buf, int nbytes);
 #define O_WRONLY 1
 #define O_RDWR 2
 
-typedef enum {
-  S_IRWXU
-  // etc
-} mode_t;
-
 int creat (const char *, mode_t mode);
 
 void
-- 
2.17.1

[committed] RISC-V: Suppress -Wclass-memaccess warning

[Kito Cheng]

poly_int64 is non-trivial type, we need to clean up manully instead
of memset to prevent this warning.

../../gcc/gcc/config/riscv/riscv.cc: In function 'void 
riscv_compute_frame_info()':
../../gcc/gcc/config/riscv/riscv.cc:4113:10: error: 'void* memset(void*, int, 
size_t)' clearing an object of non-trivial type 'struct riscv_frame_info'; use 
assignment or value-initialization instead [-Werror=class-memaccess]
 4113 |   memset (frame, 0, sizeof (*frame));
  |   ~~~^~~
../../gcc/gcc/config/riscv/riscv.cc:101:17: note: 'struct riscv_frame_info' 
declared here
  101 | struct GTY(())  riscv_frame_info {
  | ^~~~
cc1plus: all warnings being treated as errors

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_frame_info): Introduce `reset(void)`;
(riscv_frame_info::reset(void)): New.
(riscv_compute_frame_info): Use riscv_frame_info::reset instead
of memset when clean frame.
---
 gcc/config/riscv/riscv.cc | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6341dc98daa..4d439e15392 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -123,6 +123,9 @@ struct GTY(())  riscv_frame_info {
 
   /* The offset of arg_pointer_rtx from the bottom of the frame.  */
   poly_int64 arg_pointer_offset;
+
+  /* Reset this struct, clean all field to zero.  */
+  void reset(void);
 };
 
 enum riscv_privilege_levels {
@@ -392,6 +395,23 @@ static const struct riscv_tune_info 
riscv_tune_info_table[] = {
   { "size", generic, _size_tune_info },
 };
 
+void riscv_frame_info::reset(void)
+{
+  total_size = 0;
+  mask = 0;
+  fmask = 0;
+  save_libcall_adjustment = 0;
+
+  gp_sp_offset = 0;
+  fp_sp_offset = 0;
+
+  frame_pointer_offset = 0;
+
+  hard_frame_pointer_offset = 0;
+
+  arg_pointer_offset = 0;
+}
+
 /* Implement TARGET_MIN_ARITHMETIC_PRECISION.  */
 
 static unsigned int
@@ -4179,7 +4199,7 @@ riscv_compute_frame_info (void)
interrupt_save_prologue_temp = true;
 }
 
-  memset (frame, 0, sizeof (*frame));
+  frame->reset();
 
   if (!cfun->machine->naked_p)
 {
-- 
2.37.2

Re: [PATCH] RISC-V: Add RVV registers

[Kito Cheng via Gcc-patches]

Committed, thanks!

On Sat, Aug 27, 2022 at 7:09 PM  wrote:
>
> From: zhongjuzhe 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function.
> (riscv_classify_address): Disallow PLUS/LO_SUM/CONST_INT address 
> types for RVV.
> (riscv_address_insns): Add RVV modes condition.
> (riscv_binary_cost): Ditto.
> (riscv_rtx_costs): Adjust cost for RVV.
> (riscv_secondary_memory_needed): Add RVV modes condition.
> (riscv_hard_regno_nregs): Add RVV register allocation.
> (riscv_hard_regno_mode_ok): Add RVV register allocation.
> (riscv_class_max_nregs): Add RVV register allocation.
> * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Add VL/VTYPE and vector 
> registers in Dwarf.
> (UNITS_PER_V_REG): New macro.
> (FIRST_PSEUDO_REGISTER): Adjust first pseudo num for RVV.
> (V_REG_FIRST): New macro.
> (V_REG_LAST): Ditto.
> (V_REG_NUM): Ditto.
> (V_REG_P): Ditto.
> (VL_REG_P): Ditto.
> (VTYPE_REG_P): Ditto.
> (RISCV_DWARF_VL): Ditto.
> (RISCV_DWARF_VTYPE): Ditto.
> (enum reg_class): Add RVV register types.
> (REG_CLASS_CONTENTS): Add RVV register types.
> * config/riscv/riscv.md: Add VL/VTYPE register number constants.
>
> ---
>  gcc/config/riscv/riscv.cc | 100 --
>  gcc/config/riscv/riscv.h  |  90 --
>  gcc/config/riscv/riscv.md |   2 +
>  3 files changed, 173 insertions(+), 19 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 026c69ce40d..65d71544f47 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -279,7 +279,22 @@ const enum reg_class 
> riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
>FP_REGS, FP_REGS,FP_REGS,FP_REGS,
>FP_REGS, FP_REGS,FP_REGS,FP_REGS,
>FP_REGS, FP_REGS,FP_REGS,FP_REGS,
> -  FRAME_REGS,  FRAME_REGS,
> +  FRAME_REGS,  FRAME_REGS, VL_REGS,VTYPE_REGS,
> +  NO_REGS, NO_REGS,NO_REGS,NO_REGS,
> +  NO_REGS, NO_REGS,NO_REGS,NO_REGS,
> +  NO_REGS, NO_REGS,NO_REGS,NO_REGS,
> +  NO_REGS, NO_REGS,NO_REGS,NO_REGS,
> +  NO_REGS, NO_REGS,NO_REGS,NO_REGS,
> +  NO_REGS, NO_REGS,NO_REGS,NO_REGS,
> +  NO_REGS, NO_REGS,NO_REGS,NO_REGS,
> +  VM_REGS, VD_REGS,VD_REGS,VD_REGS,
> +  VD_REGS, VD_REGS,VD_REGS,VD_REGS,
> +  VD_REGS, VD_REGS,VD_REGS,VD_REGS,
> +  VD_REGS, VD_REGS,VD_REGS,VD_REGS,
> +  VD_REGS, VD_REGS,VD_REGS,VD_REGS,
> +  VD_REGS, VD_REGS,VD_REGS,VD_REGS,
> +  VD_REGS, VD_REGS,VD_REGS,VD_REGS,
> +  VD_REGS, VD_REGS,VD_REGS,VD_REGS,
>  };
>
>  /* Costs to use when optimizing for rocket.  */
> @@ -894,6 +909,14 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, 
> machine_mode mode,
>return true;
>  }
>
> +/* Return true if mode is the RVV mode.  */
> +
> +static bool
> +riscv_v_ext_vector_mode_p (machine_mode mode)
> +{
> +  return VECTOR_MODE_P (mode);
> +}
> +
>  /* Return true if X is a valid address for machine mode MODE.  If it is,
> fill in INFO appropriately.  STRICT_P is true if REG_OK_STRICT is in
> effect.  */
> @@ -912,6 +935,10 @@ riscv_classify_address (struct riscv_address_info *info, 
> rtx x,
>return riscv_valid_base_register_p (info->reg, mode, strict_p);
>
>  case PLUS:
> +  /* RVV load/store disallow any offset.  */
> +  if (riscv_v_ext_vector_mode_p (mode))
> +   return false;
> +
>info->type = ADDRESS_REG;
>info->reg = XEXP (x, 0);
>info->offset = XEXP (x, 1);
> @@ -919,6 +946,10 @@ riscv_classify_address (struct riscv_address_info *info, 
> rtx x,
>   && riscv_valid_offset_p (info->offset, mode));
>
>  case LO_SUM:
> +  /* RVV load/store disallow LO_SUM.  */
> +  if (riscv_v_ext_vector_mode_p (mode))
> +   return false;
> +
>info->type = ADDRESS_LO_SUM;
>info->reg = XEXP (x, 0);
>info->offset = XEXP (x, 1);
> @@ -937,6 +968,10 @@ riscv_classify_address (struct riscv_address_info *info, 
> rtx x,
>   && riscv_valid_lo_sum_p (info->symbol_type, mode, 
> info->offset));
>
>  case CONST_INT:
> +  /* RVV load/store disallow CONST_INT.  */
> +  if (riscv_v_ext_vector_mode_p (mode))
> +   return false;
> +
>/* Small-integer addresses don't occur very often, but they
>  are legitimate if x0 is a valid base register.  */
>info->type = ADDRESS_CONST_INT;
> @@ -1022,7 +1057,7 @@ riscv_address_insns (rtx x, machine_mode mode, bool 
> might_split_p)
>
>/* BLKmode is used for single unaligned loads and 

Re: [PATCH] RISC-V: Add RVV instructions classification

[Kito Cheng via Gcc-patches]

Committed, thanks!

On Sat, Aug 27, 2022 at 6:58 PM  wrote:
>
> From: zhongjuzhe 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add new type for vector instructions.
>
> ---
>  gcc/config/riscv/riscv.md | 100 +-
>  1 file changed, 99 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 30cd07dc6f5..ee3e7c53b78 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -195,10 +195,108 @@
>  ;; nop no operation
>  ;; ghost   an instruction that produces no real code
>  ;; bitmanipbit manipulation instructions
> +;; Classification of RVV instructions which will be added to each RVV .md 
> pattern and used by scheduler.
> +;; rdvlenb vector byte length vlenb csrr read
> +;; rdvlvector length vl csrr read
> +;; 7. Vector Loads and Stores
> +;; vldevector unit-stride load instructions
> +;; vstevector unit-stride store instructions
> +;; vldmvector unit-stride mask load instructions
> +;; vstmvector unit-stride mask store instructions
> +;; vldsvector strided load instructions
> +;; vstsvector strided store instructions
> +;; vldux   vector unordered indexed load instructions
> +;; vldox   vector ordered indexed load instructions
> +;; vstux   vector unordered indexed store instructions
> +;; vstox   vector ordered indexed store instructions
> +;; vldff   vector unit-stride fault-only-first load instructions
> +;; vldrvector whole register load instructions
> +;; vstrvector whole register store instructions
> +;; 11. Vector integer arithmetic instructions
> +;; vialu   vector single-width integer add and subtract and logical 
> nstructions
> +;; viwalu  vector widening integer add/subtract
> +;; vextvector integer extension
> +;; vicalu  vector arithmetic with carry or borrow instructions
> +;; vshift  vector single-width bit shift instructions
> +;; vnshift vector narrowing integer shift instructions
> +;; vicmp   vector integer comparison/min/max instructions
> +;; vimul   vector single-width integer multiply instructions
> +;; vidiv   vector single-width integer divide instructions
> +;; viwmul  vector widening integer multiply instructions
> +;; vimuladdvector single-width integer multiply-add instructions
> +;; viwmuladd   vector widening integer multiply-add instructions
> +;; vimerge vector integer merge instructions
> +;; vimov   vector integer move vector instructions
> +;; 12. Vector fixed-point arithmetic instructions
> +;; vsalu   vector single-width saturating add and subtract and logical 
> instructions
> +;; vaalu   vector single-width averaging add and subtract and logical 
> instructions
> +;; vsmul   vector single-width fractional multiply with rounding and 
> saturation instructions
> +;; vsshift vector single-width scaling shift instructions
> +;; vnclip  vector narrowing fixed-point clip instructions
> +;; 13. Vector floating-point instructions
> +;; vfalu   vector single-width floating-point add/subtract instructions
> +;; vfwalu  vector widening floating-point add/subtract instructions
> +;; vfmul   vector single-width floating-point multiply instructions
> +;; vfdiv   vector single-width floating-point divide instructions
> +;; vfwmul  vector widening floating-point multiply instructions
> +;; vfmuladdvector single-width floating-point multiply-add instructions
> +;; vfwmuladd   vector widening floating-point multiply-add instructions
> +;; vfsqrt  vector floating-point square-root instructions
> +;; vfrecp  vector floating-point reciprocal square-root instructions
> +;; vfcmp   vector floating-point comparison/min/max instructions
> +;; vfsgnj  vector floating-point sign-injection instructions
> +;; vfclass vector floating-point classify instruction
> +;; vfmerge vector floating-point merge instruction
> +;; vfmov   vector floating-point move instruction
> +;; vfcvtitof   vector single-width integer to floating-point instruction
> +;; vfcvtftoi   vector single-width floating-point to integer instruction
> +;; vfwcvtitof  vector widening integer to floating-point instruction
> +;; vfwcvtftoi  vector widening floating-point to integer instruction
> +;; vfwcvtftof  vector widening floating-point to floating-point instruction
> +;; vfncvtitof  vector narrowing integer to floating-point instruction
> +;; vfncvtftoi  vector narrowing floating-point to integer instruction
> +;; vfncvtftof  vector narrowing floating-point to floating-point instruction
> +;; 14. Vector reduction operations
> +;; vired   vector single-width integer reduction instructions
> +;; viwred  vector widening integer reduction instructions
> +;; vfred   vector single-width floating-point un-ordered reduction 
> instruction
> +;; vfredo  vector 

[PATCH] libstdc++: Introduce GNU/Hurd-specific libstdc++ os-defines.h

[Samuel Thibault via Gcc-patches]

This is notably needed because in glibc 2.34, the move of pthread functions
into libc.so happened for Linux only, not GNU/Hurd.

The pthread_self() function can also always be used fine as it is.

libstdc++-v3/ChangeLog:

* config/os/gnu/os_defines.h: New file.
* config/os/gnu/ctype_base.h: New file.
* config/os/gnu/ctype_configure_char.cc: New file.
* config/os/gnu/ctype_inline.h: New file.
* configure.host: On gnu* host, use os/gnu instead of os/gnu-linux.

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index ba5939d9003..dd288cce2ca 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,11 @@
+2022-08-28  Samuel Thibault  
+
+   * config/os/gnu/os_defines.h: New file.
+   * config/os/gnu/ctype_base.h: New file.
+   * config/os/gnu/ctype_configure_char.cc: New file.
+   * config/os/gnu/ctype_inline.h: New file.
+   * configure.host: On gnu* host, use os/gnu instead of os/gnu-linux.
+
 2022-08-27  Patrick Palka  
 
* testsuite/20_util/logical_traits/requirements/base_classes.cc: New 
test.
diff --git a/libstdc++-v3/config/os/gnu/ctype_base.h 
b/libstdc++-v3/config/os/gnu/ctype_base.h
new file mode 100644
index 000..955146543db
--- /dev/null
+++ b/libstdc++-v3/config/os/gnu/ctype_base.h
@@ -0,0 +1,66 @@
+// Locale support -*- C++ -*-
+
+// Copyright (C) 1997-2022 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// Under Section 7 of GPL version 3, you are granted additional
+// permissions described in the GCC Runtime Library Exception, version
+// 3.1, as published by the Free Software Foundation.
+
+// You should have received a copy of the GNU General Public License and
+// a copy of the GCC Runtime Library Exception along with this program;
+// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+// .
+
+/** @file bits/ctype_base.h
+ *  This is an internal header file, included by other library headers.
+ *  Do not attempt to use it directly. @headername{locale}
+ */
+
+//
+// ISO C++ 14882: 22.1  Locales
+//
+
+// Information as gleaned from /usr/include/ctype.h
+
+namespace std _GLIBCXX_VISIBILITY(default)
+{
+_GLIBCXX_BEGIN_NAMESPACE_VERSION
+
+  /// @brief  Base class for ctype.
+  struct ctype_base
+  {
+// Non-standard typedefs.
+typedef const int* __to_type;
+
+// NB: Offsets into ctype::_M_table force a particular size
+// on the mask type. Because of this, we don't use an enum.
+typedef unsigned short mask;
+static const mask upper= _ISupper;
+static const mask lower= _ISlower;
+static const mask alpha= _ISalpha;
+static const mask digit= _ISdigit;
+static const mask xdigit   = _ISxdigit;
+static const mask space= _ISspace;
+static const mask print= _ISprint;
+static const mask graph= _ISalpha | _ISdigit | _ISpunct;
+static const mask cntrl= _IScntrl;
+static const mask punct= _ISpunct;
+static const mask alnum= _ISalpha | _ISdigit;
+#if __cplusplus >= 201103L
+static const mask blank= _ISblank;
+#endif
+  };
+
+_GLIBCXX_END_NAMESPACE_VERSION
+} // namespace
diff --git a/libstdc++-v3/config/os/gnu/ctype_configure_char.cc 
b/libstdc++-v3/config/os/gnu/ctype_configure_char.cc
new file mode 100644
index 000..5a88fc11ab3
--- /dev/null
+++ b/libstdc++-v3/config/os/gnu/ctype_configure_char.cc
@@ -0,0 +1,196 @@
+// Locale support -*- C++ -*-
+
+// Copyright (C) 2011-2022 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// Under Section 7 of GPL version 3, you are granted additional
+// permissions described in the GCC Runtime Library Exception, version
+// 3.1, as published by the Free Software Foundation.
+
+// You should have received a copy of the GNU General Public License and
+// a copy of the GCC Runtime Library Exception along with this program;

Re: [PATCH] x86: Cast stride to __PTRDIFF_TYPE__ in AMX intrinsics

[Hongtao Liu via Gcc-patches]

On Sat, Aug 27, 2022 at 12:51 AM H.J. Lu  wrote:
>
> On Mon, Aug 22, 2022 at 7:05 PM Hongtao Liu  wrote:
> >
> > On Tue, Aug 23, 2022 at 1:02 AM H.J. Lu  wrote:
> > >
> > > On 64-bit Windows, long is 32 bits and can't be used as stride in memory
> > > operand when base is a pointer which is 64 bits.  Cast stride to
> > > __PTRDIFF_TYPE__, instead of long.
> > Ok.
> > >
> > > PR target/106714
> > > * config/i386/amxtileintrin.h (_tile_loadd_internal): Cast to
> > > __PTRDIFF_TYPE__.
> > > (_tile_stream_loadd_internal): Likewise.
> > > (_tile_stored_internal): Likewise.
> > > ---
> > >  gcc/config/i386/amxtileintrin.h | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/gcc/config/i386/amxtileintrin.h 
> > > b/gcc/config/i386/amxtileintrin.h
> > > index 7b5a39eba72..06f18aa9bfb 100644
> > > --- a/gcc/config/i386/amxtileintrin.h
> > > +++ b/gcc/config/i386/amxtileintrin.h
> > > @@ -62,7 +62,7 @@ _tile_release (void)
> > >  #define _tile_loadd_internal(dst,base,stride)  \
> > >__asm__ volatile \
> > >("{tileloadd\t(%0,%1,1), %%tmm"#dst"|tileloadd\t%%tmm"#dst", 
> > > [%0+%1*1]}" \
> > > -   :: "r" ((const void*) (base)), "r" ((long) (stride)))
> > > +   :: "r" ((const void*) (base)), "r" ((__PTRDIFF_TYPE__) (stride)))
> > >
> > >  #define _tile_stream_loadd(dst,base,stride)\
> > >_tile_stream_loadd_internal (dst, base, stride)
> > > @@ -70,7 +70,7 @@ _tile_release (void)
> > >  #define _tile_stream_loadd_internal(dst,base,stride)   \
> > >__asm__ volatile \
> > >("{tileloaddt1\t(%0,%1,1), %%tmm"#dst"|tileloaddt1\t%%tmm"#dst", 
> > > [%0+%1*1]}" \
> > > -   :: "r" ((const void*) (base)), "r" ((long) (stride)))
> > > +   :: "r" ((const void*) (base)), "r" ((__PTRDIFF_TYPE__) (stride)))
> > >
> > >  #define _tile_stored(dst,base,stride)  \
> > >_tile_stored_internal (dst, base, stride)
> > > @@ -78,7 +78,7 @@ _tile_release (void)
> > >  #define _tile_stored_internal(src,base,stride) \
> > >__asm__ volatile \
> > >("{tilestored\t%%tmm"#src", (%0,%1,1)|tilestored\t[%0+%1*1], 
> > > %%tmm"#src"}" \
> > > -   :: "r" ((void*) (base)), "r" ((long) (stride)) \
> > > +   :: "r" ((void*) (base)), "r" ((__PTRDIFF_TYPE__) (stride)) \
> > > : "memory")
> > >
> > >  #define _tile_zero(dst)\
> > > --
> > > 2.37.2
> > >
> >
> >
> > --
> > BR,
> > Hongtao
>
> OK to backport it to GCC 12 branch?
Ok.
>
>
> --
> H.J.



-- 
BR,
Hongtao

Re: [PATCH] Always default to DWARF2_DEBUG if not specified, warn about deprecated STABS

[Jeff Law via Gcc-patches]

On 8/28/2022 1:50 AM, Jan-Benedict Glaw wrote:

On Tue, 2021-09-21 16:25:19 +0200, Richard Biener via Gcc-patches 
 wrote:

This makes defaults.h choose DWARF2_DEBUG if PREFERRED_DEBUGGING_TYPE
is not specified by the target and errors out if DWARF DWARF is not supported.

While I think the pdp11 bits arreved, the rest did not (yet). Just
checked my auto-builder logs. When building current HEAD as

../gcc/configure --prefix=... --enable-werror-always \
--enable-languages=all --disable-gcov \
--disable-shared --disable-threads --without-headers \
--target=...
make V=1 all-gcc

ALL of these targets won't build right now:
aarch64-elf
aarch64-rtems
alpha64-dec-vms
alpha-dec-vms
arm-eabi
arm-rtems
arm-symbianelf
arm-uclinux_eabi
bfin-elf
bfin-rtems
bfin-uclinux
c6x-elf
c6x-uclinux
cris-elf
fido-elf
fr30-elf
ft32-elf
i686-elf
i686-lynxos
i686-nto-qnx
i686-pc-msdosdjgpp
i686-rtems
i686-wrs-vxworks
i686-wrs-vxworksae
lm32-elf
lm32-rtems
lm32-uclinux
m32c-elf
m68k-elf
m68k-rtems
m68k-uclinux
moxie-elf
moxie-rtems
moxie-uclinux
powerpc-eabi
powerpc-eabialtivec
powerpc-eabisim
powerpc-eabisimaltivec
powerpc-ibm-aix7.1
powerpc-ibm-aix7.2
powerpcle-eabi
powerpcle-eabisim
powerpcle-elf
powerpc-lynxos
powerpc-rtems
powerpc-wrs-vxworks
powerpc-wrs-vxworksmils
powerpc-xilinx-eabi
ppc-elf
s390x-ibm-tpf
sh-elf
sh-rtems
sh-superh-elf
sh-wrs-vxworks
sparc64-elf
sparc64-rtems
sparc-elf
sparc-leon-elf
sparc-rtems
sparc-wrs-vxworks
visium-elf
x86_64-elf --with-fpmath=sse
x86_64-rtems
xtensa-elf

Umm, most of those -elf targets do build.  See:

http://law-sandy.freeddns.org:8080


Jeff

Re: [PATCH] 32-bit PA-RISC with HP-UX: remove deprecated ports

[John David Anglin]

On 2022-08-26 3:15 a.m., Martin Liška wrote:

Removes the deprecated ports. If I'm correct all hpux9,hpux10 should be removed
as they only provide 32-bit targets. On the contrary, hpux11 supports hppa64 
that
we still do support.

It is my understanding that the 32-bit hppa hpux targets were deprecated 
because they don't
support ELF and the DWARF debug format (.stabs is to be removed). Some of the 
changes to
libtool.m4 affect the 32-bit ia64 hpux target.  As far as I know, it supports 
ELF and the DWARF
debug format.

Possibly, the removal of ia64-hpux should be considered but I think it's a 
separate issue.



Ready to be installed?
Thanks,
Martin

ChangeLog:

* config.rpath: Delete hpux9 and hpux10.
* configure: Regenerate.
* configure.ac: Delete hpux9 and hpux10.
* libgo/config/libtool.m4: Ignore 32-bit
hpux targets.
* libgo/configure: Regenerate.
* libtool.m4: Delete hpux9 and hpux10.

The libtool.m4 files are from GNU libtool.  I don't think these files should be 
changed.

Dave

--
John David Anglin  dave.ang...@bell.net

[PATCH] nvptx: Silence unused variable warning

[Jan-Benedict Glaw]

Hi!

The nvptx backend defines ASM_OUTPUT_DEF along with
ASM_OUTPUT_DEF_FROM_DECLS.  Much like the rs6000 coff target, nvptx
triggers an unused variable warning:

/usr/lib/gcc-snapshot/bin/g++  -fno-PIE -c   -g -O2   -DIN_GCC  
-DCROSS_DIRECTORY_STRUCTURE   -fno-exceptions -fno-rtti 
-fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings 
-Wcast-qual -Wmissing-format-attribute -Woverloaded-virtual -pedantic 
-Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Werror -fno-common 
 -DHAVE_CONFIG_H -I. -I. -I../../gcc/gcc -I../../gcc/gcc/. 
-I../../gcc/gcc/../include -I../../gcc/gcc/../libcpp/include 
-I../../gcc/gcc/../libcody  -I../../gcc/gcc/../libdecnumber 
-I../../gcc/gcc/../libdecnumber/dpd -I../libdecnumber 
-I../../gcc/gcc/../libbacktrace   -o varasm.o -MT varasm.o -MMD -MP -MF 
./.deps/varasm.TPo ../../gcc/gcc/varasm.cc
../../gcc/gcc/varasm.cc: In function 'void 
output_constant_pool_contents(rtx_constant_pool*)':
../../gcc/gcc/varasm.cc:4318:21: error: unused variable 'name' 
[-Werror=unused-variable]
 4318 | const char *name = XSTR (desc->sym, 0);
  | ^~~~
cc1plus: all warnings being treated as errors
make[1]: *** [Makefile:1145: varasm.o] Error 1


Fixed the same way:

diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h
index ed72c253191..71297440566 100644
--- a/gcc/config/nvptx/nvptx.h
+++ b/gcc/config/nvptx/nvptx.h
@@ -321,6 +321,9 @@ struct GTY(()) machine_function
 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
   do   \
 {  \
+  (void) (FILE);   \
+  (void) (LABEL1); \
+  (void) (LABEL2); \
   gcc_unreachable ();  \
 }  \
   while (0)


Ok for HEAD?

Thanks,
  Jan-Benedict

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Re: [PATCH] Always default to DWARF2_DEBUG if not specified, warn about deprecated STABS

[Jan-Benedict Glaw]

On Tue, 2021-09-21 16:25:19 +0200, Richard Biener via Gcc-patches 
 wrote:
> This makes defaults.h choose DWARF2_DEBUG if PREFERRED_DEBUGGING_TYPE
> is not specified by the target and errors out if DWARF DWARF is not supported.

While I think the pdp11 bits arreved, the rest did not (yet). Just
checked my auto-builder logs. When building current HEAD as

../gcc/configure --prefix=... --enable-werror-always \
--enable-languages=all --disable-gcov \
--disable-shared --disable-threads --without-headers \
--target=...
make V=1 all-gcc

ALL of these targets won't build right now:
aarch64-elf
aarch64-rtems
alpha64-dec-vms
alpha-dec-vms
arm-eabi
arm-rtems
arm-symbianelf
arm-uclinux_eabi
bfin-elf
bfin-rtems
bfin-uclinux
c6x-elf
c6x-uclinux
cris-elf
fido-elf
fr30-elf
ft32-elf
i686-elf
i686-lynxos
i686-nto-qnx
i686-pc-msdosdjgpp
i686-rtems
i686-wrs-vxworks
i686-wrs-vxworksae
lm32-elf
lm32-rtems
lm32-uclinux
m32c-elf
m68k-elf
m68k-rtems
m68k-uclinux
moxie-elf
moxie-rtems
moxie-uclinux
powerpc-eabi
powerpc-eabialtivec
powerpc-eabisim
powerpc-eabisimaltivec
powerpc-ibm-aix7.1
powerpc-ibm-aix7.2
powerpcle-eabi
powerpcle-eabisim
powerpcle-elf
powerpc-lynxos
powerpc-rtems
powerpc-wrs-vxworks
powerpc-wrs-vxworksmils
powerpc-xilinx-eabi
ppc-elf
s390x-ibm-tpf
sh-elf
sh-rtems
sh-superh-elf
sh-wrs-vxworks
sparc64-elf
sparc64-rtems
sparc-elf
sparc-leon-elf
sparc-rtems
sparc-wrs-vxworks
visium-elf
x86_64-elf --with-fpmath=sse
x86_64-rtems
xtensa-elf

So I'd like to reignite the discussion about a DWARF2 fallback. :)

Thanks,
  Jan-Benedict

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