Re: [PATCH 0/8] PowerPC future support for Dense Math

[Richard Biener via Gcc-patches]

On Fri, Feb 3, 2023 at 10:16 PM Michael Meissner via Gcc-patches
 wrote:
>
> These patches were originally posted on November 10th.  Segher has asked that 
> I
> repost them.  These patches are somewhat changed since the original posting to
> address some of the comments.
>
> https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605581.html
>
> In the first patch (adding -mcpu=future), I have taken out the code of making
> -mtune=future act as -mtune=power10.  Instead I went through all of the places
> that look at the tuning (mostly in power10.md and rs6000.cc), and added future
> as an option.  Obviously at a later time, we will provide a separate tuning
> file for future (or whatever the new name will be if the instructions are 
> added
> officially).  But for now, it will suffice.
>
> In patch #3, I fixed the opcode for clearing a dense math register that Peter
> had noticed.  I was using the name based on the existing clear instruction,
> instead of the new instruction.
>
> In patch #6, I fixed the code, relying on the changes for setting the 
> precision
> field to 16 bits.  Since that patch will not be able to go into GCC 13 at
> present, we might skip that support for now.  The important thing for existing
> users of the MMA code is the support for accumulators being in the separate
> dense math registers rather than overlapping does need to go in, and we can
> probably delay the 1,024 bit register support, or implement in a different
> fashion.
>
> In the insn names, I tried to switch to using _vsx instead of _fpr for the
> existing MMA support instructions.  I also tried to clear up the comments to
> specify ISA 3.1 instead of power10 when talking about the existing MMA
> support.
>
> The following is from the original posting (slightly modified):
>
> This patch is very preliminary support for a potential new feature to the
> PowerPC that extends the current power10 MMA architecture.  This feature may 
> or
> may not be present in any specific future PowerPC processor.
>
> In the current MMA subsystem for Power10, there are 8 512-bit accumulator
> registers.  These accumulators are each tied to sets of 4 FPR registers.  When
> you issue a prime instruction, it makes sure the accumulator is a copy of the 
> 4
> FPR registers the accumulator is tied to.  When you issue a deprime
> instruction, it makes sure that the accumulator data content is logically
> copied to the matching FPR register.
>
> In the potential dense math system, the accumulators are moved to separate
> registers called dense math registers (DM registers or DMR).  The DMRs are 
> then
> extended to 1,024 bits and new instructions will be added to deal with all
> 1,024 bits of the DMRs.
>
> If you take existing MMA code, it will work as long as you don't do anything
> with accumulators, and you follow the rules in the ISA 3.1 documentation for
> using the MMA subsystem.
>
> These patches add support for the 512-bit accumulators within the dense math
> system, and for allocation of the 1,024-bit DMRs.  At this time, no additional
> built-in functions will be done to support any dense math features other than
> doing data movement between the DMRs and the VSX registers.  Before we can 
> look
> at adding any new dense math support other than data movement, we need the GCC
> compiler to be able to allocate and use these DMRs.
>
> There are 8 patches in this patch set:
>
> 1) The first patch just adds -mcpu=future as an option to add new support.
> This is similar to the -mcpu=future that we did before power10 was announced.
>
> 2) The second patch enables GCC to use the load and store vector pair
> instructions to optimize memory copy operations in the compiler.  For power10,
> we needed to just stay with normal vector load/stores for memory copy
> operations.
>
> 3) The third patch enables 512-bit accumulators store in DMRs.  This patch
> enables the register allocation, but it does not move the existing MMA to use
> these registers.
>
> 4) The fourth patch switches the MMA subsystem to use 512-bit accumulators
> within DMRs if you use -mcpu=future.
>
> 5) The fifth patch switches the names of the MMA instructions to use the dense
> math equivalent name if -mcpu=future.
>
> 6) The sixth patch enables using the full 1,024-bit DMRs.  Right now, all you
> can do with DMRs is move a VSX register to a DMR register, and to move a DMR
> register to a VSX register.  [As I mentioned above, at the moment, this patch
> is problematical as is]
>
> 7) The seventh patch is not DMR related.  It adds support for variants of the
> load/store vector with length instruction that may be added in future PowerPC
> processors.  These variants eliminate having to shift the byte length left by
> 56 bits.
>
> 8) The eighth patch is also not DMR related.  It adds support for a saturating
> subtract operation that may be added to future PowerPC processors.
>
> In terms of changes, we now use the wD constraint for accumulators.  If you
> compile with 

Re: [PATCH] ubsan: Fix up another spot that should have been BUILT_IN_UNREACHABLE_TRAPS [PR108655]

[Richard Biener via Gcc-patches]

On Fri, Feb 3, 2023 at 9:15 PM Jakub Jelinek via Gcc-patches
 wrote:
>
> Hi!
>
> We ICE on the following testcase, because ivcanon calls
> gimple_build_builtin_unreachable but doesn't expect it would need vops.
> BUILT_IN_UNREACHABLE_TRAP I've introduced yesterday doesn't need
> vops and should be used in that case instead of BUILT_IN_TRAP which
> needs them.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

OK.

> 2023-02-03  Jakub Jelinek  
>
> PR tree-optimization/108655
> * ubsan.cc (sanitize_unreachable_fn): For -funreachable-traps
> or -fsanitize=unreachable -fsanitize-trap=unreachable return
> BUILT_IN_UNREACHABLE_TRAP decl rather than BUILT_IN_TRAP.
>
> * gcc.dg/pr108655.c: New test.
>
> --- gcc/ubsan.cc.jj 2023-01-02 09:32:38.393053992 +0100
> +++ gcc/ubsan.cc2023-02-03 11:40:47.047399386 +0100
> @@ -649,7 +649,7 @@ sanitize_unreachable_fn (tree *data, loc
>? (flag_sanitize_trap & SANITIZE_UNREACHABLE)
>: flag_unreachable_traps)
>  {
> -  fn = builtin_decl_explicit (BUILT_IN_TRAP);
> +  fn = builtin_decl_explicit (BUILT_IN_UNREACHABLE_TRAP);
>*data = NULL_TREE;
>  }
>else if (san)
> --- gcc/testsuite/gcc.dg/pr108655.c.jj  2023-02-03 11:46:39.533190031 +0100
> +++ gcc/testsuite/gcc.dg/pr108655.c 2023-02-03 11:46:28.272356439 +0100
> @@ -0,0 +1,15 @@
> +/* PR tree-optimization/108655 */
> +/* { dg-do compile } */
> +/* { dg-options "-w -O1 -funreachable-traps" } */
> +
> +void
> +foo (void)
> +{
> +  int i, j;
> +  for (; i;)
> +;
> +  for (; i < 6;)
> +for (j = 0; j < 6; ++j)
> +  i += j;
> +  __builtin_trap ();
> +}
>
> Jakub
>

Re: [DOC PATCH] Document the VEC_PERM_EXPR tree code (and minor clean-ups).

[Richard Biener via Gcc-patches]

On Sat, Feb 4, 2023 at 9:35 PM Roger Sayle  wrote:
>
>
> This patch (primarily) documents the VEC_PERM_EXPR tree code in
> generic.texi.  For ease of review, it is provided below as a pair
> of diffs.  The first contains just the new text added to describe
> VEC_PERM_EXPR, the second tidies up this part of the documentation
> by sorting the tree codes into alphabetical order, and providing
> consistent section naming/capitalization, so changing this section
> from "Vectors" to "Vector Expressions" (matching the nearby
> "Unary and Binary Expressions").
>
> Tested with make pdf and make html on x86_64-pc-linux-gnu.
> The reviewer(s) can decide whether to approve just the new content,
> or the content+clean-up.  Ok for mainline?

+@item VEC_PERM_EXPR
+This node represents a vector permute/blend operation.  The three operands
+must be vectors of the same number of elements.  The first and second
+operands must be vectors of the same type as the entire expression,

this was recently relaxed for the case of constant permutes in which case
the first and second operands only have to have the same element type
as the result.  See tree-cfg.cc:verify_gimple_assign_ternary.

The following description will become a bit more awkward here and
for rhs1/rhs2 with different number of elements the modulo interpretation
doesn't hold - I believe we require in-bounds elements for constant
permutes.  Richard can probably clarify things here.

Thanks,
Richard.

>
>
> 2023-02-04  Roger Sayle  
>
> gcc/ChangeLog
> * doc/generic.texi : Standardize capitalization
> of section titles from "Expression trees".
> : Likewise standardize capitalization
> from "Language-dependent trees".
> : Capitalized from "Constant Expressions".
> : Standardized section name from "Vectors".
> Document VEC_PERM_EXPR tree code.  Sort tree codes alphabetically.
>
>
> Thanks in advance,
> Roger
> --
>

Re: realpath() patch to fix symlinks resolution for win32

[Jonathan Yong via Gcc-patches]

On 1/18/23 10:44, i.nixman--- via Gcc-patches wrote:

hello again!

the final version of the path for 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108350


successfully bootstraped for x86_64-mingw32 and x86_64-linux.

could anyone apply it please?



best!


Looks good to me, please supply the appropriate changelog.

[PATCH] RISC-V: Add vzext.vf2 C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vzext_vf2-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_mu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_mu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_mu-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tu-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tum-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tum-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tum-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vzext_vf2-1.C   | 216 ++
 .../g++.target/riscv/rvv/base/vzext_vf2-2.C   | 216 ++
 .../g++.target/riscv/rvv/base/vzext_vf2-3.C   | 216 ++
 .../riscv/rvv/base/vzext_vf2_mu-1.C   | 111 +
 .../riscv/rvv/base/vzext_vf2_mu-2.C   | 111 +
 .../riscv/rvv/base/vzext_vf2_mu-3.C   | 111 +
 .../riscv/rvv/base/vzext_vf2_tu-1.C   | 111 +
 .../riscv/rvv/base/vzext_vf2_tu-2.C   | 111 +
 .../riscv/rvv/base/vzext_vf2_tu-3.C   | 111 +
 .../riscv/rvv/base/vzext_vf2_tum-1.C  | 111 +
 .../riscv/rvv/base/vzext_vf2_tum-2.C  | 111 +
 .../riscv/rvv/base/vzext_vf2_tum-3.C  | 111 +
 .../riscv/rvv/base/vzext_vf2_tumu-1.C | 111 +
 .../riscv/rvv/base/vzext_vf2_tumu-2.C | 111 +
 .../riscv/rvv/base/vzext_vf2_tumu-3.C | 111 +
 15 files changed, 1980 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C
new file mode 100644
index 000..4e9c81cf87f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2(vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2(vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2(vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2(vuint8m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2(vuint8m2_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint16m8_t test___riscv_vzext_vf2(vuint8m4_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf2(vuint16mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf2(vuint16mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf2(vuint16m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf2(vuint16m2_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf2(vuint16m4_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf2(vuint32mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf2(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf2(vuint32m1_t 

[PATCH] RISC-V: Add vzext.vf4 C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vzext_vf4-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_mu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_mu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_mu-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tu-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tum-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tum-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tum-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vzext_vf4-1.C   | 132 ++
 .../g++.target/riscv/rvv/base/vzext_vf4-2.C   | 132 ++
 .../g++.target/riscv/rvv/base/vzext_vf4-3.C   | 132 ++
 .../riscv/rvv/base/vzext_vf4_mu-1.C   |  69 +
 .../riscv/rvv/base/vzext_vf4_mu-2.C   |  69 +
 .../riscv/rvv/base/vzext_vf4_mu-3.C   |  69 +
 .../riscv/rvv/base/vzext_vf4_tu-1.C   |  69 +
 .../riscv/rvv/base/vzext_vf4_tu-2.C   |  69 +
 .../riscv/rvv/base/vzext_vf4_tu-3.C   |  69 +
 .../riscv/rvv/base/vzext_vf4_tum-1.C  |  69 +
 .../riscv/rvv/base/vzext_vf4_tum-2.C  |  69 +
 .../riscv/rvv/base/vzext_vf4_tum-3.C  |  69 +
 .../riscv/rvv/base/vzext_vf4_tumu-1.C |  69 +
 .../riscv/rvv/base/vzext_vf4_tumu-2.C |  69 +
 .../riscv/rvv/base/vzext_vf4_tumu-3.C |  69 +
 15 files changed, 1224 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C
new file mode 100644
index 000..5875271fa88
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint32mf2_t test___riscv_vzext_vf4(vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf4(vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf4(vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf4(vuint8m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf4(vuint8m2_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf4(vuint16mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf4(vuint16mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf4(vuint16m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf4(vuint16m2_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_vzext_vf4(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(mask,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf4(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(mask,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf4(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf4(mask,op1,vl);

[PATCH] RISC-V: Add vzext.vf8 C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vzext_vf8-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_mu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_mu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_mu-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tu-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tum-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tum-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tum-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vzext_vf8-1.C   | 62 +++
 .../g++.target/riscv/rvv/base/vzext_vf8-2.C   | 62 +++
 .../g++.target/riscv/rvv/base/vzext_vf8-3.C   | 62 +++
 .../riscv/rvv/base/vzext_vf8_mu-1.C   | 34 ++
 .../riscv/rvv/base/vzext_vf8_mu-2.C   | 34 ++
 .../riscv/rvv/base/vzext_vf8_mu-3.C   | 34 ++
 .../riscv/rvv/base/vzext_vf8_tu-1.C   | 34 ++
 .../riscv/rvv/base/vzext_vf8_tu-2.C   | 34 ++
 .../riscv/rvv/base/vzext_vf8_tu-3.C   | 34 ++
 .../riscv/rvv/base/vzext_vf8_tum-1.C  | 34 ++
 .../riscv/rvv/base/vzext_vf8_tum-2.C  | 34 ++
 .../riscv/rvv/base/vzext_vf8_tum-3.C  | 34 ++
 .../riscv/rvv/base/vzext_vf8_tumu-1.C | 34 ++
 .../riscv/rvv/base/vzext_vf8_tumu-2.C | 34 ++
 .../riscv/rvv/base/vzext_vf8_tumu-3.C | 34 ++
 15 files changed, 594 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C
new file mode 100644
index 000..caf23bc78d9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8(vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vuint8m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(op1,vl);
+}
+
+
+vuint64m1_t test___riscv_vzext_vf8(vbool64_t mask,vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8(vbool32_t mask,vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8(vbool16_t mask,vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8(vbool8_t mask,vuint8m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf8(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 

[PATCH] RISC-V: Add vsext constraint tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/unop_v_constraint-2.c: New test.

---
 .../riscv/rvv/base/unop_v_constraint-2.c  | 132 ++
 1 file changed, 132 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
new file mode 100644
index 000..19f9365b42b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
@@ -0,0 +1,132 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_vector.h"
+
+/*
+** f1:
+** vsetivli\tzero,4,e32,m1,tu,ma
+** vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
+** vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out)
+{
+vint16mf2_t v = __riscv_vle16_v_i16mf2 (in, 4);
+vint16mf2_t v2 = __riscv_vle16_v_i16mf2_tu (v, in, 4);
+vint32m1_t v3 = __riscv_vsext_vf2_i32m1 (v2, 4);
+vint32m1_t v4 = __riscv_vsext_vf2_i32m1_tu (v3, v2, 4);
+__riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f2:
+** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsetivli\tzero,4,e32,m1,ta,ma
+** vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vsetvli\tzero,zero,e64,m2,ta,ma
+** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+** vse64\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out)
+{
+vbool32_t mask = *(vbool32_t*)in;
+asm volatile ("":::"memory");
+vint16mf2_t v = __riscv_vle16_v_i16mf2 (in, 4);
+vint32m1_t v3 = __riscv_vsext_vf2_i32m1 (v, 4);
+vint64m2_t v4 = __riscv_vsext_vf2_i64m2_m (mask, v3, 4);
+__riscv_vse64_v_i64m2 (out, v4, 4);
+}
+
+/*
+** f3:
+** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsetivli\tzero,4,e32,m1,tu,mu
+** vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
+** vle16\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out)
+{
+vbool32_t mask = *(vbool32_t*)in;
+asm volatile ("":::"memory");
+vint16mf2_t v = __riscv_vle16_v_i16mf2 (in, 4);
+vint16mf2_t v2 = __riscv_vle16_v_i16mf2_tumu (mask, v, in, 4);
+vint32m1_t v3 = __riscv_vsext_vf2_i32m1 (v2, 4);
+vint32m1_t v4 = __riscv_vsext_vf2_i32m1_tumu (mask, v3, v2, 4);
+__riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/*
+** f4:
+** vsetivli\tzero,4,e16,mf4,tu,ma
+** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
+** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vse16\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f4 (void * in, void *out)
+{
+vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
+vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4);
+vint16mf4_t v3 = __riscv_vsext_vf2_i16mf4 (v2, 4);
+vint16mf4_t v4 = __riscv_vsext_vf2_i16mf4_tu (v3, v2, 4);
+__riscv_vse16_v_i16mf4 (out, v4, 4);
+}
+
+/*
+** f5:
+** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsetivli\tzero,4,e16,mf4,ta,ma
+** vle8.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vsetvli\tzero,zero,e32,mf2,ta,ma
+** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f5 (void * in, void *out)
+{
+vbool64_t mask = *(vbool64_t*)in;
+asm volatile ("":::"memory");
+vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
+vint16mf4_t v3 = __riscv_vsext_vf2_i16mf4 (v, 4);
+vint32mf2_t v4 = __riscv_vsext_vf2_i32mf2_m (mask, v3, 4);
+__riscv_vse32_v_i32mf2 (out, v4, 4);
+}
+
+/*
+** f6:
+** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
+** vsetivli\tzero,4,e16,mf4,tu,mu
+** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
+** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
+** vsext\.vf2\tv[0-9]+,\s*v[0-9]+
+** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
+** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void f6 (void * in, void *out)
+{
+vbool64_t mask = *(vbool64_t*)in;
+asm volatile ("":::"memory");
+vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
+vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4);
+vint16mf4_t v3 = __riscv_vsext_vf2_i16mf4 (v2, 4);
+vint16mf4_t v4 = __riscv_vsext_vf2_i16mf4_tumu (mask, v3, v2, 4);
+__riscv_vse16_v_i16mf4 (out, v4, 4);
+}
-- 
2.36.1

[PATCH] RISC-V: Add vsext.vf2 C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vsext_vf2-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vsext_vf2-1.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vsext_vf2-2.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vsext_vf2-3.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vsext_vf2_m-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vsext_vf2_m-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vsext_vf2_m-3.c | 111 ++
 .../riscv/rvv/base/vsext_vf2_mu-1.c   | 111 ++
 .../riscv/rvv/base/vsext_vf2_mu-2.c   | 111 ++
 .../riscv/rvv/base/vsext_vf2_mu-3.c   | 111 ++
 .../riscv/rvv/base/vsext_vf2_tu-1.c   | 111 ++
 .../riscv/rvv/base/vsext_vf2_tu-2.c   | 111 ++
 .../riscv/rvv/base/vsext_vf2_tu-3.c   | 111 ++
 .../riscv/rvv/base/vsext_vf2_tum-1.c  | 111 ++
 .../riscv/rvv/base/vsext_vf2_tum-2.c  | 111 ++
 .../riscv/rvv/base/vsext_vf2_tum-3.c  | 111 ++
 .../riscv/rvv/base/vsext_vf2_tumu-1.c | 111 ++
 .../riscv/rvv/base/vsext_vf2_tumu-2.c | 111 ++
 .../riscv/rvv/base/vsext_vf2_tumu-3.c | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c
new file mode 100644
index 000..eb8fdb8adff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vsext_vf2_i16mf4(vint8mf8_t op1,size_t vl)
+{
+return __riscv_vsext_vf2_i16mf4(op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vsext_vf2_i16mf2(vint8mf4_t op1,size_t vl)
+{
+return __riscv_vsext_vf2_i16mf2(op1,vl);
+}
+
+
+vint16m1_t test___riscv_vsext_vf2_i16m1(vint8mf2_t op1,size_t vl)
+{
+return __riscv_vsext_vf2_i16m1(op1,vl);
+}
+
+
+vint16m2_t test___riscv_vsext_vf2_i16m2(vint8m1_t op1,size_t vl)
+{
+return __riscv_vsext_vf2_i16m2(op1,vl);
+}
+
+
+vint16m4_t test___riscv_vsext_vf2_i16m4(vint8m2_t op1,size_t vl)
+{
+return __riscv_vsext_vf2_i16m4(op1,vl);
+}
+
+
+vint16m8_t 

[PATCH] RISC-V: Add vsext.vf4 C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vsext_vf4-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vsext_vf4-1.c   | 69 +++
 .../gcc.target/riscv/rvv/base/vsext_vf4-2.c   | 69 +++
 .../gcc.target/riscv/rvv/base/vsext_vf4-3.c   | 69 +++
 .../gcc.target/riscv/rvv/base/vsext_vf4_m-1.c | 69 +++
 .../gcc.target/riscv/rvv/base/vsext_vf4_m-2.c | 69 +++
 .../gcc.target/riscv/rvv/base/vsext_vf4_m-3.c | 69 +++
 .../riscv/rvv/base/vsext_vf4_mu-1.c   | 69 +++
 .../riscv/rvv/base/vsext_vf4_mu-2.c   | 69 +++
 .../riscv/rvv/base/vsext_vf4_mu-3.c   | 69 +++
 .../riscv/rvv/base/vsext_vf4_tu-1.c   | 69 +++
 .../riscv/rvv/base/vsext_vf4_tu-2.c   | 69 +++
 .../riscv/rvv/base/vsext_vf4_tu-3.c   | 69 +++
 .../riscv/rvv/base/vsext_vf4_tum-1.c  | 69 +++
 .../riscv/rvv/base/vsext_vf4_tum-2.c  | 69 +++
 .../riscv/rvv/base/vsext_vf4_tum-3.c  | 69 +++
 .../riscv/rvv/base/vsext_vf4_tumu-1.c | 69 +++
 .../riscv/rvv/base/vsext_vf4_tumu-2.c | 69 +++
 .../riscv/rvv/base/vsext_vf4_tumu-3.c | 69 +++
 18 files changed, 1242 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c
new file mode 100644
index 000..f853ceafce9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint32mf2_t test___riscv_vsext_vf4_i32mf2(vint8mf8_t op1,size_t vl)
+{
+return __riscv_vsext_vf4_i32mf2(op1,vl);
+}
+
+
+vint32m1_t test___riscv_vsext_vf4_i32m1(vint8mf4_t op1,size_t vl)
+{
+return __riscv_vsext_vf4_i32m1(op1,vl);
+}
+
+
+vint32m2_t test___riscv_vsext_vf4_i32m2(vint8mf2_t op1,size_t vl)
+{
+return __riscv_vsext_vf4_i32m2(op1,vl);
+}
+
+
+vint32m4_t test___riscv_vsext_vf4_i32m4(vint8m1_t op1,size_t vl)
+{
+return __riscv_vsext_vf4_i32m4(op1,vl);
+}
+
+
+vint32m8_t test___riscv_vsext_vf4_i32m8(vint8m2_t op1,size_t vl)
+{
+return __riscv_vsext_vf4_i32m8(op1,vl);
+}
+
+
+vint64m1_t 

[PATCH] RISC-V: Add vsext.vf8 C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vsext_vf8-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vsext_vf8-1.c   | 34 +++
 .../gcc.target/riscv/rvv/base/vsext_vf8-2.c   | 34 +++
 .../gcc.target/riscv/rvv/base/vsext_vf8-3.c   | 34 +++
 .../gcc.target/riscv/rvv/base/vsext_vf8_m-1.c | 34 +++
 .../gcc.target/riscv/rvv/base/vsext_vf8_m-2.c | 34 +++
 .../gcc.target/riscv/rvv/base/vsext_vf8_m-3.c | 34 +++
 .../riscv/rvv/base/vsext_vf8_mu-1.c   | 34 +++
 .../riscv/rvv/base/vsext_vf8_mu-2.c   | 34 +++
 .../riscv/rvv/base/vsext_vf8_mu-3.c   | 34 +++
 .../riscv/rvv/base/vsext_vf8_tu-1.c   | 34 +++
 .../riscv/rvv/base/vsext_vf8_tu-2.c   | 34 +++
 .../riscv/rvv/base/vsext_vf8_tu-3.c   | 34 +++
 .../riscv/rvv/base/vsext_vf8_tum-1.c  | 34 +++
 .../riscv/rvv/base/vsext_vf8_tum-2.c  | 34 +++
 .../riscv/rvv/base/vsext_vf8_tum-3.c  | 34 +++
 .../riscv/rvv/base/vsext_vf8_tumu-1.c | 34 +++
 .../riscv/rvv/base/vsext_vf8_tumu-2.c | 34 +++
 .../riscv/rvv/base/vsext_vf8_tumu-3.c | 34 +++
 18 files changed, 612 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c
new file mode 100644
index 000..e922129cd09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test___riscv_vsext_vf8_i64m1(vint8mf8_t op1,size_t vl)
+{
+return __riscv_vsext_vf8_i64m1(op1,vl);
+}
+
+
+vint64m2_t test___riscv_vsext_vf8_i64m2(vint8mf4_t op1,size_t vl)
+{
+return __riscv_vsext_vf8_i64m2(op1,vl);
+}
+
+
+vint64m4_t test___riscv_vsext_vf8_i64m4(vint8mf2_t op1,size_t vl)
+{
+return __riscv_vsext_vf8_i64m4(op1,vl);
+}
+
+
+vint64m8_t test___riscv_vsext_vf8_i64m8(vint8m1_t op1,size_t vl)
+{
+return __riscv_vsext_vf8_i64m8(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf8\s+v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { 

[PATCH] RISC-V: Add vzext.vf2 C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vzext_vf2-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_m-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_m-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_m-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vzext_vf2-1.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vzext_vf2-2.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vzext_vf2-3.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vzext_vf2_m-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vzext_vf2_m-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vzext_vf2_m-3.c | 111 ++
 .../riscv/rvv/base/vzext_vf2_mu-1.c   | 111 ++
 .../riscv/rvv/base/vzext_vf2_mu-2.c   | 111 ++
 .../riscv/rvv/base/vzext_vf2_mu-3.c   | 111 ++
 .../riscv/rvv/base/vzext_vf2_tu-1.c   | 111 ++
 .../riscv/rvv/base/vzext_vf2_tu-2.c   | 111 ++
 .../riscv/rvv/base/vzext_vf2_tu-3.c   | 111 ++
 .../riscv/rvv/base/vzext_vf2_tum-1.c  | 111 ++
 .../riscv/rvv/base/vzext_vf2_tum-2.c  | 111 ++
 .../riscv/rvv/base/vzext_vf2_tum-3.c  | 111 ++
 .../riscv/rvv/base/vzext_vf2_tumu-1.c | 111 ++
 .../riscv/rvv/base/vzext_vf2_tumu-2.c | 111 ++
 .../riscv/rvv/base/vzext_vf2_tumu-3.c | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c
new file mode 100644
index 000..f5599339a36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vzext_vf2_u16mf4(vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf2_u16mf4(op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_vzext_vf2_u16mf2(vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf2_u16mf2(op1,vl);
+}
+
+
+vuint16m1_t test___riscv_vzext_vf2_u16m1(vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf2_u16m1(op1,vl);
+}
+
+
+vuint16m2_t test___riscv_vzext_vf2_u16m2(vuint8m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf2_u16m2(op1,vl);
+}
+
+
+vuint16m4_t test___riscv_vzext_vf2_u16m4(vuint8m2_t op1,size_t vl)
+{
+return __riscv_vzext_vf2_u16m4(op1,vl);
+}
+
+
+vuint16m8_t 

[PATCH] RISC-V: Add vzext.vf4 C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vzext_vf4-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_m-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_m-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_m-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vzext_vf4-1.c   | 69 +++
 .../gcc.target/riscv/rvv/base/vzext_vf4-2.c   | 69 +++
 .../gcc.target/riscv/rvv/base/vzext_vf4-3.c   | 69 +++
 .../gcc.target/riscv/rvv/base/vzext_vf4_m-1.c | 69 +++
 .../gcc.target/riscv/rvv/base/vzext_vf4_m-2.c | 69 +++
 .../gcc.target/riscv/rvv/base/vzext_vf4_m-3.c | 69 +++
 .../riscv/rvv/base/vzext_vf4_mu-1.c   | 69 +++
 .../riscv/rvv/base/vzext_vf4_mu-2.c   | 69 +++
 .../riscv/rvv/base/vzext_vf4_mu-3.c   | 69 +++
 .../riscv/rvv/base/vzext_vf4_tu-1.c   | 69 +++
 .../riscv/rvv/base/vzext_vf4_tu-2.c   | 69 +++
 .../riscv/rvv/base/vzext_vf4_tu-3.c   | 69 +++
 .../riscv/rvv/base/vzext_vf4_tum-1.c  | 69 +++
 .../riscv/rvv/base/vzext_vf4_tum-2.c  | 69 +++
 .../riscv/rvv/base/vzext_vf4_tum-3.c  | 69 +++
 .../riscv/rvv/base/vzext_vf4_tumu-1.c | 69 +++
 .../riscv/rvv/base/vzext_vf4_tumu-2.c | 69 +++
 .../riscv/rvv/base/vzext_vf4_tumu-3.c | 69 +++
 18 files changed, 1242 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c
new file mode 100644
index 000..43df7caf4e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint32mf2_t test___riscv_vzext_vf4_u32mf2(vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf4_u32mf2(op1,vl);
+}
+
+
+vuint32m1_t test___riscv_vzext_vf4_u32m1(vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf4_u32m1(op1,vl);
+}
+
+
+vuint32m2_t test___riscv_vzext_vf4_u32m2(vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf4_u32m2(op1,vl);
+}
+
+
+vuint32m4_t test___riscv_vzext_vf4_u32m4(vuint8m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf4_u32m4(op1,vl);
+}
+
+
+vuint32m8_t test___riscv_vzext_vf4_u32m8(vuint8m2_t op1,size_t vl)
+{
+return __riscv_vzext_vf4_u32m8(op1,vl);
+}
+
+
+vuint64m1_t 

[PATCH] RISC-V: Add vzext.vf8 C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vzext_vf8-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_m-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_m-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_m-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vzext_vf8-1.c   | 34 +++
 .../gcc.target/riscv/rvv/base/vzext_vf8-2.c   | 34 +++
 .../gcc.target/riscv/rvv/base/vzext_vf8-3.c   | 34 +++
 .../gcc.target/riscv/rvv/base/vzext_vf8_m-1.c | 34 +++
 .../gcc.target/riscv/rvv/base/vzext_vf8_m-2.c | 34 +++
 .../gcc.target/riscv/rvv/base/vzext_vf8_m-3.c | 34 +++
 .../riscv/rvv/base/vzext_vf8_mu-1.c   | 34 +++
 .../riscv/rvv/base/vzext_vf8_mu-2.c   | 34 +++
 .../riscv/rvv/base/vzext_vf8_mu-3.c   | 34 +++
 .../riscv/rvv/base/vzext_vf8_tu-1.c   | 34 +++
 .../riscv/rvv/base/vzext_vf8_tu-2.c   | 34 +++
 .../riscv/rvv/base/vzext_vf8_tu-3.c   | 34 +++
 .../riscv/rvv/base/vzext_vf8_tum-1.c  | 34 +++
 .../riscv/rvv/base/vzext_vf8_tum-2.c  | 34 +++
 .../riscv/rvv/base/vzext_vf8_tum-3.c  | 34 +++
 .../riscv/rvv/base/vzext_vf8_tumu-1.c | 34 +++
 .../riscv/rvv/base/vzext_vf8_tumu-2.c | 34 +++
 .../riscv/rvv/base/vzext_vf8_tumu-3.c | 34 +++
 18 files changed, 612 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c
new file mode 100644
index 000..c0620ec27b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint64m1_t test___riscv_vzext_vf8_u64m1(vuint8mf8_t op1,size_t vl)
+{
+return __riscv_vzext_vf8_u64m1(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_vzext_vf8_u64m2(vuint8mf4_t op1,size_t vl)
+{
+return __riscv_vzext_vf8_u64m2(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_vzext_vf8_u64m4(vuint8mf2_t op1,size_t vl)
+{
+return __riscv_vzext_vf8_u64m4(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_vzext_vf8_u64m8(vuint8m1_t op1,size_t vl)
+{
+return __riscv_vzext_vf8_u64m8(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { 

[PATCH] RISC-V: Add vsext/vzext C/C++ intrinsic support

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/iterators.md: Add sign_extend/zero_extend.
* config/riscv/riscv-vector-builtins-bases.cc (class ext): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Add vsext/vzext support.
* config/riscv/riscv-vector-builtins-functions.def (vsext): New macro 
define.
(vzext): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Adjust 
for vsext/vzext support.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WEXTI_OPS): New 
macro define.
(DEF_RVV_QEXTI_OPS): Ditto.
(DEF_RVV_OEXTI_OPS): Ditto.
(DEF_RVV_WEXTU_OPS): Ditto.
(DEF_RVV_QEXTU_OPS): Ditto.
(DEF_RVV_OEXTU_OPS): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): Ditto.
(DEF_RVV_QEXTI_OPS): Ditto.
(DEF_RVV_OEXTI_OPS): Ditto.
(DEF_RVV_WEXTU_OPS): Ditto.
(DEF_RVV_QEXTU_OPS): Ditto.
(DEF_RVV_OEXTU_OPS): Ditto.
(rvv_arg_type_info::get_base_vector_type): Add sign_exted/zero_extend 
support.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
* config/riscv/vector-iterators.md (z): New attribute.
* config/riscv/vector.md (@pred__vf2): New pattern.
(@pred__vf4): Ditto.
(@pred__vf8): Ditto.

---
 gcc/config/riscv/iterators.md |   4 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  25 
 .../riscv/riscv-vector-builtins-bases.h   |   2 +
 .../riscv/riscv-vector-builtins-functions.def |   6 +
 .../riscv/riscv-vector-builtins-shapes.cc |  21 ++-
 .../riscv/riscv-vector-builtins-types.def | 104 ++
 gcc/config/riscv/riscv-vector-builtins.cc | 131 +-
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/vector-iterators.md  |  39 ++
 gcc/config/riscv/vector.md|  80 ++-
 10 files changed, 401 insertions(+), 14 deletions(-)

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 7e5415cc80b..f95dd405e12 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -207,7 +207,9 @@
 (ss_plus "ssadd")
 (us_plus "usadd")
 (ss_minus "sssub")
-(us_minus "ussub")])
+(us_minus "ussub")
+(sign_extend "extend")
+(zero_extend "zero_extend")])
 
 ;;  code attributes
 (define_code_attr or_optab [(ior "ior")
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 7e6ee1d7b53..1a9469a370a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -197,6 +197,27 @@ public:
   }
 };
 
+/* Implements vsext.vf2/vsext.vf4/vsext.vf8/vzext.vf2/vzext.vf4/vzext.vf8.  */
+template
+class ext : public function_base
+{
+public:
+  rtx expand (function_expander ) const override
+  {
+switch (e.op_info->op)
+  {
+  case OP_TYPE_vf2:
+   return e.use_exact_insn (code_for_pred_vf2 (CODE, e.vector_mode ()));
+  case OP_TYPE_vf4:
+   return e.use_exact_insn (code_for_pred_vf4 (CODE, e.vector_mode ()));
+  case OP_TYPE_vf8:
+   return e.use_exact_insn (code_for_pred_vf8 (CODE, e.vector_mode ()));
+  default:
+   gcc_unreachable ();
+  }
+  }
+};
+
 static CONSTEXPR const vsetvl vsetvl_obj;
 static CONSTEXPR const vsetvl vsetvlmax_obj;
 static CONSTEXPR const loadstore vle_obj;
@@ -241,6 +262,8 @@ static CONSTEXPR const binop vdivu_obj;
 static CONSTEXPR const binop vremu_obj;
 static CONSTEXPR const unop vneg_obj;
 static CONSTEXPR const unop vnot_obj;
+static CONSTEXPR const ext vsext_obj;
+static CONSTEXPR const ext vzext_obj;
 static CONSTEXPR const binop vsadd_obj;
 static CONSTEXPR const binop vssub_obj;
 static CONSTEXPR const binop vsaddu_obj;
@@ -295,6 

Re: [PATCH v3] c++: -Wdangling-reference with reference wrapper [PR107532]

[Jason Merrill via Gcc-patches]

On 1/24/23 17:49, Marek Polacek wrote:

On Fri, Jan 20, 2023 at 03:19:54PM -0500, Jason Merrill wrote:

On 1/19/23 21:03, Marek Polacek wrote:

On Thu, Jan 19, 2023 at 01:02:02PM -0500, Jason Merrill wrote:

On 1/18/23 20:13, Marek Polacek wrote:

On Wed, Jan 18, 2023 at 04:07:59PM -0500, Jason Merrill wrote:

On 1/18/23 12:52, Marek Polacek wrote:

Here, -Wdangling-reference triggers where it probably shouldn't, causing
some grief.  The code in question uses a reference wrapper with a member
function returning a reference to a subobject of a non-temporary object:

  const Plane & meta = fm.planes().inner();

I've tried a few approaches, e.g., checking that the member function's
return type is the same as the type of the enclosing class (which is
the case for member functions returning *this), but that then breaks
Wdangling-reference4.C with std::optional.

So I figured that perhaps we want to look at the object we're invoking
the member function(s) on and see if that is a temporary, as in, don't
warn about

  const Plane & meta = fm.planes().inner();

but do warn about

  const Plane & meta = FrameMetadata().planes().inner();

It's ugly, but better than asking users to add #pragmas into their code.


Hmm, that doesn't seem right; the former is only OK because Ref is in fact a
reference-like type.  If planes() returned a class that held data, we would
want to warn.


Sure, it's always some kind of tradeoff with warnings :/.

In this case, we might recognize the reference-like class because it has a
reference member and a constructor taking the same reference type.


That occurred to me too, but then I found out that std::reference_wrapper
actually uses T*, not T&, as you say.  But here's a patch to do that
(I hope).

That wouldn't help with std::reference_wrapper or std::ref_view because they
have pointer members instead of references, but perhaps loosening the check
to include that case would make sense?


Sorry, I don't understand what you mean by loosening the check.  I could
hardcode std::reference_wrapper and std::ref_view but I don't think that's
what you meant.


Indeed that's not what I meant, but as I was saying in our meeting I think
it's worth doing; the compiler has various tweaks to handle specific
standard-library classes better.

Okay, done in the patch below.  Except that I'm not including a test for
std::ranges::ref_view because I don't really know how that works.


Surely I cannot _not_ warn for any class that contains a T*.


I was thinking if a constructor takes a T& and the class has a T* that would
be close enough, though this also wouldn't handle the standard library
classes so the benefit is questionable.


Here's the patch so that we have some actual code to discuss...  Thanks.

-- >8 --
Here, -Wdangling-reference triggers where it probably shouldn't, causing
some grief.  The code in question uses a reference wrapper with a member
function returning a reference to a subobject of a non-temporary object:

 const Plane & meta = fm.planes().inner();

I've tried a few approaches, e.g., checking that the member function's
return type is the same as the type of the enclosing class (which is
the case for member functions returning *this), but that then breaks
Wdangling-reference4.C with std::optional.

Perhaps we want to look at the member function's enclosing class
to see if it's a reference wrapper class (meaning, has a reference
member and a constructor taking the same reference type) and don't
warn if so, supposing that the member function returns a reference
to a non-temporary object.

It's ugly, but better than asking users to add #pragmas into their code.

PR c++/107532

gcc/cp/ChangeLog:

* call.cc (do_warn_dangling_reference): Don't warn when the
member function comes from a reference wrapper class.


Let's factor the new code out into e.g. reference_like_class_p


Done.  Thanks,

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?

-- >8 --
Here, -Wdangling-reference triggers where it probably shouldn't, causing
some grief.  The code in question uses a reference wrapper with a member
function returning a reference to a subobject of a non-temporary object:

const Plane & meta = fm.planes().inner();

I've tried a few approaches, e.g., checking that the member function's
return type is the same as the type of the enclosing class (which is
the case for member functions returning *this), but that then breaks
Wdangling-reference4.C with std::optional.

Perhaps we want to look at the member function's enclosing class
to see if it's a reference wrapper class (meaning, has a reference
member and a constructor taking the same reference type, or is
std::reference_wrapper or std::ranges::ref_view) and don't warn if so,
supposing that the member function returns a reference to a non-temporary
object.

It's ugly, but better than asking users to add #pragmas into their code.

PR c++/107532

gcc/cp/ChangeLog:

* call.cc 

Re: [PATCH 2/4] libbacktrace: detect executable path on windows

[Ian Lance Taylor via Gcc-patches]

On Sun, Feb 5, 2023 at 1:21 AM Björn Schäpers  wrote:
>
> Am 24.01.2023 um 19:32 schrieb Ian Lance Taylor:
> > On Tue, Jan 24, 2023 at 10:12 AM Eli Zaretskii via Gcc-patches
> >  wrote:
> >>
> >>> From: Ian Lance Taylor 
> >>> Date: Tue, 24 Jan 2023 09:58:10 -0800
> >>> Cc: g...@hazardy.de, gcc-patches@gcc.gnu.org, g...@gcc.gnu.org
> >>>
> >>> I'd rather that the patch look like the appended.  Can someone with a
> >>> Windows system test to see what that builds and passes the tests?
> >>
> >> ENOPATCH
> >
> > Gah.
> >
> > Ian
> >
> That seems to be my original patch, right? That one I have tested (and
> am actually using) on x86 and x64 windows.

It's very similar but I changed the windows_get_executable_path function.

Ian

Re: *PING* [PATCH] Fortran: prevent redundant integer division truncation warnings [PR108592]

[Jerry D via Gcc-patches]

On 2/5/23 11:33 AM, Harald Anlauf via Fortran wrote:

Early gentle ping.

Am 30.01.23 um 22:55 schrieb Harald Anlauf via Gcc-patches:

Dear Fortranners,

the subject says it all: in some cases we emit redundant integer division
truncation warnings (2 or 4), where just one would have been sufficient.
This is solved by using gfc_warning instead of gfc_warning_now.

The testcase uses a suggestion by Andrew to verify that we get the
desired warning exactly once.

Regtested on x86_64-pc-linux-gnu.  OK for mainline?

Thanks,
Harald





The patch is gentle enough to be OK to commit.

Thanks,

Jerry

Re: [PATCH 2/2] c++: speculative constexpr and is_constant_evaluated [PR108243]

[Jason Merrill via Gcc-patches]

On 2/3/23 15:51, Patrick Palka wrote:

On Mon, 30 Jan 2023, Jason Merrill wrote:


On 1/27/23 17:02, Patrick Palka wrote:

This PR illustrates that __builtin_is_constant_evaluated currently acts
as an optimization barrier for our speculative constexpr evaluation,
since we don't want to prematurely fold the builtin to false if the
expression in question would be later manifestly constant evaluated (in
which case it must be folded to true).

This patch fixes this by permitting __builtin_is_constant_evaluated
to get folded as false during cp_fold_function, since at that point
we're sure we're doing manifestly constant evaluation.  To that end
we add a flags parameter to cp_fold that controls what mce_value the
CALL_EXPR case passes to maybe_constant_value.

bootstrapped and rgetsted no x86_64-pc-linux-gnu, does this look OK for
trunk?

PR c++/108243

gcc/cp/ChangeLog:

* cp-gimplify.cc (enum fold_flags): Define.
(cp_fold_data::genericize): Replace this data member with ...
(cp_fold_data::fold_flags): ... this.
(cp_fold_r): Adjust cp_fold_data use and cp_fold_calls.
(cp_fold_function): Likewise.
(cp_fold_maybe_rvalue): Likewise.
(cp_fully_fold_init): Likewise.
(cp_fold): Add fold_flags parameter.  Don't cache if flags
isn't empty.
: Pass mce_false to maybe_constant_value
if if ff_genericize is set.

gcc/testsuite/ChangeLog:

* g++.dg/opt/pr108243.C: New test.
---
   gcc/cp/cp-gimplify.cc   | 76 ++---
   gcc/testsuite/g++.dg/opt/pr108243.C | 29 +++
   2 files changed, 76 insertions(+), 29 deletions(-)
   create mode 100644 gcc/testsuite/g++.dg/opt/pr108243.C

diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
index a35cedd05cc..d023a63768f 100644
--- a/gcc/cp/cp-gimplify.cc
+++ b/gcc/cp/cp-gimplify.cc
@@ -43,12 +43,20 @@ along with GCC; see the file COPYING3.  If not see
   #include "omp-general.h"
   #include "opts.h"
   +/* Flags for cp_fold and cp_fold_r.  */
+
+enum fold_flags {
+  ff_none = 0,
+  /* Whether we're being called from cp_fold_function.  */
+  ff_genericize = 1 << 0,
+};
+
   /* Forward declarations.  */
 static tree cp_genericize_r (tree *, int *, void *);
   static tree cp_fold_r (tree *, int *, void *);
   static void cp_genericize_tree (tree*, bool);
-static tree cp_fold (tree);
+static tree cp_fold (tree, fold_flags);
 /* Genericize a TRY_BLOCK.  */
   @@ -996,9 +1004,8 @@ struct cp_genericize_data
   struct cp_fold_data
   {
 hash_set pset;
-  bool genericize; // called from cp_fold_function?
-
-  cp_fold_data (bool g): genericize (g) {}
+  fold_flags flags;
+  cp_fold_data (fold_flags flags): flags (flags) {}
   };
 static tree
@@ -1039,7 +1046,7 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void
*data_)
 break;
   }
   -  *stmt_p = stmt = cp_fold (*stmt_p);
+  *stmt_p = stmt = cp_fold (*stmt_p, data->flags);
   if (data->pset.add (stmt))
   {
@@ -1119,12 +1126,12 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void
*data_)
 here rather than in cp_genericize to avoid problems with the
invisible
 reference transition.  */
   case INIT_EXPR:
-  if (data->genericize)
+  if (data->flags & ff_genericize)
cp_genericize_init_expr (stmt_p);
 break;
 case TARGET_EXPR:
-  if (data->genericize)
+  if (data->flags & ff_genericize)
cp_genericize_target_expr (stmt_p);
   /* Folding might replace e.g. a COND_EXPR with a TARGET_EXPR; in
@@ -1157,7 +1164,7 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void
*data_)
   void
   cp_fold_function (tree fndecl)
   {
-  cp_fold_data data (/*genericize*/true);
+  cp_fold_data data (ff_genericize);
 cp_walk_tree (_SAVED_TREE (fndecl), cp_fold_r, , NULL);
   }
   @@ -2375,7 +2382,7 @@ cp_fold_maybe_rvalue (tree x, bool rval)
   {
 while (true)
   {
-  x = cp_fold (x);
+  x = cp_fold (x, ff_none);
 if (rval)
x = mark_rvalue_use (x);
 if (rval && DECL_P (x)
@@ -2434,7 +2441,7 @@ cp_fully_fold_init (tree x)
 if (processing_template_decl)
   return x;
 x = cp_fully_fold (x);
-  cp_fold_data data (/*genericize*/false);
+  cp_fold_data data (ff_none);
 cp_walk_tree (, cp_fold_r, , NULL);
 return x;
   }
@@ -2469,7 +2476,7 @@ clear_fold_cache (void)
   Function returns X or its folded variant.  */
 static tree
-cp_fold (tree x)
+cp_fold (tree x, fold_flags flags)
   {
 tree op0, op1, op2, op3;
 tree org_x = x, r = NULL_TREE;
@@ -2490,8 +2497,11 @@ cp_fold (tree x)
 if (fold_cache == NULL)
   fold_cache = hash_map::create_ggc (101);
   -  if (tree *cached = fold_cache->get (x))
-return *cached;
+  bool cache_p = (flags == ff_none);
+
+  if (cache_p)
+if (tree *cached = fold_cache->get (x))
+  return *cached;
   uid_sensitive_constexpr_evaluation_checker c;
   @@ -2526,7 +2536,7 @@ cp_fold (tree x)

*PING* [PATCH] Fortran: prevent redundant integer division truncation warnings [PR108592]

[Harald Anlauf via Gcc-patches]

Early gentle ping.

Am 30.01.23 um 22:55 schrieb Harald Anlauf via Gcc-patches:

Dear Fortranners,

the subject says it all: in some cases we emit redundant integer division
truncation warnings (2 or 4), where just one would have been sufficient.
This is solved by using gfc_warning instead of gfc_warning_now.

The testcase uses a suggestion by Andrew to verify that we get the
desired warning exactly once.

Regtested on x86_64-pc-linux-gnu.  OK for mainline?

Thanks,
Harald

Re: [PATCH] c++: equivalence of non-dependent calls [PR107461]

[Jason Merrill via Gcc-patches]

On 2/5/23 09:57, Patrick Palka wrote:

On Sat, 4 Feb 2023, Jason Merrill wrote:


On 2/4/23 20:41, Jason Merrill wrote:

On 2/4/23 20:08, Patrick Palka wrote:

On Sat, 4 Feb 2023, Jason Merrill wrote:


On 2/4/23 15:31, Patrick Palka wrote:

After r13-5684-g59e0376f607805 the (pruned) callee of a non-dependent
CALL_EXPR is a bare FUNCTION_DECL rather than ADDR_EXPR of
FUNCTION_DECL.
This innocent change revealed that cp_tree_equal doesn't first check
dependentness of a CALL_EXPR before treating the callee as a dependent
name, which manifests as us incorrectly accepting the first two
testcases below and rejecting the third:

    * In the first testcase, cp_tree_equal incorrectly returns true for
  the two non-dependent CALL_EXPRs f(0) and f(0) (whose
CALL_EXPR_FN
  are different FUNCTION_DECLs) and so we treat #2 as a
redeclaration
  of #1.

    * Same issue in the second testcase, for f() and f().

    * In the third testcase, cp_tree_equal incorrectly returns true for
  f() and f() which causes us to conflate the
two
  dependent specializations A()(U()))> and
  A()(U()))>, leading to a bogus error.

This patch fixes this by making called_fns_equal treat two callees as
dependent names only if the CALL_EXPRs in question are dependent.

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK
for
trunk/12?  Patch generated with -w to ignore noisy whitespace changes.

 PR c++/107461

gcc/cp/ChangeLog:

 * pt.cc (iterative_hash_template_arg) : Treat
 the callee as a dependent name only if the CALL_EXPR is
 dependent.
 * tree.cc (called_fns_equal): Take two CALL_EXPRs instead of
 CALL_EXPR_FNs thereof.  As above.
 (cp_tree_equal) : Adjust call to called_fns_equal.

gcc/testsuite/ChangeLog:

 * g++.dg/cpp0x/overload5.C: New test.
 * g++.dg/cpp0x/overload5a.C: New test.
 * g++.dg/cpp0x/overload6.C: New test.
---
    gcc/cp/pt.cc    |  1 +
    gcc/cp/tree.cc  | 33
++---
    gcc/testsuite/g++.dg/cpp0x/overload5.C  | 12 +
    gcc/testsuite/g++.dg/cpp0x/overload5a.C | 10 
    gcc/testsuite/g++.dg/cpp0x/overload6.C  | 16 
    5 files changed, 58 insertions(+), 14 deletions(-)
    create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload5.C
    create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload5a.C
    create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload6.C

diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index 255332dc0c1..c9360240cd2 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -1841,6 +1841,7 @@ iterative_hash_template_arg (tree arg, hashval_t
val)
    case CALL_EXPR:
  {
    tree fn = CALL_EXPR_FN (arg);
+    if (TREE_TYPE (arg) == NULL_TREE)


How about changing dependent_name to take the CALL_EXPR rather than the
CALL_EXPR_FN?  That would mean some changes to write_expression to move
the
dependent_name handling into the CALL_EXPR handling, but that doesn't
seem
like a bad thing.  Other callers seem like a trivial change.


Indeed changing dependent_name seems best, but I'm worried about such a
refactoring to write_expression causing unintended mangling changes at
this stage.  Because it seems the CALL_EXPR case of write_expression
isn't the user of the dependent_name branch of write_expression, at
least according to the following patch which causes us to ICE on
mangle{37,57,58,76}.C:


Yeah, I tried the same thing.  Maybe for GCC 13 better to add a new function
rather than change the current one.


Sounds good, like so?  Only regtested so far.  Full bootstrap and
regtest running on x86_64-pc-linux-gnu.

-- >8 --

Subject: [PATCH] c++: equivalence of non-dependent calls [PR107461]

After r13-5684-g59e0376f607805 the (pruned) callee of a non-dependent
CALL_EXPR is a bare FUNCTION_DECL rather than ADDR_EXPR of FUNCTION_DECL.
This innocent change revealed that cp_tree_equal doesn't first check
dependentness of a CALL_EXPR before treating a FUNCTION_DECL callee as a
dependent name, which manifests as us incorrectly accepting the first
two testcases below and rejecting the third:

  * In the first testcase, cp_tree_equal incorrectly returns true for
the two non-dependent CALL_EXPRs f(0) and f(0) (whose CALL_EXPR_FN
are different FUNCTION_DECLs) and so we treat #2 as a redeclaration
of #1.

  * Same issue in the second testcase, for f() and f().

  * In the third testcase, cp_tree_equal incorrectly returns true for
f() and f() which causes us to conflate the two
dependent specializations A()(U()))> and
A()(U()))>, leading to a bogus error.

This patch fixes this by making called_fns_equal treat two callees as
dependent names only if the overall CALL_EXPRs are dependent, via a new
convenience function call_expr_dependent_name that is like dependent_name
but also checks dependence of the overall CALL_EXPR.

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk/12?  Patch generated with -w 

[pushed] doc: Remove note on PW32

[Gerald Pfeifer]

Indeed looking at http://pw32.sourceforge.net indicates this has gone the 
way of the dodo.

Pushed.

Gerald


gcc/ChangeLog:

* doc/install.texi (Specific): Remove PW32.
---
 gcc/doc/install.texi | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index b1861a6a437..8ef5c1414da 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -5182,9 +5182,6 @@ support the Interix subsystem.  See above.
 
 Old target names including *-*-winnt and *-*-windowsnt are no longer used.
 
-PW32 (i386-pc-pw32) support was never completed, and the project seems to
-be inactive.  See @uref{http://pw32.sourceforge.net/} for more information.
-
 UWIN support has been removed due to a lack of maintenance.
 
 @html
-- 
2.39.1

[pushed] wwwdocs: mirrors: Remove ftp.uvsq.fr mirror

[Gerald Pfeifer]

ftp.uvsq.fr has been unreachable for an extensive period of time
(tested from different networks).

Thank you for your service in the past, ftpma...@uvsq.fr!

Gerald
---
 htdocs/mirrors.html | 1 -
 1 file changed, 1 deletion(-)

diff --git a/htdocs/mirrors.html b/htdocs/mirrors.html
index 963fc7c3..b49aa76c 100644
--- a/htdocs/mirrors.html
+++ b/htdocs/mirrors.html
@@ -19,7 +19,6 @@ mirrors.  The following sites mirror the gcc.gnu.org 
download site
 
 France (no snapshots): ftp://ftp.lip6.fr/pub/gcc/;>ftp.lip6.fr, thanks to 
ftpma...@lip6.fr
 France, Brittany: ftp://ftp.irisa.fr/pub/mirrors/gcc.gnu.org/gcc/;>ftp.irisa.fr, thanks 
to ftpma...@irisa.fr
-France, Versailles: ftp://ftp.uvsq.fr/pub/gcc/;>ftp.uvsq.fr, 
thanks to ftpma...@uvsq.fr
 Germany, Berlin: https://ftp.fu-berlin.de/unix/languages/gcc/;>ftp.fu-berlin.de, 
thanks to f...@fu-berlin.de
 Germany: https://ftp.gwdg.de/pub/misc/gcc/;>ftp.gwdg.de, 
thanks to f...@gwdg.de
 Germany: https://ftp.mpi-inf.mpg.de/mirrors/gnu/mirror/gcc.gnu.org/pub/gcc/;>mpi-sb.mpg.de,
 thanks to ftpad...@mpi-sb.mpg.de
-- 
2.39.1

Re: libquadmath fix for 94756 and 87204

[NightStrike via Gcc-patches]

Jakub, ping

On Thu, Jan 26, 2023, 12:50 i.nixman--- via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:

> hello,
>
> could someone look at the patch attached please?
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610392.html
>

Re: [PATCH] c++: equivalence of non-dependent calls [PR107461]

[Patrick Palka via Gcc-patches]

On Sat, 4 Feb 2023, Jason Merrill wrote:

> On 2/4/23 20:41, Jason Merrill wrote:
> > On 2/4/23 20:08, Patrick Palka wrote:
> > > On Sat, 4 Feb 2023, Jason Merrill wrote:
> > > 
> > > > On 2/4/23 15:31, Patrick Palka wrote:
> > > > > After r13-5684-g59e0376f607805 the (pruned) callee of a non-dependent
> > > > > CALL_EXPR is a bare FUNCTION_DECL rather than ADDR_EXPR of
> > > > > FUNCTION_DECL.
> > > > > This innocent change revealed that cp_tree_equal doesn't first check
> > > > > dependentness of a CALL_EXPR before treating the callee as a dependent
> > > > > name, which manifests as us incorrectly accepting the first two
> > > > > testcases below and rejecting the third:
> > > > > 
> > > > >    * In the first testcase, cp_tree_equal incorrectly returns true for
> > > > >  the two non-dependent CALL_EXPRs f(0) and f(0) (whose
> > > > > CALL_EXPR_FN
> > > > >  are different FUNCTION_DECLs) and so we treat #2 as a
> > > > > redeclaration
> > > > >  of #1.
> > > > > 
> > > > >    * Same issue in the second testcase, for f() and f().
> > > > > 
> > > > >    * In the third testcase, cp_tree_equal incorrectly returns true for
> > > > >  f() and f() which causes us to conflate the
> > > > > two
> > > > >  dependent specializations A()(U()))> and
> > > > >  A()(U()))>, leading to a bogus error.
> > > > > 
> > > > > This patch fixes this by making called_fns_equal treat two callees as
> > > > > dependent names only if the CALL_EXPRs in question are dependent.
> > > > > 
> > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK
> > > > > for
> > > > > trunk/12?  Patch generated with -w to ignore noisy whitespace changes.
> > > > > 
> > > > > PR c++/107461
> > > > > 
> > > > > gcc/cp/ChangeLog:
> > > > > 
> > > > > * pt.cc (iterative_hash_template_arg) : Treat
> > > > > the callee as a dependent name only if the CALL_EXPR is
> > > > > dependent.
> > > > > * tree.cc (called_fns_equal): Take two CALL_EXPRs instead of
> > > > > CALL_EXPR_FNs thereof.  As above.
> > > > > (cp_tree_equal) : Adjust call to called_fns_equal.
> > > > > 
> > > > > gcc/testsuite/ChangeLog:
> > > > > 
> > > > > * g++.dg/cpp0x/overload5.C: New test.
> > > > > * g++.dg/cpp0x/overload5a.C: New test.
> > > > > * g++.dg/cpp0x/overload6.C: New test.
> > > > > ---
> > > > >    gcc/cp/pt.cc    |  1 +
> > > > >    gcc/cp/tree.cc  | 33
> > > > > ++---
> > > > >    gcc/testsuite/g++.dg/cpp0x/overload5.C  | 12 +
> > > > >    gcc/testsuite/g++.dg/cpp0x/overload5a.C | 10 
> > > > >    gcc/testsuite/g++.dg/cpp0x/overload6.C  | 16 
> > > > >    5 files changed, 58 insertions(+), 14 deletions(-)
> > > > >    create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload5.C
> > > > >    create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload5a.C
> > > > >    create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload6.C
> > > > > 
> > > > > diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
> > > > > index 255332dc0c1..c9360240cd2 100644
> > > > > --- a/gcc/cp/pt.cc
> > > > > +++ b/gcc/cp/pt.cc
> > > > > @@ -1841,6 +1841,7 @@ iterative_hash_template_arg (tree arg, hashval_t
> > > > > val)
> > > > >    case CALL_EXPR:
> > > > >  {
> > > > >    tree fn = CALL_EXPR_FN (arg);
> > > > > +    if (TREE_TYPE (arg) == NULL_TREE)
> > > > 
> > > > How about changing dependent_name to take the CALL_EXPR rather than the
> > > > CALL_EXPR_FN?  That would mean some changes to write_expression to move
> > > > the
> > > > dependent_name handling into the CALL_EXPR handling, but that doesn't
> > > > seem
> > > > like a bad thing.  Other callers seem like a trivial change.
> > > 
> > > Indeed changing dependent_name seems best, but I'm worried about such a
> > > refactoring to write_expression causing unintended mangling changes at
> > > this stage.  Because it seems the CALL_EXPR case of write_expression
> > > isn't the user of the dependent_name branch of write_expression, at
> > > least according to the following patch which causes us to ICE on
> > > mangle{37,57,58,76}.C:
> > 
> > Yeah, I tried the same thing.  Maybe for GCC 13 better to add a new function
> > rather than change the current one.

Sounds good, like so?  Only regtested so far.  Full bootstrap and
regtest running on x86_64-pc-linux-gnu.

-- >8 --

Subject: [PATCH] c++: equivalence of non-dependent calls [PR107461]

After r13-5684-g59e0376f607805 the (pruned) callee of a non-dependent
CALL_EXPR is a bare FUNCTION_DECL rather than ADDR_EXPR of FUNCTION_DECL.
This innocent change revealed that cp_tree_equal doesn't first check
dependentness of a CALL_EXPR before treating a FUNCTION_DECL callee as a
dependent name, which manifests as us incorrectly accepting the first
two testcases below and rejecting the third:

 * In the first testcase, cp_tree_equal incorrectly returns true for
   the two non-dependent CALL_EXPRs f(0) and f(0) (whose 

Re: [PATCH 2/4] libbacktrace: detect executable path on windows

[Björn Schäpers]

Am 24.01.2023 um 19:32 schrieb Ian Lance Taylor:

On Tue, Jan 24, 2023 at 10:12 AM Eli Zaretskii via Gcc-patches
 wrote:



From: Ian Lance Taylor 
Date: Tue, 24 Jan 2023 09:58:10 -0800
Cc: g...@hazardy.de, gcc-patches@gcc.gnu.org, g...@gcc.gnu.org

I'd rather that the patch look like the appended.  Can someone with a
Windows system test to see what that builds and passes the tests?


ENOPATCH


Gah.

Ian

That seems to be my original patch, right? That one I have tested (and 
am actually using) on x86 and x64 windows.