Re: [PATCH 1/1] [V2] [RISC-V] support cm.push cm.pop cm.popret in zcmp

[Sinan via Gcc-patches]

>> +/* Return TRUE if Zcmp push and pop insns should be
>> + avoided. FALSE otherwise.
>> + Only use multi push & pop if all GPRs masked can be covered,
>> + and stack access is SP based,
>> + and GPRs are at top of the stack frame,
>> + and no conflicts in stack allocation with other features */
>> +static bool
>> +riscv_avoid_multi_push(const struct riscv_frame_info *frame)
>> +{
>> + if (!TARGET_ZCMP
>> + || crtl->calls_eh_return
>> + || frame_pointer_needed
>> + || cfun->machine->interrupt_handler_p
>> + || cfun->machine->varargs_size != 0
>> + || crtl->args.pretend_args_size != 0
>> + || (frame->mask & ~ MULTI_PUSH_GPR_MASK))
>> + return true;
>> +
>> + return false;
>> +}
Any reason to skip generating push/pop in the cases where a frame pointer is 
needed?
IIRC, only code compiled with O1 and above will omit frame pointer, if so then 
code with
O0 will never generate cm.push/pop. 
Same question for interrupt_handler_p. I think cm.push/pop can handle this 
case. e.g.
the test case zc-zcmp-push-pop-6.c from Jiawei's patch.
BR,
Sinan
--
Sender:Fei Gao 
Sent At:2023 May 16 (Tue.) 17:34
Recipient:sinan.lin ; jiawei ; 
shihua ; lidie 
Cc:Fei Gao 
Subject:[PATCH 1/1] [V2] [RISC-V] support cm.push cm.pop cm.popret in zcmp
Zcmp can share the same logic as save-restore in stack allocation: 
pre-allocation
by cm.push, step 1 and step 2.
please be noted cm.push pushes ra, s0-s11 in reverse order than what 
save-restore does.
So adaption has been done in .cfi directives in my patch.
gcc/ChangeLog:
 * config/riscv/predicates.md (slot_0_offset_operand): predicates for slot 0 
offset.
 (slot_1_offset_operand): likewise
 (slot_2_offset_operand): likewise
 (slot_3_offset_operand): likewise
 (slot_4_offset_operand): likewise
 (slot_5_offset_operand): likewise
 (slot_6_offset_operand): likewise
 (slot_7_offset_operand): likewise
 (slot_8_offset_operand): likewise
 (slot_9_offset_operand): likewise
 (slot_10_offset_operand): likewise
 (slot_11_offset_operand): likewise
 (slot_12_offset_operand): likewise
 (stack_push_up_to_ra_operand): predicates for stack adjust of pushing ra
 (stack_push_up_to_s0_operand): predicates for stack adjust of pushing ra, s0
 (stack_push_up_to_s1_operand): likewise
 (stack_push_up_to_s2_operand): likewise
 (stack_push_up_to_s3_operand): likewise
 (stack_push_up_to_s4_operand): likewise
 (stack_push_up_to_s5_operand): likewise
 (stack_push_up_to_s6_operand): likewise
 (stack_push_up_to_s7_operand): likewise
 (stack_push_up_to_s8_operand): likewise
 (stack_push_up_to_s9_operand): likewise
 (stack_push_up_to_s11_operand): likewise
 (stack_pop_up_to_ra_operand): predicates for stack adjust of poping ra
 (stack_pop_up_to_s0_operand): predicates for stack adjust of poping ra, s0
 (stack_pop_up_to_s1_operand): likewise
 (stack_pop_up_to_s2_operand): likewise
 (stack_pop_up_to_s3_operand): likewise
 (stack_pop_up_to_s4_operand): likewise
 (stack_pop_up_to_s5_operand): likewise
 (stack_pop_up_to_s6_operand): likewise
 (stack_pop_up_to_s7_operand): likewise
 (stack_pop_up_to_s8_operand): likewise
 (stack_pop_up_to_s9_operand): likewise
 (stack_pop_up_to_s11_operand): likewise
 * config/riscv/riscv-protos.h (riscv_zcmp_valid_slot_offset_p): declaration
 (riscv_zcmp_valid_stack_adj_bytes_p): declaration
 * config/riscv/riscv.cc (struct riscv_frame_info): comment change
 (riscv_avoid_multi_push): helper function of riscv_use_multi_push
 (riscv_use_multi_push): true if multi push is used
 (riscv_multi_push_sregs_count): num of sregs in multi-push
 (riscv_multi_push_regs_count): num of regs in multi-push
 (riscv_16bytes_align): align to 16 bytes
 (riscv_stack_align): moved to a better place
 (riscv_save_libcall_count): no functional change
 (riscv_compute_frame_info): add zcmp frame info
 (riscv_adjust_multi_push_cfi_prologue): adjust cfi for cm.push
 (get_slot_offset_rtx): get the rtx of slot to push or pop
 (riscv_gen_multi_push_pop_insn): gen function for multi push and pop
 (riscv_expand_prologue): allocate stack by cm.push
 (riscv_adjust_multi_pop_cfi_epilogue): adjust cfi for cm.pop[ret]
 (riscv_expand_epilogue): allocate stack by cm.pop[ret]
 (zcmp_base_adj): calculate stack adjustment base size
 (zcmp_additional_adj): calculate stack adjustment additional size
 (riscv_zcmp_valid_slot_offset_p): check if offset is valid for a slot
 (riscv_zcmp_valid_stack_adj_bytes_p): check if stack adjustment size is valid
 * config/riscv/riscv.h (RETURN_ADDR_MASK): mask of ra
 (S0_MASK): likewise
 (S1_MASK): likewise
 (S2_MASK): likewise
 (S3_MASK): likewise
 (S4_MASK): likewise
 (S5_MASK): likewise
 (S6_MASK): likewise
 (S7_MASK): likewise
 (S8_MASK): likewise
 (S9_MASK): likewise
 (S10_MASK): likewise
 (S11_MASK): likewise
 (MULTI_PUSH_GPR_MASK): GPR_MASK that cm.push can cover at most
 (ZCMP_MAX_SPIMM): max spimm value
 (ZCMP_SP_INC_STEP): zcmp sp increment step
 (ZCMP_INVALID_S0S10_SREGS_COUNTS): num of s0-s10
 (ZCMP_S0S11_SREGS_COUNTS): num of 

Re: [PATCH v1] tree-ssa-sink: Improve code sinking pass.

[Ajit Agarwal via Gcc-patches]

Hello Richard:

On 22/05/23 6:26 pm, Richard Biener wrote:
> On Thu, May 18, 2023 at 9:14 AM Ajit Agarwal  wrote:
>>
>> Hello All:
>>
>> This patch improves code sinking pass to sink statements before call to 
>> reduce
>> register pressure.
>> Review comments are incorporated.
>>
>> Bootstrapped and regtested on powerpc64-linux-gnu.
>>
>> Thanks & Regards
>> Ajit
>>
>>
>> tree-ssa-sink: Improve code sinking pass.
>>
>> Code Sinking sinks the blocks after call. This increases
>> register pressure for callee-saved registers. Improves
>> code sinking before call in the use blocks or immediate
>> dominator of use blocks.
>>
>> 2023-05-18  Ajit Kumar Agarwal  
>>
>> gcc/ChangeLog:
>>
>> * tree-ssa-sink.cc (statement_sink_location): Modifed to
>> move statements before calls.
>> (block_call_p): New function.
>> (def_use_same_block): New function.
>> (select_best_block): Add heuristics to select the best
>> blocks in the immediate post dominator.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.dg/tree-ssa/ssa-sink-20.c: New testcase.
>> * gcc.dg/tree-ssa/ssa-sink-21.c: New testcase.
>> ---
>>  gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-20.c |  16 ++
>>  gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-21.c |  20 +++
>>  gcc/tree-ssa-sink.cc| 159 ++--
>>  3 files changed, 185 insertions(+), 10 deletions(-)
>>  create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-20.c
>>  create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-21.c
>>
>> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-20.c 
>> b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-20.c
>> new file mode 100644
>> index 000..716bc1f9257
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-20.c
>> @@ -0,0 +1,16 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -fdump-tree-sink -fdump-tree-optimized 
>> -fdump-tree-sink-stats" } */
>> +
>> +void bar();
>> +int j;
>> +void foo(int a, int b, int c, int d, int e, int f)
>> +{
>> +  int l;
>> +  l = a + b + c + d +e + f;
>> +  if (a != 5)
>> +{
>> +  bar();
>> +  j = l;
>> +}
>> +}
>> +/* { dg-final { scan-tree-dump-times "Sunk statements: 5" 1 "sink" } } */
> 
> this doesn't verify the place we sink to?
>

I am not sure how to verify the place we sink to with dg-final.
 
>> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-21.c 
>> b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-21.c
>> new file mode 100644
>> index 000..ff41e2ea8ae
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-21.c
>> @@ -0,0 +1,20 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -fdump-tree-sink-stats -fdump-tree-sink-stats" } */
>> +
>> +void bar();
>> +int j, x;
>> +void foo(int a, int b, int c, int d, int e, int f)
>> +{
>> +  int l;
>> +  l = a + b + c + d +e + f;
>> +  if (a != 5)
>> +{
>> +  bar();
>> +  if (b != 3)
>> +x = 3;
>> +  else
>> +x = 5;
>> +  j = l;
>> +}
>> +}
>> +/* { dg-final { scan-tree-dump-times "Sunk statements: 5" 1 "sink" } } */
> 
> likewise.  So both tests already pass before the patch?
> 
>> diff --git a/gcc/tree-ssa-sink.cc b/gcc/tree-ssa-sink.cc
>> index 87b1d40c174..76556e7795b 100644
>> --- a/gcc/tree-ssa-sink.cc
>> +++ b/gcc/tree-ssa-sink.cc
>> @@ -171,6 +171,72 @@ nearest_common_dominator_of_uses (def_operand_p def_p, 
>> bool *debug_stmts)
>>return commondom;
>>  }
>>
>> +/* Return TRUE if immediate uses of the defs in
>> +   USE occur in the same block as USE, FALSE otherwise.  */
>> +
>> +bool
>> +def_use_same_block (gimple *stmt)
>> +{
>> +  use_operand_p use_p;
>> +  def_operand_p def_p;
>> +  imm_use_iterator imm_iter;
>> +  ssa_op_iter iter;
>> +
>> +  FOR_EACH_SSA_DEF_OPERAND (def_p, stmt, iter, SSA_OP_DEF)
>> +{
>> +  FOR_EACH_IMM_USE_FAST (use_p, imm_iter, DEF_FROM_PTR (def_p))
>> +   {
>> + if (is_gimple_debug (USE_STMT (use_p)))
>> +   continue;
>> +
>> + if (use_p
> 
> use_p is never null
> 
>> + && (gimple_bb (USE_STMT (use_p)) == gimple_bb (stmt)))
>> +   return true;
> 
> the function behavior is obviously odd ...
> 
>> +   }
>> + }
>> +  return false;
>> +}
>> +
>> +/* Return TRUE if the block has only calls, FALSE otherwise. */
>> +
>> +bool
>> +block_call_p (basic_block bb)
>> +{
>> +  int i = 0;
>> +  bool is_call = false;
>> +  gimple_stmt_iterator gsi = gsi_last_bb (bb);
>> +  gimple *last_stmt = gsi_stmt (gsi);
>> +
>> +  if (last_stmt && gimple_code (last_stmt) == GIMPLE_COND)
>> +{
>> +  if (!gsi_end_p (gsi))
>> +   gsi_prev ();
>> +
>> +   for (; !gsi_end_p (gsi);)
>> +{
>> +  gimple *stmt = gsi_stmt (gsi);
>> +
>> +  /* We have already seen a call.  */
>> +  if (is_call)
>> +return false;
> 
> Likewise.  Do you want to check whether a block has
> a single stmt and that is a call and that is followed by
> a condition?  It looks like a very convoluted way to 

[PATCH] [libstdc++] [testsuite] xfail double-prec from_chars for x86_64 ldbl

[Alexandre Oliva via Gcc-patches]

When long double is wider than double, but from_chars is implemented
in terms of double, tests that involve the full precision of long
double are expected to fail.  Mark them as such on x86_64-*-vxworks*.

Tested on x86_64-vxworks7r2 with gcc-12.  Ok to install?


for  libstdc++-v3/ChangeLog

* testsuite/20_util/from_chars/4.cc: Skip long double test06
on x86_64-vxworks.
* testsuite/20_util/to_chars/long_double.cc: Xfail run on
x86_64-vxworks.
---
 libstdc++-v3/testsuite/20_util/from_chars/4.cc |2 +-
 .../testsuite/20_util/to_chars/long_double.cc  |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/testsuite/20_util/from_chars/4.cc 
b/libstdc++-v3/testsuite/20_util/from_chars/4.cc
index c3594f9014bd3..63a32b511be4e 100644
--- a/libstdc++-v3/testsuite/20_util/from_chars/4.cc
+++ b/libstdc++-v3/testsuite/20_util/from_chars/4.cc
@@ -18,7 +18,7 @@
 //  is supported in C++14 as a GNU extension
 // { dg-do run { target c++14 } }
 // { dg-add-options ieee }
-// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* } }
+// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* 
x86_64-*-vxworks* } }
 
 #include 
 #include 
diff --git a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc 
b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
index 08363d9d04003..df02dff935f40 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/long_double.cc
@@ -36,7 +36,7 @@
 
 // On systems that use double-precision from_chars for long double,
 // this is expected to fail.
-// { dg-xfail-run-if "from_chars limited to double-precision" { 
aarch64-*-vxworks* i*86-*-vxworks* } }
+// { dg-xfail-run-if "from_chars limited to double-precision" { 
aarch64-*-vxworks* i*86-*-vxworks* x86_64-*-vxworks* } }
 
 // { dg-require-effective-target ieee_floats }
 // { dg-require-effective-target size32plus }


-- 
Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
   Free Software Activist   GNU Toolchain Engineer
Disinformation flourishes because many people care deeply about injustice
but very few check the facts.  Ask me about 

RE: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Tuesday, May 30, 2023 10:18 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches ; Kito.cheng ; 
palmer ; palmer ; jeffreyalaw 
; Robin Dapp 
Subject: Re: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV 
auto-vectorization support

LGTM

On Tue, May 30, 2023 at 10:15 AM juzhe.zh...@rivai.ai  
wrote:
>
> Ok for trunk ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-29 12:35
> To: gcc-patches
> CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
> Juzhe-Zhong
> Subject: [PATCH V2] RISC-V: Add floating-point to integer conversion 
> RVV auto-vectorization support
> From: Juzhe-Zhong 
>
> Even though we can't support floating-point operations which are 
> depending on FRM yet, (for example vfadd support is blocked) since the 
> RVV intrinsic doc is not updated and we can't support mode switching for this.
>
> We can support floating-point to integer conversion now since it's not 
> depending on FRM and we don't need mode switching support for this ('rtz' 
> conversions independent FRM).
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (2): New pattern.
> * config/riscv/iterators.md: New attribute.
> * config/riscv/vector-iterators.md: New attribute.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New 
> test.
>
> ---
> gcc/config/riscv/autovec.md   | 23 
> gcc/config/riscv/iterators.md |  4 +-
> gcc/config/riscv/vector-iterators.md  |  5 ++
> .../rvv/autovec/conversions/vfcvt_rtz-run.c   | 52 +++
> .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  6 +++
> .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  6 +++
> .../autovec/conversions/vfcvt_rtz-template.h  | 15 ++
> 7 files changed, 110 insertions(+), 1 deletion(-) create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32g
> cv.c create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64g
> cv.c create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-templ
> ate.h
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md 
> index b24867ae4d0..3989ffb26ee 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -478,6 +478,29 @@
>DONE;
> })
> +;; 
> +=
> +
> +;; == Conversions
> +;; 
> +=
> +
> +
> +;; 
> +-
> +
> +;;  [INT<-FP] Conversions
> +;; 
> +-
> +
> +;; Includes:
> +;; - vfcvt.rtz.xu.f.v
> +;; - vfcvt.rtz.x.f.v
> +;; 
> +-
> +
> +
> +(define_expand "2"
> +  [(set (match_operand: 0 "register_operand")  
> +(any_fix:
> +   (match_operand:VF 1 "register_operand")))]
> +  "TARGET_VECTOR"
> +{
> +  insn_code icode = code_for_pred (, mode);
> +  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, 
> +operands);
> +  DONE;
> +})
> +
> ;; 
> ==
> ===
> ;; == Unary arithmetic
> ;; 
> ==
> === diff --git a/gcc/config/riscv/iterators.md 
> b/gcc/config/riscv/iterators.md index 8afe98e4410..d374a10810c 100644
> --- a/gcc/config/riscv/iterators.md
> +++ b/gcc/config/riscv/iterators.md
> @@ -225,7 +225,9 @@
> (ss_minus "sssub")
> (us_minus "ussub")
> (sign_extend "extend")
> - (zero_extend "zero_extend")])
> + (zero_extend "zero_extend")
> + (fix "fix_trunc")
> + (unsigned_fix "fixuns_trunc")])
> ;;  code attributes
> (define_code_attr or_optab [(ior "ior") diff --git 
> a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 70fb5b80b1b..937ec3c7f67 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -1208,6 +1208,11 @@
>(VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF 
> "VNx8DI") (VNx16DF "VNx16DI")
> ])
> +(define_mode_attr vconvert [
> +  (VNx1SF "vnx1si") (VNx2SF "vnx2si") (VNx4SF "vnx4si") (VNx8SF 
> +"vnx8si") (VNx16SF "vnx16si") (VNx32SF "vnx32si")
> +  (VNx1DF "vnx1di") (VNx2DF "vnx2di") (VNx4DF "vnx4di") (VNx8DF 
> +"vnx8di") (VNx16DF "vnx16di")
> +])
> +
> 

Re: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support

[Kito Cheng via Gcc-patches]

LGTM

On Tue, May 30, 2023 at 10:15 AM juzhe.zh...@rivai.ai
 wrote:
>
> Ok for trunk ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-29 12:35
> To: gcc-patches
> CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
> Juzhe-Zhong
> Subject: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV 
> auto-vectorization support
> From: Juzhe-Zhong 
>
> Even though we can't support floating-point operations which are depending
> on FRM yet, (for example vfadd support is blocked) since the RVV intrinsic 
> doc is not updated
> and we can't support mode switching for this.
>
> We can support floating-point to integer conversion now since it's not 
> depending on FRM and
> we don't need mode switching support for this ('rtz' conversions independent 
> FRM).
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (2): New pattern.
> * config/riscv/iterators.md: New attribute.
> * config/riscv/vector-iterators.md: New attribute.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New 
> test.
>
> ---
> gcc/config/riscv/autovec.md   | 23 
> gcc/config/riscv/iterators.md |  4 +-
> gcc/config/riscv/vector-iterators.md  |  5 ++
> .../rvv/autovec/conversions/vfcvt_rtz-run.c   | 52 +++
> .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  6 +++
> .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  6 +++
> .../autovec/conversions/vfcvt_rtz-template.h  | 15 ++
> 7 files changed, 110 insertions(+), 1 deletion(-)
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index b24867ae4d0..3989ffb26ee 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -478,6 +478,29 @@
>DONE;
> })
> +;; =
> +;; == Conversions
> +;; =
> +
> +;; -
> +;;  [INT<-FP] Conversions
> +;; -
> +;; Includes:
> +;; - vfcvt.rtz.xu.f.v
> +;; - vfcvt.rtz.x.f.v
> +;; -
> +
> +(define_expand "2"
> +  [(set (match_operand: 0 "register_operand")
> + (any_fix:
> +   (match_operand:VF 1 "register_operand")))]
> +  "TARGET_VECTOR"
> +{
> +  insn_code icode = code_for_pred (, mode);
> +  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
> +  DONE;
> +})
> +
> ;; =
> ;; == Unary arithmetic
> ;; =
> diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
> index 8afe98e4410..d374a10810c 100644
> --- a/gcc/config/riscv/iterators.md
> +++ b/gcc/config/riscv/iterators.md
> @@ -225,7 +225,9 @@
> (ss_minus "sssub")
> (us_minus "ussub")
> (sign_extend "extend")
> - (zero_extend "zero_extend")])
> + (zero_extend "zero_extend")
> + (fix "fix_trunc")
> + (unsigned_fix "fixuns_trunc")])
> ;;  code attributes
> (define_code_attr or_optab [(ior "ior")
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 70fb5b80b1b..937ec3c7f67 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -1208,6 +1208,11 @@
>(VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF "VNx8DI") 
> (VNx16DF "VNx16DI")
> ])
> +(define_mode_attr vconvert [
> +  (VNx1SF "vnx1si") (VNx2SF "vnx2si") (VNx4SF "vnx4si") (VNx8SF "vnx8si") 
> (VNx16SF "vnx16si") (VNx32SF "vnx32si")
> +  (VNx1DF "vnx1di") (VNx2DF "vnx2di") (VNx4DF "vnx4di") (VNx8DF "vnx8di") 
> (VNx16DF "vnx16di")
> +])
> +
> (define_mode_attr VNCONVERT [
>(VNx1SF "VNx1HI") (VNx2SF "VNx2HI") (VNx4SF "VNx4HI") (VNx8SF "VNx8HI") 
> (VNx16SF "VNx16HI") (VNx32SF "VNx32HI")
>(VNx1DI "VNx1SF") (VNx2DI "VNx2SF") (VNx4DI "VNx4SF") (VNx8DI "VNx8SF") 
> (VNx16DI "VNx16SF")
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
> new file 

RE: [PATCH V2] RISC-V: Fix warning in riscv.md

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Tuesday, May 30, 2023 10:10 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH V2] RISC-V: Fix warning in riscv.md

LGTM :)

On Tue, May 30, 2023 at 10:09 AM  wrote:
>
> From: Juzhe-Zhong 
>
> Notice there is warning:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def* 
> gen_anddi3(rtx, rtx, rtx)’:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
>
> Add unsigned conversion to fix this warning.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Fix signed and unsigned comparison warning.
>
> ---
>  gcc/config/riscv/riscv.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md 
> index aba203318a7..f545874edc1 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1353,9 +1353,9 @@
>if (CONST_INT_P (operands[2]))
>  {
>enum machine_mode tmode = VOIDmode;
> -  if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> +  if (UINTVAL (operands[2]) == GET_MODE_MASK (HImode))
> tmode = HImode;
> -  else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> +  else if (UINTVAL (operands[2]) == GET_MODE_MASK (SImode))
> tmode = SImode;
>
>if (tmode != VOIDmode)
> --
> 2.36.3
>

RE: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Tuesday, May 30, 2023 10:04 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches ; Kito.cheng ; 
palmer ; palmer ; jeffreyalaw 
; Robin Dapp 
Subject: Re: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

LGTM

On Tue, May 30, 2023 at 8:30 AM juzhe.zh...@rivai.ai  
wrote:
>
> Hi, this patch is same implementation as FMA which has been merged.
> Ok for trunk?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-29 14:53
> To: gcc-patches
> CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
> Juzhe-Zhong
> Subject: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support
> From: Juzhe-Zhong 
>
> Like FMA, Add FNMA (VNMSAC or VNMSUB) auto-vectorization support.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (fnma4): New pattern.
> (*fnma): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.
>
> ---
> gcc/config/riscv/autovec.md   |  45 
> .../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
> .../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
> .../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
> .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
> .../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
> .../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
> 7 files changed, 432 insertions(+)
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md 
> index eff3e484fb4..a1028d71467 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -606,3 +606,48 @@
>}
>[(set_attr "type" "vimuladd")
> (set_attr "mode" "")])
> +
> +;; 
> +-
> +
> +;;  [INT] VNMSAC and VNMSUB
> +;; 
> +-
> +
> +;; Includes:
> +;; - vnmsac
> +;; - vnmsub
> +;; 
> +-
> +
> +
> +(define_expand "fnma4"
> +  [(parallel
> +[(set (match_operand:VI 0 "register_operand" "=vr")
> +   (minus:VI
> + (match_operand:VI 3 "register_operand"   " vr")
> + (mult:VI
> +   (match_operand:VI 1 "register_operand" " vr")
> +   (match_operand:VI 2 "register_operand" " vr"
> + (clobber (match_scratch:SI 4))])]
> +  "TARGET_VECTOR"
> +  {})
> +
> +(define_insn_and_split "*fnma"
> +  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?")
> + (minus:VI
> +   (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
> +   (mult:VI
> + (match_operand:VI 1 "register_operand" " %0, vr,   vr")
> + (match_operand:VI 2 "register_operand" " vr, vr,   vr"
> +   (clobber (match_scratch:SI 4 "=r,r,r"))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& reload_completed"
> +  [(const_int 0)]
> +  {
> +PUT_MODE (operands[4], Pmode);
> +riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
> +if (which_alternative == 2)
> +  emit_insn (gen_rtx_SET (operands[0], operands[3]));
> +rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
> operands[0]};
> +riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
> (mode),
> +riscv_vector::RVV_TERNOP, ops, operands[4]);
> +DONE;
> +  }
> +  [(set_attr "type" "vimuladd")
> +   (set_attr "mode" "")])
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> new file mode 100644
> index 000..22d11de89a1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
> +--param=riscv-autovec-preference=scalable" } */
> +
> +#include 
> +
> +#define TEST_TYPE(TYPE)  
>   \
> +  __attribute__ ((noipa)) void ternop_##TYPE 

Re: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support

[juzhe.zh...@rivai.ai]

Ok for trunk ?



juzhe.zh...@rivai.ai
 
From: juzhe.zhong
Date: 2023-05-29 12:35
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV 
auto-vectorization support
From: Juzhe-Zhong 
 
Even though we can't support floating-point operations which are depending
on FRM yet, (for example vfadd support is blocked) since the RVV intrinsic doc 
is not updated
and we can't support mode switching for this.
 
We can support floating-point to integer conversion now since it's not 
depending on FRM and
we don't need mode switching support for this ('rtz' conversions independent 
FRM).
 
gcc/ChangeLog:
 
* config/riscv/autovec.md (2): New pattern.
* config/riscv/iterators.md: New attribute.
* config/riscv/vector-iterators.md: New attribute.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New 
test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New 
test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New 
test.
 
---
gcc/config/riscv/autovec.md   | 23 
gcc/config/riscv/iterators.md |  4 +-
gcc/config/riscv/vector-iterators.md  |  5 ++
.../rvv/autovec/conversions/vfcvt_rtz-run.c   | 52 +++
.../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  6 +++
.../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  6 +++
.../autovec/conversions/vfcvt_rtz-template.h  | 15 ++
7 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h
 
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b24867ae4d0..3989ffb26ee 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -478,6 +478,29 @@
   DONE;
})
+;; =
+;; == Conversions
+;; =
+
+;; -
+;;  [INT<-FP] Conversions
+;; -
+;; Includes:
+;; - vfcvt.rtz.xu.f.v
+;; - vfcvt.rtz.x.f.v
+;; -
+
+(define_expand "2"
+  [(set (match_operand: 0 "register_operand")
+ (any_fix:
+   (match_operand:VF 1 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+  DONE;
+})
+
;; =
;; == Unary arithmetic
;; =
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 8afe98e4410..d374a10810c 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -225,7 +225,9 @@
(ss_minus "sssub")
(us_minus "ussub")
(sign_extend "extend")
- (zero_extend "zero_extend")])
+ (zero_extend "zero_extend")
+ (fix "fix_trunc")
+ (unsigned_fix "fixuns_trunc")])
;;  code attributes
(define_code_attr or_optab [(ior "ior")
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 70fb5b80b1b..937ec3c7f67 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1208,6 +1208,11 @@
   (VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF "VNx8DI") 
(VNx16DF "VNx16DI")
])
+(define_mode_attr vconvert [
+  (VNx1SF "vnx1si") (VNx2SF "vnx2si") (VNx4SF "vnx4si") (VNx8SF "vnx8si") 
(VNx16SF "vnx16si") (VNx32SF "vnx32si")
+  (VNx1DF "vnx1di") (VNx2DF "vnx2di") (VNx4DF "vnx4di") (VNx8DF "vnx8di") 
(VNx16DF "vnx16di")
+])
+
(define_mode_attr VNCONVERT [
   (VNx1SF "VNx1HI") (VNx2SF "VNx2HI") (VNx4SF "VNx4HI") (VNx8SF "VNx8HI") 
(VNx16SF "VNx16HI") (VNx32SF "VNx32HI")
   (VNx1DI "VNx1SF") (VNx2DI "VNx2SF") (VNx4DI "VNx4SF") (VNx8DI "VNx8SF") 
(VNx16DI "VNx16SF")
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
new file mode 100644
index 000..05f8d911ad7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
@@ -0,0 +1,52 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model 
--param=riscv-autovec-preference=scalable" } */
+

Re: [PATCH V2] RISC-V: Fix warning in riscv.md

[Kito Cheng via Gcc-patches]

LGTM :)

On Tue, May 30, 2023 at 10:09 AM  wrote:
>
> From: Juzhe-Zhong 
>
> Notice there is warning:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def* 
> gen_anddi3(rtx, rtx, rtx)’:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
>
> Add unsigned conversion to fix this warning.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Fix signed and unsigned comparison warning.
>
> ---
>  gcc/config/riscv/riscv.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index aba203318a7..f545874edc1 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1353,9 +1353,9 @@
>if (CONST_INT_P (operands[2]))
>  {
>enum machine_mode tmode = VOIDmode;
> -  if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> +  if (UINTVAL (operands[2]) == GET_MODE_MASK (HImode))
> tmode = HImode;
> -  else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> +  else if (UINTVAL (operands[2]) == GET_MODE_MASK (SImode))
> tmode = SImode;
>
>if (tmode != VOIDmode)
> --
> 2.36.3
>

[PATCH V2] RISC-V: Fix warning in riscv.md

[juzhe . zhong]

From: Juzhe-Zhong 

Notice there is warning:
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ???rtx_def* 
gen_anddi3(rtx, rtx, rtx):
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))

Add unsigned conversion to fix this warning.

gcc/ChangeLog:

* config/riscv/riscv.md: Fix signed and unsigned comparison warning.

---
 gcc/config/riscv/riscv.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index aba203318a7..f545874edc1 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1353,9 +1353,9 @@
   if (CONST_INT_P (operands[2]))
 {
   enum machine_mode tmode = VOIDmode;
-  if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
+  if (UINTVAL (operands[2]) == GET_MODE_MASK (HImode))
tmode = HImode;
-  else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
+  else if (UINTVAL (operands[2]) == GET_MODE_MASK (SImode))
tmode = SImode;
 
   if (tmode != VOIDmode)
-- 
2.36.3

Re: [PATCH] RISC-V: Fix warning in riscv.md

[Kito Cheng via Gcc-patches]

You could use UINTVAL rather than (unsigned HOST_WIDE_INT) INTVAL

On Tue, May 30, 2023 at 9:14 AM  wrote:
>
> From: Juzhe-Zhong 
>
> Notice there is warning:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def* 
> gen_anddi3(rtx, rtx, rtx)’:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
>
> Add unsigned conversion to fix this warning.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Fix signed and unsigned comparison warning.
>
> ---
>  gcc/config/riscv/riscv.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index aba203318a7..3d71f59c3a9 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1353,9 +1353,9 @@
>if (CONST_INT_P (operands[2]))
>  {
>enum machine_mode tmode = VOIDmode;
> -  if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> +  if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) == GET_MODE_MASK 
> (HImode))
> tmode = HImode;
> -  else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> +  else if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) == 
> GET_MODE_MASK (SImode))
> tmode = SImode;
>
>if (tmode != VOIDmode)
> --
> 2.36.3
>

Re: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

[Kito Cheng via Gcc-patches]

LGTM

On Tue, May 30, 2023 at 8:30 AM juzhe.zh...@rivai.ai
 wrote:
>
> Hi, this patch is same implementation as FMA which has been merged.
> Ok for trunk?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-29 14:53
> To: gcc-patches
> CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
> Juzhe-Zhong
> Subject: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support
> From: Juzhe-Zhong 
>
> Like FMA, Add FNMA (VNMSAC or VNMSUB) auto-vectorization support.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (fnma4): New pattern.
> (*fnma): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.
>
> ---
> gcc/config/riscv/autovec.md   |  45 
> .../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
> .../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
> .../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
> .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
> .../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
> .../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
> 7 files changed, 432 insertions(+)
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index eff3e484fb4..a1028d71467 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -606,3 +606,48 @@
>}
>[(set_attr "type" "vimuladd")
> (set_attr "mode" "")])
> +
> +;; -
> +;;  [INT] VNMSAC and VNMSUB
> +;; -
> +;; Includes:
> +;; - vnmsac
> +;; - vnmsub
> +;; -
> +
> +(define_expand "fnma4"
> +  [(parallel
> +[(set (match_operand:VI 0 "register_operand" "=vr")
> +   (minus:VI
> + (match_operand:VI 3 "register_operand"   " vr")
> + (mult:VI
> +   (match_operand:VI 1 "register_operand" " vr")
> +   (match_operand:VI 2 "register_operand" " vr"
> + (clobber (match_scratch:SI 4))])]
> +  "TARGET_VECTOR"
> +  {})
> +
> +(define_insn_and_split "*fnma"
> +  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?")
> + (minus:VI
> +   (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
> +   (mult:VI
> + (match_operand:VI 1 "register_operand" " %0, vr,   vr")
> + (match_operand:VI 2 "register_operand" " vr, vr,   vr"
> +   (clobber (match_scratch:SI 4 "=r,r,r"))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& reload_completed"
> +  [(const_int 0)]
> +  {
> +PUT_MODE (operands[4], Pmode);
> +riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
> +if (which_alternative == 2)
> +  emit_insn (gen_rtx_SET (operands[0], operands[3]));
> +rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
> operands[0]};
> +riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
> (mode),
> +riscv_vector::RVV_TERNOP, ops, operands[4]);
> +DONE;
> +  }
> +  [(set_attr "type" "vimuladd")
> +   (set_attr "mode" "")])
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> new file mode 100644
> index 000..22d11de89a1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
> --param=riscv-autovec-preference=scalable" } */
> +
> +#include 
> +
> +#define TEST_TYPE(TYPE)  
>   \
> +  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst,  
>   \
> +   TYPE *__restrict a,  \
> +   TYPE *__restrict b, int n)   \
> +  {  
>   \
> +for (int i = 0; i < n; i++)  
>   \
> +  dst[i] += -(a[i] * b[i]);

Re: [PATCH] LoongArch: Set 4 * (issue rate) as the default for -falign-functions and -falign-loops

[Lulu Cheng]

在 2023/5/29 下午2:09, Xi Ruoyao 写道:

On Tue, 2023-04-18 at 21:06 +0800, Lulu Cheng wrote:

Hi, ruoyao:

Thank you so much for making this submission. But we are testing the
impact of these two alignment parameters

(also including -falign-jumps and -falign-lables ) on performance. So
before the result comes out, this patch will

not be merged into the main branch for the time being.

Hi!

Is there an estimate when the benchmark will be done?  If it will be
done soon I'll wait for the result before performing a full system
rebuild, otherwise I'll use my gut feeling to specify a -falign-
functions= value for the build :).

Sorry for taking so long to reply to the email. From our current test 
results,


the performance of the SPEC is best when combined with -falign-loops=16,

-falign-jumps=16, -falign-functions=32 and -falign-lables=16.

[PATCH] RISC-V: Fix warning in riscv.md

[juzhe . zhong]

From: Juzhe-Zhong 

Notice there is warning:
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ???rtx_def* 
gen_anddi3(rtx, rtx, rtx)???:
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
between signed and unsigned integer expressions [-Wsign-compare]
   else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))

Add unsigned conversion to fix this warning.

gcc/ChangeLog:

* config/riscv/riscv.md: Fix signed and unsigned comparison warning.

---
 gcc/config/riscv/riscv.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index aba203318a7..3d71f59c3a9 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1353,9 +1353,9 @@
   if (CONST_INT_P (operands[2]))
 {
   enum machine_mode tmode = VOIDmode;
-  if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
+  if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) == GET_MODE_MASK 
(HImode))
tmode = HImode;
-  else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
+  else if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) == GET_MODE_MASK 
(SImode))
tmode = SImode;
 
   if (tmode != VOIDmode)
-- 
2.36.3

Re: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

[juzhe.zh...@rivai.ai]

Hi, this patch is same implementation as FMA which has been merged.
Ok for trunk?



juzhe.zh...@rivai.ai
 
From: juzhe.zhong
Date: 2023-05-29 14:53
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support
From: Juzhe-Zhong 
 
Like FMA, Add FNMA (VNMSAC or VNMSUB) auto-vectorization support.
 
gcc/ChangeLog:
 
* config/riscv/autovec.md (fnma4): New pattern.
(*fnma): Ditto.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.
 
---
gcc/config/riscv/autovec.md   |  45 
.../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
.../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
.../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
.../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
.../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
.../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
7 files changed, 432 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
 
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index eff3e484fb4..a1028d71467 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -606,3 +606,48 @@
   }
   [(set_attr "type" "vimuladd")
(set_attr "mode" "")])
+
+;; -
+;;  [INT] VNMSAC and VNMSUB
+;; -
+;; Includes:
+;; - vnmsac
+;; - vnmsub
+;; -
+
+(define_expand "fnma4"
+  [(parallel
+[(set (match_operand:VI 0 "register_operand" "=vr")
+   (minus:VI
+ (match_operand:VI 3 "register_operand"   " vr")
+ (mult:VI
+   (match_operand:VI 1 "register_operand" " vr")
+   (match_operand:VI 2 "register_operand" " vr"
+ (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fnma"
+  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?")
+ (minus:VI
+   (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
+   (mult:VI
+ (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+ (match_operand:VI 2 "register_operand" " vr, vr,   vr"
+   (clobber (match_scratch:SI 4 "=r,r,r"))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+PUT_MODE (operands[4], Pmode);
+riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
+if (which_alternative == 2)
+  emit_insn (gen_rtx_SET (operands[0], operands[3]));
+rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
+riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
(mode),
+riscv_vector::RVV_TERNOP, ops, operands[4]);
+DONE;
+  }
+  [(set_attr "type" "vimuladd")
+   (set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
new file mode 100644
index 000..22d11de89a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=scalable" } */
+
+#include 
+
+#define TEST_TYPE(TYPE)
\
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst,
\
+   TYPE *__restrict a,  \
+   TYPE *__restrict b, int n)   \
+  {
\
+for (int i = 0; i < n; i++)
\
+  dst[i] += -(a[i] * b[i]);
\
+  }
+
+#define TEST_ALL() 
\
+  TEST_TYPE (int8_t)   
\
+  TEST_TYPE (uint8_t)  
\
+  TEST_TYPE (int16_t) 

Re: [PATCH 1/2] Implementation of new RISCV optimizations pass: fold-mem-offsets.

[Jeff Law via Gcc-patches]

On 5/25/23 08:02, Manolis Tsamis wrote:

On Thu, May 25, 2023 at 4:53 PM Richard Biener via Gcc-patches
 wrote:


On Thu, May 25, 2023 at 3:32 PM Jeff Law via Gcc-patches
 wrote:




On 5/25/23 07:01, Richard Biener via Gcc-patches wrote:

On Thu, May 25, 2023 at 2:36 PM Manolis Tsamis  wrote:


Implementation of the new RISC-V optimization pass for memory offset
calculations, documentation and testcases.


Why do fwprop or combine not what you want to do?

I think a lot of them end up coming from register elimination.


Why isn't this a problem for other targets then?  Or maybe it is and this
shouldn't be a machine specific pass?  Maybe postreload-gcse should
perform strength reduction (I can't think of any other post reload pass
that would do something even remotely related).

Richard.



It should be a problem for other targets as well (especially RISC-style ISAs).

It can be easily seen by comparing the generated code for the
testcases: Example for testcase-2 on AArch64:
https://godbolt.org/z/GMT1K7Ebr
Although the patterns in the test cases are the ones that are simple
as the complex ones manifest in complex programs, the case still
holds.
The code for this pass is quite generic and could work for most/all
targets if that would be interesting.
Interestly enough, fold-mem-offsets seems to interact strangely with the 
load/store pair support on aarch64.  Note show store2a uses 2 stp 
instructions on the trunk, but 4 str instructions with fold-mem-offsets. 
 Yet in load1r we're able to generate a load-quad rather than two load 
pairs.  Weird.


jeff

Re: [PATCH] PR target/107172: Avoid "unusual" MODE_CC comparisons in simplify-rtx.cc

[Jeff Law via Gcc-patches]

On 5/26/23 13:43, Roger Sayle wrote:


I believe that a better (or supplementary) fix to PR target/107172 is to
avoid
producing incorrect (but valid) RTL in simplify_const_relational_operation
when
presented with questionable (obviously invalid) expressions, such as those
produced during combine.  Just as with the "first do no harm" clause with
the
Hippocratic Oath, simplify-rtx (probably) shouldn't unintentionally
transform
invalid RTL expressions, into incorrect (non-equivalent) but valid RTL that
may be inappropriately recognized by recog.

In this specific case, many GCC backends represent their flags register via
MODE_CC, whose representation is intentionally "opaque" to the middle-end.
The only use of MODE_CC comprehensible to the middle-end's RTL optimizers
is relational comparisons between the result of a COMPARE rtx (op0) and zero
(op1).  Any other uses of MODE_CC should be left alone, and some might argue
indicate representational issues in the backend.

In practice, CPUs occasionally have numerous instructions that affect the
flags register(s) other than comparisons [AVR's setc, powerpc's mtcrf,
x86's clc, stc and cmc and x86_64's ptest that sets C and Z flags in
non-obvious ways, c.f. PR target/109973].  Currently care has to be taken,
wrapping these in UNSPEC, to avoid combine inappropriately merging flags
setters with flags consumers (such as conditional jumps).  It's safer to
teach simplify_const_relational_operation not to modify expressions that
it doesn't understand/recognize.

This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32}
with no new failures.  Ok for mainline?


2023-05-26  Roger Sayle  

gcc/ChangeLog
* simplify-rtx.cc (simplify_const_relational_operation): Return
early
if we have a MODE_CC comparison that isn't a COMPARE against
const0_rtx.

OK
jeff

Re: [PATCH] rtlanal: Change return type of predicate functions from int to bool

[Jeff Law via Gcc-patches]

On 5/29/23 08:38, Uros Bizjak via Gcc-patches wrote:

gcc/ChangeLog:

 * rtl.h (rtx_addr_can_trap_p): Change return type from int to bool.
 (rtx_unstable_p): Ditto.
 (reg_mentioned_p): Ditto.
 (reg_referenced_p): Ditto.
 (reg_used_between_p): Ditto.
 (reg_set_between_p): Ditto.
 (modified_between_p): Ditto.
 (no_labels_between_p): Ditto.
 (modified_in_p): Ditto.
 (reg_set_p): Ditto.
 (multiple_sets): Ditto.
 (set_noop_p): Ditto.
 (noop_move_p): Ditto.
 (reg_overlap_mentioned_p): Ditto.
 (dead_or_set_p): Ditto.
 (dead_or_set_regno_p): Ditto.
 (find_reg_fusage): Ditto.
 (find_regno_fusage): Ditto.
 (side_effects_p): Ditto.
 (volatile_refs_p): Ditto.
 (volatile_insn_p): Ditto.
 (may_trap_p_1): Ditto.
 (may_trap_p): Ditto.
 (may_trap_or_fault_p): Ditto.
 (computed_jump_p): Ditto.
 (auto_inc_p): Ditto.
 (loc_mentioned_in_p): Ditto.
 * rtlanal.cc (computed_jump_p_1): Adjust forward declaration.
 (rtx_unstable_p): Change return type from int to bool
 and adjust function body accordingly.
 (rtx_addr_can_trap_p): Ditto.
 (reg_mentioned_p): Ditto.
 (no_labels_between_p): Ditto.
 (reg_used_between_p): Ditto.
 (reg_referenced_p): Ditto.
 (reg_set_between_p): Ditto.
 (reg_set_p): Ditto.
 (modified_between_p): Ditto.
 (modified_in_p): Ditto.
 (multiple_sets): Ditto.
 (set_noop_p): Ditto.
 (noop_move_p): Ditto.
 (reg_overlap_mentioned_p): Ditto.
 (dead_or_set_p): Ditto.
 (dead_or_set_regno_p): Ditto.
 (find_reg_fusage): Ditto.
 (find_regno_fusage): Ditto.
 (remove_node_from_insn_list): Ditto.
 (volatile_insn_p): Ditto.
 (volatile_refs_p): Ditto.
 (side_effects_p): Ditto.
 (may_trap_p_1): Ditto.
 (may_trap_p): Ditto.
 (may_trap_or_fault_p): Ditto.
 (computed_jump_p): Ditto.
 (auto_inc_p): Ditto.
 (loc_mentioned_in_p): Ditto.
 * combine.cc (can_combine_p): Update indirect function.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

OK for master?

OK.

jeff

Re: [PATCH v2 0/5] A small Texinfo refinement

[Sandra Loosemore]

n 5/29/23 11:26, Arsen Arsenović wrote:

Hi,

NightStrike  writes:


Can you include texinfo in a top-level directory and have it built
with the build, like you can with dejagnu? That's generally a
decent path for building new gcc on older systems.


Note that the Texinfo requirement wasn't bumped, so nothing changed
in this regard, [snip]


That is correct.  The only change we ended up making was to the build 
instructions, which now point out that new versions of Texinfo produce 
better HTML output, but that the version of Texinfo packaged with your 
OS distribution is adequate for building GCC otherwise.  We have GCC 
developers using quite old LTS distros with even older versions of 
Texinfo, so we would find out about it if something broke backward 
compatibility of the documentation.


-Sandra

[x86_64 PATCH] PR target/109973: CCZmode and CCCmode variants of [v]ptest.

[Roger Sayle]

This is my proposed minimal fix for PR target/109973 (hopefully suitable
for backporting) that follows Jakub Jelinek's suggestion that we introduce
CCZmode and CCCmode variants of ptest and vptest, so that the i386
backend treats [v]ptest instructions similarly to testl instructions;
using different CCmodes to indicate which condition flags are desired,
and then relying on the RTL cmpelim pass to eliminate redundant tests.

This conveniently matches Intel's intrinsics, that provide different
functions for retrieving different flags, _mm_testz_si128 tests the
Z flag, _mm_testc_si128 tests the carry flag.  Currently we use the
same instruction (pattern) for both, and unfortunately the *ptest_and
optimization is only valid when the ptest/vptest instruction is used to
set/test the Z flag.

The downside, as predicted by Jakub, is that GCC's cmpelim pass is
currently COMPARE-centric and not able to merge the ptests from expressions
such as _mm256_testc_si256 (a, b) + _mm256_testz_si256 (a, b), which is a
known issue, PR target/80040.  I've some follow-up patches to improve
things, but this first patch fixes the wrong-code regression, replacing
it with a rare missed-optimization (hopefully suitable for GCC 13).

The only change that was unanticipated was the tweak to ix86_match_ccmode.
Oddly, CCZmode is allowable for CCmode, but CCCmode isn't.  Given that
CCZmode means just the Z flag, CCCmode means just the C flag, and
CCmode means all the flags, I'm guessing this asymmetry is unintentional.
Perhaps a super-safe fix is to explicitly test for CCZmode, CCCmode or
CCmode
in the *_ptest pattern's predicate, and not attempt to
re-use ix86_match_ccmode?

This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32}
with no new failures.  Ok for mainline?


2023-05-29  Roger Sayle  

gcc/ChangeLog
PR targt/109973
* config/i386/i386-builtin.def (__builtin_ia32_ptestz128): Use new
CODE_for_sse4_1_ptestzv2di.
(__builtin_ia32_ptestc128): Use new CODE_for_sse4_1_ptestcv2di.
(__builtin_ia32_ptestz256): Use new CODE_for_avx_ptestzv4di.
(__builtin_ia32_ptestc256): Use new CODE_for_avx_ptestcv4di.
* config/i386/i386-expand.cc (ix86_expand_branch): Use CCZmode
when expanding UNSPEC_PTEST to compare against zero.
* config/i386/i386-features.cc (scalar_chain::convert_compare):
Likewise generate CCZmode UNSPEC_PTESTs when converting comparisons.
(general_scalar_chain::convert_insn): Use CCZmode for COMPARE
result.
(timode_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
* config/i386/i386.cc (ix86_match_ccmode): Allow the SET_SRC to be
an UNSPEC, in addition to a COMPARE.  Consider CCCmode to be a form
of CCmode.
* config/i386/sse.md (define_split): When splitting UNSPEC_MOVMSK
to UNSPEC_PTEST, preserve the FLAG_REG mode as CCZ.
(*_ptest): Add asterisk to hide define_insn.
Remove ":CC" flags specification, and use ix86_match_ccmode instead.
(_ptestz): New define_expand to specify CCZ.
(_ptestc): New define_expand to specify CCC.
(_ptest): A define_expand using CC to preserve the
current behavior.
(*ptest_and): Specify CCZ to only perform this optimization
when only the Z flag is required.

gcc/testsuite/ChangeLog
PR targt/109973
* gcc.target/i386/pr109973-1.c: New test case.
* gcc.target/i386/pr109973-2.c: Likewise.


Thanks,
Roger
--

diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index c91e380..383b68a 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -1004,8 +1004,8 @@ BDESC (OPTION_MASK_ISA_SSE4_1, 0, 
CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_
 BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_roundv4sf2, 
"__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) 
V4SF_FTYPE_V4SF)
 BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_roundv4sf2_sfix, 
"__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) 
V4SI_FTYPE_V4SF)
 
-BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_ptestv2di, 
"__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) 
INT_FTYPE_V2DI_V2DI_PTEST)
-BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_ptestv2di, 
"__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) 
INT_FTYPE_V2DI_V2DI_PTEST)
+BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_ptestzv2di, 
"__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) 
INT_FTYPE_V2DI_V2DI_PTEST)
+BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_ptestcv2di, 
"__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) 
INT_FTYPE_V2DI_V2DI_PTEST)
 BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_ptestv2di, 
"__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) 
INT_FTYPE_V2DI_V2DI_PTEST)
 
 /* SSE4.2 */
@@ -1164,8 +1164,8 @@ BDESC 

Re: [PATCH v2 0/5] A small Texinfo refinement

[Arsen Arsenović via Gcc-patches]

Hi,

NightStrike  writes:

> Can you include texinfo in a top-level directory and have it built with the
> build, like you can with dejagnu? That's generally a decent path for
> building new gcc on older systems.

Note that the Texinfo requirement wasn't bumped, so nothing changed in
this regard, however, I believe that this is already done, as I see the
following in Makefile.def:

  host_modules= { module= texinfo; no_install= true; };

(... and some relevant logic in configure.ac)


I'm not a fan of building dependencies in-tree, but I can see the
usefulness; I believe a superior solution would be one that adds .info
(et al.) files to all generated tarballs (including snapshots), hence
eliminating any extra deps anyway.  These files aren't system-specific,
after all, as they are neither code nor conditionally compiled.

This is also assumed practice in other packages.

Have a lovely day.
-- 
Arsen Arsenović


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Re: [PATCH] RISC-V: Optimize TARGET_XTHEADCONDMOV

[Jeff Law via Gcc-patches]

On 5/25/23 18:52, Die Li wrote:

This patch allows less instructions to be used when TARGET_XTHEADCONDMOV is 
enabled.

Provide an example from the existing testcases.

Testcase:
int ConEmv_imm_imm_reg(int x, int y){
   if (x == 1000) return 10;
   return y;
}

Cflags:
-O2 -march=rv64gc_xtheadcondmov -mabi=lp64d

before patch:
ConEmv_imm_imm_reg:
addia5,a0,-1000
li  a0,10
th.mvneza0,zero,a5
th.mveqza1,zero,a5
or  a0,a0,a1
ret

after patch:
ConEmv_imm_imm_reg:
addia5,a0,-1000
li  a0,10
th.mvneza0,a1,a5
ret

Signed-off-by: Die Li 

gcc/ChangeLog:

 * config/riscv/riscv.cc (riscv_expand_conditional_move_onesided): 
Delete.
 (riscv_expand_conditional_move):  Reuse the TARGET_SFB_ALU expand 
process for TARGET_XTHEADCONDMOV

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Update the output.
 * gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Likewise.

I've made minor formatting adjustments and pushed this to the trunk.



@@ -3492,14 +3462,12 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
&& GET_MODE (op0) == mode
&& GET_MODE (op1) == mode
&& (code == EQ || code == NE))
+need_eq_ne_p = true;

So the need_eq_ne_p should have indented 2 spaces in from the IF statement.


+
+  if (need_eq_ne_p || (TARGET_SFB_ALU
+  && GET_MODE (op0) == word_mode))This should have been:

  if (need_eq_ne_p
  || (TARGET_SFB_ALU && GET_MODE (op0) == word_mode))

I've fixed this as well.

I would recommend you review the GCC coding guidelines.  While I fixed 
the problems this time, I'll likely ask you to do so in the future.


jeff

Re: [PATCH] RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs

[Jeff Law via Gcc-patches]

On 5/25/23 01:54, juzhe.zh...@rivai.ai wrote:

From: Juzhe-Zhong 

gcc/ChangeLog:

 * config/riscv/riscv-vector-builtins.cc (register_frm): New function.
 (DEF_RVV_FRM_ENUM): New macro.
 (handle_pragma_vector): Add FRM enum
 * config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
 (RNE): Ditto.
 (RTZ): Ditto.
 (RDN): Ditto.
 (RUP): Ditto.
 (RMM): Ditto.

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/rvv/base/frm-1.c: New test.

OK
jeff

[PATCH 2/2] ipa-cp: Feed results of IPA-CP into value numbering

[Martin Jambor]

Hi,

PRs 68930 and 92497 show that when IPA-CP figures out constants in
aggregate parameters or when passed by reference but the loads happen
in an inlined function the information is lost.  This happens even
when the inlined function itself was known to have - or even cloned to
have - such constants in incoming parameters because the transform
phase of IPA passes is not run on them.  See discussion in the bugs
for reasons why.

Honza suggested that we can plug the results of IPA-CP analysis into
value numbering, so that FRE can figure out that some loads fetch
known constants.  This is what this patch does.

This version of the patch uses the new way we represent aggregate
constants discovered IPA-CP and so avoids linear scan to find them.
Similarly, it depends on the previous patch which avoids potentially
slow linear look ups of indices of PARM_DECLs when there are many of
them.

Bootstrapped, LTO-bootstrapped and LTO-profiledbootstrapped and tested
on x86_64-linux.  OK for trunk?

Thanks,

Martin


gcc/ChangeLog:

2023-05-26  Martin Jambor  

PR ipa/68930
PR ipa/92497
* ipa-prop.h (ipcp_get_aggregate_const): Declare.
* ipa-prop.cc (ipcp_get_aggregate_const): New function.
(ipcp_transform_function): Do not deallocate transformation info.
* tree-ssa-sccvn.cc: Include alloc-pool.h, symbol-summary.h and
ipa-prop.h.
(vn_reference_lookup_2): When hitting default-def vuse, query
IPA-CP transformation info for any known constants.

gcc/testsuite/ChangeLog:

2022-09-05  Martin Jambor  

PR ipa/68930
PR ipa/92497
* gcc.dg/ipa/pr92497-1.c: New test.
* gcc.dg/ipa/pr92497-2.c: Likewise.
---
 gcc/ipa-prop.cc  | 33 +
 gcc/ipa-prop.h   |  3 +++
 gcc/testsuite/gcc.dg/ipa/pr92497-1.c | 26 
 gcc/testsuite/gcc.dg/ipa/pr92497-2.c | 26 
 gcc/tree-ssa-sccvn.cc| 36 +++-
 5 files changed, 118 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/ipa/pr92497-1.c
 create mode 100644 gcc/testsuite/gcc.dg/ipa/pr92497-2.c

diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc
index f0976e363f7..fb2c0c0466b 100644
--- a/gcc/ipa-prop.cc
+++ b/gcc/ipa-prop.cc
@@ -5765,6 +5765,34 @@ ipcp_modif_dom_walker::before_dom_children (basic_block 
bb)
   return NULL;
 }
 
+/* If IPA-CP discovered a constant in parameter PARM at OFFSET of a given SIZE
+   - whether passed by reference or not is given by BY_REF - return that
+   constant.  Otherwise return NULL_TREE.  */
+
+tree
+ipcp_get_aggregate_const (struct function *func, tree parm, bool by_ref,
+ HOST_WIDE_INT bit_offset, HOST_WIDE_INT bit_size)
+{
+  cgraph_node *node = cgraph_node::get (func->decl);
+  ipcp_transformation *ts = ipcp_get_transformation_summary (node);
+
+  if (!ts || !ts->m_agg_values)
+return NULL_TREE;
+
+  int index = ts->get_param_index (func->decl, parm);
+  if (index < 0)
+return NULL_TREE;
+
+  ipa_argagg_value_list avl (ts);
+  unsigned unit_offset = bit_offset / BITS_PER_UNIT;
+  tree v = avl.get_value (index, unit_offset, by_ref);
+  if (!v
+  || maybe_ne (tree_to_poly_int64 (TYPE_SIZE (TREE_TYPE (v))), bit_size))
+return NULL_TREE;
+
+  return v;
+}
+
 /* Return true if we have recorded VALUE and MASK about PARM.
Set VALUE and MASk accordingly.  */
 
@@ -6037,11 +6065,6 @@ ipcp_transform_function (struct cgraph_node *node)
 free_ipa_bb_info (bi);
   fbi.bb_infos.release ();
 
-  ipcp_transformation *s = ipcp_transformation_sum->get (node);
-  s->m_agg_values = NULL;
-  s->bits = NULL;
-  s->m_vr = NULL;
-
   vec_free (descriptors);
   if (cfg_changed)
 delete_unreachable_blocks_update_callgraph (node, false);
diff --git a/gcc/ipa-prop.h b/gcc/ipa-prop.h
index 211b12ff6b3..f68fa4a12dd 100644
--- a/gcc/ipa-prop.h
+++ b/gcc/ipa-prop.h
@@ -1221,6 +1221,9 @@ void ipa_dump_param (FILE *, class ipa_node_params *info, 
int i);
 void ipa_release_body_info (struct ipa_func_body_info *);
 tree ipa_get_callee_param_type (struct cgraph_edge *e, int i);
 bool ipcp_get_parm_bits (tree, tree *, widest_int *);
+tree ipcp_get_aggregate_const (struct function *func, tree parm, bool by_ref,
+  HOST_WIDE_INT bit_offset,
+  HOST_WIDE_INT bit_size);
 bool unadjusted_ptr_and_unit_offset (tree op, tree *ret,
 poly_int64 *offset_ret);
 
diff --git a/gcc/testsuite/gcc.dg/ipa/pr92497-1.c 
b/gcc/testsuite/gcc.dg/ipa/pr92497-1.c
new file mode 100644
index 000..eb8f2e75fd0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ipa/pr92497-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-early-inlining"  } */
+
+struct a {int a;};
+static int //__attribute__ ((noinline))
+foo (struct a a)
+{
+  if (!__builtin_constant_p (a.a))
+__builtin_abort ();
+  return a.a;
+}
+
+static int 

[PATCH 1/2] ipa-cp: Avoid long linear searches through DECL_ARGUMENTS

[Martin Jambor]

Hi,

there have been concerns that linear searches through DECL_ARGUMENTS
that are often necessary to compute the index of a particular
PARM_DECL which is the key to results of IPA-CP can happen often
enough to be a compile time issue, especially if we plug the results
into value numbering, as I intend to do with a follow-up patch.

This patch creates a hash map to do the look-up for all functions
which have some information discovered by IPA-CP and which have 32
parameters or more.  32 is a hard-wired magical constant here to
capture the trade-off between the memory allocation overhead and
length of the linear search.  I do not think it is worth making it a
--param but if people think it appropriate, I can turn it into one.

Bootstrapped, tested and LTO bootstrapped on x86_64-linux, both as-is
and with themagical constant dropped to 4 so that the has lookup path
is also well excercised.  OK for master?

Thanks,

Martin


gcc/ChangeLog:

2023-05-26  Martin Jambor  

* ipa-prop.h (struct ipcp_transformation): Rearrange members
according to C++ class coding convention, add m_tree_to_idx,
get_param_index and maybe_create_parm_idx_map.
* ipa-cp.cc (ipcp_transformation::get_param_index): New function.
(ipcp_transformation::maype_create_parm_idx_map): Likewise.
* ipa-prop.cc (ipcp_get_parm_bits): Use get_param_index.
(ipcp_update_bits): Accept TS as a parameter, assume it is not NULL.
(ipcp_update_vr): Likewise.
(ipcp_transform_function): Call, maybe_create_parm_idx_map of TS, bail
out quickly if empty, pass it to ipcp_update_bits and ipcp_update_vr.
---
 gcc/ipa-cp.cc   | 45 +
 gcc/ipa-prop.cc | 44 +++-
 gcc/ipa-prop.h  | 33 +
 3 files changed, 89 insertions(+), 33 deletions(-)

diff --git a/gcc/ipa-cp.cc b/gcc/ipa-cp.cc
index 0f37bb5e336..9f8b07b2398 100644
--- a/gcc/ipa-cp.cc
+++ b/gcc/ipa-cp.cc
@@ -6761,3 +6761,48 @@ ipa_cp_cc_finalize (void)
   orig_overall_size = 0;
   ipcp_free_transformation_sum ();
 }
+
+/* Given PARAM which must be a parameter of function FNDECL described by THIS,
+   return its index in the DECL_ARGUMENTS chain, using a pre-computed hash map
+   if avialable (which is pre-computed only if there are many parameters).  Can
+   return -1 if param is static chain not represented among DECL_ARGUMENTS. */
+
+int
+ipcp_transformation::get_param_index (const_tree fndecl, const_tree param) 
const
+{
+  gcc_assert (TREE_CODE (param) == PARM_DECL);
+  if (m_tree_to_idx)
+{
+  unsigned *pr = m_tree_to_idx->get(param);
+  if (!pr)
+   {
+ gcc_assert (DECL_STATIC_CHAIN (fndecl));
+ return -1;
+   }
+  return (int) *pr;
+}
+
+  unsigned index = 0;
+  for (tree p = DECL_ARGUMENTS (fndecl); p; p = DECL_CHAIN (p), index++)
+if (p == param)
+  return (int) index;
+
+  gcc_assert (DECL_STATIC_CHAIN (fndecl));
+  return -1;
+}
+
+/* Assuming THIS describes FNDECL and it has sufficiently many parameters to
+   justify the overhead, creat a has map from parameter trees to their
+   indices.  */
+void
+ipcp_transformation::maybe_create_parm_idx_map (tree fndecl)
+{
+  int c = count_formal_params (fndecl);
+  if (c < 32)
+return;
+
+  m_tree_to_idx = hash_map::create_ggc (c);
+  unsigned index = 0;
+  for (tree p = DECL_ARGUMENTS (fndecl); p; p = DECL_CHAIN (p), index++)
+m_tree_to_idx->put (p, index);
+}
diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc
index ab6de9f10da..f0976e363f7 100644
--- a/gcc/ipa-prop.cc
+++ b/gcc/ipa-prop.cc
@@ -5776,16 +5776,9 @@ ipcp_get_parm_bits (tree parm, tree *value, widest_int 
*mask)
   if (!ts || vec_safe_length (ts->bits) == 0)
 return false;
 
-  int i = 0;
-  for (tree p = DECL_ARGUMENTS (current_function_decl);
-   p != parm; p = DECL_CHAIN (p))
-{
-  i++;
-  /* Ignore static chain.  */
-  if (!p)
-   return false;
-}
-
+  int i = ts->get_param_index (current_function_decl, parm);
+  if (i < 0)
+return false;
   clone_info *cinfo = clone_info::get (cnode);
   if (cinfo && cinfo->param_adjustments)
 {
@@ -5802,16 +5795,12 @@ ipcp_get_parm_bits (tree parm, tree *value, widest_int 
*mask)
   return true;
 }
 
-
-/* Update bits info of formal parameters as described in
-   ipcp_transformation.  */
+/* Update bits info of formal parameters of NODE as described in TS.  */
 
 static void
-ipcp_update_bits (struct cgraph_node *node)
+ipcp_update_bits (struct cgraph_node *node, ipcp_transformation *ts)
 {
-  ipcp_transformation *ts = ipcp_get_transformation_summary (node);
-
-  if (!ts || vec_safe_length (ts->bits) == 0)
+  if (vec_safe_is_empty (ts->bits))
 return;
   vec  = *ts->bits;
   unsigned count = bits.length ();
@@ -5913,14 +5902,12 @@ ipcp_update_bits (struct cgraph_node *node)
 }
 }
 
-/* Update value range of formal parameters as described in
-   ipcp_transformation.  

Re: [COMMITTED] ada: Remove the body of System.Storage_Elements

[Jan-Benedict Glaw]

On Mon, 2023-05-29 16:11:26 +0200, Marc Poulhiès  wrote:
> Jan-Benedict Glaw  writes:
> > (A full build log is at
> > http://toolchain.lug-owl.de/laminar/jobs/gcc-aarch64-linux/74)
> >
> > Is this an issue with the patch? Or does it need a newer Ada compiler
> > to for building it?
> 
> Hello Jan,
> 
> IIUC, your base compiler is "g++ (Debian 20230315-1) 13.0.1 20230315".
> 
> It looks like you are doing a native build with bootstrap. If that's the
> case it should work correctly.
> 
> Can you elaborate how you build GCC?

My host compileris Debian's "gcc-snapshot", by now some two months
old. (As Eric wrote, it's probably just too old.) That compiler is
given for CC/CXX. The new build is just (as I wrote in the initial
mail) the configure/make call. So I'll just wait for the next drop for
Debian's "gcc-snapshot" package. I see that there are already a good
number of additional commits on the package source, I guess a new
package version is imminent.

MfG, JBG

-- 


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Re: [PATCH v2 0/5] A small Texinfo refinement

[NightStrike via Gcc-patches]

On Fri, Mar 10, 2023, 14:00 Gerald Pfeifer  wrote:

> On Fri, 10 Mar 2023, Sandra Loosemore wrote:
> > AFAIK we have not knowingly changed any specific requirements beyond the
> > stated 4.7 and 4.9 for PDF output, but it concerns me that nobody is
> > likely to be using versions that old on a regular basis to make sure
> > they continue to work and we haven't unknowingly introduced dependencies
> > on newer Texinfo features.
>
> I'm generally very interested in ensuring we do not hurt users who do not
> have the latest and greatest of the day. On the other hand, if there's a
> few people using (more or less deliberately abandonware) we should not
> feel too bad if something breaks.
>

Can you include texinfo in a top-level directory and have it built with the
build, like you can with dejagnu? That's generally a decent path for
building new gcc on older systems.

>

Re: [PATCH] Implement ipa_vr hashing.

[Martin Jambor]

Hi,

On Mon, May 22 2023, Aldy Hernandez via Gcc-patches wrote:
> Implement hashing for ipa_vr.  When all is said and done, all these
> patches incurr a 7.64% slowdown for ipa-cp, with is entirely covered by
> the similar 7% increase in this area last week.  So we get type agnostic
> ranges with "infinite" range precision close to free.

Do you know why/where this slow-down happens?  Do we perhaps want to
limit the "infiniteness" a little somehow?

Also, jump functions live for a long time, have you looked at how memory
hungry they become?  I hope that the hashing would be good at preventing
any issues.

Generally, I think I OK with the patches if the impact on memory is not
too bad, though I guess they depend on the one I looked at last week, so
we may focus on that one first.

Thanks,

Martin

>
> There is no change in overall compilation.
>
> OK?
>
> gcc/ChangeLog:
>
>   * ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Adjust for use with
>   ipa_vr instead of value_range.
>   (gt_pch_nx): Same.
>   (gt_ggc_mx): Same.
>   (ipa_get_value_range): Same.
>   * value-range.cc (gt_pch_nx): Move to ipa-prop.cc and adjust for
>   ipa_vr.
>   (gt_ggc_mx): Same.
> ---
>  gcc/ipa-prop.cc| 76 +++---
>  gcc/value-range.cc | 15 -
>  2 files changed, 45 insertions(+), 46 deletions(-)
>
> diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc
> index c46a89f1b49..6383bc11e0a 100644
> --- a/gcc/ipa-prop.cc
> +++ b/gcc/ipa-prop.cc
> @@ -109,53 +109,53 @@ struct ipa_bit_ggc_hash_traits : public 
> ggc_cache_remove 
>  /* Hash table for avoid repeated allocations of equal ipa_bits.  */
>  static GTY ((cache)) hash_table 
> *ipa_bits_hash_table;
>  
> -/* Traits for a hash table for reusing value_ranges used for IPA.  Note that
> -   the equiv bitmap is not hashed and is expected to be NULL.  */
> +/* Traits for a hash table for reusing ranges.  */
>  
> -struct ipa_vr_ggc_hash_traits : public ggc_cache_remove 
> +struct ipa_vr_ggc_hash_traits : public ggc_cache_remove 
>  {
> -  typedef value_range *value_type;
> -  typedef value_range *compare_type;
> +  typedef ipa_vr *value_type;
> +  typedef const vrange *compare_type;
>static hashval_t
> -  hash (const value_range *p)
> +  hash (const ipa_vr *p)
>  {
> -  tree min, max;
> -  value_range_kind kind = get_legacy_range (*p, min, max);
> -  inchash::hash hstate (kind);
> -  inchash::add_expr (min, hstate);
> -  inchash::add_expr (max, hstate);
> +  // This never get called, except in the verification code, as
> +  // ipa_get_value_range() calculates the hash itself.  This
> +  // function is mostly here for completness' sake.
> +  Value_Range vr;
> +  p->get_vrange (vr);
> +  inchash::hash hstate;
> +  add_vrange (vr, hstate);
>return hstate.end ();
>  }
>static bool
> -  equal (const value_range *a, const value_range *b)
> +  equal (const ipa_vr *a, const vrange *b)
>  {
> -  return (types_compatible_p (a->type (), b->type ())
> -   && *a == *b);
> +  return a->equal_p (*b);
>  }
>static const bool empty_zero_p = true;
>static void
> -  mark_empty (value_range *)
> +  mark_empty (ipa_vr *)
>  {
>p = NULL;
>  }
>static bool
> -  is_empty (const value_range *p)
> +  is_empty (const ipa_vr *p)
>  {
>return p == NULL;
>  }
>static bool
> -  is_deleted (const value_range *p)
> +  is_deleted (const ipa_vr *p)
>  {
> -  return p == reinterpret_cast (1);
> +  return p == reinterpret_cast (1);
>  }
>static void
> -  mark_deleted (value_range *)
> +  mark_deleted (ipa_vr *)
>  {
> -  p = reinterpret_cast (1);
> +  p = reinterpret_cast (1);
>  }
>  };
>  
> -/* Hash table for avoid repeated allocations of equal value_ranges.  */
> +/* Hash table for avoid repeated allocations of equal ranges.  */
>  static GTY ((cache)) hash_table *ipa_vr_hash_table;
>  
>  /* Holders of ipa cgraph hooks: */
> @@ -265,6 +265,22 @@ ipa_vr::dump (FILE *out) const
>  fprintf (out, "NO RANGE");
>  }
>  
> +// ?? These stubs are because we use an ipa_vr in a hash_traits and
> +// hash-traits.h defines an extern of gt_ggc_mx (T &) instead of
> +// picking up the gt_ggc_mx (T *) version.
> +void
> +gt_pch_nx (ipa_vr *)
> +{
> +  return gt_pch_nx ((ipa_vr *) x);
> +}
> +
> +void
> +gt_ggc_mx (ipa_vr *)
> +{
> +  return gt_ggc_mx ((ipa_vr *) x);
> +}
> +
> +
>  /* Return true if DECL_FUNCTION_SPECIFIC_OPTIMIZATION of the decl associated
> with NODE should prevent us from analyzing it for the purposes of IPA-CP. 
>  */
>  
> @@ -2284,27 +2300,25 @@ ipa_set_jfunc_bits (ipa_jump_func *jf, const 
> widest_int ,
>jf->bits = ipa_get_ipa_bits_for_value (value, mask);
>  }
>  
> -/* Return a pointer to a value_range just like *TMP, but either find it in
> -   ipa_vr_hash_table or allocate it in GC memory.  TMP->equiv must be NULL.  
> */
> +/* Return a 

[PATCH] rtlanal: Change return type of predicate functions from int to bool

[Uros Bizjak via Gcc-patches]

gcc/ChangeLog:

* rtl.h (rtx_addr_can_trap_p): Change return type from int to bool.
(rtx_unstable_p): Ditto.
(reg_mentioned_p): Ditto.
(reg_referenced_p): Ditto.
(reg_used_between_p): Ditto.
(reg_set_between_p): Ditto.
(modified_between_p): Ditto.
(no_labels_between_p): Ditto.
(modified_in_p): Ditto.
(reg_set_p): Ditto.
(multiple_sets): Ditto.
(set_noop_p): Ditto.
(noop_move_p): Ditto.
(reg_overlap_mentioned_p): Ditto.
(dead_or_set_p): Ditto.
(dead_or_set_regno_p): Ditto.
(find_reg_fusage): Ditto.
(find_regno_fusage): Ditto.
(side_effects_p): Ditto.
(volatile_refs_p): Ditto.
(volatile_insn_p): Ditto.
(may_trap_p_1): Ditto.
(may_trap_p): Ditto.
(may_trap_or_fault_p): Ditto.
(computed_jump_p): Ditto.
(auto_inc_p): Ditto.
(loc_mentioned_in_p): Ditto.
* rtlanal.cc (computed_jump_p_1): Adjust forward declaration.
(rtx_unstable_p): Change return type from int to bool
and adjust function body accordingly.
(rtx_addr_can_trap_p): Ditto.
(reg_mentioned_p): Ditto.
(no_labels_between_p): Ditto.
(reg_used_between_p): Ditto.
(reg_referenced_p): Ditto.
(reg_set_between_p): Ditto.
(reg_set_p): Ditto.
(modified_between_p): Ditto.
(modified_in_p): Ditto.
(multiple_sets): Ditto.
(set_noop_p): Ditto.
(noop_move_p): Ditto.
(reg_overlap_mentioned_p): Ditto.
(dead_or_set_p): Ditto.
(dead_or_set_regno_p): Ditto.
(find_reg_fusage): Ditto.
(find_regno_fusage): Ditto.
(remove_node_from_insn_list): Ditto.
(volatile_insn_p): Ditto.
(volatile_refs_p): Ditto.
(side_effects_p): Ditto.
(may_trap_p_1): Ditto.
(may_trap_p): Ditto.
(may_trap_or_fault_p): Ditto.
(computed_jump_p): Ditto.
(auto_inc_p): Ditto.
(loc_mentioned_in_p): Ditto.
* combine.cc (can_combine_p): Update indirect function.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

OK for master?

Uros.
diff --git a/gcc/combine.cc b/gcc/combine.cc
index a23caeed96f..304c020ec79 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -1735,7 +1735,7 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn 
*pred ATTRIBUTE_UNUSED,
   rtx_insn *p;
   rtx link;
   bool all_adjacent = true;
-  int (*is_volatile_p) (const_rtx);
+  bool (*is_volatile_p) (const_rtx);
 
   if (succ)
 {
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 364782b6060..4041207efd9 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -3612,9 +3612,9 @@ inline rtx single_set (const rtx_insn *insn)
 }
 
 extern scalar_int_mode get_address_mode (rtx mem);
-extern int rtx_addr_can_trap_p (const_rtx);
+extern bool rtx_addr_can_trap_p (const_rtx);
 extern bool nonzero_address_p (const_rtx);
-extern int rtx_unstable_p (const_rtx);
+extern bool rtx_unstable_p (const_rtx);
 extern bool rtx_varies_p (const_rtx, bool);
 extern bool rtx_addr_varies_p (const_rtx, bool);
 extern rtx get_call_rtx_from (const rtx_insn *);
@@ -3626,22 +3626,22 @@ extern void split_const (rtx, rtx *, rtx *);
 extern rtx strip_offset (rtx, poly_int64_pod *);
 extern poly_int64 get_args_size (const_rtx);
 extern bool unsigned_reg_p (rtx);
-extern int reg_mentioned_p (const_rtx, const_rtx);
+extern bool reg_mentioned_p (const_rtx, const_rtx);
 extern int count_occurrences (const_rtx, const_rtx, int);
-extern int reg_referenced_p (const_rtx, const_rtx);
-extern int reg_used_between_p (const_rtx, const rtx_insn *, const rtx_insn *);
-extern int reg_set_between_p (const_rtx, const rtx_insn *, const rtx_insn *);
+extern bool reg_referenced_p (const_rtx, const_rtx);
+extern bool reg_used_between_p (const_rtx, const rtx_insn *, const rtx_insn *);
+extern bool reg_set_between_p (const_rtx, const rtx_insn *, const rtx_insn *);
 extern int commutative_operand_precedence (rtx);
 extern bool swap_commutative_operands_p (rtx, rtx);
-extern int modified_between_p (const_rtx, const rtx_insn *, const rtx_insn *);
-extern int no_labels_between_p (const rtx_insn *, const rtx_insn *);
-extern int modified_in_p (const_rtx, const_rtx);
-extern int reg_set_p (const_rtx, const_rtx);
-extern int multiple_sets (const_rtx);
-extern int set_noop_p (const_rtx);
-extern int noop_move_p (const rtx_insn *);
+extern bool modified_between_p (const_rtx, const rtx_insn *, const rtx_insn *);
+extern bool no_labels_between_p (const rtx_insn *, const rtx_insn *);
+extern bool modified_in_p (const_rtx, const_rtx);
+extern bool reg_set_p (const_rtx, const_rtx);
+extern bool multiple_sets (const_rtx);
+extern bool set_noop_p (const_rtx);
+extern bool noop_move_p (const rtx_insn *);
 extern bool refers_to_regno_p (unsigned int, unsigned int, const_rtx, rtx *);
-extern int reg_overlap_mentioned_p (const_rtx, const_rtx);
+extern bool reg_overlap_mentioned_p (const_rtx, const_rtx);
 extern const_rtx set_of (const_rtx, const_rtx);
 extern void record_hard_reg_sets (rtx, const_rtx, void *);
 extern void record_hard_reg_uses (rtx *, void *);
@@ -3652,14 +3652,14 @@ extern 

Re: [COMMITTED] ada: Remove the body of System.Storage_Elements

[Marc Poulhiès via Gcc-patches]

Jan-Benedict Glaw  writes:

> (A full build log is at
> http://toolchain.lug-owl.de/laminar/jobs/gcc-aarch64-linux/74)
>
> Is this an issue with the patch? Or does it need a newer Ada compiler
> to for building it?

Hello Jan,

IIUC, your base compiler is "g++ (Debian 20230315-1) 13.0.1 20230315".

It looks like you are doing a native build with bootstrap. If that's the
case it should work correctly.

Can you elaborate how you build GCC?

Thanks,
Marc

Re: [COMMITTED] ada: Remove the body of System.Storage_Elements

[Eric Botcazou via Gcc-patches]

> Is this an issue with the patch? Or does it need a newer Ada compiler
> to for building it?

Neither, it's very likely an issue with your build procedure: you need to use 
a matching host Ada compiler to build a cross Ada compiler, that's documented 
in https://gcc.gnu.org/install/prerequisites.html#GNAT-prerequisite

"In order to build a cross compiler, it is strongly recommended to install the 
new compiler as native first, and then use it to build the cross compiler. 
Other native compiler versions may work but this is not guaranteed and will 
typically fail with hard to understand compilation errors during the build."

-- 
Eric Botcazou

[COMMITTED] i386: Also require TARGET_AVX512BW to generate truncv16hiv16qi2 [PR110021]

[Uros Bizjak via Gcc-patches]

gcc/ChangeLog:

PR target/110021
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also require
TARGET_AVX512BW to generate truncv16hiv16qi2.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Uros.
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 0d8953b8c75..5d21810669a 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -23361,7 +23361,7 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, 
rtx op1, rtx op2)
 {
 case E_V16QImode:
   himode = V16HImode;
-  if (TARGET_AVX512VL)
+  if (TARGET_AVX512VL && TARGET_AVX512BW)
gen_truncate = gen_truncv16hiv16qi2;
   break;
 case E_V32QImode:

Re: [COMMITTED] ada: Remove the body of System.Storage_Elements

[Jan-Benedict Glaw]

Hi Eric!

On Tue, 2023-05-23 10:08:26 +0200, Marc Poulhiès via Gcc-patches 
 wrote:
> From: Eric Botcazou 
> 
> All the subprograms declared in the unit have convention Intrinsic and
> their current implementation makes some implicit assumptions that are
> not valid universally, so it is replaced by a direct expansion.
> 
> This is mostly straightforward because Resolve_Intrinsic_Operator already
> contains the required circuitry, but a few adjustements are necessary.

Starting with this commit, my CI builder cannt build GCC:

../gcc/configure '--with-pkgversion=basepoints/gcc-14-1314-gff313e1c74b, built 
at 1685339868' 
--prefix=/var/lib/laminar/run/gcc-aarch64-linux/74/toolchain-install 
--enable-werror-always --enable-languages=all --disable-gcov --disable-shared 
--disable-threads --target=aarch64-linux --without-headers

make V=1 all-gcc
[...]
mkdir -p ada/
/usr/lib/gcc-snapshot/bin/gcc -c -g -O2-gnatpg -gnata -W -Wall -nostdinc 
-I- -I. -Iada/generated -Iada -I../../gcc/gcc/ada -Iada/libgnat 
-I../../gcc/gcc/ada/libgnat -Iada/gcc-interface 
-I../../gcc/gcc/ada/gcc-interface ../../gcc/gcc/ada/spark_xrefs.adb -o 
ada/spark_xrefs.o
s-stoele.ads:84:13: error: unrecognized intrinsic subprogram
make[1]: *** [../../gcc/gcc/ada/gcc-interface/Make-lang.in:165: 
ada/spark_xrefs.o] Error 1
make[1]: Leaving directory 
'/var/lib/laminar/run/gcc-aarch64-linux/74/toolchain-build/gcc'
make: *** [Makefile:4637: all-gcc] Error 2

(A full build log is at
http://toolchain.lug-owl.de/laminar/jobs/gcc-aarch64-linux/74)

Is this an issue with the patch? Or does it need a newer Ada compiler
to for building it?

MfG, JBG

-- 


signature.asc
Description: PGP signature

Re: RISC-V: Use extension instructions instead of bitwise "and"

[Jeff Law via Gcc-patches]

On 5/23/23 13:46, Jivan Hakobyan via Gcc-patches wrote:

In the case where the target supports extension instructions,
it is preferable to use that instead of doing the same in other ways.
For the following case

void foo (unsigned long a, unsigned long* ptr) {
 ptr[0] = a & 0xUL;
 ptr[1] &= 0xUL;
}

GCC generates
foo:
 li  a5,-1
 srlia5,a5,32
 and a0,a0,a5
 sd  a0,0(a1)
 ld  a4,8(a1)
 and a5,a4,a5
 sd  a5,8(a1)
 ret

but it will be profitable to generate this one

foo:
   zext.w a0,a0
   sd a0,0(a1)
   lwu a5,8(a1)
   sd a5,8(a1)
   ret

This patch fixes mentioned issue.
It supports HI -> DI, HI->SI and SI -> DI extensions.

gcc/ChangeLog:
 * config/riscv/riscv.md (and3): New expander.
 (*and3) New pattern.
 * config/riscv/predicates.md (arith_operand_or_mode_mask): New
 predicate.

gcc/testsuite/ChangeLog:
 * gcc.target/riscv/and-extend-1.c: New test
 * gcc.target/riscv/and-extend-2.c: New test

Thanks.  I made some minor whitespace fixes and pushed this to the trunk.

Jeff

RE: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc.

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 9:30 PM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 
; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc.

LGTM

On Mon, May 29, 2023 at 9:03 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to remove unnecessary comments of some self 
> explained parameters and try a better name to avoid misleading.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary
> comments and rename local variables.
> (emit_nonvlmax_insn): Diito.
> (emit_vlmax_merge_insn): Ditto.
> (emit_vlmax_cmp_insn): Ditto.
> (emit_vlmax_cmp_mu_insn): Ditto.
> (emit_scalar_move_insn): Ditto.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-v.cc | 96 
> +++--
>  1 file changed, 49 insertions(+), 47 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc 
> index 20b589bf51b..6ec24dba98d 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -349,16 +349,16 @@ autovec_use_vlmax_p (void)  void  
> emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl)  {
> -  machine_mode data_mode = GET_MODE (ops[0]);
> -  machine_mode mask_mode = get_mask_mode (data_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ true,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ true,
> - /*DEST_MODE*/ data_mode,
> - /*MASK_MODE*/ mask_mode);
> +  machine_mode dest_mode = GET_MODE (ops[0]);  machine_mode mask_mode 
> + = get_mask_mode (dest_mode).require ();  
> + insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ true,
> + /* USE_REAL_MERGE_P */ false,
> + /* HAS_AVL_P */ true,
> + /* VLMAX_P */ true,
> + dest_mode,
> + mask_mode);
>
>e.set_policy (TAIL_ANY);
>e.set_policy (MASK_ANY);
> @@ -373,16 +373,16 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx 
> *ops, rtx vl)  void  emit_nonvlmax_insn (unsigned icode, int op_num, 
> rtx *ops, rtx avl)  {
> -  machine_mode data_mode = GET_MODE (ops[0]);
> -  machine_mode mask_mode = get_mask_mode (data_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ true,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ false,
> - /*DEST_MODE*/ data_mode,
> - /*MASK_MODE*/ mask_mode);
> +  machine_mode dest_mode = GET_MODE (ops[0]);  machine_mode mask_mode 
> + = get_mask_mode (dest_mode).require ();  
> + insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ true,
> + /* USE_REAL_MERGE_P */ false,
> + /* HAS_AVL_P */ true,
> + /* VLMAX_P */ false,
> + dest_mode,
> + mask_mode);
>
>e.set_policy (TAIL_ANY);
>e.set_policy (MASK_ANY);
> @@ -396,14 +396,14 @@ emit_vlmax_merge_insn (unsigned icode, int 
> op_num, rtx *ops)  {
>machine_mode dest_mode = GET_MODE (ops[0]);
>machine_mode mask_mode = get_mask_mode (dest_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ false,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ true,
> - /*DEST_MODE*/ dest_mode,
> - /*MASK_MODE*/ mask_mode);
> +  insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ 

Re: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc.

[Kito Cheng via Gcc-patches]

LGTM

On Mon, May 29, 2023 at 9:03 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to remove unnecessary comments of some self
> explained parameters and try a better name to avoid misleading.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary
> comments and rename local variables.
> (emit_nonvlmax_insn): Diito.
> (emit_vlmax_merge_insn): Ditto.
> (emit_vlmax_cmp_insn): Ditto.
> (emit_vlmax_cmp_mu_insn): Ditto.
> (emit_scalar_move_insn): Ditto.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-v.cc | 96 +++--
>  1 file changed, 49 insertions(+), 47 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 20b589bf51b..6ec24dba98d 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -349,16 +349,16 @@ autovec_use_vlmax_p (void)
>  void
>  emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl)
>  {
> -  machine_mode data_mode = GET_MODE (ops[0]);
> -  machine_mode mask_mode = get_mask_mode (data_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ true,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ true,
> - /*DEST_MODE*/ data_mode,
> - /*MASK_MODE*/ mask_mode);
> +  machine_mode dest_mode = GET_MODE (ops[0]);
> +  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
> +  insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ true,
> + /* USE_REAL_MERGE_P */ false,
> + /* HAS_AVL_P */ true,
> + /* VLMAX_P */ true,
> + dest_mode,
> + mask_mode);
>
>e.set_policy (TAIL_ANY);
>e.set_policy (MASK_ANY);
> @@ -373,16 +373,16 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, 
> rtx vl)
>  void
>  emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl)
>  {
> -  machine_mode data_mode = GET_MODE (ops[0]);
> -  machine_mode mask_mode = get_mask_mode (data_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ true,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ false,
> - /*DEST_MODE*/ data_mode,
> - /*MASK_MODE*/ mask_mode);
> +  machine_mode dest_mode = GET_MODE (ops[0]);
> +  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
> +  insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ true,
> + /* USE_REAL_MERGE_P */ false,
> + /* HAS_AVL_P */ true,
> + /* VLMAX_P */ false,
> + dest_mode,
> + mask_mode);
>
>e.set_policy (TAIL_ANY);
>e.set_policy (MASK_ANY);
> @@ -396,14 +396,14 @@ emit_vlmax_merge_insn (unsigned icode, int op_num, rtx 
> *ops)
>  {
>machine_mode dest_mode = GET_MODE (ops[0]);
>machine_mode mask_mode = get_mask_mode (dest_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ false,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ true,
> - /*DEST_MODE*/ dest_mode,
> - /*MASK_MODE*/ mask_mode);
> +  insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ false,
> + /* USE_REAL_MERGE_P */ false,
> + /* HAS_AVL_P */ true,
> + /* VLMAX_P */ true,
> + dest_mode,
> +

[PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc.

[Pan Li via Gcc-patches]

From: Pan Li 

This patch would like to remove unnecessary comments of some self
explained parameters and try a better name to avoid misleading.

Signed-off-by: Pan Li 

gcc/ChangeLog:

* config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary
comments and rename local variables.
(emit_nonvlmax_insn): Diito.
(emit_vlmax_merge_insn): Ditto.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(emit_scalar_move_insn): Ditto.

Signed-off-by: Pan Li 
---
 gcc/config/riscv/riscv-v.cc | 96 +++--
 1 file changed, 49 insertions(+), 47 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 20b589bf51b..6ec24dba98d 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -349,16 +349,16 @@ autovec_use_vlmax_p (void)
 void
 emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl)
 {
-  machine_mode data_mode = GET_MODE (ops[0]);
-  machine_mode mask_mode = get_mask_mode (data_mode).require ();
-  insn_expander e (/*OP_NUM*/ op_num,
- /*HAS_DEST_P*/ true,
- /*FULLY_UNMASKED_P*/ true,
- /*USE_REAL_MERGE_P*/ false,
- /*HAS_AVL_P*/ true,
- /*VLMAX_P*/ true,
- /*DEST_MODE*/ data_mode,
- /*MASK_MODE*/ mask_mode);
+  machine_mode dest_mode = GET_MODE (ops[0]);
+  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
+  insn_expander e (op_num,
+ /* HAS_DEST_P */ true,
+ /* FULLY_UNMASKED_P */ true,
+ /* USE_REAL_MERGE_P */ false,
+ /* HAS_AVL_P */ true,
+ /* VLMAX_P */ true,
+ dest_mode,
+ mask_mode);
 
   e.set_policy (TAIL_ANY);
   e.set_policy (MASK_ANY);
@@ -373,16 +373,16 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, 
rtx vl)
 void
 emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl)
 {
-  machine_mode data_mode = GET_MODE (ops[0]);
-  machine_mode mask_mode = get_mask_mode (data_mode).require ();
-  insn_expander e (/*OP_NUM*/ op_num,
- /*HAS_DEST_P*/ true,
- /*FULLY_UNMASKED_P*/ true,
- /*USE_REAL_MERGE_P*/ false,
- /*HAS_AVL_P*/ true,
- /*VLMAX_P*/ false,
- /*DEST_MODE*/ data_mode,
- /*MASK_MODE*/ mask_mode);
+  machine_mode dest_mode = GET_MODE (ops[0]);
+  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
+  insn_expander e (op_num,
+ /* HAS_DEST_P */ true,
+ /* FULLY_UNMASKED_P */ true,
+ /* USE_REAL_MERGE_P */ false,
+ /* HAS_AVL_P */ true,
+ /* VLMAX_P */ false,
+ dest_mode,
+ mask_mode);
 
   e.set_policy (TAIL_ANY);
   e.set_policy (MASK_ANY);
@@ -396,14 +396,14 @@ emit_vlmax_merge_insn (unsigned icode, int op_num, rtx 
*ops)
 {
   machine_mode dest_mode = GET_MODE (ops[0]);
   machine_mode mask_mode = get_mask_mode (dest_mode).require ();
-  insn_expander e (/*OP_NUM*/ op_num,
- /*HAS_DEST_P*/ true,
- /*FULLY_UNMASKED_P*/ false,
- /*USE_REAL_MERGE_P*/ false,
- /*HAS_AVL_P*/ true,
- /*VLMAX_P*/ true,
- /*DEST_MODE*/ dest_mode,
- /*MASK_MODE*/ mask_mode);
+  insn_expander e (op_num,
+ /* HAS_DEST_P */ true,
+ /* FULLY_UNMASKED_P */ false,
+ /* USE_REAL_MERGE_P */ false,
+ /* HAS_AVL_P */ true,
+ /* VLMAX_P */ true,
+ dest_mode,
+ mask_mode);
 
   e.set_policy (TAIL_ANY);
   e.emit_insn ((enum insn_code) icode, ops);
@@ -414,14 +414,14 @@ void
 emit_vlmax_cmp_insn (unsigned icode, rtx *ops)
 {
   machine_mode mode = GET_MODE (ops[0]);
-  insn_expander 

RE: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[Li, Pan2 via Gcc-patches]

Looks there may be unnecessary due to  the release/gcc-13 has the code as is.

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 15f66efaa48..cd696da5d89 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -388,7 +388,7 @@ (define_attr "avl_type" ""
 (symbol_ref "INTVAL (operands[7])"))

 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
- viwalu,viwmul,vnshift,vimuladd,vaalu,vsmul,vsshift,\
+ viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
  
vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
  vfsgnj,vfcmp,vfmuladd,vslideup,vslidedown,vislide1up,\
  
vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 6:35 PM
To: Li, Pan2 
Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng 
; palmer ; Robin Dapp 
; jeffreyalaw 
Subject: Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

pushed the bug fixed part to gcc 13 branch

On Mon, May 29, 2023 at 12:52 PM Li, Pan2 via Gcc-patches 
 wrote:
>
> Committed with 2 patches, thanks Kito.
>
> Pan
>
> From: juzhe.zh...@rivai.ai 
> Sent: Monday, May 29, 2023 11:19 AM
> To: kito.cheng 
> Cc: gcc-patches ; Kito.cheng 
> ; palmer ; Robin Dapp 
> ; jeffreyalaw ; Li, Pan2 
> 
> Subject: Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization 
> support
>
> This is existing bug in GCC 13. I think I should split into 2 patches.
>
> 
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-05-29 11:17
> To: juzhe.zhong
> CC: gcc-patches; 
> kito.cheng; 
> palmer; 
> rdapp.gcc; 
> jeffreyalaw; 
> pan2.li
> Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support 
> LGTM, but with one question.
>
> On Fri, May 26, 2023 at 7:36 PM 
> mailto:juzhe.zh...@rivai.ai>> wrote:
> >
> > From: Juzhe-Zhong 
> > mailto:juzhe.zh...@rivai.ai>>
> >
> > This patch support FMA auto-vectorization pattern.
> > 1. Let's RA decide vmacc or vmadd.
> > 2. Fix bug of vector.md which generate incorrect information to VSETVL
> >PASS when testing ternop-3.c.
>
> Does this bug also appear in GCC 13? or this is new bug introduced at 
> trunk
>

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

[Jeff Law via Gcc-patches]

On 5/28/23 21:46, Jin Ma wrote:

When testing a extension, it is often necessary for a certain program not to
need some kind of extension, such as the bitmanip extension, to evaluate the
performance or codesize of the extension. However, the current multilib rules
will report an error when it is not a superset of the MULTILIB_REQUIRED list,
which will cause the program to be unable to link normally, thus failing to
achieve the expected purpose.


  Hmm, I have troubles understanding what is going on here.  What do you
refer to by saying: "it is not a superset of the MULTILIB_REQUIRED list"?


This is a new matching rule added by kito for the multilib of riscv:
https://github.com/gcc-mirror/gcc/commit/d72ca12b846a9f5c01674b280b1817876c77888f


  There should be no problem with linking compiled modules together that
make use of different extensions, with the static linker figuring out the
combined set of extensions actually required at run time for the program
loader to consider, as long as the modules do not have contradicting
requirements, e.g. big vs little endianness or RV32 vs RV64.

  Can you give me a specific example (compilation options and multilibs
available) of a failure you refer to?


A simple example:
1. Use "--disable-multilib --with-abi =lp64d --with-arch 
=rv64imafdc_zba_zbb_zbc_zbs"
to build the toolchain".
2. Use the toolchain to test the impact of zba_zbb_zbc_zbs extensions on the
performance and codesize of some functions or files in the program.

In this case, I may need to use the command "-mabi=lp64d -march=rv64imafdc" for
the compilation of a specific .c file in the program, which will cause the link 
to
fail and throw the following error: "FATAL ERROR: Can't find suitable multilib 
set for
'-march=rv64imafdc'/'-mabi=lp64d'". This does not satisfy the purpose of the 
test.


I feel this case should be build with --with-arch =rv64imafdc and test
with -march=rv64imafdc and  -march=rv64imafdc_zba_zbb_zbc_zbs,
but anyway I am OK with option :P


Yes, but with "--with-arch=rv64imafdc" building toolchains, the library will 
not contain
zba_zbb_zbc_zbs extensions, so how can we quickly and easily eliminate the 
impact of not
using zba_zbb_zbc_zbs extensions in a certain program on program performance 
and codesize?

Although-mno-multilib-check is unsafe, it is useful during the development and 
testing phases.
But I'm not sure that's a good reason to include an unsafe option like 
this in the official GCC sources.


This is the kind of thing that I'd tend to think belongs as a local change.

jeff

Re: [PATCH] RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE.

[Jeff Law via Gcc-patches]

On 5/29/23 05:01, Jin Ma wrote:

Reference: 
https://github.com/gcc-mirror/gcc/commit/d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5

RISC-V should also be implemented to handle no_insn patterns for pipelining.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): New function.
(TARGET_SCHED_VARIABLE_ISSUE): New macro.
---
  gcc/config/riscv/riscv.cc | 21 +
  1 file changed, 21 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3954fc07a8b..559fa9cd7e0 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6225,6 +6225,24 @@ riscv_issue_rate (void)
return tune_param->issue_rate;
  }
  
+/* Implement TARGET_SCHED_VARIABLE_ISSUE.  */

+
+static int
+riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
+{
+  if (DEBUG_INSN_P (insn))
+return more;
+
+  rtx_code code = GET_CODE (PATTERN (insn));
+  if (code == USE || code == CLOBBER)
+return more;
+
+  if (get_attr_type (insn) == TYPE_UNKNOWN)
+return more;
+
+  return more - 1;
+}
The problem is that INSN is *much* more likely to be a real instruction 
that takes real resources, even if it is TYPE_UNKNOWN.
TYPE_UNKNOWN here is actually an indicator of what I would consider a 
bug in the backend, specifically that we have INSNs that do not provide 
a mapping for the schedulers to suitable types.


With that in mind I'd much rather get to the point where we can do 
something like this for TYPE_UNKNOWN:


type = get_attr_type (insn);
gcc_assert (type != TYPE_UNKNOWN);

That way if we ever encounter a TYPE_UNKNOWN during development, we can 
fix it in the md files in a sensible manner.  I don't know if we are 
close to being able to do that.  We fixed a ton of stuff in bitmanip.md, 
but I don't think there's been a thorough review of the port to find 
other instances of TYPE_UNKNOWN INSNs.



The other thing if this code probably wants to handle GHOST type 
instructions.  While GHOST is used for instructions which generate no 
code, it might seem they should return "more" as those INSNs take no 
resources.  But GHOST is actually used for things like the blockage insn 
which should end a cycle from an issue standpoint.  So the right 
handling of a GHOST is something like this:


if (type == TYPE_GHOST)
  return 0;

Jeff

[PATCH] RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE.

[Jin Ma via Gcc-patches]

Reference: 
https://github.com/gcc-mirror/gcc/commit/d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5

RISC-V should also be implemented to handle no_insn patterns for pipelining.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): New function.
(TARGET_SCHED_VARIABLE_ISSUE): New macro.
---
 gcc/config/riscv/riscv.cc | 21 +
 1 file changed, 21 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3954fc07a8b..559fa9cd7e0 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6225,6 +6225,24 @@ riscv_issue_rate (void)
   return tune_param->issue_rate;
 }
 
+/* Implement TARGET_SCHED_VARIABLE_ISSUE.  */
+
+static int
+riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
+{
+  if (DEBUG_INSN_P (insn))
+return more;
+
+  rtx_code code = GET_CODE (PATTERN (insn));
+  if (code == USE || code == CLOBBER)
+return more;
+
+  if (get_attr_type (insn) == TYPE_UNKNOWN)
+return more;
+
+  return more - 1;
+}
+
 /* Auxiliary function to emit RISC-V ELF attribute. */
 static void
 riscv_emit_attribute ()
@@ -7671,6 +7689,9 @@ riscv_vectorize_related_mode (machine_mode vector_mode, 
scalar_mode element_mode
 #undef TARGET_SCHED_ISSUE_RATE
 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
 
+#undef  TARGET_SCHED_VARIABLE_ISSUE
+#define TARGET_SCHED_VARIABLE_ISSUE riscv_sched_variable_issue
+
 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
 
-- 
2.17.1

[PATCH] In the pipeline, UNRECOG INSN is not executed in advance if it starts a live range.

[Jin Ma via Gcc-patches]

  Unrecog insns (such as CLOBBER, USE) does not represent real instructions, 
but in the
process of pipeline optimization, they will wait for transmission in ready list 
like
other insns, without considering resource conflicts and cycles. This results in 
a
multi-issue CPU architecture that can be issued at any time if other regular 
insns
have resource conflicts or cannot be launched for other reasons. As a result, 
its
position is advanced in the generated insns sequence, which will affect register
allocation and often lead to more redundant mov instructions.

A simple example:
https://github.com/majin2020/gcc-test/blob/master/test.c
This is a function in the dhrystone benchmark.

https://github.com/majin2020/gcc-test/blob/0b08c1a13de9663d7d9aba7539b960ec0607ca24/test.c.299r.sched1
This is a log of the pass 'sched1' When issue_rate == 2. Among them, insn 13 
and 14 are
much ahead of schedule, which risks generating redundant mov instructions, 
which seems
unreasonable.

Therefore, I submit patch again on the basis of the last review opinions to try 
to solve
this problem.

This is the new log of shed1 after patch is added.
https://github.com/majin2020/gcc-test/commit/efcb43e3369e771bde702955048bfe3f501263dd

gcc/ChangeLog:

* haifa-sched.cc (unrecog_insn_for_forw_only_p): New.
(prune_ready_list): UNRECOG INSN is not executed in advance if it 
starts a
live range.
---
 gcc/haifa-sched.cc | 44 +++-
 1 file changed, 39 insertions(+), 5 deletions(-)

diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc
index 2c881ede0ec..205680a4936 100644
--- a/gcc/haifa-sched.cc
+++ b/gcc/haifa-sched.cc
@@ -765,6 +765,23 @@ real_insn_for_shadow (rtx_insn *insn)
   return pair->i1;
 }
 
+/* Return true if INSN is unrecog that starts a live range.  */
+
+static bool
+unrecog_insn_for_forw_only_p (rtx_insn *insn)
+{
+  if (insn && !INSN_P (insn) && recog_memoized (insn) >= 0)
+return false;
+
+  if ((GET_CODE (PATTERN (insn)) == CLOBBER
+   || GET_CODE (PATTERN (insn)) == USE)
+  && !sd_lists_empty_p (insn, SD_LIST_FORW)
+  && sd_lists_empty_p (insn, SD_LIST_BACK))
+return true;
+
+  return false;
+}
+
 /* For a pair P of insns, return the fixed distance in cycles from the first
insn after which the second must be scheduled.  */
 static int
@@ -6320,11 +6337,28 @@ prune_ready_list (state_t temp_state, bool 
first_cycle_insn_p,
}
  else if (recog_memoized (insn) < 0)
{
- if (!first_cycle_insn_p
- && (GET_CODE (PATTERN (insn)) == ASM_INPUT
- || asm_noperands (PATTERN (insn)) >= 0))
-   cost = 1;
- reason = "asm";
+ if (GET_CODE (PATTERN (insn)) == ASM_INPUT
+ || asm_noperands (PATTERN (insn)) >= 0)
+   {
+ reason = "asm";
+ if (!first_cycle_insn_p)
+   cost = 1;
+   }
+ else if (unrecog_insn_for_forw_only_p (insn))
+   {
+ reason = "unrecog insn";
+ if (!first_cycle_insn_p)
+   cost = 1;
+ else
+   {
+ int j = i;
+ while (n > ++j)
+   if (!unrecog_insn_for_forw_only_p (ready_element 
(, j)))
+ break;
+
+ cost = (j == n) ? 0 : 1;
+   }
+   }
}
  else if (sched_pressure != SCHED_PRESSURE_NONE)
{
-- 
2.17.1

Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[Kito Cheng via Gcc-patches]

pushed the bug fixed part to gcc 13 branch

On Mon, May 29, 2023 at 12:52 PM Li, Pan2 via Gcc-patches
 wrote:
>
> Committed with 2 patches, thanks Kito.
>
> Pan
>
> From: juzhe.zh...@rivai.ai 
> Sent: Monday, May 29, 2023 11:19 AM
> To: kito.cheng 
> Cc: gcc-patches ; Kito.cheng 
> ; palmer ; Robin Dapp 
> ; jeffreyalaw ; Li, Pan2 
> 
> Subject: Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
>
> This is existing bug in GCC 13. I think I should split into 2 patches.
>
> 
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-05-29 11:17
> To: juzhe.zhong
> CC: gcc-patches; 
> kito.cheng; palmer; 
> rdapp.gcc; 
> jeffreyalaw; pan2.li
> Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
> LGTM, but with one question.
>
> On Fri, May 26, 2023 at 7:36 PM 
> mailto:juzhe.zh...@rivai.ai>> wrote:
> >
> > From: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>
> >
> > This patch support FMA auto-vectorization pattern.
> > 1. Let's RA decide vmacc or vmadd.
> > 2. Fix bug of vector.md which generate incorrect information to VSETVL
> >PASS when testing ternop-3.c.
>
> Does this bug also appear in GCC 13? or this is new bug introduced at trunk
>

RE: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Li, Pan2 
Sent: Monday, May 29, 2023 1:38 PM
To: Kito Cheng 
Cc: Robin Dapp ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang 

Subject: RE: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

Thanks Kito, will commit this after the vec_init repeated sequence patch.

Pan

-Original Message-
From: Kito Cheng 
Sent: Monday, May 29, 2023 10:20 AM
To: Li, Pan2 
Cc: Robin Dapp ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang 

Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

LGTM

On Fri, May 26, 2023 at 2:32 PM Li, Pan2 via Gcc-patches 
 wrote:
>
> Thanks Robin.
>
> Sorry for not mentioned that it depends on another patch 
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619536.html, which is in 
> the reviewing queue.
>
> Yes, totally agree we can remove the comments for some parameters excepts the 
> Boolean ones, as well as the term data related. I can file another PATCH to 
> make it happen due to it is another thing besides magic number elimination.
>
> Pan
>
> -Original Message-
> From: Robin Dapp 
> Sent: Friday, May 26, 2023 2:24 PM
> To: Li, Pan2 ; gcc-patches@gcc.gnu.org
> Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; 
> Wang, Yanzhang 
> Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc
>
> Hi,
>
> > This patch would like to remove the magic number in the riscv-v.cc, 
> > and align the same value to one macro.
>
> > diff --git a/gcc/config/riscv/riscv-v.cc 
> > b/gcc/config/riscv/riscv-v.cc index 458020ce0a1..20b589bf51b 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -351,13 +351,15 @@ emit_vlmax_insn (unsigned icode, int op_num, 
> > rtx *ops, rtx vl)  {
> >machine_mode data_mode = GET_MODE (ops[0]);
> >machine_mode mask_mode = get_mask_mode (data_mode).require ();
> > -  /* We have a maximum of 11 operands for RVV instruction patterns 
> > according to
> > -   * vector.md.  */
> > -  insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
> > -/*FULLY_UNMASKED_P*/ true,
> > -/*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true,
> > -/*VLMAX_P*/ true,
> > -/*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode);
> > +  insn_expander e (/*OP_NUM*/ op_num,
> > +   /*HAS_DEST_P*/ true,
> > +   /*FULLY_UNMASKED_P*/ true,
> > +   /*USE_REAL_MERGE_P*/ false,
> > +   /*HAS_AVL_P*/ true,
> > +   /*VLMAX_P*/ true,
> > +   /*DEST_MODE*/ data_mode,
> > +   /*MASK_MODE*/ mask_mode);
>
> I don't see where RVV_INSN_OPERANDS_MAX is defined.  Maybe you missed to 
> include that hunk?
>
> Apart from that maybe you could also remove the comments for dest_mode, 
> mask_mode and op_num?  I think the general "custom" is to just add them for 
> bool arguments and name non-bool arguments descriptively.  Here that could 
> mean renaming data_mode to dest_mode where appropriate (usually data_mode is 
> used to distinguish between data mode and comparison mode in conditionals, 
> not in regular insns where everything is "data").
>
> Regards
>  Robin

[PATCH] mips: Fix overaligned function arguments [PR109435]

[Jovan Dmitrovic]

This patch changes alignment for typedef types when passed as
arguments, making the alignment equal to the alignment of
original (aliased) types.

This change makes it impossible for a typedef type to have
alignment that is less than its size.

Signed-off-by: Jovan Dmitrovic 

gcc/ChangeLog:
PR target/109435
* config/mips/mips.cc (mips_function_arg_alignment): Returns
the alignment of function argument. In case of typedef type,
it returns the aligment of the aliased type.
(mips_function_arg_boundary): Relocated calculation of the
aligment of function arguments.

gcc/testsuite/ChangeLog:
PR target/109435
* gcc.target/mips/align-1.c: New test.
---
 gcc/config/mips/mips.cc | 18 +-
 gcc/testsuite/gcc.target/mips/align-1.c | 33 +
 2 files changed, 50 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/align-1.c

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ca822758b41..2019b7cd7d9 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -6190,6 +6190,22 @@ mips_arg_partial_bytes (cumulative_args_t cum, const 
function_arg_info )
   return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
 }
 
+/* Given MODE and TYPE of a function argument, return the alignment in
+   bits. In case of typedef, alignment of its original type is
+   used.  */
+
+static unsigned int
+mips_function_arg_alignment (machine_mode mode, const_tree type)
+{
+  if (!type)
+return GET_MODE_ALIGNMENT (mode);
+
+  if (is_typedef_decl (TYPE_NAME (type)))
+type = DECL_ORIGINAL_TYPE (TYPE_NAME (type));
+
+  return TYPE_ALIGN (type);
+}
+
 /* Implement TARGET_FUNCTION_ARG_BOUNDARY.  Every parameter gets at
least PARM_BOUNDARY bits of alignment, but will be given anything up
to STACK_BOUNDARY bits if the type requires it.  */
@@ -6198,8 +6214,8 @@ static unsigned int
 mips_function_arg_boundary (machine_mode mode, const_tree type)
 {
   unsigned int alignment;
+  alignment = mips_function_arg_alignment (mode, type);
 
-  alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
   if (alignment < PARM_BOUNDARY)
 alignment = PARM_BOUNDARY;
   if (alignment > STACK_BOUNDARY)
diff --git a/gcc/testsuite/gcc.target/mips/align-1.c 
b/gcc/testsuite/gcc.target/mips/align-1.c
new file mode 100644
index 000..816751b8099
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/align-1.c
@@ -0,0 +1,33 @@
+/* Check that typedef alignment does not affect passing of function
+   parameters. */
+/* { dg-do run { target { "mips*-*-linux*" } } } */
+
+#include 
+
+typedef struct ui8
+{
+  unsigned v[8];
+} uint8 __attribute__ ((aligned(64)));
+
+unsigned
+callee (int x, uint8 a)
+{
+  return a.v[0];
+}
+
+uint8
+identity (uint8 in)
+{
+  return in;
+}
+
+int
+main (void)
+{
+  uint8 vec = {{1, 2, 3, 4, 5, 6, 7, 8}};
+  uint8 temp = identity (vec);
+  unsigned temp2 = callee (1, identity (vec));
+  assert (callee (1, temp) == 1);
+  assert (temp2 == 1);
+  return 0;
+}
-- 
2.34.1

Re: [C PATCH 3/4] introduce ubsan checking for assigment of VM types 3/4

[Martin Uecker via Gcc-patches]

c: introduce ubsan checking for assigment of VM types 3/4

Support instrumentation of function arguments for functions
called via a declaration.  We can support only simple size
expressions without side effects, because the UBSan
instrumentation is done before the call, but the expressions
are evaluated in the callee.

gcc/c-family:
* c-ubsan.cc (ubsan_instrument_vm_assign): Add arguments
for size expressions.
* c-ubsan.h (ubsan_instrument_vm_assign): Dito.

gcc/c:
* c-typeck.cc (process_vm_constraints): Add support
for instrumenting function arguments.

gcc/testsuide/gcc.dg:
* ubsan/vm-bounds-2.c: Update.
* ubsan/vm-bounds-3.c: New test.
* ubsan/vm-bounds-4.c: New test.

diff --git a/gcc/c-family/c-ubsan.cc b/gcc/c-family/c-ubsan.cc
index 59ef9708188..a8f95aa39e8 100644
--- a/gcc/c-family/c-ubsan.cc
+++ b/gcc/c-family/c-ubsan.cc
@@ -337,19 +337,13 @@ ubsan_instrument_vla (location_t loc, tree size)
 /* Instrument assignment of variably modified types.  */
 
 tree
-ubsan_instrument_vm_assign (location_t loc, tree a, tree b)
+ubsan_instrument_vm_assign (location_t loc, tree a, tree as, tree b, tree bs)
 {
   tree t, tt;
 
   gcc_assert (TREE_CODE (a) == ARRAY_TYPE);
   gcc_assert (TREE_CODE (b) == ARRAY_TYPE);
 
-  tree as = TYPE_MAX_VALUE (TYPE_DOMAIN (a));
-  tree bs = TYPE_MAX_VALUE (TYPE_DOMAIN (b));
-
-  as = fold_build2 (PLUS_EXPR, sizetype, as, size_one_node);
-  bs = fold_build2 (PLUS_EXPR, sizetype, bs, size_one_node);
-
   t = build2 (NE_EXPR, boolean_type_node, as, bs);
   if (flag_sanitize_trap & SANITIZE_VLA)
 tt = build_call_expr_loc (loc, builtin_decl_explicit (BUILT_IN_TRAP), 0);
diff --git a/gcc/c-family/c-ubsan.h b/gcc/c-family/c-ubsan.h
index 1b07b0645f2..42be1d691a8 100644
--- a/gcc/c-family/c-ubsan.h
+++ b/gcc/c-family/c-ubsan.h
@@ -26,7 +26,7 @@ extern tree ubsan_instrument_shift (location_t, enum 
tree_code, tree, tree);
 extern tree ubsan_instrument_vla (location_t, tree);
 extern tree ubsan_instrument_return (location_t);
 extern tree ubsan_instrument_bounds (location_t, tree, tree *, bool);
-extern tree ubsan_instrument_vm_assign (location_t, tree, tree);
+extern tree ubsan_instrument_vm_assign (location_t, tree, tree, tree, tree);
 extern bool ubsan_array_ref_instrumented_p (const_tree);
 extern void ubsan_maybe_instrument_array_ref (tree *, bool);
 extern void ubsan_maybe_instrument_reference (tree *);
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index a8fccc6f6ed..aeddac315fc 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -3408,7 +3408,8 @@ static tree
 convert_argument (location_t ploc, tree function, tree fundecl,
  tree type, tree origtype, tree val, tree valtype,
  bool npc, tree rname, int parmnum, int argnum,
- bool excess_precision, int warnopt)
+ bool excess_precision, int warnopt,
+ vec *instr_vec)
 {
   /* Formal parm type is specified by a function prototype.  */
 
@@ -3567,7 +3568,7 @@ convert_argument (location_t ploc, tree function, tree 
fundecl,
val, origtype, ic_argpass,
npc, fundecl, function,
parmnum + 1, warnopt,
-   NULL);
+   instr_vec);
 
   if (targetm.calls.promote_prototypes (fundecl ? TREE_TYPE (fundecl) : 0)
   && INTEGRAL_TYPE_P (type)
@@ -3582,15 +3583,111 @@ convert_argument (location_t ploc, tree function, tree 
fundecl,
 
 static tree
 process_vm_constraints (location_t location,
-   vec *instr_vec)
+   vec *instr_vec,
+   tree function, tree fundecl, vec *values)
 {
   unsigned int i;
   struct instrument_data* d;
   tree instr_expr = void_node;
+  tree args = NULL;
+
+  /* Find the arguments for the function declaration / type.  */
+  if (function)
+{
+  if (FUNCTION_DECL == TREE_CODE (function))
+   {
+ fundecl = function;
+ args = DECL_ARGUMENTS (fundecl);
+   }
+  else
+   {
+ /* Functions called via pointers are not yet supported.  */
+ return void_node;
+   }
+}
 
   FOR_EACH_VEC_SAFE_ELT (instr_vec, i, d)
 {
-  tree in = ubsan_instrument_vm_assign (location, d->t1, d->t2);
+  tree t1 = d->t1;
+  tree t2 = d->t2;
+
+  gcc_assert (ARRAY_TYPE == TREE_CODE (t1));
+  gcc_assert (ARRAY_TYPE == TREE_CODE (t2));
+
+  tree as = TYPE_MAX_VALUE (TYPE_DOMAIN (t1));
+  tree bs = TYPE_MAX_VALUE (TYPE_DOMAIN (t2));
+
+  gcc_assert (as);
+  gcc_assert (bs);
+
+  as = fold_build2 (PLUS_EXPR, sizetype, as, size_one_node);
+  bs = fold_build2 (PLUS_EXPR, sizetype, bs, size_one_node);
+
+   

Re: [C PATCH 2/4] introduce ubsan checking for assigment of VM types 2/4

[Martin Uecker via Gcc-patches]

c: introduce ubsan checking for assigment of VM types 2/4

When checking compatibility of types during assignment, collect
all pairs of types where the outermost bound needs to match at
run-time.  This list is then processed to add UBSan checks for
each bound.

gcc/c-family:
* c-ubsan.cc (ubsan_instrument_vm_assign): New function.
* c-ubsan.h (ubsan_instrument_vm_assign: New function.

gcc/c:
* c-typeck.cc (struct instrument_data). New structure.
(comp_target_types_instr convert_for_assignment_instrument): New
interfaces for existing functions.
(struct comptypes_data): Add instrumentation.
(comptypes_check_enum_int_intr): New interface.
(comptypes_check_enum_int): Old interface (calls new).
(comptypes_internal): Collect VLA types needed for UBSan.
(comp_target_types_instr): New interface.
(comp_target_types): Old interface (calls new).
(function_types_compatible_p): No instrumentation for function
arguments.
(process_vm_constraints): New function.
(convert_for_assignment_instrument): New interface.
(convert_for_assignment): Instrument assignments.
* sanitizer.def: Add sanitizer builtins.

gcc/testsuite:
* gcc.dg/ubsan/vm-bounds-1.c: New test.
* gcc.dg/ubsan/vm-bounds-1b.c: New test.
* gcc.dg/ubsan/vm-bounds-2.c: New test.

libsanitizer/ubsan:
* ubsan_checks.inc: Add UBSan check.
* ubsan_handlers.cpp (handleVMBoundsMismatch): New function.
* ubsan_handlers.h (struct VMBoundsMismatchData): New structure.
(vm_bounds_mismatch): New handler.

diff --git a/gcc/c-family/c-ubsan.cc b/gcc/c-family/c-ubsan.cc
index 51aa83a378d..59ef9708188 100644
--- a/gcc/c-family/c-ubsan.cc
+++ b/gcc/c-family/c-ubsan.cc
@@ -334,6 +334,48 @@ ubsan_instrument_vla (location_t loc, tree size)
   return t;
 }
 
+/* Instrument assignment of variably modified types.  */
+
+tree
+ubsan_instrument_vm_assign (location_t loc, tree a, tree b)
+{
+  tree t, tt;
+
+  gcc_assert (TREE_CODE (a) == ARRAY_TYPE);
+  gcc_assert (TREE_CODE (b) == ARRAY_TYPE);
+
+  tree as = TYPE_MAX_VALUE (TYPE_DOMAIN (a));
+  tree bs = TYPE_MAX_VALUE (TYPE_DOMAIN (b));
+
+  as = fold_build2 (PLUS_EXPR, sizetype, as, size_one_node);
+  bs = fold_build2 (PLUS_EXPR, sizetype, bs, size_one_node);
+
+  t = build2 (NE_EXPR, boolean_type_node, as, bs);
+  if (flag_sanitize_trap & SANITIZE_VLA)
+tt = build_call_expr_loc (loc, builtin_decl_explicit (BUILT_IN_TRAP), 0);
+  else
+{
+  tree data = ubsan_create_data ("__ubsan_vm_data", 1, ,
+ubsan_type_descriptor (a, 
UBSAN_PRINT_ARRAY),
+ubsan_type_descriptor (b, 
UBSAN_PRINT_ARRAY),
+ubsan_type_descriptor (sizetype),
+NULL_TREE, NULL_TREE);
+  data = build_fold_addr_expr_loc (loc, data);
+  enum built_in_function bcode
+   = (flag_sanitize_recover & SANITIZE_VLA)
+ ? BUILT_IN_UBSAN_HANDLE_VM_BOUNDS_MISMATCH
+ : BUILT_IN_UBSAN_HANDLE_VM_BOUNDS_MISMATCH_ABORT;
+  tt = builtin_decl_explicit (bcode);
+  tt = build_call_expr_loc (loc, tt, 3, data,
+   ubsan_encode_value (as),
+   ubsan_encode_value (bs));
+}
+  t = build3 (COND_EXPR, void_type_node, t, tt, void_node);
+
+  return t;
+}
+
+
 /* Instrument missing return in C++ functions returning non-void.  */
 
 tree
diff --git a/gcc/c-family/c-ubsan.h b/gcc/c-family/c-ubsan.h
index fef1033e1e4..1b07b0645f2 100644
--- a/gcc/c-family/c-ubsan.h
+++ b/gcc/c-family/c-ubsan.h
@@ -26,6 +26,7 @@ extern tree ubsan_instrument_shift (location_t, enum 
tree_code, tree, tree);
 extern tree ubsan_instrument_vla (location_t, tree);
 extern tree ubsan_instrument_return (location_t);
 extern tree ubsan_instrument_bounds (location_t, tree, tree *, bool);
+extern tree ubsan_instrument_vm_assign (location_t, tree, tree);
 extern bool ubsan_array_ref_instrumented_p (const_tree);
 extern void ubsan_maybe_instrument_array_ref (tree *, bool);
 extern void ubsan_maybe_instrument_reference (tree *);
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index 2a1b7321b45..a8fccc6f6ed 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -94,6 +94,9 @@ struct comptypes_data;
 static int tagged_types_tu_compatible_p (const_tree, const_tree,
 struct comptypes_data *);
 static int comp_target_types (location_t, tree, tree);
+struct instrument_data;
+static int comp_target_types_instr (location_t, tree, tree,
+   vec *);
 static int function_types_compatible_p (const_tree, const_tree,
struct comptypes_data *);
 

RE: [PATCH v7] RISC-V: Using merge approach to optimize repeating sequence in vec_init

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 5:33 PM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, 
Yanzhang 
Subject: Re: [PATCH v7] RISC-V: Using merge approach to optimize repeating 
sequence in vec_init

LGTM, thanks

On Mon, May 29, 2023 at 4:54 PM Pan Li via Gcc-patches 
 wrote:
>
> From: Pan Li 
>
> This patch would like to optimize the VLS vector initialization like 
> repeating sequence. From the vslide1down to the vmerge with a simple 
> cost model, aka every instruction only has 1 cost.
>
> Given code with -march=rv64gcv_zvl256b --param 
> riscv-autovec-preference=fixed-vlmax
> typedef int64_t vnx32di __attribute__ ((vector_size (256)));
>
> __attribute__ ((noipa)) void
> f_vnx32di (int64_t a, int64_t b, int64_t *out) {
>   vnx32di v = {
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
>   };
>   *(vnx32di *) out = v;
> }
>
> Before this patch:
> vslide1down.vx (x31 times)
>
> After this patch:
> li  a5,-1431654400
> addia5,a5,-1365
> li  a3,-1431654400
> addia3,a3,-1366
> sllia5,a5,32
> add a5,a5,a3
> vsetvli a4,zero,e64,m8,ta,ma
> vmv.v.x v8,a0
> vmv.s.x v0,a5
> vmerge.vxm  v8,v8,a1,v0
> vs8r.v  v8,0(a2)
>
> Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab 
> into SEW = 128 element and then broadcast this big element.
>
> Signed-off-by: Pan Li  Co-Authored by: Juzhe-Zhong 
> 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (enum insn_type): New type.
> * config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
> (rvv_builder::can_duplicate_repeating_sequence_p): Align the 
> referenced
> class member.
> (rvv_builder::get_merged_repeating_sequence): Ditto.
> (rvv_builder::repeating_sequence_use_merge_profitable_p): New function
> to evaluate the optimization cost.
> (rvv_builder::get_merge_scalar_mask): New function to get the merge
> mask.
> (emit_scalar_move_insn): New function to emit vmv.s.x.
> (emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
> (emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
> vmv.v.x.
> (get_repeating_sequence_dup_machine_mode): New function to get the dup
> machine mode.
> (expand_vector_init_merge_repeating_sequence): New function to perform
> the optimization.
> (expand_vec_init): Add this vector init optimization.
> * config/riscv/riscv.h (BITS_PER_WORD): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: 
> New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-protos.h   |   1 +
>  gcc/config/riscv/riscv-v.cc   | 225 +-
>  gcc/config/riscv/riscv.h  |   1 +
>  .../vls-vlmax/init-repeat-sequence-1.c|  21 ++
>  .../vls-vlmax/init-repeat-sequence-2.c|  24 ++
>  .../vls-vlmax/init-repeat-sequence-3.c|  25 ++
>  .../vls-vlmax/init-repeat-sequence-4.c|  15 ++
>  .../vls-vlmax/init-repeat-sequence-5.c|  17 ++
>  .../vls-vlmax/init-repeat-sequence-run-1.c|  47 
>  .../vls-vlmax/init-repeat-sequence-run-2.c|  46 
>  .../vls-vlmax/init-repeat-sequence-run-3.c|  41 
>  11 files changed, 457 insertions(+), 6 deletions(-)  create mode 
> 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-1.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-2.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-3.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-4.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-5.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-run-1.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-run-2.c  create mode 100644 
> 

Re: [C PATCH 4/4] introduce ubsan checking for assigment of VM types 4/4

[Martin Uecker via Gcc-patches]

c: introduce ubsan checking for assigment of VM types 4/4

Support instrumentation of functions called via pointers.  To do so,
record the declaration with the parameter types, so that it can be
retrieved later.

gcc/c:
c-decl.cc (get_parm_info): Record function declaration
for arguments.
c-type.cc (process_vm_constraints): Instrument functions
called via pointers.

gcc/testsuide/gcc.dg:
* ubsan/vm-bounds-2.c: Add warning.
* ubsan/vm-bounds-5.c: New test.

diff --git a/gcc/c/c-decl.cc b/gcc/c/c-decl.cc
index 1af51c4acfc..c33adf7e5fe 100644
--- a/gcc/c/c-decl.cc
+++ b/gcc/c/c-decl.cc
@@ -8410,6 +8410,9 @@ get_parm_info (bool ellipsis, tree expr)
 declared types.  The back end may override this later.  */
  DECL_ARG_TYPE (decl) = type;
  types = tree_cons (0, type, types);
+
+ /* Record the decl for use of UBSan bounds checking.  */
+ TREE_PURPOSE (types) = decl;
}
  break;
 
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index aeddac315fc..43e7b96a55f 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -3601,9 +3601,20 @@ process_vm_constraints (location_t location,
}
   else
{
- /* Functions called via pointers are not yet supported.  */
- return void_node;
+ while (FUNCTION_TYPE != TREE_CODE (function))
+   function = TREE_TYPE (function);
+
+ args = TREE_PURPOSE (TYPE_ARG_TYPES (function));
+
+ if (!args)
+   {
+ /* FIXME: this can happen when forming composite types for the
+conditional operator.  */
+ warning_at (location, 0, "Function call not instrumented.");
+ return void_node;
+   }
}
+  gcc_assert (PARM_DECL == TREE_CODE (args));
 }
 
   FOR_EACH_VEC_SAFE_ELT (instr_vec, i, d)
diff --git a/gcc/testsuite/gcc.dg/ubsan/vm-bounds-2.c 
b/gcc/testsuite/gcc.dg/ubsan/vm-bounds-2.c
index 22f06231eaa..093cbddd2ea 100644
--- a/gcc/testsuite/gcc.dg/ubsan/vm-bounds-2.c
+++ b/gcc/testsuite/gcc.dg/ubsan/vm-bounds-2.c
@@ -31,7 +31,7 @@ void f(void)
 
int u = 3; int v = 4;
char a[u][v];
-   (1 ? f1 : f2)(u, v, a);
+   (1 ? f1 : f2)(u, v, a); /* { dg-warning "Function call not 
instrumented." } */
 }
 
 /* size expression in parameter */
diff --git a/gcc/testsuite/gcc.dg/ubsan/vm-bounds-5.c 
b/gcc/testsuite/gcc.dg/ubsan/vm-bounds-5.c
new file mode 100644
index 000..1a251e39deb
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ubsan/vm-bounds-5.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-options "-fsanitize=vla-bound" } */
+
+
+void foo1(void (*p)(int n, char (*a)[n]))
+{
+   char A0[3];
+   (*p)(3, );
+   (*p)(4, );   /* */
+   /* { dg-output "bound 4 of type 'char \\\[\\\*\\\]' does not match 
bound 3 of type 'char \\\[3\\\]'\[^\n\r]*(\n|\r\n|\r)" } */
+}
+
+void b0(int n, char (*a)[n]) { }
+
+
+int n;
+
+void foo2(void (*p)(int n, char (*a)[n]))
+{
+   n = 4;
+   char A0[3];
+   (*p)(3, );
+   (*p)(4, );
+   /* { dg-output "\[^\n\r]*bound 4 of type 'char \\\[\\\*\\\]' does not 
match bound 3 of type 'char \\\[3\\\]'\[^\n\r]*(\n|\r\n|\r)" } */
+}
+
+void foo3(void (*p)(int n0, char (*a)[n]))
+{
+   n = 4;
+   char A0[3];
+   (*p)(3, );   /* */
+   /* { dg-output "\[^\n\r]*bound 4 of type 'char \\\[\\\*\\\]' does not 
match bound 3 of type 'char \\\[3\\\]'\[^\n\r]*(\n|\r\n|\r)" } */
+   (*p)(4, );   /* */
+   /* { dg-output "\[^\n\r]*bound 4 of type 'char \\\[\\\*\\\]' does not 
match bound 3 of type 'char \\\[3\\\]'\[^\n\r]*(\n|\r\n|\r)" } */
+}
+
+void foo4(void (*p)(int n, char (*a)[n]))
+{
+   n = 3;
+   char A0[3];
+   (*p)(3, );
+   (*p)(4, );   /* */
+   /* { dg-output "\[^\n\r]*bound 4 of type 'char \\\[\\\*\\\]' does not 
match bound 3 of type 'char \\\[3\\\]'" } */
+}
+
+
+void foo5(void (*p)(int n0, char (*a)[n]))
+{
+   n = 3;
+   char A0[3];
+   (*p)(3, );
+   (*p)(4, );
+}
+
+
+void b1(int n0, char (*a)[n]) { }
+
+
+
+int main()
+{
+   foo1();
+
+   foo2();
+   foo3(); // we should diagnose mismatch and run-time discrepancies
+
+   foo4();
+   foo5(); // we should diagnose mismatch and run-time discrepancies
+}
+
+
+

[C PATCH 1/4] introduce ubsan checking for assigment of VM types 1/4

[Martin Uecker via Gcc-patches]

Hi Joseph and Martin,

this series adds UBSan checking for assignment of variably-modified
types, i.e. it checks that size expressions on both sides of the 
assignment match.

1. no functional change, adds a structure argument to the
comptypes family functions in the C FE.

2. checking for all assignments except function arguments
including the libsanitizer changes (no upstream discussion so far)

3. checking for function arguments, but only when the function is
referenced using its declaration.

4. checking for functions called via a pointer


Q1: Should this be -fsanitize=vla-bound ? I used it because it is
related and does not have much functionality.

Q2: I now have warnings when a function can not be instrumented
because size expressions are too complicated or information was
lost before. Probably this needs to have a flag.

Martin



c: introduce ubsan checking for assigment of VM types 1/4

Reorganize recursive type checking to use a structure to
store information collected during the recursion and
returned to the caller (enum_and_init_p, different_types_p).

gcc/c:
* c-typeck.cc (struct comptypes_data): Add structure.
(tagged_types_tu_compatible_p,
function_types_compatible_p, type_lists_compatible_p,
comptyes_internal): Add structure to interface and
adapt calls.
(comptypes, comptypes_check_enum_int,
comptypes_check_different_types): Adapt calls.

diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index 22e240a3c2a..2a1b7321b45 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -90,12 +90,14 @@ static bool require_constant_elements;
 static bool require_constexpr_value;
 
 static tree qualify_type (tree, tree);
-static int tagged_types_tu_compatible_p (const_tree, const_tree, bool *,
-bool *);
+struct comptypes_data;
+static int tagged_types_tu_compatible_p (const_tree, const_tree,
+struct comptypes_data *);
 static int comp_target_types (location_t, tree, tree);
-static int function_types_compatible_p (const_tree, const_tree, bool *,
-   bool *);
-static int type_lists_compatible_p (const_tree, const_tree, bool *, bool *);
+static int function_types_compatible_p (const_tree, const_tree,
+   struct comptypes_data *);
+static int type_lists_compatible_p (const_tree, const_tree,
+   struct comptypes_data *);
 static tree lookup_field (tree, tree);
 static int convert_arguments (location_t, vec, tree,
  vec *, vec *, tree,
@@ -125,7 +127,8 @@ static tree find_init_member (tree, struct obstack *);
 static void readonly_warning (tree, enum lvalue_use);
 static int lvalue_or_else (location_t, const_tree, enum lvalue_use);
 static void record_maybe_used_decl (tree);
-static int comptypes_internal (const_tree, const_tree, bool *, bool *);
+static int comptypes_internal (const_tree, const_tree,
+  struct comptypes_data *data);
 
 /* Return true if EXP is a null pointer constant, false otherwise.  */
 
@@ -1039,6 +1042,12 @@ common_type (tree t1, tree t2)
   return c_common_type (t1, t2);
 }
 
+struct comptypes_data {
+
+  bool enum_and_int_p;
+  bool different_types_p;
+};
+
 /* Return 1 if TYPE1 and TYPE2 are compatible types for assignment
or various other operations.  Return 2 if they are compatible
but a warning may be needed if you use them together.  */
@@ -1049,7 +1058,9 @@ comptypes (tree type1, tree type2)
   const struct tagged_tu_seen_cache * tagged_tu_seen_base1 = 
tagged_tu_seen_base;
   int val;
 
-  val = comptypes_internal (type1, type2, NULL, NULL);
+  struct comptypes_data data = { };
+  val = comptypes_internal (type1, type2, );
+
   free_all_tagged_tu_seen_up_to (tagged_tu_seen_base1);
 
   return val;
@@ -1064,7 +1075,10 @@ comptypes_check_enum_int (tree type1, tree type2, bool 
*enum_and_int_p)
   const struct tagged_tu_seen_cache * tagged_tu_seen_base1 = 
tagged_tu_seen_base;
   int val;
 
-  val = comptypes_internal (type1, type2, enum_and_int_p, NULL);
+  struct comptypes_data data = { };
+  val = comptypes_internal (type1, type2, );
+  *enum_and_int_p = data.enum_and_int_p;
+
   free_all_tagged_tu_seen_up_to (tagged_tu_seen_base1);
 
   return val;
@@ -1080,7 +1094,10 @@ comptypes_check_different_types (tree type1, tree type2,
   const struct tagged_tu_seen_cache * tagged_tu_seen_base1 = 
tagged_tu_seen_base;
   int val;
 
-  val = comptypes_internal (type1, type2, NULL, different_types_p);
+  struct comptypes_data data = { };
+  val = comptypes_internal (type1, type2, );
+  *different_types_p = data.different_types_p;
+
   free_all_tagged_tu_seen_up_to (tagged_tu_seen_base1);
 
   return val;
@@ -1089,19 +1106,18 @@ comptypes_check_different_types (tree type1, tree type2,
 /* Return 1 if TYPE1 and TYPE2 are 

[COMMITTED] MAINTAINERS file: Replace spaces with tabs

[Martin Jambor]

Hi,

This change, separating Benjamin's name and email address with tabs
rather than spaces, makes contrib/check-MAINTAINERS.py script happy
about our MAINTAINERS file again, so I tool the liberty of committing
this as obvious.

Thanks,

Martin


ChangeLog:

2023-05-29  Martin Jambor  

* MAINTAINERS: Replace spaces with tabs.
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b1d174af280..2dc51154446 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -600,7 +600,7 @@ Antoniu Pop 

 Siddhesh Poyarekar 
 Vidya Praveen  
 Thomas Preud'homme 
-Benjamin Priour 
+Benjamin Priour
 Vladimir Prus  
 Hafiz Abid Qadeer  
 Yao Qi 
-- 
2.40.1

Re: [PATCH v7] RISC-V: Using merge approach to optimize repeating sequence in vec_init

[Kito Cheng via Gcc-patches]

LGTM, thanks

On Mon, May 29, 2023 at 4:54 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to optimize the VLS vector initialization like
> repeating sequence. From the vslide1down to the vmerge with a simple
> cost model, aka every instruction only has 1 cost.
>
> Given code with -march=rv64gcv_zvl256b --param 
> riscv-autovec-preference=fixed-vlmax
> typedef int64_t vnx32di __attribute__ ((vector_size (256)));
>
> __attribute__ ((noipa)) void
> f_vnx32di (int64_t a, int64_t b, int64_t *out)
> {
>   vnx32di v = {
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
>   };
>   *(vnx32di *) out = v;
> }
>
> Before this patch:
> vslide1down.vx (x31 times)
>
> After this patch:
> li  a5,-1431654400
> addia5,a5,-1365
> li  a3,-1431654400
> addia3,a3,-1366
> sllia5,a5,32
> add a5,a5,a3
> vsetvli a4,zero,e64,m8,ta,ma
> vmv.v.x v8,a0
> vmv.s.x v0,a5
> vmerge.vxm  v8,v8,a1,v0
> vs8r.v  v8,0(a2)
>
> Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab into
> SEW = 128 element and then broadcast this big element.
>
> Signed-off-by: Pan Li 
> Co-Authored by: Juzhe-Zhong 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (enum insn_type): New type.
> * config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
> (rvv_builder::can_duplicate_repeating_sequence_p): Align the 
> referenced
> class member.
> (rvv_builder::get_merged_repeating_sequence): Ditto.
> (rvv_builder::repeating_sequence_use_merge_profitable_p): New function
> to evaluate the optimization cost.
> (rvv_builder::get_merge_scalar_mask): New function to get the merge
> mask.
> (emit_scalar_move_insn): New function to emit vmv.s.x.
> (emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
> (emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
> vmv.v.x.
> (get_repeating_sequence_dup_machine_mode): New function to get the dup
> machine mode.
> (expand_vector_init_merge_repeating_sequence): New function to perform
> the optimization.
> (expand_vec_init): Add this vector init optimization.
> * config/riscv/riscv.h (BITS_PER_WORD): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: 
> New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-protos.h   |   1 +
>  gcc/config/riscv/riscv-v.cc   | 225 +-
>  gcc/config/riscv/riscv.h  |   1 +
>  .../vls-vlmax/init-repeat-sequence-1.c|  21 ++
>  .../vls-vlmax/init-repeat-sequence-2.c|  24 ++
>  .../vls-vlmax/init-repeat-sequence-3.c|  25 ++
>  .../vls-vlmax/init-repeat-sequence-4.c|  15 ++
>  .../vls-vlmax/init-repeat-sequence-5.c|  17 ++
>  .../vls-vlmax/init-repeat-sequence-run-1.c|  47 
>  .../vls-vlmax/init-repeat-sequence-run-2.c|  46 
>  .../vls-vlmax/init-repeat-sequence-run-3.c|  41 
>  11 files changed, 457 insertions(+), 6 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 0462f96c8d5..277845673d4 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -142,6 +142,7 @@ enum insn_type
>RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff 

[PATCH v7] RISC-V: Using merge approach to optimize repeating sequence in vec_init

[Pan Li via Gcc-patches]

From: Pan Li 

This patch would like to optimize the VLS vector initialization like
repeating sequence. From the vslide1down to the vmerge with a simple
cost model, aka every instruction only has 1 cost.

Given code with -march=rv64gcv_zvl256b --param 
riscv-autovec-preference=fixed-vlmax
typedef int64_t vnx32di __attribute__ ((vector_size (256)));

__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
  vnx32di v = {
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
  };
  *(vnx32di *) out = v;
}

Before this patch:
vslide1down.vx (x31 times)

After this patch:
li  a5,-1431654400
addia5,a5,-1365
li  a3,-1431654400
addia3,a3,-1366
sllia5,a5,32
add a5,a5,a3
vsetvli a4,zero,e64,m8,ta,ma
vmv.v.x v8,a0
vmv.s.x v0,a5
vmerge.vxm  v8,v8,a1,v0
vs8r.v  v8,0(a2)

Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab into
SEW = 128 element and then broadcast this big element.

Signed-off-by: Pan Li 
Co-Authored by: Juzhe-Zhong 

gcc/ChangeLog:

* config/riscv/riscv-protos.h (enum insn_type): New type.
* config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
(rvv_builder::can_duplicate_repeating_sequence_p): Align the referenced
class member.
(rvv_builder::get_merged_repeating_sequence): Ditto.
(rvv_builder::repeating_sequence_use_merge_profitable_p): New function
to evaluate the optimization cost.
(rvv_builder::get_merge_scalar_mask): New function to get the merge
mask.
(emit_scalar_move_insn): New function to emit vmv.s.x.
(emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
(emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
vmv.v.x.
(get_repeating_sequence_dup_machine_mode): New function to get the dup
machine mode.
(expand_vector_init_merge_repeating_sequence): New function to perform
the optimization.
(expand_vec_init): Add this vector init optimization.
* config/riscv/riscv.h (BITS_PER_WORD): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: New 
test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: New 
test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: New 
test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: New 
test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: New 
test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: 
New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: 
New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: 
New test.

Signed-off-by: Pan Li 
---
 gcc/config/riscv/riscv-protos.h   |   1 +
 gcc/config/riscv/riscv-v.cc   | 225 +-
 gcc/config/riscv/riscv.h  |   1 +
 .../vls-vlmax/init-repeat-sequence-1.c|  21 ++
 .../vls-vlmax/init-repeat-sequence-2.c|  24 ++
 .../vls-vlmax/init-repeat-sequence-3.c|  25 ++
 .../vls-vlmax/init-repeat-sequence-4.c|  15 ++
 .../vls-vlmax/init-repeat-sequence-5.c|  17 ++
 .../vls-vlmax/init-repeat-sequence-run-1.c|  47 
 .../vls-vlmax/init-repeat-sequence-run-2.c|  46 
 .../vls-vlmax/init-repeat-sequence-run-3.c|  41 
 11 files changed, 457 insertions(+), 6 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 0462f96c8d5..277845673d4 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -142,6 +142,7 @@ enum insn_type
   RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand.  */
   RVV_UNOP_MU = RVV_UNOP + 2,/* Likewise.  */
   RVV_TERNOP = 5,
+  RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md.  */
 };
 enum vlmul_type
 {
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a5715bb466c..8c920532549 100644
--- 

RE: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence

[Li, Pan2 via Gcc-patches]

Updated the PATCH v7 for comments addressing.

https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619939.html

Pan

From: Li, Pan2
Sent: Thursday, May 25, 2023 11:17 AM
To: juzhe.zh...@rivai.ai; gcc-patches 
Cc: Kito.cheng ; Wang, Yanzhang 
Subject: RE: [PATCH v6] RISC-V: Using merge approach to optimize repeating 
sequence

Oops, forget to remove it in previous version, will wait a while and update 
them together.

Pan

From: juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>
Sent: Thursday, May 25, 2023 11:14 AM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v6] RISC-V: Using merge approach to optimize repeating 
sequence


* machmode.h (VECTOR_BOOL_MODE_P): New macro.

--- a/gcc/machmode.h

+++ b/gcc/machmode.h

@@ -134,6 +134,10 @@ extern const unsigned char mode_class[NUM_MACHINE_MODES];

|| GET_MODE_CLASS (MODE) == MODE_VECTOR_ACCUM\

|| GET_MODE_CLASS (MODE) == MODE_VECTOR_UACCUM)



+/* Nonzero if MODE is a vector bool mode.  */

+#define VECTOR_BOOL_MODE_P(MODE)\

+  (GET_MODE_CLASS (MODE) == MODE_VECTOR_BOOL)   \

+
Why do you add this? But no use. You should drop this.


juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-05-25 11:09
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to optimize the VLS vector initialization like
repeating sequence. From the vslide1down to the vmerge with a simple
cost model, aka every instruction only has 1 cost.

Given code with -march=rv64gcv_zvl256b --param 
riscv-autovec-preference=fixed-vlmax
typedef int64_t vnx32di __attribute__ ((vector_size (256)));

__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
  vnx32di v = {
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
  };
  *(vnx32di *) out = v;
}

Before this patch:
vslide1down.vx (x31 times)

After this patch:
li a5,-1431654400
addi a5,a5,-1365
li a3,-1431654400
addi a3,a3,-1366
slli a5,a5,32
add a5,a5,a3
vsetvli a4,zero,e64,m8,ta,ma
vmv.v.x v8,a0
vmv.s.x v0,a5
vmerge.vxm v8,v8,a1,v0
vs8r.v v8,0(a2)

Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab into
SEW = 128 element and then broadcast this big element.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored by: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

gcc/ChangeLog:

* config/riscv/riscv-protos.h (enum insn_type): New type.
* config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
(rvv_builder::can_duplicate_repeating_sequence_p): Align the
referenced class member.
(rvv_builder::get_merged_repeating_sequence):
(rvv_builder::repeating_sequence_use_merge_profitable_p): New
function to evaluate the optimization cost.
(rvv_builder::get_merge_scalar_mask): New function to get the
merge mask.
(emit_scalar_move_insn): New function to emit vmv.s.x.
(emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
(emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
vmv.v.x.
(get_repeating_sequence_dup_machine_mode): New function to get
the dup machine mode.
(expand_vector_init_merge_repeating_sequence): New function to
perform the optimization.
(expand_vec_init): Add this vector init optimization.
* config/riscv/riscv.h (BITS_PER_WORD): New macro.
* machmode.h (VECTOR_BOOL_MODE_P): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: New test.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
---
gcc/config/riscv/riscv-protos.h   |   1 +
gcc/config/riscv/riscv-v.cc   | 225 +-
gcc/config/riscv/riscv.h  |   1 +
gcc/machmode.h|   4 +
.../vls-vlmax/init-repeat-sequence-1.c|  21 ++
.../vls-vlmax/init-repeat-sequence-2.c|  24 ++
.../vls-vlmax/init-repeat-sequence-3.c|  25 

[COMMITTED] ada: Use Code_Address attribute to determine subprogram addresses

[Marc Poulhiès via Gcc-patches]

From: Patrick Bernardi 

The runtime used label addresses to determine the code address of
subprograms because the subprogram's canonical address on some targets
is a descriptor or a stub. Simplify the code by using the Code_Address
attribute instead, which is designed to return the code address of a
subprogram. This also works around a current GNAT-LLVM limitation where
the address of a label is incorrectly calculated when using -O1. As a
result, we can now build a-except.adb and g-debpoo.adb at -O1 again with
GNAT-LLVM.

gcc/ada/

* libgnat/a-excach.adb (Call_Chain): Replace
Code_Address_For_AAA/ZZZ functions with AAA/ZZZ'Code_Address.
* libgnat/a-except.adb (Code_Address_For_AAA/ZZZ): Delete.
(AAA/ZZZ): New null procedures.
* libgnat/g-debpoo.adb
(Code_Address_For_Allocate_End): Delete.
(Code_Address_For_Deallocate_End): Delete.
(Code_Address_For_Dereference_End): Delete.
(Allocate): Remove label and use Code_Address attribute to
determine subprogram addresses.
(Dellocate): Likewise.
(Dereference): Likewise.
(Allocate_End): Convert to null procedure.
(Dellocate_End): Likewise.
(Dereference_End): Likewise.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/libgnat/a-excach.adb |  4 +-
 gcc/ada/libgnat/a-except.adb | 60 -
 gcc/ada/libgnat/g-debpoo.adb | 73 +++-
 3 files changed, 48 insertions(+), 89 deletions(-)

diff --git a/gcc/ada/libgnat/a-excach.adb b/gcc/ada/libgnat/a-excach.adb
index 840da0c439f..784194d421e 100644
--- a/gcc/ada/libgnat/a-excach.adb
+++ b/gcc/ada/libgnat/a-excach.adb
@@ -66,8 +66,8 @@ begin
 (Traceback   => Excep.Tracebacks,
  Max_Len => Max_Tracebacks,
  Len => Excep.Num_Tracebacks,
- Exclude_Min => Code_Address_For_AAA,
- Exclude_Max => Code_Address_For_ZZZ,
+ Exclude_Min => AAA'Code_Address,
+ Exclude_Max => ZZZ'Code_Address,
  Skip_Frames => 3);
end if;
 
diff --git a/gcc/ada/libgnat/a-except.adb b/gcc/ada/libgnat/a-except.adb
index 7d728d6acfa..20a773661ae 100644
--- a/gcc/ada/libgnat/a-except.adb
+++ b/gcc/ada/libgnat/a-except.adb
@@ -65,29 +65,32 @@ package body Ada.Exceptions is
--  from C clients using the given external name, even though they are not
--  technically visible in the Ada sense.
 
-   function Code_Address_For_AAA return System.Address;
-   function Code_Address_For_ZZZ return System.Address;
-   --  Return start and end of procedures in this package
+   procedure AAA;
+   procedure ZZZ;
+   --  Start and end of procedures in this package
--
-   --  These procedures are used to provide exclusion bounds in
-   --  calls to Call_Chain at exception raise points from this unit. The
-   --  purpose is to arrange for the exception tracebacks not to include
-   --  frames from subprograms involved in the raise process, as these are
-   --  meaningless from the user's standpoint.
+   --  These procedures are used to provide exclusion bounds in calls to
+   --  Call_Chain at exception raise points from this unit. The purpose is
+   --  to arrange for the exception tracebacks not to include frames from
+   --  subprograms involved in the raise process, as these are meaningless
+   --  from the user's standpoint.
--
--  For these bounds to be meaningful, we need to ensure that the object
-   --  code for the subprograms involved in processing a raise is located
-   --  after the object code Code_Address_For_AAA and before the object
-   --  code Code_Address_For_ZZZ. This will indeed be the case as long as
-   --  the following rules are respected:
+   --  code for the subprograms involved in processing a raise is located after
+   --  the object code AAA and before the object code ZZZ. This will indeed be
+   --  the case as long as the following rules are respected:
--
--  1) The bodies of the subprograms involved in processing a raise
-   -- are located after the body of Code_Address_For_AAA and before the
-   -- body of Code_Address_For_ZZZ.
+   -- are located after the body of AAA and before the body of ZZZ.
--
--  2) No pragma Inline applies to any of these subprograms, as this
-- could delay the corresponding assembly output until the end of
-- the unit.
+   --
+   --  To obtain the address of AAA and ZZZ, use the Code_Address attribute
+   --  instead of the Address attribute as the latter will return the address
+   --  of a stub or descriptor on some platforms. This include IA-64,
+   --  PowerPC/AIX, big-endian PowerPC64 and HPUX.
 
procedure Call_Chain (Excep : EOA);
--  Store up to Max_Tracebacks in Excep, corresponding to the current
@@ -771,24 +774,15 @@ package body Ada.Exceptions is
Rmsg_36 : constant String := "stream operation not allowed" & NUL;
Rmsg_37 : constant String := "build-in-place 

[COMMITTED] ada: Set g-spogwa as a GNATRTL_SOCKETS_OBJS

[Marc Poulhiès via Gcc-patches]

From: Cedric Landet 

g-spogwa.adb is the body of the procedure GNAT.Sockets.Poll.G_Wait.
This is a socket specific procedure. It should only be built for
systems that support sockets.

gcc/ada/

* Makefile.rtl: Move g-spogwa$(objext) from GNATRTL_NONTASKING_OBJS
to GNATRTL_SOCKETS_OBJS

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/Makefile.rtl | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index 3da32fa6668..e2f437ff6e5 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -478,7 +478,6 @@ GNATRTL_NONTASKING_OBJS= \
   g-speche$(objext) \
   g-spipat$(objext) \
   g-spitbo$(objext) \
-  g-spogwa$(objext) \
   g-sptabo$(objext) \
   g-sptain$(objext) \
   g-sptavs$(objext) \
@@ -856,7 +855,7 @@ GNATLIB_SHARED = gnatlib
 # to LIBGNAT_TARGET_PAIRS.
 
 GNATRTL_SOCKETS_OBJS = g-soccon$(objext) g-socket$(objext) g-socthi$(objext) \
-  g-soliop$(objext) g-sothco$(objext) g-socpol$(objext)
+  g-soliop$(objext) g-sothco$(objext) g-socpol$(objext) g-spogwa$(objext)
 
 DUMMY_SOCKETS_TARGET_PAIRS = \
   g-socket.adb

[COMMITTED] ada: Define sigset for systems that does not suport sockets

[Marc Poulhiès via Gcc-patches]

From: Cedric Landet 

In s-oscons-tmplt.c, sigset is defined inside the HAVE_SOCKETS bloc.
A platform could require sigset without supporting sockets.

gcc/ada/

* s-oscons-tmplt.c: move the definition of sigset out of the
HAVE_SOCKETS bloc.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/s-oscons-tmplt.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/ada/s-oscons-tmplt.c b/gcc/ada/s-oscons-tmplt.c
index 5480e55a5bb..28d42c5a459 100644
--- a/gcc/ada/s-oscons-tmplt.c
+++ b/gcc/ada/s-oscons-tmplt.c
@@ -1796,11 +1796,6 @@ CND(SIZEOF_struct_hostent, "struct hostent")
 #define SIZEOF_struct_servent (sizeof (struct servent))
 CND(SIZEOF_struct_servent, "struct servent")
 
-#if defined (__linux__) || defined (__ANDROID__) || defined (__QNX__)
-#define SIZEOF_sigset (sizeof (sigset_t))
-CND(SIZEOF_sigset, "sigset")
-#endif
-
 #if defined(_WIN32) || defined(__vxworks)
 #define SIZEOF_nfds_t sizeof (int) * 8
 #define SIZEOF_socklen_t sizeof (size_t)
@@ -1938,6 +1933,11 @@ CST(Poll_Linkname, "")
 
 #endif /* HAVE_SOCKETS */
 
+#if defined (__linux__) || defined (__ANDROID__) || defined (__QNX__)
+#define SIZEOF_sigset (sizeof (sigset_t))
+CND(SIZEOF_sigset, "sigset")
+#endif
+
 /*
 
-
-- 
2.40.0

[COMMITTED] ada: Remove extra whitespace from FOR loops

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Whitespace cleanup.

gcc/ada/
* doc/gnat_ugn/gnat_and_program_execution.rst
(Some Useful Memory Pools): Remove extra whitespace from examples.
* sem_aggr.adb (Make_String_Into_Aggregate): Remove extra whitespace.
* gnat_ugn.texi: Regenerate.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst | 4 ++--
 gcc/ada/gnat_ugn.texi   | 6 +++---
 gcc/ada/sem_aggr.adb| 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst 
b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst
index 5dab2d45626..9eb6b1c60aa 100644
--- a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst
+++ b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst
@@ -3530,12 +3530,12 @@ leak memory even though it does not perform explicit 
deallocation:
for A'Storage_Pool use X;
v : A;
 begin
-   for I in  1 .. 50 loop
+   for I in 1 .. 50 loop
   v := new Integer;
end loop;
 end Internal;
  begin
-for I in  1 .. 100 loop
+for I in 1 .. 100 loop
Internal;
 end loop;
  end Pooloc1;
diff --git a/gcc/ada/gnat_ugn.texi b/gcc/ada/gnat_ugn.texi
index be234881f37..3d94a1ad255 100644
--- a/gcc/ada/gnat_ugn.texi
+++ b/gcc/ada/gnat_ugn.texi
@@ -22302,12 +22302,12 @@ procedure Pooloc1 is
   for A'Storage_Pool use X;
   v : A;
begin
-  for I in  1 .. 50 loop
+  for I in 1 .. 50 loop
  v := new Integer;
   end loop;
end Internal;
 begin
-   for I in  1 .. 100 loop
+   for I in 1 .. 100 loop
   Internal;
end loop;
 end Pooloc1;
@@ -29479,8 +29479,8 @@ to permit their use in free software.
 
 @printindex ge
 
-@anchor{cf}@w{  }
 @anchor{gnat_ugn/gnat_utility_programs switches-related-to-project-files}@w{   
   }
+@anchor{cf}@w{  }
 
 @c %**end of body
 @bye
diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb
index edd495b8359..73046267256 100644
--- a/gcc/ada/sem_aggr.adb
+++ b/gcc/ada/sem_aggr.adb
@@ -828,7 +828,7 @@ package body Sem_Aggr is
 
begin
   P := Loc + 1;
-  for J in  1 .. Strlen loop
+  for J in 1 .. Strlen loop
  C := Get_String_Char (Str, J);
  Set_Character_Literal_Name (C);
 
-- 
2.40.0

[COMMITTED] ada: Call idiomatic routine in Expand_Simple_Function_Return

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

In the primary stack case, Insert_Actions is invoked when the expression is
being rewritten, whereas Insert_List_Before_And_Analyze is invoked in the
secondary stack case.  The former is idiomatic, the latter is not.

gcc/ada/

* exp_ch6.adb (Expand_Simple_Function_Return): Call Insert_Actions
consistently when rewriting the expression.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch6.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/exp_ch6.adb b/gcc/ada/exp_ch6.adb
index 87560462315..b19db8fb74d 100644
--- a/gcc/ada/exp_ch6.adb
+++ b/gcc/ada/exp_ch6.adb
@@ -6895,7 +6895,7 @@ package body Exp_Ch6 is
 
Temp := Make_Temporary (Loc, 'R', Alloc_Node);
 
-   Insert_List_Before_And_Analyze (N, New_List (
+   Insert_Actions (Exp, New_List (
  Make_Full_Type_Declaration (Loc,
Defining_Identifier => Acc_Typ,
Type_Definition =>
-- 
2.40.0

[COMMITTED] ada: Fix spurious error on imported generic function with precondition

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

It occurs during the instantiation because the compiler forgets the context
of the generic declaration.

gcc/ada/

* freeze.adb (Wrap_Imported_Subprogram): Use Copy_Subprogram_Spec in
both cases to copy the spec of the subprogram.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/freeze.adb | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/gcc/ada/freeze.adb b/gcc/ada/freeze.adb
index 5d3413c1505..8ebf10bd576 100644
--- a/gcc/ada/freeze.adb
+++ b/gcc/ada/freeze.adb
@@ -6063,12 +6063,6 @@ package body Freeze is
  then
 --  Here we do the wrap
 
---  Note on calls to Copy_Separate_Tree. The trees we are copying
---  here are fully analyzed, but we definitely want fully syntactic
---  unanalyzed trees in the body we construct, so that the analysis
---  generates the right visibility, and that is exactly what the
---  calls to Copy_Separate_Tree give us.
-
 Prag := Copy_Import_Pragma;
 
 --  Fix up spec so it is no longer imported and has convention Ada
@@ -6127,7 +6121,7 @@ package body Freeze is
 Specification  => Copy_Subprogram_Spec (Spec),
 Declarations   => New_List (
   Make_Subprogram_Declaration (Loc,
-Specification => Copy_Separate_Tree (Spec)),
+Specification => Copy_Subprogram_Spec (Spec)),
   Prag),
 Handled_Statement_Sequence =>
   Make_Handled_Sequence_Of_Statements (Loc,
-- 
2.40.0

[COMMITTED] ada: Cleanup detection of type support subprogram entities

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Avoid repeated calls to Get_TSS_Name. Code cleanup related to handling
of dispatching operations in GNATprove; semantics is unaffected.

gcc/ada/

* exp_aggr.adb (Convert_Aggr_In_Allocator): Replace Get_TSS_Name
with a high-level Is_TSS.
* sem_ch6.adb (Check_Conformance): Replace DECLARE block and
nested IF with a call to Get_TSS_Name and a membership test.
(Has_Reliable_Extra_Formals): Refactor repeated calls to
Get_TSS_Name.
* sem_disp.adb (Check_Dispatching_Operation): Replace repeated
calls to Get_TSS_Name with a membership test.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_aggr.adb |  3 +-
 gcc/ada/sem_ch6.adb  | 73 +++-
 gcc/ada/sem_disp.adb |  6 ++--
 3 files changed, 35 insertions(+), 47 deletions(-)

diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb
index c4a016ed3d4..93fcac5439e 100644
--- a/gcc/ada/exp_aggr.adb
+++ b/gcc/ada/exp_aggr.adb
@@ -4487,8 +4487,7 @@ package body Exp_Aggr is
 
 while Present (Stmt) loop
if Nkind (Stmt) = N_Procedure_Call_Statement
- and then Get_TSS_Name (Entity (Name (Stmt)))
-= TSS_Slice_Assign
+ and then Is_TSS (Entity (Name (Stmt)), TSS_Slice_Assign)
then
   Param := First (Parameter_Associations (Stmt));
   Insert_Actions
diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb
index 495e8b1c538..17c50f6e676 100644
--- a/gcc/ada/sem_ch6.adb
+++ b/gcc/ada/sem_ch6.adb
@@ -6005,41 +6005,35 @@ package body Sem_Ch6 is
   --  avoids some redundant error messages.
 
   and then not Error_Posted (New_Formal)
-then
-   --  It is allowed to omit the null-exclusion in case of stream
-   --  attribute subprograms. We recognize stream subprograms
-   --  through their TSS-generated suffix.
 
-   declare
-  TSS_Name : constant TSS_Name_Type := Get_TSS_Name (New_Id);
+  --  It is allowed to omit the null-exclusion in case of stream
+  --  attribute subprograms. We recognize stream subprograms
+  --  through their TSS-generated suffix.
 
-   begin
-  if TSS_Name /= TSS_Stream_Read
-and then TSS_Name /= TSS_Stream_Write
-and then TSS_Name /= TSS_Stream_Input
-and then TSS_Name /= TSS_Stream_Output
-  then
- --  Here we have a definite conformance error. It is worth
- --  special casing the error message for the case of a
- --  controlling formal (which excludes null).
+  and then Get_TSS_Name (New_Id) not in TSS_Stream_Read
+  | TSS_Stream_Write
+  | TSS_Stream_Input
+  | TSS_Stream_Output
+then
+   --  Here we have a definite conformance error. It is worth
+   --  special casing the error message for the case of a
+   --  controlling formal (which excludes null).
 
- if Is_Controlling_Formal (New_Formal) then
-Error_Msg_Node_2 := Scope (New_Formal);
-Conformance_Error
- ("\controlling formal & of & excludes null, "
-  & "declaration must exclude null as well",
-  New_Formal);
+   if Is_Controlling_Formal (New_Formal) then
+  Error_Msg_Node_2 := Scope (New_Formal);
+  Conformance_Error
+("\controlling formal & of & excludes null, "
+ & "declaration must exclude null as well",
+ New_Formal);
 
- --  Normal case (couldn't we give more detail here???)
+  --  Normal case (couldn't we give more detail here???)
 
- else
-Conformance_Error
-  ("\type of & does not match!", New_Formal);
- end if;
+   else
+  Conformance_Error
+("\type of & does not match!", New_Formal);
+   end if;
 
- return;
-  end if;
-   end;
+   return;
 end if;
  end if;
 
@@ -10650,21 +10644,16 @@ package body Sem_Ch6 is
 
   else
  declare
-Typ : constant Entity_Id :=
-Underlying_Type (Find_Dispatching_Type (Alias_E));
+TSS_Name : constant TSS_Name_Type := Get_TSS_Name (E);
+Typ  : constant Entity_Id :=
+  Underlying_Type (Find_Dispatching_Type 

[COMMITTED] ada: Fix bogus error on conditional expression with only user-defined literals

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

This implements the recursive resolution of conditional expressions whose
dependent expressions are (all) user-defined literals the same way it is
implemented for operators.

gcc/ada/

* sem_res.adb (Has_Applicable_User_Defined_Literal): Make it clear
that the predicate also checks the node itself.
(Try_User_Defined_Literal): Move current implementation to...
Deal only with literals, named numbers and conditional expressions
whose dependent expressions are literals or named numbers.
(Try_User_Defined_Literal_For_Operator): ...this.  Remove multiple
return False statements and put a single one at the end.
(Resolve): Call Try_User_Defined_Literal instead of directly
Has_Applicable_User_Defined_Literal for all nodes.  Call
Try_User_Defined_Literal_For_Operator for operator nodes.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 127 ++--
 1 file changed, 98 insertions(+), 29 deletions(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 8a5f87b80ed..899b5b5c522 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -111,10 +111,9 @@ package body Sem_Res is
function Has_Applicable_User_Defined_Literal
  (N   : Node_Id;
   Typ : Entity_Id) return Boolean;
-   --  If N is a literal or a named number, check whether Typ
-   --  has a user-defined literal aspect that can apply to N.
-   --  If present, replace N with a call to the corresponding
-   --  function and return True.
+   --  Check whether N is a literal or a named number, and whether Typ has a
+   --  user-defined literal aspect that may apply to N. In this case, replace
+   --  N with a call to the corresponding function and return True.
 
procedure Check_Discriminant_Use (N : Node_Id);
--  Enforce the restrictions on the use of discriminants when constraining
@@ -306,11 +305,20 @@ package body Sem_Res is
function Try_User_Defined_Literal
  (N   : Node_Id;
   Typ : Entity_Id) return Boolean;
-   --  If an operator node has a literal operand, check whether the type
-   --  of the context, or the type of the other operand has a user-defined
-   --  literal aspect that can be applied to the literal to resolve the node.
-   --  If such aspect exists, replace literal with a call to the
-   --  corresponding function and return True, return false otherwise.
+   --  If the node is a literal or a named number or a conditional expression
+   --  whose dependent expressions are all literals or named numbers, and the
+   --  context type has a user-defined literal aspect, then rewrite the node
+   --  or its leaf nodes as calls to the corresponding function, which plays
+   --  the role of an implicit conversion.
+
+   function Try_User_Defined_Literal_For_Operator
+ (N   : Node_Id;
+  Typ : Entity_Id) return Boolean;
+   --  If an operator node has a literal operand, check whether the type of the
+   --  context, or that of the other operand has a user-defined literal aspect
+   --  that can be applied to the literal to resolve the node. If such aspect
+   --  exists, replace literal with a call to the corresponding function and
+   --  return True, return false otherwise.
 
function Unique_Fixed_Point_Type (N : Node_Id) return Entity_Id;
--  A universal_fixed expression in an universal context is unambiguous if
@@ -600,6 +608,7 @@ package body Sem_Res is
 
  Analyze_And_Resolve (N, Typ);
  return True;
+
   else
  return False;
   end if;
@@ -3061,14 +3070,11 @@ package body Sem_Res is
end;
 end if;
 
---  If node is a literal and context type has a user-defined
---  literal aspect, rewrite node as a call to the corresponding
---  function, which plays the role of an implicit conversion.
+--  Check whether the node is a literal or a named number or a
+--  conditional expression whose dependent expressions are all
+--  literals or named numbers.
 
-if Nkind (N) in N_Numeric_Or_String_Literal | N_Identifier
-  and then Has_Applicable_User_Defined_Literal (N, Typ)
-then
-   Analyze_And_Resolve (N, Typ);
+if Try_User_Defined_Literal (N, Typ) then
return;
 end if;
 
@@ -3179,7 +3185,7 @@ package body Sem_Res is
--  its operands may be a user-defined literal.
 
elsif Nkind (N) in N_Op and then No (Entity (N)) then
-  if Try_User_Defined_Literal (N, Typ) then
+  if Try_User_Defined_Literal_For_Operator (N, Typ) then
  return;
   else
  Unresolved_Operator (N);
@@ -13322,6 +13328,78 @@ package body Sem_Res is
  (N   : Node_Id;
   Typ : Entity_Id) return Boolean
is
+   begin
+  if 

[COMMITTED] ada: Fix wrong finalization for case expression in expression function

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

This happens when the case expression contains a single alternative.

gcc/ada/

* exp_ch5.adb (Expand_N_Case_Statement): Do not remove the statement
if it is the node to be wrapped by a transient scope.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch5.adb | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/exp_ch5.adb b/gcc/ada/exp_ch5.adb
index 30af98b3fc0..2be6e7e021e 100644
--- a/gcc/ada/exp_ch5.adb
+++ b/gcc/ada/exp_ch5.adb
@@ -4127,11 +4127,15 @@ package body Exp_Ch5 is
 
  --  If there is only a single alternative, just replace it with the
  --  sequence of statements since obviously that is what is going to
- --  be executed in all cases.
+ --  be executed in all cases, except if it is the node to be wrapped
+ --  by a transient scope, because this would cause the sequence of
+ --  statements to be leaked out of the transient scope.
 
  Len := List_Length (Alternatives (N));
 
- if Len = 1 then
+ if Len = 1
+   and then not (Scope_Is_Transient and then Node_To_Be_Wrapped = N)
+ then
 
 --  We still need to evaluate the expression if it has any side
 --  effects.
-- 
2.40.0

[COMMITTED] ada: Fix memory leak in expression function returning Big_Integer

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

We fail to establish a transient scope around the return statement because
the function returns a controlled type, but this is no longer problematic
because controlled types are no longer returned on the secondary stack.

gcc/ada/

* exp_ch7.adb (Establish_Transient_Scope.Find_Transient_Context):
Bail out for a simple return statement only if the transient scope
and the function both require secondary stack management, or else
if the function is a thunk.
* sem_res.adb (Resolve_Call): Do not create a transient scope when
the call is the expression of a simple return statement.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch7.adb | 32 
 gcc/ada/sem_res.adb | 12 
 2 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/gcc/ada/exp_ch7.adb b/gcc/ada/exp_ch7.adb
index 1586e8fbfca..520bb099d33 100644
--- a/gcc/ada/exp_ch7.adb
+++ b/gcc/ada/exp_ch7.adb
@@ -4717,21 +4717,29 @@ package body Exp_Ch7 is
   return Curr;
 
when N_Simple_Return_Statement =>
+  declare
+ Fun_Id : constant Entity_Id :=
+   Return_Applies_To (Return_Statement_Entity (Curr));
 
-  --  A return statement is not a valid transient context when
-  --  the function itself requires transient scope management
-  --  because the result will be reclaimed too early.
-
-  if Requires_Transient_Scope (Etype
-   (Return_Applies_To (Return_Statement_Entity (Curr
-  then
- return Empty;
+  begin
+ --  A transient context that must manage the secondary
+ --  stack cannot be a return statement of a function that
+ --  itself requires secondary stack management, because
+ --  the function's result would be reclaimed too early.
+ --  And returns of thunks never require transient scopes.
+
+ if (Manage_Sec_Stack
+  and then Needs_Secondary_Stack (Etype (Fun_Id)))
+   or else Is_Thunk (Fun_Id)
+ then
+return Empty;
 
-  --  General case for return statements
+ --  General case for return statements
 
-  else
- return Curr;
-  end if;
+ else
+return Curr;
+ end if;
+  end;
 
--  Special
 
diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 899b5b5c522..b16e48917f2 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -6960,6 +6960,12 @@ package body Sem_Res is
   --  want to create a transient scope (this could occur in the case of a
   --  static string-returning call).
 
+  --  h) If the subprogram is an ignored ghost entity, because it does not
+  --  return anything.
+
+  --  i) If the call is the expression of a simple return statement, since
+  --  it will be handled as a tail call by Expand_Simple_Function_Return.
+
   if Is_Inlined (Nam)
 and then Has_Pragma_Inline (Nam)
 and then Nkind (Unit_Declaration_Node (Nam)) = N_Subprogram_Declaration
@@ -6972,16 +6978,14 @@ package body Sem_Res is
 or else Is_Intrinsic_Subprogram (Nam)
 or else Is_Inlinable_Expression_Function (Nam)
 or else Is_Static_Function_Call (N)
+or else Is_Ignored_Ghost_Entity (Nam)
+or else Nkind (Parent (N)) = N_Simple_Return_Statement
   then
  null;
 
-  --  A return statement from an ignored Ghost function does not use the
-  --  secondary stack (or any other one).
-
   elsif Expander_Active
 and then Ekind (Nam) in E_Function | E_Subprogram_Type
 and then Requires_Transient_Scope (Etype (Nam))
-and then not Is_Ignored_Ghost_Entity (Nam)
   then
  Establish_Transient_Scope (N, Needs_Secondary_Stack (Etype (Nam)));
 
-- 
2.40.0

[COMMITTED] ada: Fix small fallout of previous change

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

It may lead to an infinite recursion if no interpretation exists.

gcc/ada/

* sem_res.adb (Try_User_Defined_Literal): Restrict previous change
to non-leaf nodes.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 17b74ea65d5..1d4b9acb8ea 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -1,15 +1,17 @@ package body Sem_Res is
  --  Both operands must have the same type as the context
  --  (ignoring for now fixed-point and exponentiation ops).
 
- if Covers (Typ, Etype (Right_Opnd (N)))
-   or else Has_Applicable_User_Defined_Literal (Right_Opnd (N), Typ)
+ if Has_Applicable_User_Defined_Literal (Right_Opnd (N), Typ)
+   or else (Nkind (Left_Opnd (N)) in N_Op
+ and then Covers (Typ, Etype (Right_Opnd (N
  then
 Resolve (Left_Opnd (N), Typ);
 Analyze_And_Resolve (N, Typ);
 return True;
 
- elsif Covers (Typ, Etype (Left_Opnd (N)))
-   or else Has_Applicable_User_Defined_Literal (Left_Opnd (N), Typ)
+ elsif Has_Applicable_User_Defined_Literal (Left_Opnd (N), Typ)
+   or else (Nkind (Right_Opnd (N)) in N_Op
+ and then Covers (Typ, Etype (Left_Opnd (N
  then
 Resolve (Right_Opnd (N), Typ);
 Analyze_And_Resolve (N, Typ);
-- 
2.40.0

[COMMITTED] ada: Fix remaining failures in Roman Numbers test

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

The test is inspired from the example of user-defined literals given in the
Ada 2022 RM.  Mixed Arabic numbers/Roman numbers computations are rejected
because the second resolution pass would try to resolve Arabic numbers only
as user-defined literals.

gcc/ada/

* sem_res.adb (Try_User_Defined_Literal): For arithmetic operators,
also accept operands whose type is covered by the resolution type.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 066072a6afe..17b74ea65d5 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -1,12 +1,16 @@ package body Sem_Res is
  --  Both operands must have the same type as the context
  --  (ignoring for now fixed-point and exponentiation ops).
 
- if Has_Applicable_User_Defined_Literal (Right_Opnd (N), Typ) then
+ if Covers (Typ, Etype (Right_Opnd (N)))
+   or else Has_Applicable_User_Defined_Literal (Right_Opnd (N), Typ)
+ then
 Resolve (Left_Opnd (N), Typ);
 Analyze_And_Resolve (N, Typ);
 return True;
 
- elsif Has_Applicable_User_Defined_Literal (Left_Opnd (N), Typ) then
+ elsif Covers (Typ, Etype (Left_Opnd (N)))
+   or else Has_Applicable_User_Defined_Literal (Left_Opnd (N), Typ)
+ then
 Resolve (Right_Opnd (N), Typ);
 Analyze_And_Resolve (N, Typ);
 return True;
-- 
2.40.0

[COMMITTED] ada: Attach pre/post on access-to-subprogram to internal subprogram type

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Aspects Pre/Post that annotate access-to-subprogram type were attached
to the source entity (whose kind is either E_Access_Subprogram_Type or
E_Access_Protected_Subprogram_Type). However, it is more convenient to
attach them to the internal entity (whose kind is E_Subprogram_Type), so
that both Pre/Post aspects and First_Formal/Next_Formal chain are
attached to the same entity, just like for ordinary subprograms.

The drawback of having the Post aspect attached to an internal entity is
that name in prefixes of attribute Result no longer match the name of
entity where this Post aspect is attached. However, currently there is
no code that relies on this matching and, in general, there are fewer
routines that deal with attribute Result so they are easier to adapt
than the code that queries the Pre/Post aspects.

gcc/ada/

* contracts.adb
(Add_Pre_Post_Condition): Attach pre/post aspects to E_Subprogram_Type
entity.
(Analyze_Entry_Or_Subprogram_Contract): Adapt to use full type
declaration for a contract attached to E_Subprogram_Type entity.
* sem_prag.adb
(Analyze_Pre_Post_Condition): Add pre/post aspects to the designed type.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/contracts.adb | 12 
 gcc/ada/sem_prag.adb  |  6 +-
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
index 15b65ee4c06..7625abf9554 100644
--- a/gcc/ada/contracts.adb
+++ b/gcc/ada/contracts.adb
@@ -334,7 +334,7 @@ package body Contracts is
 if Is_OK_Classification then
Add_Classification;
 
-elsif Ekind (Id) in Access_Subprogram_Kind
+elsif Ekind (Id) = E_Subprogram_Type
 and then Prag_Nam in Name_Precondition
| Name_Postcondition
 then
@@ -665,7 +665,10 @@ package body Contracts is
   Freeze_Id : Entity_Id := Empty)
is
   Items : constant Node_Id := Contract (Subp_Id);
-  Subp_Decl : constant Node_Id := Unit_Declaration_Node (Subp_Id);
+  Subp_Decl : constant Node_Id :=
+(if Ekind (Subp_Id) = E_Subprogram_Type
+ then Associated_Node_For_Itype (Subp_Id)
+ else Unit_Declaration_Node (Subp_Id));
 
   Saved_SM  : constant SPARK_Mode_Type := SPARK_Mode;
   Saved_SMP : constant Node_Id := SPARK_Mode_Pragma;
@@ -1593,8 +1596,9 @@ package body Contracts is
 
   --  Analyze Pre/Post on access-to-subprogram type
 
-  if Is_Access_Subprogram_Type (Type_Id) then
- Analyze_Entry_Or_Subprogram_Contract (Type_Id);
+  if Ekind (Type_Id) in Access_Subprogram_Kind then
+ Analyze_Entry_Or_Subprogram_Contract
+   (Directly_Designated_Type (Type_Id));
   end if;
end Analyze_Type_Contract;
 
diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index 0d62b04cc37..0de410a2392 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -5265,7 +5265,11 @@ package body Sem_Prag is
  --  Chain the pragma on the contract for further processing by
  --  Analyze_Pre_Post_Condition_In_Decl_Part.
 
- Add_Contract_Item (N, Subp_Id);
+ if Ekind (Subp_Id) in Access_Subprogram_Kind then
+Add_Contract_Item (N, Directly_Designated_Type (Subp_Id));
+ else
+Add_Contract_Item (N, Subp_Id);
+ end if;
 
  --  Fully analyze the pragma when it appears inside an entry or
  --  subprogram body because it cannot benefit from forward references.
-- 
2.40.0

[COMMITTED] ada: Fix wrong finalization for loop on indexed container

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

The problem is that a transient temporary created for the constant indexing
of the container is finalized almost immediately after its creation.

gcc/ada/

* exp_util.adb (Is_Finalizable_Transient.Is_Indexed_Container):
New predicate to detect a temporary created to hold the result of
a constant indexing on a container.
(Is_Finalizable_Transient.Is_Iterated_Container): Adjust a couple
of obsolete comments.
(Is_Finalizable_Transient): Return False if Is_Indexed_Container
returns True on the object.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_util.adb | 102 +--
 1 file changed, 99 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_util.adb
index f010dac4978..2582524b1dd 100644
--- a/gcc/ada/exp_util.adb
+++ b/gcc/ada/exp_util.adb
@@ -8323,6 +8323,13 @@ package body Exp_Util is
   function Is_Allocated (Trans_Id : Entity_Id) return Boolean;
   --  Determine whether transient object Trans_Id is allocated on the heap
 
+  function Is_Indexed_Container
+(Trans_Id   : Entity_Id;
+ First_Stmt : Node_Id) return Boolean;
+  --  Determine whether transient object Trans_Id denotes a container which
+  --  is in the process of being indexed in the statement list starting
+  --  from First_Stmt.
+
   function Is_Iterated_Container
 (Trans_Id   : Entity_Id;
  First_Stmt : Node_Id) return Boolean;
@@ -8597,6 +8604,91 @@ package body Exp_Util is
  and then Nkind (Expr) = N_Allocator;
   end Is_Allocated;
 
+  --
+  -- Is_Indexed_Container --
+  --
+
+  function Is_Indexed_Container
+(Trans_Id   : Entity_Id;
+ First_Stmt : Node_Id) return Boolean
+  is
+ Aspect : Node_Id;
+ Call   : Node_Id;
+ Index  : Entity_Id;
+ Param  : Node_Id;
+ Stmt   : Node_Id;
+ Typ: Entity_Id;
+
+  begin
+ --  It is not possible to iterate over containers in non-Ada 2012 code
+
+ if Ada_Version < Ada_2012 then
+return False;
+ end if;
+
+ Typ := Etype (Trans_Id);
+
+ --  Handle access type created for the reference below
+
+ if Is_Access_Type (Typ) then
+Typ := Designated_Type (Typ);
+ end if;
+
+ --  Look for aspect Constant_Indexing. It may be part of a type
+ --  declaration for a container, or inherited from a base type
+ --  or parent type.
+
+ Aspect := Find_Value_Of_Aspect (Typ, Aspect_Constant_Indexing);
+
+ if Present (Aspect) then
+Index := Entity (Aspect);
+
+--  Examine the statements following the container object and
+--  look for a call to the default indexing routine where the
+--  first parameter is the transient. Such a call appears as:
+
+-- It : Access_To_Constant_Reference_Type :=
+--Constant_Indexing (Tran_Id.all, ...)'reference;
+
+Stmt := First_Stmt;
+while Present (Stmt) loop
+
+   --  Detect an object declaration which is initialized by a
+   --  controlled function call.
+
+   if Nkind (Stmt) = N_Object_Declaration
+ and then Present (Expression (Stmt))
+ and then Nkind (Expression (Stmt)) = N_Reference
+ and then Nkind (Prefix (Expression (Stmt))) = N_Function_Call
+   then
+  Call := Prefix (Expression (Stmt));
+
+  --  The call must invoke the default indexing routine of
+  --  the container and the transient object must appear as
+  --  the first actual parameter. Skip any calls whose names
+  --  are not entities.
+
+  if Is_Entity_Name (Name (Call))
+and then Entity (Name (Call)) = Index
+and then Present (Parameter_Associations (Call))
+  then
+ Param := First (Parameter_Associations (Call));
+
+ if Nkind (Param) = N_Explicit_Dereference
+   and then Entity (Prefix (Param)) = Trans_Id
+ then
+return True;
+ end if;
+  end if;
+   end if;
+
+   Next (Stmt);
+end loop;
+ end if;
+
+ return False;
+  end Is_Indexed_Container;
+
   ---
   -- Is_Iterated_Container --
   ---
@@ -8621,7 +8713,7 @@ package body Exp_Util is
 
  Typ := Etype (Trans_Id);
 
- --  Handle access type created for secondary stack use
+ --  Handle access type created for the reference below
 
  if Is_Access_Type 

[COMMITTED] ada: Fix internal error with pragma Compile_Time_{Warning, Error}

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

This happens when the pragmas are deferred to the back-end from an external
unit to the main unit that is generic, because the back-end does not compile
a main unit that is generic.

gcc/ada/

* sem_prag.adb (Process_Compile_Time_Warning_Or_Error): Do not defer
anything to the back-end when the main unit is generic.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_prag.adb | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index b74c60cd183..0d62b04cc37 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -8137,7 +8137,9 @@ package body Sem_Prag is
  --  then. For example, if the expression is "Record_Type'Size /= 32"
  --  it might be known after the back end has determined the size of
  --  Record_Type. We do not defer validation if we're inside a generic
- --  unit, because we will have more information in the instances.
+ --  unit, because we will have more information in the instances, and
+ --  this ultimately applies to the main unit itself, because it is not
+ --  compiled by the back end when it is generic.
 
  if Compile_Time_Known_Value (Arg1x) then
 Validate_Compile_Time_Warning_Or_Error (N, Sloc (Arg1));
@@ -8155,7 +8157,10 @@ package body Sem_Prag is
end if;
 end loop;
 
-if No (P) then
+if No (P)
+  and then
+Nkind (Unit (Cunit (Main_Unit))) not in N_Generic_Declaration
+then
Defer_Compile_Time_Warning_Error_To_BE (N);
 end if;
  end if;
-- 
2.40.0

[COMMITTED] ada: Allow attributes like First and Last to be read in Exceptional_Cases

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Attributes that do not read data from the object can be safely used in
consequences of Exceptional_Cases regardless of the parameter passing
mode.

gcc/ada/

* sem_res.adb (Resolve_Entity_Name): Relax rules for Exceptional_Cases.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index a31077a5f33..6d4bef8d38e 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -8117,11 +8117,19 @@ package body Sem_Res is
 --  Parameters of modes OUT or IN OUT of the subprogram shall not
 --  occur in the consequences of an exceptional contract unless
 --  they are either passed by reference or occur in the prefix
---  of a reference to the 'Old attribute.
+--  of a reference to the 'Old attribute. For convenience, we also
+--  allow them as prefixes of attributes that do not actually read
+--  data from the object.
 
 if Ekind (E) in E_Out_Parameter | E_In_Out_Parameter
   and then Within_Exceptional_Cases_Consequence (N)
   and then not In_Attribute_Old (N)
+  and then not (Nkind (Parent (N)) = N_Attribute_Reference
+  and then
+Attribute_Name (Parent (N)) in Name_Constrained
+ | Name_First
+ | Name_Last
+ | Name_Length)
   and then not Is_By_Reference_Type (Etype (E))
   and then not Is_Aliased (E)
 then
-- 
2.40.0

[COMMITTED] ada: Fix crash on semi-recursive call in access-to-subprogram contract

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Calls to access-to-subprogram from its own pre/post aspects are rejected
as illegal, e.g.:

   type F is access function (X : Natural) return Boolean with
 Pre => F.all (X);

but they caused an assertion failure in detection of recursive calls.

Now they are properly recognized as recursive, but the error is
suppressed, because it has been already posted at the call node.

gcc/ada/

* sem_res.adb (Invoked_With_Different_Arguments): Use Get_Called_Entity,
which properly deals with calls via an access-to-subprogram; fix
inconsistent use of a Call object declared in enclosing subprogram.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 1d4b9acb8ea..8a5f87b80ed 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -947,7 +947,7 @@ package body Sem_Res is
   --
 
   function Invoked_With_Different_Arguments (N : Node_Id) return Boolean is
- Subp : constant Entity_Id := Entity (Name (N));
+ Subp : constant Entity_Id := Get_Called_Entity (N);
 
  Actual : Node_Id;
  Formal : Entity_Id;
@@ -956,7 +956,7 @@ package body Sem_Res is
  --  Determine whether the formals of the invoked subprogram are not
  --  used as actuals in the call.
 
- Actual := First_Actual (Call);
+ Actual := First_Actual (N);
  Formal := First_Formal (Subp);
  while Present (Actual) and then Present (Formal) loop
 
-- 
2.40.0

[COMMITTED] ada: Fix small fallout of previous change

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

The same guard must be added to Expand_Simple_Function_Return as the one
that was added to Analyze_Function_Return.

gcc/ada/

* exp_ch6.adb (Expand_Simple_Function_Return): Deal with a rewriting
of the simple return during the adjustment of its expression.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch6.adb | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/gcc/ada/exp_ch6.adb b/gcc/ada/exp_ch6.adb
index bd4f4a1412d..87560462315 100644
--- a/gcc/ada/exp_ch6.adb
+++ b/gcc/ada/exp_ch6.adb
@@ -6641,6 +6641,13 @@ package body Exp_Ch6 is
   if Is_Boolean_Type (Exp_Typ) and then Nonzero_Is_True (Exp_Typ) then
  Adjust_Condition (Exp);
  Adjust_Result_Type (Exp, Exp_Typ);
+
+ --  The adjustment of the expression may have rewritten the return
+ --  statement itself, e.g. when it is turned into an if expression.
+
+ if Nkind (N) /= N_Simple_Return_Statement then
+return;
+ end if;
   end if;
 
   --  Do validity check if enabled for returns
-- 
2.40.0

[COMMITTED] ada: Fix memory leak in multi-dimensional array aggregate of Vector

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

It comes from a superfluous adjustment for subarray components.

gcc/ada/

* exp_aggr.adb (Initialize_Array_Component): Fix condition detecting
the nested case that requires an adjustment.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_aggr.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb
index 75e5e1402df..c4a016ed3d4 100644
--- a/gcc/ada/exp_aggr.adb
+++ b/gcc/ada/exp_aggr.adb
@@ -1459,7 +1459,7 @@ package body Exp_Aggr is
   and then not Is_Build_In_Place_Function_Call (Init_Expr)
   and then not
 (Is_Array_Type (Comp_Typ)
-  and then Is_Controlled (Component_Type (Comp_Typ))
+  and then Needs_Finalization (Component_Type (Comp_Typ))
   and then Nkind (Expr) = N_Aggregate)
 then
Adj_Call :=
-- 
2.40.0

[COMMITTED] ada: Default_Component_Value trumps Initialize/Normalize_Scalars

[Marc Poulhiès via Gcc-patches]

From: Steve Baird 

If the Default_Component_Value aspect is specified for an array type, then
specifying Initialize_Scalars or Normalize_Scalars should have no effect
on the default initialization of an object of the array type.

gcc/ada/

* exp_ch3.adb
(Expand_N_Object_Declaration.Default_Initialize_Object): Add test for
specified Default_Component_Value aspect when deciding whether
either Initialize_Scalars or Normalize_Scalars impacts default
initialization of an array object.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch3.adb | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/ada/exp_ch3.adb b/gcc/ada/exp_ch3.adb
index e23a3fde15c..5f651bacafb 100644
--- a/gcc/ada/exp_ch3.adb
+++ b/gcc/ada/exp_ch3.adb
@@ -6897,6 +6897,12 @@ package body Exp_Ch3 is
 
  and then not Has_Predicates (Component_Type (Typ))
 
+ --  Array default component value takes precedence over
+ --  Init_Or_Norm_Scalars.
+
+ and then No (Find_Aspect (Typ,
+   Aspect_Default_Component_Value))
+
  --  The component type must have a single initialization value
 
  and then Simple_Initialization_OK (Component_Type (Typ))
-- 
2.40.0

[COMMITTED] ada: Fix wrong result for membership test of null in null-excluding access type

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

The result must be False as per the RM 4.5.2 (30.2/4) clause.

gcc/ada/

* exp_ch4.adb (Expand_N_In): Deal specifically with a null operand.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch4.adb | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/exp_ch4.adb b/gcc/ada/exp_ch4.adb
index 3f864f2675c..537d7a6311c 100644
--- a/gcc/ada/exp_ch4.adb
+++ b/gcc/ada/exp_ch4.adb
@@ -6972,11 +6972,13 @@ package body Exp_Ch4 is
 
--  If the null exclusion checks are not compatible, need to
--  perform further checks. In other words, we cannot have
-   --  Ltyp including null and Typ excluding null. All other cases
-   --  are OK.
+   --  Ltyp including null or Lop being null, and Typ excluding
+   --  null. All other cases are OK.
 
Check_Null_Exclusion :=
- Can_Never_Be_Null (Typ) and then not Can_Never_Be_Null (Ltyp);
+ Can_Never_Be_Null (Typ)
+   and then (not Can_Never_Be_Null (Ltyp)
+  or else Nkind (Lop) = N_Null);
Typ := Designated_Type (Typ);
 end if;
 
-- 
2.40.0

[COMMITTED] ada: Remove redundant protection against empty lists

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Calls to First on No_List intentionally return Empty, so explicit guards
against No_List are unnecessary. Code cleanup; semantics is unaffected.

gcc/ada/

* sem_util.adb (Check_Function_Writable_Actuals): Remove guard against
a membership test with no alternatives; simplify with a membership test.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index a42b2dff60f..34ea06432cf 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -2882,9 +2882,7 @@ package body Sem_Util is
   Collect_Identifiers (Right_Opnd (N));
end if;
 
-   if Nkind (N) in N_In | N_Not_In
- and then Present (Alternatives (N))
-   then
+   if Nkind (N) in N_Membership_Test then
   Expr := First (Alternatives (N));
   while Present (Expr) loop
  Collect_Identifiers (Expr);
-- 
2.40.0

[COMMITTED] ada: Fix wrong finalization for call to BIP function in conditional expression

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

This happens when the call is a dependent expression of the conditional
expression, and the conditional expression is either the expression of a
simple return statement or the return expression of an expression function.

The reason is that the special processing of "tail calls" for BIP functions,
i.e. calls that are the expression of simple return statements or the return
expression of expression functions, is not applied.

This change makes sure that it is applied by distributing the simple return
statements enclosing conditional expressions into the dependent expressions
of the conditional expressions in almost all cases.  As a side effect, this
elides a temporary in the nonlimited by-reference case, as well as a pair of
calls to Adjust/Finalize in the nonlimited controlled case.

gcc/ada/

* exp_ch4.adb (Expand_N_Case_Expression): Distribute simple return
statements enclosing the conditional expression into the dependent
expressions in almost all cases.
(Expand_N_If_Expression): Likewise.
(Process_Transient_In_Expression): Adjust to the above distribution.
* exp_ch6.adb (Expand_Ctrl_Function_Call): Deal with calls in the
dependent expressions of a conditional expression.
* sem_ch6.adb (Analyze_Function_Return): Deal with the rewriting of
a simple return statement during the resolution of its expression.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch4.adb | 171 +++-
 gcc/ada/exp_ch6.adb |  10 ++-
 gcc/ada/sem_ch6.adb |  12 +++-
 3 files changed, 138 insertions(+), 55 deletions(-)

diff --git a/gcc/ada/exp_ch4.adb b/gcc/ada/exp_ch4.adb
index 7be240bce0e..3f864f2675c 100644
--- a/gcc/ada/exp_ch4.adb
+++ b/gcc/ada/exp_ch4.adb
@@ -5401,17 +5401,6 @@ package body Exp_Ch4 is
   --  when minimizing expressions with actions (e.g. when generating C
   --  code) since it allows us to do the optimization below in more cases.
 
-  --  Small optimization: when the case expression appears in the context
-  --  of a simple return statement, expand into
-
-  --case X is
-  --   when A =>
-  --  return AX;
-  --   when B =>
-  --  return BX;
-  --   ...
-  --end case;
-
   Case_Stmt :=
 Make_Case_Statement (Loc,
   Expression   => Expression (N),
@@ -5425,17 +5414,29 @@ package body Exp_Ch4 is
   Set_From_Conditional_Expression (Case_Stmt);
   Acts := New_List;
 
+  --  Small optimization: when the case expression appears in the context
+  --  of a simple return statement, expand into
+
+  --case X is
+  --   when A =>
+  --  return AX;
+  --   when B =>
+  --  return BX;
+  --   ...
+  --end case;
+
+  --  This makes the expansion much easier when expressions are calls to
+  --  a BIP function. But do not perform it when the return statement is
+  --  within a predicate function, as this causes spurious errors.
+
+  Optimize_Return_Stmt :=
+Nkind (Par) = N_Simple_Return_Statement and then not In_Predicate;
+
   --  Scalar/Copy case
 
   if Is_Copy_Type (Typ) then
  Target_Typ := Typ;
 
- --  Do not perform the optimization when the return statement is
- --  within a predicate function, as this causes spurious errors.
-
- Optimize_Return_Stmt :=
-   Nkind (Par) = N_Simple_Return_Statement and then not In_Predicate;
-
   --  Otherwise create an access type to handle the general case using
   --  'Unrestricted_Access.
 
@@ -5498,16 +5499,6 @@ package body Exp_Ch4 is
 --  scalar types. This approach avoids big copies and covers the
 --  limited and unconstrained cases.
 
---  Generate:
---AX'Unrestricted_Access
-
-if not Is_Copy_Type (Typ) then
-   Alt_Expr :=
- Make_Attribute_Reference (Alt_Loc,
-   Prefix => Relocate_Node (Alt_Expr),
-   Attribute_Name => Name_Unrestricted_Access);
-end if;
-
 --  Generate:
 --return AX['Unrestricted_Access];
 
@@ -5520,6 +5511,13 @@ package body Exp_Ch4 is
 --Target := AX['Unrestricted_Access];
 
 else
+   if not Is_Copy_Type (Typ) then
+  Alt_Expr :=
+Make_Attribute_Reference (Alt_Loc,
+  Prefix => Relocate_Node (Alt_Expr),
+  Attribute_Name => Name_Unrestricted_Access);
+   end if;
+
LHS := New_Occurrence_Of (Target, Loc);
Set_Assignment_OK (LHS);
 
@@ -5789,6 +5787,7 @@ package body Exp_Ch4 is
   Loc   : constant Source_Ptr := Sloc (N);
   Thenx : constant Node_Id:= Next (Cond);
   Elsex : constant Node_Id:= Next 

[COMMITTED] ada: Restore parent link for both lists and nodes in class-wide condition

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

When preanalysing class-wide conditions, we restore "Function (Object)"
to its original "Object.Function" notation. This requires the Parent
links to be fixed. We did it for nodes; now we do it for lists as well.

This patch is enough to fix assertion failure in CCG and to make the
tree well-connected. Perhaps there is a more elegant solution, but that
remains to be investigated.

gcc/ada/

* contracts.adb (Fix_Parent): Fir part both for lists and nodes.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/contracts.adb | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
index 65f341abc8f..15b65ee4c06 100644
--- a/gcc/ada/contracts.adb
+++ b/gcc/ada/contracts.adb
@@ -4936,9 +4936,11 @@ package body Contracts is
 
 begin
if Par /= Parent_Node then
-  pragma Assert (not Is_List_Member (Node)
-   or else Nkind (Par) = N_Function_Call);
-  Set_Parent (Node, Parent_Node);
+  if Is_List_Member (Node) then
+ Set_List_Parent (List_Containing (Node), Parent_Node);
+  else
+ Set_Parent (Node, Parent_Node);
+  end if;
end if;
 
return OK;
-- 
2.40.0

[COMMITTED] ada: Accept parameters of enclosing subprograms in exceptional cases

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Rules about parameters of modes OUT and IN OUT in aspect
Exceptional_Cases only apply to the parameters of the current
subprogram.

gcc/ada/

* sem_res.adb (Resolve_Entity_Name): Refine rules for Exceptional_Cases.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_res.adb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 6d4bef8d38e..066072a6afe 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -8122,6 +8122,7 @@ package body Sem_Res is
 --  data from the object.
 
 if Ekind (E) in E_Out_Parameter | E_In_Out_Parameter
+  and then Scope (E) = Current_Scope
   and then Within_Exceptional_Cases_Consequence (N)
   and then not In_Attribute_Old (N)
   and then not (Nkind (Parent (N)) = N_Attribute_Reference
-- 
2.40.0

[COMMITTED] ada: Repair support for user-defined literals in arithmetic operators

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

It was partially broken to fix a regression in error reporting, because the
fix was applied to the first pass of resolution instead of the second pass,
as needs to be done for user-defined literals.

gcc/ada/

* sem_ch4.ads (Unresolved_Operator): New procedure.
* sem_ch4.adb (Has_Possible_Literal_Aspects): Rename into...
(Has_Possible_User_Defined_Literal): ...this.  Tidy up.
(Operator_Check): Accept again unresolved operators if they have a
possible user-defined literal as operand.  Factor out the handling
of the general error message into...
(Unresolved_Operator): ...this new procedure.
* sem_res.adb (Resolve): Be prepared for unresolved operators on
entry in Ada 2022 or later.  If they are still unresolved on exit,
call Unresolved_Operator to give the error message.
(Try_User_Defined_Literal): Tidy up.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch4.adb | 254 +---
 gcc/ada/sem_ch4.ads |   3 +
 gcc/ada/sem_res.adb |  54 ++
 3 files changed, 156 insertions(+), 155 deletions(-)

diff --git a/gcc/ada/sem_ch4.adb b/gcc/ada/sem_ch4.adb
index c8bb99b6716..c76f2874957 100644
--- a/gcc/ada/sem_ch4.adb
+++ b/gcc/ada/sem_ch4.adb
@@ -256,8 +256,8 @@ package body Sem_Ch4 is
--  type is not directly visible. The routine uses this type to emit a more
--  informative message.
 
-   function Has_Possible_Literal_Aspects (N : Node_Id) return Boolean;
-   --  Ada_2022: if an operand is a literal it may be subject to an
+   function Has_Possible_User_Defined_Literal (N : Node_Id) return Boolean;
+   --  Ada 2022: if an operand is a literal, it may be subject to an
--  implicit conversion to a type for which a user-defined literal
--  function exists. During the first pass of type resolution we do
--  not know the context imposed on the literal, so we assume that
@@ -7572,19 +7572,11 @@ package body Sem_Ch4 is
 
   if Etype (N) = Any_Type then
  declare
-L : Node_Id;
-R : Node_Id;
-Op_Id : Entity_Id := Empty;
+L : constant Node_Id :=
+  (if Nkind (N) in N_Binary_Op then Left_Opnd (N) else Empty);
+R : constant Node_Id := Right_Opnd (N);
 
  begin
-R := Right_Opnd (N);
-
-if Nkind (N) in N_Binary_Op then
-   L := Left_Opnd (N);
-else
-   L := Empty;
-end if;
-
 --  If either operand has no type, then don't complain further,
 --  since this simply means that we have a propagated error.
 
@@ -7665,9 +7657,10 @@ package body Sem_Ch4 is
 then
return;
 
-elsif Present (Entity (N))
-  and then Has_Possible_Literal_Aspects (N)
-then
+--  The handling of user-defined literals is deferred to the second
+--  pass of resolution.
+
+elsif Has_Possible_User_Defined_Literal (N) then
return;
 
 --  If we have a logical operator, one of whose operands is
@@ -7882,117 +7875,19 @@ package body Sem_Ch4 is
end if;
 end if;
 
---  If we fall through then just give general message. Note that in
---  the following messages, if the operand is overloaded we choose
---  an arbitrary type to complain about, but that is probably more
---  useful than not giving a type at all.
-
-if Nkind (N) in N_Unary_Op then
-   Error_Msg_Node_2 := Etype (R);
-   Error_Msg_N ("operator& not defined for}", N);
-   return;
-
-else
-   if Nkind (N) in N_Binary_Op then
-  if not Is_Overloaded (L)
-and then not Is_Overloaded (R)
-and then Base_Type (Etype (L)) = Base_Type (Etype (R))
-  then
- Error_Msg_Node_2 := First_Subtype (Etype (R));
- Error_Msg_N ("there is no applicable operator& for}", N);
-
-  else
- --  Another attempt to find a fix: one of the candidate
- --  interpretations may not be use-visible. This has
- --  already been checked for predefined operators, so
- --  we examine only user-defined functions.
-
- Op_Id := Get_Name_Entity_Id (Chars (N));
-
- while Present (Op_Id) loop
-if Ekind (Op_Id) /= E_Operator
-  and then Is_Overloadable (Op_Id)
-then
-   if not Is_Immediately_Visible (Op_Id)
- and then not In_Use (Scope (Op_Id))
- and then not Is_Abstract_Subprogram (Op_Id)
- 

[COMMITTED] ada: Reuse routine for getting from body entity to spec entity

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Cleanup related to handling of access-to-subprogram types with Pre and
Post aspects. Behavior is unaffected.

gcc/ada/

* sem_util.adb (Check_Result_And_Post_State): Replace low-level
navigation with a high-level Unique_Entity.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 22 +-
 1 file changed, 1 insertion(+), 21 deletions(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index d71329bbcb2..64abfb11ce5 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -4546,13 +4546,12 @@ package body Sem_Util is
   --  Local variables
 
   Items: constant Node_Id := Contract (Subp_Id);
-  Subp_Decl: constant Node_Id := Unit_Declaration_Node (Subp_Id);
   Case_Prag: Node_Id := Empty;
   Post_Prag: Node_Id := Empty;
   Prag : Node_Id;
   Seen_In_Case : Boolean := False;
   Seen_In_Post : Boolean := False;
-  Spec_Id  : Entity_Id;
+  Spec_Id  : constant Entity_Id := Unique_Entity (Subp_Id);
 
--  Start of processing for Check_Result_And_Post_State
 
@@ -4570,25 +4569,6 @@ package body Sem_Util is
  return;
   end if;
 
-  --  Retrieve the entity of the subprogram spec (if any)
-
-  if Nkind (Subp_Decl) = N_Subprogram_Body
-and then Present (Corresponding_Spec (Subp_Decl))
-  then
- Spec_Id := Corresponding_Spec (Subp_Decl);
-
-  elsif Nkind (Subp_Decl) = N_Subprogram_Body_Stub
-and then Present (Corresponding_Spec_Of_Stub (Subp_Decl))
-  then
- Spec_Id := Corresponding_Spec_Of_Stub (Subp_Decl);
-
-  elsif Nkind (Subp_Decl) = N_Entry_Body then
- Spec_Id := Corresponding_Spec (Subp_Decl);
-
-  else
- Spec_Id := Subp_Id;
-  end if;
-
   --  Examine all postconditions for attribute 'Result and a post-state
 
   Prag := Pre_Post_Conditions (Items);
-- 
2.40.0

[COMMITTED] ada: Fix crash on vector initialization

[Marc Poulhiès via Gcc-patches]

Initializing a vector using

 Vec : V.Vector := [Some_Type'(Some_Abstract_Type with F => 0)];

may crash the compiler. The expander marks the N_Extension_Aggregate for
delayed expansion which never happens and incorrectly ends up in gigi.

The delayed expansion is needed for nested aggregates, which the
original code is testing for, but container aggregates are handled
differently.

Such assignments to container aggregates are later transformed into
procedure calls to the procedures named in the Aggregate aspect
definition, for which the delayed expansion is not required/expected.

gcc/ada/

* exp_aggr.adb (Convert_To_Assignments): Do not mark node for
delayed expansion if parent type has the Aggregate aspect.
* sem_util.adb (Is_Container_Aggregate): Move...
* sem_util.ads (Is_Container_Aggregate): ... here and make it
public.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_aggr.adb | 7 +--
 gcc/ada/sem_util.adb | 3 ---
 gcc/ada/sem_util.ads | 3 +++
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb
index a6a7d810185..75e5e1402df 100644
--- a/gcc/ada/exp_aggr.adb
+++ b/gcc/ada/exp_aggr.adb
@@ -5000,9 +5000,12 @@ package body Exp_Aggr is
 
   if
  --  Internal aggregate (transformed when expanding the parent)
+ --  excluding the Container aggregate as these are transformed to
+ --  procedure call later.
 
- Parent_Kind in
-   N_Aggregate | N_Extension_Aggregate | N_Component_Association
+ (Parent_Kind in
+N_Component_Association | N_Aggregate | N_Extension_Aggregate
+and then not Is_Container_Aggregate (Parent_Node))
 
  --  Allocator (see Convert_Aggr_In_Allocator)
 
diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 64abfb11ce5..a42b2dff60f 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -132,9 +132,6 @@ package body Sem_Util is
--  Determine whether arbitrary entity Id denotes an atomic object as per
--  RM C.6(7).
 
-   function Is_Container_Aggregate (Exp : Node_Id) return Boolean;
-   --  Is the given expression a container aggregate?
-
generic
   with function Is_Effectively_Volatile_Entity
 (Id : Entity_Id) return Boolean;
diff --git a/gcc/ada/sem_util.ads b/gcc/ada/sem_util.ads
index b5bcd267e33..d1bbc6af0e8 100644
--- a/gcc/ada/sem_util.ads
+++ b/gcc/ada/sem_util.ads
@@ -1475,6 +1475,9 @@ package Sem_Util is
--  Return True if the loop has no side effect and can therefore be
--  marked for removal. Return False if N is not a N_Loop_Statement.
 
+   function Is_Container_Aggregate (Exp : Node_Id) return Boolean;
+   --  Is the given expression a container aggregate?
+
function Is_Newly_Constructed
  (Exp : Node_Id; Context_Requires_NC : Boolean) return Boolean;
--  Indicates whether a given expression is "newly constructed" (RM 4.4).
-- 
2.40.0

[COMMITTED] ada: Tune message for missing 'Result in Contract_Cases

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Make the message consistent with the one for postcondition.

gcc/ada/

* sem_util.adb (Check_Result_And_Post_State): Tune message.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 9d12ee71d93..1839214332d 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -4644,7 +4644,8 @@ package body Sem_Util is
   --  attribute 'Result.
 
   elsif Present (Case_Prag) and then not Seen_In_Case then
- Error_Msg_N ("contract cases do not mention result?.t?", Case_Prag);
+ Error_Msg_N
+   ("contract cases do not mention function result?.t?", Case_Prag);
 
   --  The function has non-trivial postconditions only and they do not
   --  mention attribute 'Result.
-- 
2.40.0

[COMMITTED] ada: Crash on aggregate for tagged record with discriminants

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

The frontend may crash processing an aggregate initializing
a derived tagged record type that has discriminants.

gcc/ada/

* sem_aggr.adb
(Resolve_Record_Aggregate): For aggregates of derived tagged
record types with discriminants, when collecting components
from ancestors, pass to subprogram Gather_Components the
parent type. Required to report errors on wrong aggregate
components.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_aggr.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb
index fd0779e66d7..edd495b8359 100644
--- a/gcc/ada/sem_aggr.adb
+++ b/gcc/ada/sem_aggr.adb
@@ -5632,7 +5632,7 @@ package body Sem_Aggr is
end if;
 
Record_Def := Type_Definition (Parent (Base_Type (Parent_Typ)));
-   Gather_Components (Empty,
+   Gather_Components (Parent_Typ,
  Component_List (Record_Extension_Part (Record_Def)),
  Governed_By   => New_Assoc_List,
  Into  => Components,
-- 
2.40.0

[COMMITTED] ada: Fix spurious error on nested instantiations with generic renaming

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

The problem is that the renaming slightly changes the form of a global
reference that was saved during the analysis of a generic package, and
that is sufficient to fool the code adjusting global references during
the instantiation.

gcc/ada/

* sem_ch12.adb (Copy_Generic_Node): Test the original node kind
for the sake of consistency.  For identifiers and other entity
names and operators, accept an expanded name as associated node.
Replace "or" with "or else" in condtion and fix its formatting.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch12.adb | 27 ++-
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/gcc/ada/sem_ch12.adb b/gcc/ada/sem_ch12.adb
index a9a3e322917..2562d1a0812 100644
--- a/gcc/ada/sem_ch12.adb
+++ b/gcc/ada/sem_ch12.adb
@@ -7953,11 +7953,11 @@ package body Sem_Ch12 is
 
   --  Special casing for identifiers and other entity names and operators
 
-  if Nkind (New_N) in N_Character_Literal
-| N_Expanded_Name
-| N_Identifier
-| N_Operator_Symbol
-| N_Op
+  if Nkind (N) in N_Character_Literal
+| N_Expanded_Name
+| N_Identifier
+| N_Operator_Symbol
+| N_Op
   then
  if not Instantiating then
 
@@ -8161,6 +8161,15 @@ package body Sem_Ch12 is
   then
  Set_Entity (New_N, Assoc);
 
+  --  Cope with the rewriting into expanded name that may have
+  --  occurred in between, e.g. in Check_Generic_Child_Unit for
+  --  generic renaming declarations.
+
+  elsif Nkind (Assoc) = N_Expanded_Name then
+ Rewrite (N, New_Copy_Tree (Assoc));
+ Set_Associated_Node (N, Assoc);
+ return Copy_Generic_Node (N, Parent_Id, Instantiating);
+
   --  The name in the call may be a selected component if the
   --  call has not been analyzed yet, as may be the case for
   --  pre/post conditions in a generic unit.
@@ -8171,10 +8180,10 @@ package body Sem_Ch12 is
  Set_Entity (New_N, Entity (Name (Assoc)));
 
   elsif Nkind (Assoc) in N_Entity
-and then (Expander_Active or
-(GNATprove_Mode
-  and then not In_Spec_Expression
-  and then not Inside_A_Generic))
+and then (Expander_Active
+   or else (GNATprove_Mode
+ and then not In_Spec_Expression
+ and then not Inside_A_Generic))
   then
  --  Inlining case: we are copying a tree that contains
  --  global entities, which are preserved in the copy to be
-- 
2.40.0

[COMMITTED] ada: Tune message for pre/post on access-to-subprogram in old Ada

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Fix grammar in error message; make it consistent with a similar message
for pre/postcondition on formal subprogram.

gcc/ada/

* sem_prag.adb (Analyze_Pre_Post_Condition): Tune error message.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_prag.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index 88dacf5cc57..b74c60cd183 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -5245,7 +5245,7 @@ package body Sem_Prag is
  then
 if Ada_Version < Ada_2022 then
Error_Msg_Ada_2022_Feature
- ("pre/postcondition access-to-subprogram", Loc);
+ ("pre/postcondition on access-to-subprogram", Loc);
raise Pragma_Exit;
 end if;
 
-- 
2.40.0

[COMMITTED] ada: Fix retrieval of spec entity from entry body entity

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

When retrieving entities of subprogram spec we only handled functions
and procedures, but not entries. This had no consequences, because we
then only applied checks to functions, but still is worth a cleanup, so
the code is easier to adapt for access-to-subprogram entities as well.

gcc/ada/

* sem_util.adb (Check_Result_And_Post_State): Properly handle entry
bodies.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 1839214332d..d71329bbcb2 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -4582,6 +4582,9 @@ package body Sem_Util is
   then
  Spec_Id := Corresponding_Spec_Of_Stub (Subp_Decl);
 
+  elsif Nkind (Subp_Decl) = N_Entry_Body then
+ Spec_Id := Corresponding_Spec (Subp_Decl);
+
   else
  Spec_Id := Subp_Id;
   end if;
-- 
2.40.0

[COMMITTED] ada: Refining handling of inlining for CCG

[Marc Poulhiès via Gcc-patches]

From: Arnaud Charlet 

By marking relevant functions inline when -gnatn is used.

gcc/ada/

* sem_ch7.adb: Refine handling of inlining for CCG

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch7.adb | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/gcc/ada/sem_ch7.adb b/gcc/ada/sem_ch7.adb
index aed09f30934..ecb4bbe3e56 100644
--- a/gcc/ada/sem_ch7.adb
+++ b/gcc/ada/sem_ch7.adb
@@ -319,8 +319,9 @@ package body Sem_Ch7 is
 function Set_Referencer_Of_Non_Subprograms return Boolean is
 begin
--  An inlined subprogram body acts as a referencer
-   --  unless we generate C code since inlining is then
-   --  handled by the C compiler.
+   --  unless we generate C code without -gnatn where we want
+   --  to favor generating static inline functions as much as
+   --  possible.
 
--  Note that we test Has_Pragma_Inline here in addition
--  to Is_Inlined. We are doing this for a client, since
@@ -329,7 +330,9 @@ package body Sem_Ch7 is
--  should occur, so we need to catch all cases where the
--  subprogram may be inlined by the client.
 
-   if (not CCG_Mode or else Has_Pragma_Inline_Always (Decl_Id))
+   if (not CCG_Mode
+ or else Has_Pragma_Inline_Always (Decl_Id)
+ or else Inline_Active)
  and then (Is_Inlined (Decl_Id)
 or else Has_Pragma_Inline (Decl_Id))
then
-- 
2.40.0

[COMMITTED] ada: Spurious error on string interpolation

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

The frontend reports spurious errors on operators found in
interpolated string literals.

gcc/ada/

* scans.ads (Inside_Interpolated_String_Expression): New variable.
* par-ch2.adb (P_Interpolated_String_Literal): Set/clear new
variable when parsing interpolated string expressions.
* scng.adb (Set_String): Skip processing operator symbols when we
arescanning an interpolated string literal.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/par-ch2.adb | 17 +
 gcc/ada/scans.ads   |  3 +++
 gcc/ada/scng.adb| 10 +-
 3 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/gcc/ada/par-ch2.adb b/gcc/ada/par-ch2.adb
index b6814bdec17..af92f5ac353 100644
--- a/gcc/ada/par-ch2.adb
+++ b/gcc/ada/par-ch2.adb
@@ -225,6 +225,7 @@ package body Ch2 is
function P_Interpolated_String_Literal return Node_Id is
   Elements_List : constant List_Id := New_List;
   NL_Node   : Node_Id;
+  Saved_State   : constant Boolean := Inside_Interpolated_String_Literal;
   String_Node   : Node_Id;
 
begin
@@ -245,9 +246,17 @@ package body Ch2 is
 --  Interpolated expression
 
 if Token = Tok_Left_Curly_Bracket then
-   Scan; --  past '{'
-   Append_To (Elements_List, P_Expression);
-   T_Right_Curly_Bracket;
+   declare
+  Saved_In_Expr : constant Boolean :=
+Inside_Interpolated_String_Expression;
+
+   begin
+  Scan; --  past '{'
+  Inside_Interpolated_String_Expression := True;
+  Append_To (Elements_List, P_Expression);
+  Inside_Interpolated_String_Expression := Saved_In_Expr;
+  T_Right_Curly_Bracket;
+   end;
 else
if Prev_Token = Tok_String_Literal then
   NL_Node := New_Node (N_String_Literal, Token_Ptr);
@@ -266,7 +275,7 @@ package body Ch2 is
  end loop;
   end if;
 
-  Inside_Interpolated_String_Literal := False;
+  Inside_Interpolated_String_Literal := Saved_State;
   Set_Expressions (String_Node, Elements_List);
 
   return String_Node;
diff --git a/gcc/ada/scans.ads b/gcc/ada/scans.ads
index 19e13b6c703..00381bb4a55 100644
--- a/gcc/ada/scans.ads
+++ b/gcc/ada/scans.ads
@@ -482,6 +482,9 @@ package Scans is
--  or aspect. Used to allow/require nonstandard style rules for =>+ with
--  -gnatyt.
 
+   Inside_Interpolated_String_Expression : Boolean := False;
+   --  True while parsing an interpolated string expression
+
Inside_Interpolated_String_Literal : Boolean := False;
--  True while parsing an interpolated string literal
 
diff --git a/gcc/ada/scng.adb b/gcc/ada/scng.adb
index abf9c68cd3d..c2707df5cab 100644
--- a/gcc/ada/scng.adb
+++ b/gcc/ada/scng.adb
@@ -951,12 +951,20 @@ package body Scng is
 C3   : Character;
 
  begin
+--  Skip processing operator symbols if we are scanning an
+--  interpolated string literal.
+
+if Inside_Interpolated_String_Literal
+  and then not Inside_Interpolated_String_Expression
+then
+   null;
+
 --  Token_Name is currently set to Error_Name. The following
 --  section of code resets Token_Name to the proper Name_Op_xx
 --  value if the string is a valid operator symbol, otherwise it is
 --  left set to Error_Name.
 
-if Slen = 1 then
+elsif Slen = 1 then
C1 := Source (Token_Ptr + 1);
 
case C1 is
-- 
2.40.0

[COMMITTED] ada: Add QNX specific version of System.Parameters

[Marc Poulhiès via Gcc-patches]

From: Johannes Kliemann 

The QNX runtimes used the default implementation of
System.Parameters that defines a default stack size
of 2 MB. The QNX specific version uses the QNX default
stack size of 256 KB instead.

gcc/ada/

* Makefile.rtl (QNX): Use s-parame__qnx.adb for s-parame.adb.
* libgnat/s-parame__qnx.adb: Add QNX specific version of
System.Parameters.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/Makefile.rtl  |  1 +
 gcc/ada/libgnat/s-parame__qnx.adb | 81 +++
 2 files changed, 82 insertions(+)
 create mode 100644 gcc/ada/libgnat/s-parame__qnx.adb

diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index 2cfdd8dc613..3da32fa6668 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -1412,6 +1412,7 @@ ifeq ($(strip $(filter-out arm aarch64 %qnx,$(target_cpu) 
$(target_os))),)
   s-taspri.adshttp://www.gnu.org/licenses/>.  --
+--  --
+-- GNAT was originally developed  by the GNAT team at  New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc.  --
+--  --
+--
+
+--  This is the version for AArch64 QNX
+
+package body System.Parameters is
+
+   -
+   -- Adjust_Storage_Size --
+   -
+
+   function Adjust_Storage_Size (Size : Size_Type) return Size_Type is
+   begin
+  if Size = Unspecified_Size then
+ return Default_Stack_Size;
+  elsif Size < Minimum_Stack_Size then
+ return Minimum_Stack_Size;
+  else
+ return Size;
+  end if;
+   end Adjust_Storage_Size;
+
+   
+   -- Default_Stack_Size --
+   
+
+   function Default_Stack_Size return Size_Type is
+  Default_Stack_Size : constant Integer;
+  pragma Import (C, Default_Stack_Size, "__gl_default_stack_size");
+   begin
+  if Default_Stack_Size = -1 then
+ --  256K is the default stack size on aarch64 QNX
+ return 256 * 1024;
+  elsif Size_Type (Default_Stack_Size) < Minimum_Stack_Size then
+ return Minimum_Stack_Size;
+  else
+ return Size_Type (Default_Stack_Size);
+  end if;
+   end Default_Stack_Size;
+
+   
+   -- Minimum_Stack_Size --
+   
+
+   function Minimum_Stack_Size return Size_Type is
+   begin
+  --  256 is the value of PTHREAD_STACK_MIN on QNX and
+  --  12K is required for stack-checking. The value is
+  --  rounded up to a multiple of a 4K page.
+  return 16 * 1024;
+   end Minimum_Stack_Size;
+
+end System.Parameters;
-- 
2.40.0

[COMMITTED] ada: Simplify removal of formals from the scope

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Calls to Install_Formals are typically enclosed by Push_Scope/End_Scope.
There were just two such calls that instead used Pop_Scope, but most
likely that was by mistake.

Cleanup related to handling of class-wide contracts. Behavior appears to
be unaffected.

gcc/ada/

* contracts.adb (Remove_Formals): Remove.
(Preanalyze_Condition): Replace Pop_Scope with End_Scope.
* sem_ch13.adb (Build_Discrete_Static_Predicate): Replace
Pop_Scope with End_Scope; enclose Install_Formals within
Push_Scope/End_Scope.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/contracts.adb | 21 +
 gcc/ada/sem_ch13.adb  |  4 ++--
 2 files changed, 3 insertions(+), 22 deletions(-)

diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
index 9d02887cfa1..65f341abc8f 100644
--- a/gcc/ada/contracts.adb
+++ b/gcc/ada/contracts.adb
@@ -4846,9 +4846,6 @@ package body Contracts is
   --  Traverse Expr and clear the Controlling_Argument of calls to
   --  nonabstract functions.
 
-  procedure Remove_Formals (Id : Entity_Id);
-  --  Remove formals from homonym chains and make them not visible
-
   procedure Restore_Original_Selected_Component;
   --  Traverse Expr searching for dispatching calls to functions whose
   --  original node was a selected component, and replace them with
@@ -4898,21 +4895,6 @@ package body Contracts is
  Remove_Ctrl_Args (Expr);
   end Remove_Controlling_Arguments;
 
-  
-  -- Remove_Formals --
-  
-
-  procedure Remove_Formals (Id : Entity_Id) is
- F : Entity_Id := First_Formal (Id);
-
-  begin
- while Present (F) loop
-Set_Is_Immediately_Visible (F, False);
-Remove_Homonym (F);
-Next_Formal (F);
- end loop;
-  end Remove_Formals;
-
   -
   -- Restore_Original_Selected_Component --
   -
@@ -5032,8 +5014,7 @@ package body Contracts is
   Preanalyze_Spec_Expression (Expr, Standard_Boolean);
 
   Inside_Class_Condition_Preanalysis := False;
-  Remove_Formals (Subp);
-  Pop_Scope;
+  End_Scope;
 
   --  If this preanalyzed condition has occurrences of dispatching calls
   --  using the Object.Operation notation, during preanalysis such calls
diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index 958b26ebb0d..85c9d92e630 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -9757,10 +9757,10 @@ package body Sem_Ch13 is
 
--  Resolve new expression in function context
 
-   Install_Formals (Predicate_Function (Typ));
Push_Scope (Predicate_Function (Typ));
+   Install_Formals (Predicate_Function (Typ));
Analyze_And_Resolve (Expr, Standard_Boolean);
-   Pop_Scope;
+   End_Scope;
 end if;
  end;
   end;
-- 
2.40.0

[COMMITTED] ada: Restore SPARK_Mode On for numerical functions

[Marc Poulhiès via Gcc-patches]

From: Yannick Moy 

GNATprove has ad-hoc support for the standard numerical functions, which
consists in emitting an unprovable preconditions on cases which could
lead to an overflow. These functions are thus valid to call from SPARK
code.

gcc/ada/

* libgnat/a-ngelfu.ads: Restore SPARK_Mode from context.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/libgnat/a-ngelfu.ads | 6 --
 1 file changed, 6 deletions(-)

diff --git a/gcc/ada/libgnat/a-ngelfu.ads b/gcc/ada/libgnat/a-ngelfu.ads
index ae06ea710eb..f6d6c9643af 100644
--- a/gcc/ada/libgnat/a-ngelfu.ads
+++ b/gcc/ada/libgnat/a-ngelfu.ads
@@ -116,17 +116,14 @@ is
  Post => (if X = 0.0 then Tan'Result = 0.0);
 
function Tan (X, Cycle : Float_Type'Base) return Float_Type'Base with
- SPARK_Mode => Off,  --  Tan can overflow for some values of X and Cycle
  Pre  => Cycle > 0.0
and then abs Float_Type'Base'Remainder (X, Cycle) /= 0.25 * Cycle,
  Post => (if X = 0.0 then Tan'Result = 0.0);
 
function Cot (X : Float_Type'Base) return Float_Type'Base with
- SPARK_Mode => Off,  --  Cot can overflow for some values of X
  Pre => X /= 0.0;
 
function Cot (X, Cycle : Float_Type'Base) return Float_Type'Base with
- SPARK_Mode => Off,  --  Cot can overflow for some values of X and Cycle
  Pre => Cycle > 0.0
and then X /= 0.0
and then Float_Type'Base'Remainder (X, Cycle) /= 0.0
@@ -179,11 +176,9 @@ is
  Post => (if X > 0.0 and then Y = 0.0 then Arccot'Result = 0.0);
 
function Sinh (X : Float_Type'Base) return Float_Type'Base with
- SPARK_Mode => Off,  --  Sinh can overflow for some values of X
  Post => (if X = 0.0 then Sinh'Result = 0.0);
 
function Cosh (X : Float_Type'Base) return Float_Type'Base with
- SPARK_Mode => Off,  --  Cosh can overflow for some values of X
  Post => Cosh'Result >= 1.0
and then (if X = 0.0 then Cosh'Result = 1.0);
 
@@ -192,7 +187,6 @@ is
and then (if X = 0.0 then Tanh'Result = 0.0);
 
function Coth (X : Float_Type'Base) return Float_Type'Base with
- SPARK_Mode => Off,  --  Coth can overflow for some values of X
  Pre  => X /= 0.0,
  Post => abs Coth'Result >= 1.0;
 
-- 
2.40.0

[COMMITTED] ada: Analyze pre/post on access-to-subprogram without a wrapper

[Marc Poulhiès via Gcc-patches]

From: Piotr Trojanek 

Aspects Pre/Post attached to an access-to-subprogram type were relocated
to a spec of a wrapper subprogram and analyzed there; the body of the
wrapper was only created with expansion enabled. However, there were
several problems with this approach.

When switch -gnat2022 was missing, we didn't relocate the Pre/Post
aspects to wrapper and complained that their placement is incorrect
(because we wrongly assumed that relocation is unconditional). Now we
gently inform, that these aspects are Ada 2022 features that require
-gnat20222 switch.

When switch -gnata was missing, we entirely bypassed analysis of the
Pre/Post aspects on access-to-subprogram. This was unlike for Pre/Post
aspects on subprograms, which are checked for legality regardless of the
-gnata switch.

Finally, in the GNATprove backend we were picking the Pre/Post contract
on an access-to-subprogram type from the wrapper, which was awkward as
otherwise we had to ignore the wrapper specs and special-case for their
missing bodies. In general, it is cleaner for GNATprove to extract the
aspect expressions from where they originally appear and not from
various expansion artifacts like access-to-subprogram wrappers (but the
same applies to predication functions, type invariant procedures and
default initialization procedures).

Now we analyze the Pre/Post aspects on the types where they are
originally attached, regardless of the -gnata switch. Once we adapt
GNATprove to pick the aspect expression from there, we will stop
creating the wrapper spec when expansion is disabled.

gcc/ada/

* contracts.adb
(Add_Pre_Post_Condition): Adapt to handle pre/post of an
access-to-subprogram type.
(Analyze_Type_Contract): Analyze pre/post of an
access-to-subprogram.
* contracts.ads
(Analyze_Type_Contract): Adapt comment.
* sem_ch3.adb
(Build_Access_Subprogram_Wrapper): Copy pre/post aspects to
wrapper spec and keep it on the type.
* sem_prag.adb
(Analyze_Pre_Post_Condition): Expect pre/post aspects on
access-to-subprogram and complain if they appear without -gnat2022
switch.
(Analyze_Pre_Post_Condition_In_Decl_Part): Adapt to handle
pre/post on an access-to-subprogram type entity.
* sem_attr.adb (Analyze_Attribute_Old_Result): Likewise.
(Result): Likewise.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/contracts.adb | 20 ++--
 gcc/ada/contracts.ads |  2 ++
 gcc/ada/sem_attr.adb  | 13 +
 gcc/ada/sem_ch3.adb   | 15 +++
 gcc/ada/sem_prag.adb  | 22 ++
 5 files changed, 54 insertions(+), 18 deletions(-)

diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
index d3ceaa92e10..012ea33cf89 100644
--- a/gcc/ada/contracts.adb
+++ b/gcc/ada/contracts.adb
@@ -311,10 +311,13 @@ package body Contracts is
   --  The four volatility refinement pragmas are ok for all types.
   --  Part_Of is ok for task types and protected types.
   --  Depends and Global are ok for task types.
+  --
+  --  Precondition and Postcondition are added separately; they are allowed
+  --  for access-to-subprogram types.
 
   elsif Is_Type (Id) then
  declare
-Is_OK : constant Boolean :=
+Is_OK_Classification : constant Boolean :=
   Prag_Nam in Name_Async_Readers
 | Name_Async_Writers
 | Name_Effective_Reads
@@ -326,9 +329,16 @@ package body Contracts is
| Name_Global)
   or else (Ekind (Id) = E_Protected_Type
  and Prag_Nam = Name_Part_Of);
+
  begin
-if Is_OK then
+if Is_OK_Classification then
Add_Classification;
+
+elsif Ekind (Id) in Access_Subprogram_Kind
+and then Prag_Nam in Name_Precondition
+   | Name_Postcondition
+then
+   Add_Pre_Post_Condition;
 else
 
--  The pragma is not a proper contract item
@@ -1580,6 +1590,12 @@ package body Contracts is
begin
   Check_Type_Or_Object_External_Properties
 (Type_Or_Obj_Id => Type_Id);
+
+  --  Analyze Pre/Post on access-to-subprogram type
+
+  if Is_Access_Subprogram_Type (Type_Id) then
+ Analyze_Entry_Or_Subprogram_Contract (Type_Id);
+  end if;
end Analyze_Type_Contract;
 
---
diff --git a/gcc/ada/contracts.ads b/gcc/ada/contracts.ads
index 0625b9fc029..d52e1aaed4a 100644
--- a/gcc/ada/contracts.ads
+++ b/gcc/ada/contracts.ads
@@ -139,6 +139,8 @@ package Contracts is
--Async_Writers
--Effective_Reads
--Effective_Writes
+   --Postcondition
+   --Precondition
--
--  In the case of a protected or task type, there will also be
--  a call 

[COMMITTED] ada: Fix restoration of parent link

[Marc Poulhiès via Gcc-patches]

When resetting the parent link after having restored the selected
component node, the assertion used was incorrectly triggered when the
traversal hits the members of the parameters association list, as in:

   This.Some_Func (Param1, Param2).Dispatching_Call

When restoring the selected component for Dispatching_Call, the
assertion was wrongly triggered when passed Param1 and Param2.

gcc/ada/

* contracts.adb (Restore_Original_Selected_Component): Adjust assertion.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/contracts.adb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
index 012ea33cf89..9d02887cfa1 100644
--- a/gcc/ada/contracts.adb
+++ b/gcc/ada/contracts.adb
@@ -4954,7 +4954,8 @@ package body Contracts is
 
 begin
if Par /= Parent_Node then
-  pragma Assert (not Is_List_Member (Node));
+  pragma Assert (not Is_List_Member (Node)
+   or else Nkind (Par) = N_Function_Call);
   Set_Parent (Node, Parent_Node);
end if;
 
-- 
2.40.0

RE: [PATCH] Handle FMA friendly in reassoc pass

[Cui, Lili via Gcc-patches]

I will rebase and commit this patch, thanks!

Lili.


> -Original Message-
> From: Cui, Lili 
> Sent: Thursday, May 25, 2023 7:30 AM
> To: gcc-patches@gcc.gnu.org
> Cc: richard.guent...@gmail.com; li...@linux.ibm.com; Cui, Lili
> 
> Subject: [PATCH] Handle FMA friendly in reassoc pass
> 
> From: Lili Cui 
> 
> Make some changes in reassoc pass to make it more friendly to fma pass
> later.
> Using FMA instead of mult + add reduces register pressure and insruction
> retired.
> 
> There are mainly two changes
> 1. Put no-mult ops and mult ops alternately at the end of the queue, which is
> conducive to generating more fma and reducing the loss of FMA when
> breaking the chain.
> 2. Rewrite the rewrite_expr_tree_parallel function to try to build parallel
> chains according to the given correlation width, keeping the FMA chance as
> much as possible.
> 
> With the patch applied
> 
> On ICX:
> 507.cactuBSSN_r: Improved by 1.7% for multi-copy .
> 503.bwaves_r   : Improved by  0.60% for single copy .
> 507.cactuBSSN_r: Improved by  1.10% for single copy .
> 519.lbm_r  : Improved by  2.21% for single copy .
> no measurable changes for other benchmarks.
> 
> On aarch64
> 507.cactuBSSN_r: Improved by 1.7% for multi-copy.
> 503.bwaves_r   : Improved by 6.00% for single-copy.
> no measurable changes for other benchmarks.
> 
> TEST1:
> 
> float
> foo (float a, float b, float c, float d, float *e) {
>return  *e  + a * b + c * d ;
> }
> 
> For "-Ofast -mfpmath=sse -mfma" GCC generates:
> vmulss  %xmm3, %xmm2, %xmm2
> vfmadd132ss %xmm1, %xmm2, %xmm0
> vaddss  (%rdi), %xmm0, %xmm0
> ret
> 
> With this patch GCC generates:
> vfmadd213ss   (%rdi), %xmm1, %xmm0
> vfmadd231ss   %xmm2, %xmm3, %xmm0
> ret
> 
> TEST2:
> 
> for (int i = 0; i < N; i++)
> {
>   a[i] += b[i]* c[i] + d[i] * e[i] + f[i] * g[i] + h[i] * j[i] + k[i] * l[i] 
> + m[i]* o[i] +
> p[i]; }
> 
> For "-Ofast -mfpmath=sse -mfma"  GCC generates:
>   vmovapd e(%rax), %ymm4
>   vmulpd  d(%rax), %ymm4, %ymm3
>   addq$32, %rax
>   vmovapd c-32(%rax), %ymm5
>   vmovapd j-32(%rax), %ymm6
>   vmulpd  h-32(%rax), %ymm6, %ymm2
>   vmovapd a-32(%rax), %ymm6
>   vaddpd  p-32(%rax), %ymm6, %ymm0
>   vmovapd g-32(%rax), %ymm7
>   vfmadd231pd b-32(%rax), %ymm5, %ymm3
>   vmovapd o-32(%rax), %ymm4
>   vmulpd  m-32(%rax), %ymm4, %ymm1
>   vmovapd l-32(%rax), %ymm5
>   vfmadd231pd f-32(%rax), %ymm7, %ymm2
>   vfmadd231pd k-32(%rax), %ymm5, %ymm1
>   vaddpd  %ymm3, %ymm0, %ymm0
>   vaddpd  %ymm2, %ymm0, %ymm0
>   vaddpd  %ymm1, %ymm0, %ymm0
>   vmovapd %ymm0, a-32(%rax)
>   cmpq$8192, %rax
>   jne .L4
>   vzeroupper
>   ret
> 
> with this patch applied GCC breaks the chain with width = 2 and generates 6
> fma:
> 
>   vmovapd a(%rax), %ymm2
>   vmovapd c(%rax), %ymm0
>   addq$32, %rax
>   vmovapd e-32(%rax), %ymm1
>   vmovapd p-32(%rax), %ymm5
>   vmovapd g-32(%rax), %ymm3
>   vmovapd j-32(%rax), %ymm6
>   vmovapd l-32(%rax), %ymm4
>   vmovapd o-32(%rax), %ymm7
>   vfmadd132pd b-32(%rax), %ymm2, %ymm0
>   vfmadd132pd d-32(%rax), %ymm5, %ymm1
>   vfmadd231pd f-32(%rax), %ymm3, %ymm0
>   vfmadd231pd h-32(%rax), %ymm6, %ymm1
>   vfmadd231pd k-32(%rax), %ymm4, %ymm0
>   vfmadd231pd m-32(%rax), %ymm7, %ymm1
>   vaddpd  %ymm1, %ymm0, %ymm0
>   vmovapd %ymm0, a-32(%rax)
>   cmpq$8192, %rax
>   jne .L2
>   vzeroupper
>   ret
> 
> gcc/ChangeLog:
> 
>   PR gcc/98350
>   * tree-ssa-reassoc.cc
>   (rewrite_expr_tree_parallel): Rewrite this function.
>   (rank_ops_for_fma): New.
>   (reassociate_bb): Handle new function.
> 
> gcc/testsuite/ChangeLog:
> 
>   PR gcc/98350
>   * gcc.dg/pr98350-1.c: New test.
>   * gcc.dg/pr98350-2.c: Ditto.
> ---
>  gcc/testsuite/gcc.dg/pr98350-1.c |  31   gcc/testsuite/gcc.dg/pr98350-
> 2.c |  11 ++
>  gcc/tree-ssa-reassoc.cc  | 256 +--
>  3 files changed, 215 insertions(+), 83 deletions(-)  create mode 100644
> gcc/testsuite/gcc.dg/pr98350-1.c  create mode 100644
> gcc/testsuite/gcc.dg/pr98350-2.c
> 
> diff --git a/gcc/testsuite/gcc.dg/pr98350-1.c b/gcc/testsuite/gcc.dg/pr98350-
> 1.c
> new file mode 100644
> index 000..6bcf78a19ab
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/pr98350-1.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-Ofast  -fdump-tree-widening_mul" } */
> +
> +/* Test that the compiler properly optimizes multiply and add
> +   to generate more FMA instructions.  */ #define N 1024 double a[N];
> +double b[N]; double c[N]; double d[N]; double e[N]; double f[N]; double
> +g[N]; double h[N]; double j[N]; double k[N]; double l[N]; double m[N];
> +double o[N]; double p[N];
> +
> +
> +void
> +foo (void)
> +{
> +  for (int i = 0; i < N; i++)
> +  {

[PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

[juzhe . zhong]

From: Juzhe-Zhong 

Like FMA, Add FNMA (VNMSAC or VNMSUB) auto-vectorization support.

gcc/ChangeLog:

* config/riscv/autovec.md (fnma4): New pattern.
(*fnma): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.

---
 gcc/config/riscv/autovec.md   |  45 
 .../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
 .../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
 .../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
 .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
 .../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
 .../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
 7 files changed, 432 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index eff3e484fb4..a1028d71467 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -606,3 +606,48 @@
   }
   [(set_attr "type" "vimuladd")
(set_attr "mode" "")])
+
+;; -
+;;  [INT] VNMSAC and VNMSUB
+;; -
+;; Includes:
+;; - vnmsac
+;; - vnmsub
+;; -
+
+(define_expand "fnma4"
+  [(parallel
+[(set (match_operand:VI 0 "register_operand" "=vr")
+ (minus:VI
+   (match_operand:VI 3 "register_operand"   " vr")
+   (mult:VI
+ (match_operand:VI 1 "register_operand" " vr")
+ (match_operand:VI 2 "register_operand" " vr"
+ (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fnma"
+  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?")
+   (minus:VI
+ (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
+ (mult:VI
+   (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+   (match_operand:VI 2 "register_operand" " vr, vr,   vr"
+   (clobber (match_scratch:SI 4 "=r,r,r"))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+PUT_MODE (operands[4], Pmode);
+riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
+if (which_alternative == 2)
+  emit_insn (gen_rtx_SET (operands[0], operands[3]));
+rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
+riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
(mode),
+  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
+DONE;
+  }
+  [(set_attr "type" "vimuladd")
+   (set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
new file mode 100644
index 000..22d11de89a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=scalable" } */
+
+#include 
+
+#define TEST_TYPE(TYPE)
\
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst,
\
+ TYPE *__restrict a,  \
+ TYPE *__restrict b, int n)   \
+  {
\
+for (int i = 0; i < n; i++)
\
+  dst[i] += -(a[i] * b[i]);
\
+  }
+
+#define TEST_ALL() 
\
+  TEST_TYPE (int8_t)   
\
+  TEST_TYPE (uint8_t)  
\
+  TEST_TYPE (int16_t)  
\
+  TEST_TYPE (uint16_t) 
\

[PATCH] RISC-V: Add RVV FNMA auto-vectorization support

[juzhe . zhong]

From: Juzhe-Zhong 

Like FMA, Add FNMA auto-vectorization support.

gcc/ChangeLog:

* config/riscv/autovec.md (fnma4): New pattern.
(*fnma): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.

---
 gcc/config/riscv/autovec.md   |  45 
 .../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
 .../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
 .../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
 .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
 .../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
 .../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
 7 files changed, 432 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index eff3e484fb4..20004a8af27 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -606,3 +606,48 @@
   }
   [(set_attr "type" "vimuladd")
(set_attr "mode" "")])
+
+;; -
+;;  [INT] VMACC and VMADD
+;; -
+;; Includes:
+;; - vnmsac
+;; - vnmsub
+;; -
+
+(define_expand "fnma4"
+  [(parallel
+[(set (match_operand:VI 0 "register_operand" "=vr")
+ (minus:VI
+   (match_operand:VI 3 "register_operand"   " vr")
+   (mult:VI
+ (match_operand:VI 1 "register_operand" " vr")
+ (match_operand:VI 2 "register_operand" " vr"
+ (clobber (match_scratch:SI 4))])]
+  "TARGET_VECTOR"
+  {})
+
+(define_insn_and_split "*fnma"
+  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?")
+   (minus:VI
+ (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
+ (mult:VI
+   (match_operand:VI 1 "register_operand" " %0, vr,   vr")
+   (match_operand:VI 2 "register_operand" " vr, vr,   vr"
+   (clobber (match_scratch:SI 4 "=r,r,r"))]
+  "TARGET_VECTOR"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  {
+PUT_MODE (operands[4], Pmode);
+riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
+if (which_alternative == 2)
+  emit_insn (gen_rtx_SET (operands[0], operands[3]));
+rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
+riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
(mode),
+  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
+DONE;
+  }
+  [(set_attr "type" "vimuladd")
+   (set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
new file mode 100644
index 000..22d11de89a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
--param=riscv-autovec-preference=scalable" } */
+
+#include 
+
+#define TEST_TYPE(TYPE)
\
+  __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst,
\
+ TYPE *__restrict a,  \
+ TYPE *__restrict b, int n)   \
+  {
\
+for (int i = 0; i < n; i++)
\
+  dst[i] += -(a[i] * b[i]);
\
+  }
+
+#define TEST_ALL() 
\
+  TEST_TYPE (int8_t)   
\
+  TEST_TYPE (uint8_t)  
\
+  TEST_TYPE (int16_t)  
\
+  TEST_TYPE (uint16_t) 
\
+  TEST_TYPE 

RE: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Monday, May 29, 2023 2:02 PM
To: kito.cheng 
Cc: Kito.cheng ; Robin Dapp ; 
gcc-patches ; jeffreyalaw ; 
palmer ; palmer ; Li, Pan2 

Subject: Re: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

Yes.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-05-29 12:36
To: juzhe.zh...@rivai.ai
CC: Kito.cheng; Robin 
Dapp; gcc-patches; 
jeffreyalaw; palmer; 
palmer; pan2.li
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Ok, and just make sure this only appear for trunk, right?

juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>於 2023年5月29日 週一，12:19寫道：
This patch is fixing VSETVL PASS bug. Ok for trunk ?



juzhe.zh...@rivai.ai

From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
pan2.li; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
From: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974

PR target/109974

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.

---
gcc/config/riscv/riscv-vsetvl.cc  | 30 ++-
.../gcc.target/riscv/rvv/vsetvl/pr109974.c| 17 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9847d649d1d..fe55f4ccd30 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 return false;
   if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2)))
 return false;
-  gcc_assert (insn1->uses ().size () == insn2->uses ().size ());
+  /* RTL_SSA uses include REG_NOTE. Consider this following case:
+
+ insn1 RTL:
+ (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159])
+   (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (const_int 2 [0x2]))
+ (nil)))
+ The RTL_SSA uses of this instruction has 2 uses:
+ 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice.
+ 2. (reg:DI 14 a4 [276]) - once.
+
+ insn2 RTL:
+ (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160])
+   (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200])
+ (const_int 2 [0x2]))
+ (nil)))
+  The RTL_SSA uses of this instruction has 3 uses:
+ 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once
+ 2. (reg:DI 14 a4 [276]) - once
+ 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once
+
+  Return false when insn1->uses ().size () != insn2->uses ().size ()
+  */
+  if (insn1->uses ().size () != insn2->uses ().size ())
+return false;
   for (size_t i = 0; i < insn1->uses ().size (); i++)
 if (insn1->uses ()[i] != insn2->uses ()[i])
   return false;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
new file mode 100644
index 000..06a8562ebab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include 
+
+void
+func (int8_t *__restrict x, int64_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i++, j +=2 )
+  {
+x[i + 0] += 1;
+y[j + 0] += 1;
+y[j + 1] += 2;
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts 
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } 
*/
--
2.36.3

Re: [PATCH] LoongArch: Set 4 * (issue rate) as the default for -falign-functions and -falign-loops

[Xi Ruoyao via Gcc-patches]

On Tue, 2023-04-18 at 21:06 +0800, Lulu Cheng wrote:
> Hi, ruoyao:
> 
> Thank you so much for making this submission. But we are testing the 
> impact of these two alignment parameters
> 
> (also including -falign-jumps and -falign-lables ) on performance. So 
> before the result comes out, this patch will
> 
> not be merged into the main branch for the time being.

Hi!

Is there an estimate when the benchmark will be done?  If it will be
done soon I'll wait for the result before performing a full system
rebuild, otherwise I'll use my gut feeling to specify a -falign-
functions= value for the build :).

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

Re: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

[juzhe.zh...@rivai.ai]

Yes.



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-05-29 12:36
To: juzhe.zh...@rivai.ai
CC: Kito.cheng; Robin Dapp; gcc-patches; jeffreyalaw; palmer; palmer; pan2.li
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Ok, and just make sure this only appear for trunk, right?

juzhe.zh...@rivai.ai 於 2023年5月29日 週一，12:19寫道：
This patch is fixing VSETVL PASS bug. Ok for trunk ?



juzhe.zh...@rivai.ai

From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li; 
Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
From: Juzhe-Zhong 

Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974

PR target/109974

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.

---
gcc/config/riscv/riscv-vsetvl.cc  | 30 ++-
.../gcc.target/riscv/rvv/vsetvl/pr109974.c| 17 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9847d649d1d..fe55f4ccd30 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 return false;
   if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2)))
 return false;
-  gcc_assert (insn1->uses ().size () == insn2->uses ().size ());
+  /* RTL_SSA uses include REG_NOTE. Consider this following case:
+
+ insn1 RTL:
+ (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159])
+   (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (const_int 2 [0x2]))
+ (nil)))
+ The RTL_SSA uses of this instruction has 2 uses:
+ 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice.
+ 2. (reg:DI 14 a4 [276]) - once.
+
+ insn2 RTL:
+ (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160])
+   (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200])
+ (const_int 2 [0x2]))
+ (nil)))
+  The RTL_SSA uses of this instruction has 3 uses:
+ 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once
+ 2. (reg:DI 14 a4 [276]) - once
+ 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once
+
+  Return false when insn1->uses ().size () != insn2->uses ().size ()
+  */
+  if (insn1->uses ().size () != insn2->uses ().size ())
+return false;
   for (size_t i = 0; i < insn1->uses ().size (); i++)
 if (insn1->uses ()[i] != insn2->uses ()[i])
   return false;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
new file mode 100644
index 000..06a8562ebab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include 
+
+void
+func (int8_t *__restrict x, int64_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i++, j +=2 )
+  {
+x[i + 0] += 1;
+y[j + 0] += 1;
+y[j + 1] += 2;
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts 
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } 
*/
-- 
2.36.3