Re: [PATCH 2/2] ARC: Use intrinsics for __builtin_sub_overflow*()
OK,
Thank you for your contribution,
Claudiu
On Wed, Sep 6, 2023 at 3:50 PM Shahab Vahedi wrote:
>
> This patch covers signed and unsigned subtractions. The generated code
> would be something along these lines:
>
> signed:
> sub.f r0, r1, r2
> b.v @label
>
> unsigned:
> sub.f r0, r1, r2
> b.c @label
>
> gcc/ChangeLog:
>
> * config/arc/arc.md (subsi3_v): New insn.
> (subvsi4): New expand.
> (subsi3_c): New insn.
> (usubvsi4): New expand.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arc/overflow-2.c: New.
>
> Signed-off-by: Shahab Vahedi
> ---
> gcc/config/arc/arc.md | 48 +++
> gcc/testsuite/gcc.target/arc/overflow-2.c | 97 +++
> 2 files changed, 145 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/arc/overflow-2.c
>
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index 9d011f6b4a9..34e9e1a7f1d 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -2973,6 +2973,54 @@ archs4x, archs4xd"
>(set_attr "cpu_facility" "*,cd,*,*,*,*,*,*,*,*")
>])
>
> +(define_insn "subsi3_v"
> + [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
> + (minus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
> + (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32")))
> + (set (reg:CC_V CC_REG)
> + (compare:CC_V (sign_extend:DI (minus:SI (match_dup 1)
> + (match_dup 2)))
> + (minus:DI (sign_extend:DI (match_dup 1))
> + (sign_extend:DI (match_dup 2)]
> + ""
> + "sub.f\\t%0,%1,%2"
> + [(set_attr "cond" "set")
> +(set_attr "type" "compare")
> +(set_attr "length" "4,4,4,8")])
> +
> +(define_expand "subvsi4"
> + [(match_operand:SI 0 "register_operand")
> + (match_operand:SI 1 "register_operand")
> + (match_operand:SI 2 "nonmemory_operand")
> + (label_ref (match_operand 3 "" ""))]
> + ""
> + "emit_insn (gen_subsi3_v (operands[0], operands[1], operands[2]));
> + arc_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
> + DONE;")
> +
> +(define_insn "subsi3_c"
> + [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
> + (minus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
> + (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32")))
> + (set (reg:CC_C CC_REG)
> + (compare:CC_C (match_dup 1)
> + (match_dup 2)))]
> + ""
> + "sub.f\\t%0,%1,%2"
> + [(set_attr "cond" "set")
> +(set_attr "type" "compare")
> +(set_attr "length" "4,4,4,8")])
> +
> +(define_expand "usubvsi4"
> + [(match_operand:SI 0 "register_operand")
> + (match_operand:SI 1 "register_operand")
> + (match_operand:SI 2 "nonmemory_operand")
> + (label_ref (match_operand 3 "" ""))]
> + ""
> + "emit_insn (gen_subsi3_c (operands[0], operands[1], operands[2]));
> +arc_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]);
> +DONE;")
> +
> (define_expand "subdi3"
>[(set (match_operand:DI 0 "register_operand" "")
> (minus:DI (match_operand:DI 1 "register_operand" "")
> diff --git a/gcc/testsuite/gcc.target/arc/overflow-2.c
> b/gcc/testsuite/gcc.target/arc/overflow-2.c
> new file mode 100644
> index 000..b4de8c03b22
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arc/overflow-2.c
> @@ -0,0 +1,97 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O1" } */
> +
> +#include
> +#include
> +
> +/*
> + * sub.f r0,r0,r1
> + * st_s r0,[r2]
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool sub_overflow (int32_t a, int32_t b, int32_t *res)
> +{
> + return __builtin_sub_overflow (a, b, res);
> +}
> +
> +/*
> + * sub.f r0,r0,-1234
> + * st_s r0,[r1]
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool subi_overflow (int32_t a, int32_t *res)
> +{
> + return __builtin_sub_overflow (a, -1234, res);
> +}
> +
> +/*
> + * sub.f r3,r0,r1
> + * st_s r3,[r2]
> + * j_s.d [blink]
> + * setlo r0,r0,r1
> + */
> +bool usub_overflow (uint32_t a, uint32_t b, uint32_t *res)
> +{
> + return __builtin_sub_overflow (a, b, res);
> +}
> +
> +/*
> + * sub.f r2,r0,4321
> + * seths r0,4320,r0
> + * j_s.d [blink]
> + * st_s r2,[r1]
> + */
> +bool usubi_overflow (uint32_t a, uint32_t *res)
> +{
> + return __builtin_sub_overflow (a, 4321, res);
> +}
> +
> +/*
> + * sub.f r0,r0,r1
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool sub_overflow_p (int32_t a, int32_t b, int32_t res)
> +{
> + return __builtin_sub_overflow_p (a, b, res);
> +}
> +
> +/*
> + * sub.f r0,r0,-1000
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool subi_overflow_p (int32_t a, int32_t res)
> +{
> + return __builtin_sub_overflow_p (a, -1000, res);
> +}
> +
> +/*
> + * j_s.d [blink]
> + * setlo r0,r0,r1
> + */
> +bool usub_overflow_p (uint32_t a, uint32_t b, uint32_t res)
> +{
> +
Re: [PATCH 1/2] ARC: Use intrinsics for __builtin_add_overflow*()
Ok.
Thank you for your contribution,
Claudiu
On Wed, Sep 6, 2023 at 3:50 PM Shahab Vahedi wrote:
>
> This patch covers signed and unsigned additions. The generated code
> would be something along these lines:
>
> signed:
> add.f r0, r1, r2
> b.v @label
>
> unsigned:
> add.f r0, r1, r2
> b.c @label
>
> gcc/ChangeLog:
>
> * config/arc/arc-modes.def: Add CC_V mode.
> * config/arc/predicates.md (proper_comparison_operator): Handle
> E_CC_Vmode.
> (equality_comparison_operator): Exclude CC_Vmode from eq/ne.
> (cc_set_register): Handle CC_Vmode.
> (cc_use_register): Likewise.
> * config/arc/arc.md (addsi3_v): New insn.
> (addvsi4): New expand.
> (addsi3_c): New insn.
> (uaddvsi4): New expand.
> * config/arc/arc-protos.h (arc_gen_unlikely_cbranch): New.
> * config/arc/arc.cc (arc_gen_unlikely_cbranch): New.
> (get_arc_condition_code): Handle E_CC_Vmode.
> (arc_init_reg_tables): Handle CC_Vmode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arc/overflow-1.c: New.
>
> Signed-off-by: Shahab Vahedi
> ---
> gcc/config/arc/arc-modes.def | 1 +
> gcc/config/arc/arc-protos.h | 1 +
> gcc/config/arc/arc.cc | 26 +-
> gcc/config/arc/arc.md | 49 +++
> gcc/config/arc/predicates.md | 14 ++-
> gcc/testsuite/gcc.target/arc/overflow-1.c | 100 ++
> 6 files changed, 187 insertions(+), 4 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/arc/overflow-1.c
>
> diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def
> index 763e880317d..69eeec5935a 100644
> --- a/gcc/config/arc/arc-modes.def
> +++ b/gcc/config/arc/arc-modes.def
> @@ -24,6 +24,7 @@ along with GCC; see the file COPYING3. If not see
>
> CC_MODE (CC_ZN);
> CC_MODE (CC_Z);
> +CC_MODE (CC_V);
> CC_MODE (CC_C);
> CC_MODE (CC_FP_GT);
> CC_MODE (CC_FP_GE);
> diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
> index 4f2db7ffb59..bc78fb0b370 100644
> --- a/gcc/config/arc/arc-protos.h
> +++ b/gcc/config/arc/arc-protos.h
> @@ -50,6 +50,7 @@ extern bool arc_check_mov_const (HOST_WIDE_INT );
> extern bool arc_split_mov_const (rtx *);
> extern bool arc_can_use_return_insn (void);
> extern bool arc_split_move_p (rtx *);
> +extern void arc_gen_unlikely_cbranch (enum rtx_code, machine_mode, rtx);
> #endif /* RTX_CODE */
>
> extern bool arc_ccfsm_branch_deleted_p (void);
> diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
> index f8c9bf17e2c..ec93d40aeb9 100644
> --- a/gcc/config/arc/arc.cc
> +++ b/gcc/config/arc/arc.cc
> @@ -1538,6 +1538,13 @@ get_arc_condition_code (rtx comparison)
> case GEU : return ARC_CC_NC;
> default : gcc_unreachable ();
> }
> +case E_CC_Vmode:
> + switch (GET_CODE (comparison))
> + {
> + case EQ : return ARC_CC_NV;
> + case NE : return ARC_CC_V;
> + default : gcc_unreachable ();
> + }
> case E_CC_FP_GTmode:
>if (TARGET_ARGONAUT_SET && TARGET_SPFP)
> switch (GET_CODE (comparison))
> @@ -1868,7 +1875,7 @@ arc_init_reg_tables (void)
> /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
> we must explicitly check for them here. */
> if (i == (int) CCmode || i == (int) CC_ZNmode || i == (int) CC_Zmode
> - || i == (int) CC_Cmode
> + || i == (int) CC_Cmode || i == (int) CC_Vmode
> || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode
> || i == CC_FPUmode || i == CC_FPUEmode || i == CC_FPU_UNEQmode)
> arc_mode_class[i] = 1 << (int) C_MODE;
> @@ -11852,6 +11859,23 @@ arc_libm_function_max_error (unsigned cfn,
> machine_mode mode,
>return default_libm_function_max_error (cfn, mode, boundary_p);
> }
>
> +/* Generate RTL for conditional branch with rtx comparison CODE in mode
> + CC_MODE. */
> +
> +void
> +arc_gen_unlikely_cbranch (enum rtx_code cmp, machine_mode cc_mode, rtx label)
> +{
> + rtx cc_reg, x;
> +
> + cc_reg = gen_rtx_REG (cc_mode, CC_REG);
> + label = gen_rtx_LABEL_REF (VOIDmode, label);
> +
> + x = gen_rtx_fmt_ee (cmp, VOIDmode, cc_reg, const0_rtx);
> + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx);
> +
> + emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
> +}
> +
> #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
> #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
>
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index d37ecbf4292..9d011f6b4a9 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -2725,6 +2725,55 @@ archs4x, archs4xd"
> }
>")
>
> +(define_insn "addsi3_v"
> + [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
> + (plus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
> + (match_operand:SI 2
Re: [PATCH] Avoid depending on destructor order
Thanks, I haven't observed it. Waiting for it, Claudiu On Mon, Sep 26, 2022 at 2:49 PM Thomas Neumann wrote: > > Hi Claudiu, > > > This change prohibits compiling of ARC backend: > > > >> + gcc_assert (in_shutdown || ob); > > > > in_shutdown is only defined when ATOMIC_FDE_FAST_PATH is defined, > > while gcc_assert is outside of any ifdef. Please can you revisit this > > line and change it accordingly. > > I have a patch ready, I am waiting for someone to approve my patch: > > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/602130.html > > Best > > Thomas
Re: [PATCH] Avoid depending on destructor order
Hi Thomas, This change prohibits compiling of ARC backend: > + gcc_assert (in_shutdown || ob); in_shutdown is only defined when ATOMIC_FDE_FAST_PATH is defined, while gcc_assert is outside of any ifdef. Please can you revisit this line and change it accordingly. Thanks, Claudiu
Re: [PATCH] arc: Fix for new ifcvt behavior [PR104154]
Hi Robin, The patch looks good. Please go ahead and merge it, please let me know if you cannot. Thank you, Claudiu On Mon, Feb 21, 2022 at 9:57 AM Robin Dapp via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > Hi, > > I figured I'd just go ahead and post this patch as well since it seems > to have fixed the arc build problems. > > It would be nice if someone could bootstrap/regtest if Jeff hasn't > already done so. I was able to verify that the two testcases attached > to the PR build cleanly but not much more. Thank you. > > Regards > Robin > > -- > > PR104154 > > gcc/ChangeLog: > > * config/arc/arc.cc (gen_compare_reg): Return the CC-mode > comparison ifcvt passed us. > > --- > > From fa98a40abd55e3a10653f6a8c5b2414a2025103b Mon Sep 17 00:00:00 2001 > From: Robin Dapp > Date: Mon, 7 Feb 2022 08:39:41 +0100 > Subject: [PATCH] arc: Fix for new ifcvt behavior [PR104154] > > ifcvt now passes a CC-mode "comparison" to backends. This patch > simply returns from gen_compare_reg () in that case since nothing > needs to be prepared anymore. > > PR104154 > > gcc/ChangeLog: > > * config/arc/arc.cc (gen_compare_reg): Return the CC-mode > comparison ifcvt passed us. > --- > gcc/config/arc/arc.cc | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc > index 8cc173519ab..5e40ec2c04d 100644 > --- a/gcc/config/arc/arc.cc > +++ b/gcc/config/arc/arc.cc > @@ -2254,6 +2254,12 @@ gen_compare_reg (rtx comparison, machine_mode omode) > > >cmode = GET_MODE (x); > + > + /* If ifcvt passed us a MODE_CC comparison we can > + just return it. It should be in the proper form already. */ > + if (GET_MODE_CLASS (cmode) == MODE_CC) > +return comparison; > + >if (cmode == VOIDmode) > cmode = GET_MODE (y); >gcc_assert (cmode == SImode || cmode == SFmode || cmode == DFmode); > -- > 2.31.1 > >
Re: [committed] arc: Fail conditional move expand patterns
Hi Robin, I don't know how I missed your arc related patch, I'll bootstrap and test your patch asap. Thanks, Claudiu On Fri, Feb 25, 2022 at 3:29 PM Robin Dapp wrote: > > If the movcc comparison is not valid it triggers an assert in the > > current implementation. This behavior is not needed as we can FAIL > > the movcc expand pattern. > > In case of a MODE_CC comparison you can also just return it as described > here https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104154 > > or here: > https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590639.html > > If there already is a "CC comparison" the backend does not need to > create one and ifcvt can make use of this, creating better sequences. > > Regards > Robin >
Re: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Thanks a lot guys. Patch is pushed. //Claudiu On Mon, Jun 14, 2021 at 12:34 AM Jeff Law wrote: > > > > On 6/13/2021 4:06 AM, Bernhard Reutner-Fischer wrote: > > On Fri, 11 Jun 2021 14:25:24 +0300 > > Claudiu Zissulescu wrote: > > > >> Hi Bernhard, > >> > >> Please find attached my latest patch, it includes (hopefully) all your > >> feedback. > >> > >> Thank you for comments, > > concise and clean, i wouldn't know what to remove. LGTM. > > thanks for your patience! > THen let's consider it approved at this point. Thanks for chiming in > Bernhard and thanks for implementing the suggestions Claudiu! > > jeff
Re: [PATCH] arc: Use separate predicated patterns for mpyd(u)
Gentle PING. On Wed, Oct 7, 2020 at 12:39 PM Claudiu Zissulescu wrote: > > From: Claudiu Zissulescu > > The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction, > which is incorrect. The mpyd(u) instruction takes as input two 32-bit > registers, returning into a double 64-bit even-odd register pair. For > the predicated case, the ARC instruction decoder expects the > destination register to be the same as the first input register. In > the big-endian case the result is swaped in the destination register > pair, however, the instruction encoding remains the same. Refurbish > the mpyd(u) patterns to take into account the above observation. > > Permission to apply this patch to master, gcc10 and gcc9 branches. > > Cheers, > Claudiu > > -xx-xx Claudiu Zissulescu > > * testsuite/gcc.target/arc/pmpyd.c: New test. > * testsuite/gcc.target/arc/tmac-1.c: Update. > * config/arc/arc.md (mpyd_arcv2hs): New template > pattern. > (*pmpyd_arcv2hs): Likewise. > (*pmpyd_imm_arcv2hs): Likewise. > (mpyd_arcv2hs): Moved into above template. > (mpyd_imm_arcv2hs): Moved into above template. > (mpydu_arcv2hs): Likewise. > (mpydu_imm_arcv2hs): Likewise. > (su_optab): New optab prefix for sign/zero-extending operations. > > Signed-off-by: Claudiu Zissulescu > --- > gcc/config/arc/arc.md | 101 +- > gcc/testsuite/gcc.target/arc/pmpyd.c | 15 > gcc/testsuite/gcc.target/arc/tmac-1.c | 2 +- > 3 files changed, 67 insertions(+), 51 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arc/pmpyd.c > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 1720e8cd2f6f..d4d9f59a3eac 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -894,6 +894,8 @@ archs4x, archs4xd" > > (define_code_iterator SEZ [sign_extend zero_extend]) > (define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) > +; Optab prefix for sign/zero-extending operations > +(define_code_attr su_optab [(sign_extend "") (zero_extend "u")]) > > (define_insn "*xt_cmp0_noout" >[(set (match_operand 0 "cc_set_register" "") > @@ -6436,66 +6438,65 @@ archs4x, archs4xd" > (set_attr "predicable" "no") > (set_attr "cond" "nocond")]) > > -(define_insn "mpyd_arcv2hs" > - [(set (match_operand:DI 0 "even_register_operand" > "=Rcr, r") > - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " > 0, c")) > -(sign_extend:DI (match_operand:SI 2 "register_operand" " > c, c" > +(define_insn "mpyd_arcv2hs" > + [(set (match_operand:DI 0 "even_register_operand" "=r") > + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r")) > +(SEZ:DI (match_operand:SI 2 "register_operand" "r" > (set (reg:DI ARCV2_ACC) > (mult:DI > - (sign_extend:DI (match_dup 1)) > - (sign_extend:DI (match_dup 2] > + (SEZ:DI (match_dup 1)) > + (SEZ:DI (match_dup 2] >"TARGET_PLUS_MACD" > - "mpyd%? %0,%1,%2" > - [(set_attr "length" "4,4") > - (set_attr "iscompact" "false") > - (set_attr "type" "multi") > - (set_attr "predicable" "yes,no") > - (set_attr "cond" "canuse,nocond")]) > - > -(define_insn "mpyd_imm_arcv2hs" > - [(set (match_operand:DI 0 "even_register_operand" > "=Rcr, r,r,Rcr, r") > - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " > 0, c,0, 0, c")) > -(match_operand 2 "immediate_operand" " > L, L,I,Cal,Cal"))) > + "mpyd%?\\t%0,%1,%2" > + [(set_attr "length" "4") > + (set_attr "iscompact" "false") > + (set_attr "type" "multi") > + (set_attr "predicable" "no")]) > + > +(define_insn "*pmpyd_arcv2hs" > + [(set (match_operand:DI 0 "even_register_operand" "=r") > + (mult:DI > +(SEZ:DI (match_operand:SI 1 "even_register_operand" "%0")) > +(SEZ:DI (match_operand:SI 2 "register_operand" "r" > (set (reg:DI ARCV2_ACC) > - (mult:DI (sign_extend:DI (match_dup 1)) > -(match_dup 2)))] > + (mult:DI > + (SEZ:DI (match_dup 1)) > + (SEZ:DI (match_dup 2] >"TARGET_PLUS_MACD" > - "mpyd%? %0,%1,%2" > - [(set_attr "length" "4,4,4,8,8") > - (set_attr "iscompact" "false") > - (set_attr "type" "multi") > - (set_attr "predicable" "yes,no,no,yes,no") > - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")]) > - > -(define_insn "mpydu_arcv2hs" > - [(set (match_operand:DI 0 "even_register_operand" > "=Rcr, r") > - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " > 0, c")) > -(zero_extend:DI (match_operand:SI 2 "register_operand" " > c, c" > + "mpyd%?\\t%0,%1,%2" > + [(set_attr "length" "4") > + (set_attr "iscompact" "false") > + (set_attr "type" "multi") > + (set_attr
Re: [PATCH] arc: Improve/add instruction patterns to better use MAC instructions.
Gentle PING.
On Fri, Oct 9, 2020 at 5:24 PM Claudiu Zissulescu wrote:
>
> From: Claudiu Zissulescu
>
> ARC MYP7+ instructions add MAC instructions for vector and scalar data
> types. This patch adds a madd pattern for 16it datum that is using the
> 32bit MAC instruction, and dot_prod patterns for v4hi vector
> types. The 64bit moves are also upgraded by using vadd2 instuction.
>
> gcc/
> -xx-xx Claudiu Zissulescu
>
> * config/arc/arc.c (arc_split_move): Recognize vadd2 instructions.
> * config/arc/arc.md (movdi_insn): Update pattern to use vadd2
> instructions.
> (movdf_insn): Likewise.
> (maddhisi4): New pattern.
> (umaddhisi4): Likewise.
> * config/arc/simdext.md (mov_int): Update pattern to use
> vadd2.
> (sdot_prodv4hi): New pattern.
> (udot_prodv4hi): Likewise.
> (arc_vec_mac_hi_v4hi): Update/renamed to
> arc_vec_mac_v2hiv2si.
> (arc_vec_mac_v2hiv2si_zero): New pattern.
>
> Signed-off-by: Claudiu Zissulescu
> ---
> gcc/config/arc/arc.c | 8
> gcc/config/arc/arc.md | 71 ---
> gcc/config/arc/constraints.md | 5 ++
> gcc/config/arc/simdext.md | 90 +++
> 4 files changed, 147 insertions(+), 27 deletions(-)
>
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index ec55cfde87a9..d5b521e75e67 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -10202,6 +10202,14 @@ arc_split_move (rtx *operands)
>return;
> }
>
> + if (TARGET_PLUS_QMACW
> + && even_register_operand (operands[0], mode)
> + && even_register_operand (operands[1], mode))
> +{
> + emit_move_insn (operands[0], operands[1]);
> + return;
> +}
> +
>if (TARGET_PLUS_QMACW
>&& GET_CODE (operands[1]) == CONST_VECTOR)
> {
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index f9fc11e51a85..1720e8cd2f6f 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -1345,8 +1345,8 @@ archs4x, archs4xd"
>")
>
> (define_insn_and_split "*movdi_insn"
> - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m")
> - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))]
> + [(set (match_operand:DI 0 "move_dest_operand" "=r, r,r, m")
> + (match_operand:DI 1 "move_double_src_operand" "r,Hi,m,rCm3"))]
>"register_operand (operands[0], DImode)
> || register_operand (operands[1], DImode)
> || (satisfies_constraint_Cm3 (operands[1])
> @@ -1358,6 +1358,13 @@ archs4x, archs4xd"
> default:
>return \"#\";
>
> +case 0:
> +if (TARGET_PLUS_QMACW
> + && even_register_operand (operands[0], DImode)
> + && even_register_operand (operands[1], DImode))
> + return \"vadd2\\t%0,%1,0\";
> +return \"#\";
> +
> case 2:
> if (TARGET_LL64
> && memory_operand (operands[1], DImode)
> @@ -1374,7 +1381,7 @@ archs4x, archs4xd"
> return \"#\";
> }
> }"
> - "reload_completed"
> + "&& reload_completed"
>[(const_int 0)]
>{
> arc_split_move (operands);
> @@ -1420,15 +1427,24 @@ archs4x, archs4xd"
>"if (prepare_move_operands (operands, DFmode)) DONE;")
>
> (define_insn_and_split "*movdf_insn"
> - [(set (match_operand:DF 0 "move_dest_operand" "=D,r,c,c,r,m")
> - (match_operand:DF 1 "move_double_src_operand" "r,D,c,E,m,c"))]
> - "register_operand (operands[0], DFmode) || register_operand (operands[1],
> DFmode)"
> + [(set (match_operand:DF 0 "move_dest_operand" "=D,r,r,r,r,m")
> + (match_operand:DF 1 "move_double_src_operand" "r,D,r,E,m,r"))]
> + "register_operand (operands[0], DFmode)
> + || register_operand (operands[1], DFmode)"
>"*
> {
> switch (which_alternative)
> {
> default:
>return \"#\";
> +
> +case 2:
> +if (TARGET_PLUS_QMACW
> + && even_register_operand (operands[0], DFmode)
> + && even_register_operand (operands[1], DFmode))
> + return \"vadd2\\t%0,%1,0\";
> +return \"#\";
> +
> case 4:
> if (TARGET_LL64
> && ((even_register_operand (operands[0], DFmode)
> @@ -6177,6 +6193,49 @@ archs4x, archs4xd"
>[(set_attr "length" "0")])
>
> ;; MAC and DMPY instructions
> +
> +; Use MAC instruction to emulate 16bit mac.
> +(define_expand "maddhisi4"
> + [(match_operand:SI 0 "register_operand" "")
> + (match_operand:HI 1 "register_operand" "")
> + (match_operand:HI 2 "extend_operand" "")
> + (match_operand:SI 3 "register_operand" "")]
> + "TARGET_PLUS_DMPY"
> + "{
> + rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
> + rtx tmp1 = gen_reg_rtx (SImode);
> + rtx tmp2 = gen_reg_rtx (SImode);
> + rtx accl = gen_lowpart (SImode, acc_reg);
> +
> + emit_move_insn (accl, operands[3]);
> + emit_insn (gen_rtx_SET (tmp1, gen_rtx_SIGN_EXTEND (SImode, operands[1])));
> + emit_insn (gen_rtx_SET (tmp2, gen_rtx_SIGN_EXTEND (SImode,
Re: [PATCH] [ARC] Allow more ABIs in GLIBC_DYNAMIC_LINKER
Done.
Thank you for your support,
Claudiu
On Thu, Apr 9, 2020 at 2:38 AM Vineet Gupta wrote:
>
> Hi Claudiu,
>
> For glibc needs can this be backported to gcc-9 please !
>
> Thx,
> -Vineet
>
> On 3/31/20 3:06 AM, Claudiu Zissulescu Ianculescu wrote:
> > Pushed.
> >
> > Thank you,
> > Claudiu
> >
> > On Sun, Mar 29, 2020 at 2:05 AM Vineet Gupta via Gcc-patches
> > wrote:
> >> Enable big-endian suffixed dynamic linker per glibc multi-abi support.
> >>
> >> And to avoid a future churn and version pairingi hassles, also allow
> >> arc700 although glibc for ARC currently doesn't support it.
> >>
> >> gcc/
> >> -xx-xx Vineet Gupta
> >> +
> >> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
> >>
> >> Signed-off-by: Vineet Gupta
> >> ---
> >> gcc/ChangeLog | 4
> >> gcc/config/arc/linux.h | 2 +-
> >> 2 files changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> >> index 86ad683a6cb0..c26a748fd51b 100644
> >> --- a/gcc/ChangeLog
> >> +++ b/gcc/ChangeLog
> >> @@ -1,3 +1,7 @@
> >> +2020-03-28 Vineet Gupta
> >> +
> >> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
> >> +
> >> 2020-03-28 Jakub Jelinek
> >>
> >> PR c/93573
> >> diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
> >> index 0b99da3fcdaf..1bbeccee7115 100644
> >> --- a/gcc/config/arc/linux.h
> >> +++ b/gcc/config/arc/linux.h
> >> @@ -29,7 +29,7 @@ along with GCC; see the file COPYING3. If not see
> >> } \
> >>while (0)
> >>
> >> -#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-arc.so.2"
> >> +#define GLIBC_DYNAMIC_LINKER
> >> "/lib/ld-linux-arc%{mbig-endian:eb}%{mcpu=arc700:700}.so.2"
> >> #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
> >>
> >> /* Note that the default is to link against dynamic libraries, if they are
> >> --
> >> 2.20.1
> >>
> > ___
> > linux-snps-arc mailing list
> > linux-snps-...@lists.infradead.org
> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_mailman_listinfo_linux-2Dsnps-2Darc=DwICAg=DPL6_X_6JkXFx7AXWqB0tg=7FgpX6o3vAhwMrMhLh-4ZJey5kjdNUwOL2CWsFwR4T8=MrObyH2ki95_7m_xHpnWX-k9eIMOsxMuSa48qhxYOCY=3ggbGwaiJuSFnFECy0ItuwBBMDAcriwCdSc3GA0UFig=
>
Re: [PATCH] [ARC] Allow more ABIs in GLIBC_DYNAMIC_LINKER
Pushed.
Thank you,
Claudiu
On Sun, Mar 29, 2020 at 2:05 AM Vineet Gupta via Gcc-patches
wrote:
>
> Enable big-endian suffixed dynamic linker per glibc multi-abi support.
>
> And to avoid a future churn and version pairingi hassles, also allow
> arc700 although glibc for ARC currently doesn't support it.
>
> gcc/
> -xx-xx Vineet Gupta
> +
> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
>
> Signed-off-by: Vineet Gupta
> ---
> gcc/ChangeLog | 4
> gcc/config/arc/linux.h | 2 +-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index 86ad683a6cb0..c26a748fd51b 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,7 @@
> +2020-03-28 Vineet Gupta
> +
> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
> +
> 2020-03-28 Jakub Jelinek
>
> PR c/93573
> diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
> index 0b99da3fcdaf..1bbeccee7115 100644
> --- a/gcc/config/arc/linux.h
> +++ b/gcc/config/arc/linux.h
> @@ -29,7 +29,7 @@ along with GCC; see the file COPYING3. If not see
> } \
>while (0)
>
> -#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-arc.so.2"
> +#define GLIBC_DYNAMIC_LINKER
> "/lib/ld-linux-arc%{mbig-endian:eb}%{mcpu=arc700:700}.so.2"
> #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
>
> /* Note that the default is to link against dynamic libraries, if they are
> --
> 2.20.1
>
