[COMMITTED] pru: Implement TARGET_CLASS_LIKELY_SPILLED_P to fix PR115013

[Dimitar Dimitrov]

Commit r15-436-g44e7855e did not fix PR115013 for PRU because
SMALL_REGISTER_CLASS_P is not returning an accurate value for the PRU
backend.

Word mode for PRU backend is defined as 8-bit, yet all ALU operations
are preferred in 32-bit mode.  Thus checking whether a register class
contains a single word_mode register would not classify the actually
single SImode register classes as small.  This affected the
multiplication source and destination register classes.

Fix by implementing TARGET_CLASS_LIKELY_SPILLED_P to treat all register
classes with SImode or smaller size as likely spilled.  This in turn
corrects the behaviour of SMALL_REGISTER_CLASS_P for PRU.

Patch was successfully regression tested for pru-unknown-elf. Firmware
size is the same when checked with embench-iot and a few example
projects.

PR rtl-optimization/115013

gcc/ChangeLog:

* config/pru/pru.cc (pru_class_likely_spilled_p): Implement
to mark classes containing one SImode register as likely
spilled.
(TARGET_CLASS_LIKELY_SPILLED_P): Define.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.cc | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc
index 41d7195d2b5..491f66432b3 100644
--- a/gcc/config/pru/pru.cc
+++ b/gcc/config/pru/pru.cc
@@ -517,6 +517,17 @@ pru_can_use_return_insn (void)
   return cfun->machine->total_size == 0;
 }
 
+/* Implement `TARGET_CLASS_LIKELY_SPILLED_P'.  The original intention
+   of the default implementation is kept, but is adjusted for PRU.
+   Return TRUE if the given class C contains a single SImode
+   (as opposed to word_mode!) register.  */
+
+static bool
+pru_class_likely_spilled_p (reg_class_t c)
+{
+  return (reg_class_size[(int) c] <= GET_MODE_SIZE (SImode));
+}
+
 /* Implement TARGET_HARD_REGNO_MODE_OK.  */
 
 static bool
@@ -3181,6 +3192,9 @@ pru_unwind_word_mode (void)
 #undef TARGET_CAN_ELIMINATE
 #define TARGET_CAN_ELIMINATE pru_can_eliminate
 
+#undef TARGET_CLASS_LIKELY_SPILLED_P
+#define TARGET_CLASS_LIKELY_SPILLED_P pru_class_likely_spilled_p
+
 #undef TARGET_HARD_REGNO_MODE_OK
 #define TARGET_HARD_REGNO_MODE_OK pru_hard_regno_mode_ok
 
-- 
2.45.0

[COMMITTED] pru: Fix register class checks in predicates

[Dimitar Dimitrov]

The register class checks in the multiply-source predicates was
incorrectly using the register number instead of the register
class for comparison.

This has slipped through all regression tests because the mulsi3 pattern
was expanded with pseudo registers. So the faulty predicate comparison
was not executed. The corresponding constraints are correct, though,
which ensured that the generated code is correct.

gcc/ChangeLog:

* config/pru/predicates.md (pru_mulsrc0_operand): Use register
class instead of register number for the check.
(pru_mulsrc1_operand): Ditto.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/predicates.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index 77b3316b98e..55635599609 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -103,7 +103,7 @@ (define_predicate "pru_mulsrc0_operand"
   else
return 0;
 
-  return REGNO_REG_CLASS (regno) == MULSRC0_REGNUM
+  return REGNO_REG_CLASS (regno) == MULSRC0_REGS
 || regno >= FIRST_PSEUDO_REGISTER;
 }
   return 0;
@@ -123,7 +123,7 @@ (define_predicate "pru_mulsrc1_operand"
   else
return 0;
 
-  return REGNO_REG_CLASS (regno) == MULSRC1_REGNUM
+  return REGNO_REG_CLASS (regno) == MULSRC1_REGS
 || regno >= FIRST_PSEUDO_REGISTER;
 }
   return 0;
-- 
2.45.0

Re: [PATCH 2/4] df: Add DF_LIVE_SUBREG problem

[Dimitar Dimitrov]

On Wed, May 08, 2024 at 11:34:48AM +0800, 陈硕 wrote:
> Hi Dimitar
> 
> 
> I send a patch just now, modifies accordingly
> 
> 
> some comments:
> 
> 
> Nit: Should have two spaces after the dot, per GNU coding style. 
> I'd suggest
> to run the contrib/check_GNU_style.py script on your patches.
> Do you mean "star" by "dot", i.e. "/*" should be "/* "?

No, I was referring to the following paragraph from
https://www.gnu.org/prep/standards/standards.html :
   "Please put two spaces after the end of a sentence in your comments, ..."

To fix, simply add a second space after the dot, e.g.:
  -   Like DF_LR, but include tracking subreg liveness. Currently used to 
provide
  +   Like DF_LR, but include tracking subreg liveness.  Currently used to 
provide


For reference, here is the output from the style checker:
  $ git show | ./contrib/check_GNU_style.py -
  === ERROR type #4: dot, space, space, new sentence (24 error(s)) ===
  ...
  gcc/df-problems.cc:1350:52:   Like DF_LR, but include tracking subreg 
liveness.█Currently used to provide

> 
> 
> These names seem a bit too short for global variables. Perhaps tuck
> them in a namespace?
> 
> Also, since these must remain empty, shouldn't they be declared as const?
> 
> namespace df {
>  const bitmap_head empty_bitmap;
>  const subregs_live empty_live;
> }
> 
> 
> 
> May be better if "namespace df" contains all DF related code? as a minor 
> modification, I add a prefix "df_" to the variables.
> Meanwhile, const seems inapropriate here, since it's returned as normal 
> pointer rather than const pointer in some funtions, 
> 
> change to const would break this return value type check, and a const_cast 
> would make the const meanlingless.
> 
> 
> more details see in the patch

Thanks for considering my suggestion.

Regards,
Dimitar
> 
> 
> regards
> Shuo
> 
> 
> 

[COMMITTED 7/9] pru: Use HOST_WIDE_INT_1U macro

[Dimitar Dimitrov]

Use the HOST_WIDE_INT_1U macro instead of literal 1 when constructing
constants for RTL.

gcc/ChangeLog:

* config/pru/pru.md (lshrdi3): Use HOST_WIDE_INT_1U macro.
(ashldi3): Ditto.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.md | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 2ceea2e7b1c..db7a5af6875 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -870,7 +870,8 @@ (define_expand "lshrdi3"
   JUMP_LABEL (j) = skip_hiset_label;
   LABEL_NUSES (skip_hiset_label)++;
 
-  emit_insn (gen_iorsi3 (dst_lo, dst_lo, GEN_INT (1 << 31)));
+  const HOST_WIDE_INT bit31_mask = HOST_WIDE_INT_1U << 31;
+  emit_insn (gen_iorsi3 (dst_lo, dst_lo, GEN_INT (bit31_mask)));
   emit_label (skip_hiset_label);
   emit_insn (gen_rtx_SET (dst_hi,
  gen_rtx_LSHIFTRT (SImode, src_hi, const1_rtx)));
@@ -959,7 +960,8 @@ (define_expand "ashldi3"
   JUMP_LABEL (j) = skip_hiset_label;
   LABEL_NUSES (skip_hiset_label)++;
 
-  emit_insn (gen_iorsi3 (dst_hi, dst_hi, GEN_INT (1 << 0)));
+  const HOST_WIDE_INT bit0_mask = HOST_WIDE_INT_1U << 0;
+  emit_insn (gen_iorsi3 (dst_hi, dst_hi, GEN_INT (bit0_mask)));
   emit_label (skip_hiset_label);
   emit_insn (gen_rtx_SET (dst_lo,
  gen_rtx_ASHIFT (SImode, src_lo, const1_rtx)));
-- 
2.45.0

[COMMITTED 9/9] pru: New validation pass for minrt

[Dimitar Dimitrov]

Add a new pru-specific pass to validate that the assumptions for the
minimal C runtime are not violated by the user program.

gcc/ChangeLog:

* config/pru/pru-passes.cc (class pass_pru_minrt_check): New
pass.
(pass_pru_minrt_check::execute): New method.
(make_pru_minrt_check): New function.
* config/pru/pru-passes.def (INSERT_PASS_AFTER): Register the
minrt check pass.
* config/pru/pru-protos.h (make_pru_minrt_check): Add
declaration.

gcc/testsuite/ChangeLog:

* g++.target/pru/minrt-1.cc: New test.
* g++.target/pru/minrt-2.cc: New test.
* g++.target/pru/minrt-3.cc: New test.
* g++.target/pru/pru.exp: New test.
* gcc.target/pru/minrt-1.c: New test.
* gcc.target/pru/minrt-2.c: New test.
* gcc.target/pru/minrt-3.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru-passes.cc| 70 +
 gcc/config/pru/pru-passes.def   |  5 ++
 gcc/config/pru/pru-protos.h |  1 +
 gcc/testsuite/g++.target/pru/minrt-1.cc | 10 
 gcc/testsuite/g++.target/pru/minrt-2.cc | 10 
 gcc/testsuite/g++.target/pru/minrt-3.cc |  9 
 gcc/testsuite/g++.target/pru/pru.exp| 34 
 gcc/testsuite/gcc.target/pru/minrt-1.c  | 10 
 gcc/testsuite/gcc.target/pru/minrt-2.c  | 10 
 gcc/testsuite/gcc.target/pru/minrt-3.c  |  9 
 10 files changed, 168 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/pru/minrt-1.cc
 create mode 100644 gcc/testsuite/g++.target/pru/minrt-2.cc
 create mode 100644 gcc/testsuite/g++.target/pru/minrt-3.cc
 create mode 100644 gcc/testsuite/g++.target/pru/pru.exp
 create mode 100644 gcc/testsuite/gcc.target/pru/minrt-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/minrt-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/minrt-3.c

diff --git a/gcc/config/pru/pru-passes.cc b/gcc/config/pru/pru-passes.cc
index d2c6ae8737d..5e7e22df65d 100644
--- a/gcc/config/pru/pru-passes.cc
+++ b/gcc/config/pru/pru-passes.cc
@@ -214,3 +214,73 @@ make_pru_tiabi_check (gcc::context *ctxt)
 {
   return new pass_pru_tiabi_check (ctxt);
 }
+
+namespace {
+
+/* Scan the tree to ensure that the compiled code by GCC
+   conforms to the non-standard minimal runtime.  */
+const pass_data pass_data_pru_minrt_check =
+{
+  GIMPLE_PASS, /* type */
+  "*pru_minrt_check", /* name */
+  OPTGROUP_NONE, /* optinfo_flags */
+  TV_NONE, /* tv_id */
+  PROP_gimple_any, /* properties_required */
+  0, /* properties_provided */
+  0, /* properties_destroyed */
+  0, /* todo_flags_start */
+  0, /* todo_flags_finish */
+};
+
+/* Implementation class for the minrt compliance-check pass.  */
+class pass_pru_minrt_check : public gimple_opt_pass
+{
+public:
+  pass_pru_minrt_check (gcc::context *ctxt)
+: gimple_opt_pass (pass_data_pru_minrt_check, ctxt)
+  {}
+
+  /* opt_pass methods: */
+  virtual unsigned int execute (function *);
+
+  virtual bool gate (function *)
+  {
+return TARGET_MINRT;
+  }
+
+}; // class pass_pru_minrt_check
+
+/* Pass implementation.  */
+unsigned
+pass_pru_minrt_check::execute (function *fun)
+{
+  const_tree fntype = TREE_TYPE (fun->decl);
+
+  if (id_equal (DECL_NAME (fun->decl), "main"))
+{
+  /* Argument list always ends with VOID_TYPE, so subtract one
+to get the number of function arguments.  */
+  const unsigned num_args = list_length (TYPE_ARG_TYPES (fntype)) - 1;
+
+  if (num_args != 0)
+   error_at (DECL_SOURCE_LOCATION (fun->decl), "function % "
+ "must have no arguments when using the "
+ "%<-minrt%> option");
+
+  /* The required CFG analysis to detect when a functions would never
+return is available only with -O1 and higher.  */
+  if (optimize >= 1 && !TREE_THIS_VOLATILE (fun->decl))
+   error_at (DECL_SOURCE_LOCATION (fun->decl), "function % "
+ "must never return when using the "
+ "%<-minrt%> option");
+}
+  return 0;
+}
+
+} // anon namespace
+
+gimple_opt_pass *
+make_pru_minrt_check (gcc::context *ctxt)
+{
+  return new pass_pru_minrt_check (ctxt);
+}
diff --git a/gcc/config/pru/pru-passes.def b/gcc/config/pru/pru-passes.def
index cdef089bd82..3eee313ac67 100644
--- a/gcc/config/pru/pru-passes.def
+++ b/gcc/config/pru/pru-passes.def
@@ -22,3 +22,8 @@
If GCC cannot output a conforming code, then an error is raised.  */
 
 INSERT_PASS_AFTER (pass_warn_unused_result, 1, pru_tiabi_check);
+
+/* If -minrt option is used, then this pass would validate
+   that the compiled code by GCC is compatible with the minimal
+   C runtime.  */
+INSERT_PASS_AFTER (pass_warn_function_noreturn, 1, pru_minrt_check);
diff --git a/gcc/config/pru/pru-protos.h b/gcc/config/pru/pru-protos.h
index 74426bb86ea..3baf605d915 100644
--- a/gcc/config/pru/pru-protos.h
++

[COMMITTED 6/9] pru: Drop usage of ATTRIBUTE_UNUSED

[Dimitar Dimitrov]

Remove usage of ATTRIBUTE_UNUSED.  Instead remove the argument's name,
which in C++ means that the argument would not be used.

gcc/ChangeLog:

* config/pru/pru-passes.cc: Drop ATTRIBUTE_UNUSED and remove
argument's name.
* config/pru/pru-pragma.cc (pru_pragma_ctable_entry): Ditto.
* config/pru/pru.cc (pru_function_profiler): Ditto.
(pru_can_eliminate): Ditto.
(pru_rtx_costs): Ditto.
(pru_insert_attributes): Ditto.
(pru_function_value): Ditto.
(pru_libcall_value): Ditto.
(pru_return_in_memory): Ditto.
(pru_builtin_decl): Ditto.
(pru_expand_builtin): Ditto.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru-passes.cc |  2 +-
 gcc/config/pru/pru-pragma.cc |  2 +-
 gcc/config/pru/pru.cc| 24 +---
 3 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/gcc/config/pru/pru-passes.cc b/gcc/config/pru/pru-passes.cc
index fdef068f6a3..a76be8fd528 100644
--- a/gcc/config/pru/pru-passes.cc
+++ b/gcc/config/pru/pru-passes.cc
@@ -68,7 +68,7 @@ public:
   /* opt_pass methods: */
   virtual unsigned int execute (function *);
 
-  virtual bool gate (function *fun ATTRIBUTE_UNUSED)
+  virtual bool gate (function *)
   {
 return pru_current_abi == PRU_ABI_TI;
   }
diff --git a/gcc/config/pru/pru-pragma.cc b/gcc/config/pru/pru-pragma.cc
index f948411aef7..73bb4b60e51 100644
--- a/gcc/config/pru/pru-pragma.cc
+++ b/gcc/config/pru/pru-pragma.cc
@@ -40,7 +40,7 @@
 
WARNING: Only immediate constant addresses are currently supported.  */
 static void
-pru_pragma_ctable_entry (cpp_reader * reader ATTRIBUTE_UNUSED)
+pru_pragma_ctable_entry (cpp_reader *)
 {
   tree ctable_index, base_addr;
   enum cpp_ttype type;
diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc
index e5ec398d2db..49d35c60d12 100644
--- a/gcc/config/pru/pru.cc
+++ b/gcc/config/pru/pru.cc
@@ -405,7 +405,7 @@ pru_get_return_address (int count)
 
 /* Implement FUNCTION_PROFILER macro.  */
 void
-pru_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
+pru_function_profiler (FILE *file, int)
 {
   fprintf (file, "\tmov\tr1, ra\n");
   fprintf (file, "\tcall\t_mcount\n");
@@ -467,7 +467,7 @@ prologue_saved_reg_p (int regno)
 
 /* Implement TARGET_CAN_ELIMINATE.  */
 static bool
-pru_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
+pru_can_eliminate (const int, const int to)
 {
   if (to == STACK_POINTER_REGNUM)
 return !frame_pointer_needed;
@@ -637,9 +637,7 @@ pru_option_override (void)
cost has been computed, and false if subexpressions should be
scanned.  In either case, *TOTAL contains the cost result.  */
 static bool
-pru_rtx_costs (rtx x, machine_mode mode,
-  int outer_code, int opno ATTRIBUTE_UNUSED,
-  int *total, bool speed ATTRIBUTE_UNUSED)
+pru_rtx_costs (rtx x, machine_mode mode, int outer_code, int, int *total, bool)
 {
   const int code = GET_CODE (x);
 
@@ -2174,7 +2172,7 @@ pru_nongeneric_pointer_addrspace (tree typ)
during the "mov" pattern expansion.  */
 
 static void
-pru_insert_attributes (tree node, tree *attributes ATTRIBUTE_UNUSED)
+pru_insert_attributes (tree node, tree *)
 {
 
   /* Validate __regio_symbol variable declarations.  */
@@ -2399,15 +2397,14 @@ pru_function_arg_advance (cumulative_args_t cum_v,
 
 /* Implement TARGET_FUNCTION_VALUE.  */
 static rtx
-pru_function_value (const_tree ret_type, const_tree fn ATTRIBUTE_UNUSED,
- bool outgoing ATTRIBUTE_UNUSED)
+pru_function_value (const_tree ret_type, const_tree, bool)
 {
   return gen_rtx_REG (TYPE_MODE (ret_type), FIRST_RETVAL_REGNUM);
 }
 
 /* Implement TARGET_LIBCALL_VALUE.  */
 static rtx
-pru_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
+pru_libcall_value (machine_mode mode, const_rtx)
 {
   return gen_rtx_REG (mode, FIRST_RETVAL_REGNUM);
 }
@@ -2421,7 +2418,7 @@ pru_function_value_regno_p (const unsigned int regno)
 
 /* Implement TARGET_RETURN_IN_MEMORY.  */
 bool
-pru_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
+pru_return_in_memory (const_tree type, const_tree)
 {
   bool in_memory = (!pru_arg_in_reg_bysize (int_size_in_bytes (type))
|| int_size_in_bytes (type) == -1);
@@ -2989,7 +2986,7 @@ pru_init_builtins (void)
 /* Implement TARGET_BUILTIN_DECL.  */
 
 static tree
-pru_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
+pru_builtin_decl (unsigned code, bool)
 {
   switch (code)
 {
@@ -3068,10 +3065,7 @@ pru_expand_delay_cycles (rtx arg)
IGNORE is nonzero if the value is to be ignored.  */
 
 static rtx
-pru_expand_builtin (tree exp, rtx target,
-   rtx subtarget ATTRIBUTE_UNUSED,
-   machine_mode mode,
-   int ignore ATTRIBUTE_UNUSED)
+pru_expand_builtin (tree exp, rtx target, rtx, machine_mode mode, int)
 {
   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (e

[COMMITTED 4/9] pru: Add pattern variants for zero extending destination

[Dimitar Dimitrov]

The higher bits in the result of some ALU operations are inherently
always zero when all input operands are smaller than 32-bits.

Add pattern variants to match when the resulting value is zero
extended, so that all operations can be effectively executed in a
single instruction.  For PRU it simply means to use a wider register for
destination.

ALU operations which cannot be presented as zero-extending their
destination are addition, subtraction and logical shift left.  The PRU
ALU performs all operations in 32-bit mode, so the carry-out and
shifted-out bits would violate the assumption that ALU operation was
performed in 16-bit or 8-bit mode, and result was zero-extended.

gcc/ChangeLog:

* config/pru/alu-zext.md (_noz0): New subst attribute.
(_impl): Allow zero-extending the destination.
(): Remove unified pattern
(ashl_impl): New distinct pattern.
(lshr_impl): Ditto.
(alu3_zext_op0_subst): New subst iterator to zero-extend the
destination register.

gcc/testsuite/ChangeLog:

* gcc.target/pru/extzv-1.c: Update to mark the new more
efficient generated code sequence.
* gcc.target/pru/extzv-2.c: Ditto.
* gcc.target/pru/extzv-3.c: Ditto.
* gcc.target/pru/zero_extend-op0.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/alu-zext.md| 38 ---
 gcc/testsuite/gcc.target/pru/extzv-1.c|  2 +-
 gcc/testsuite/gcc.target/pru/extzv-2.c|  2 +-
 gcc/testsuite/gcc.target/pru/extzv-3.c|  2 +-
 .../gcc.target/pru/zero_extend-op0.c  | 28 ++
 5 files changed, 63 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/zero_extend-op0.c

diff --git a/gcc/config/pru/alu-zext.md b/gcc/config/pru/alu-zext.md
index 04378db4774..c88eaf0ab44 100644
--- a/gcc/config/pru/alu-zext.md
+++ b/gcc/config/pru/alu-zext.md
@@ -33,6 +33,7 @@
 
 (define_subst_attr "alu2_zext" "alu2_zext_subst" "_z" "_noz")
 
+(define_subst_attr "alu3_zext_op0" "alu3_zext_op0_subst" "_z0" "_noz0")
 (define_subst_attr "alu3_zext_op1" "alu3_zext_op1_subst" "_z1" "_noz1")
 (define_subst_attr "alu3_zext_op2" "alu3_zext_op2_subst" "_z2" "_noz2")
 (define_subst_attr "alu3_zext" "alu3_zext_subst" "_z" "_noz")
@@ -44,6 +45,7 @@ (define_subst_attr "lmbd_zext" "lmbd_zext_subst" "_z" 
 "_noz")
 (define_subst_attr "bitalu_zext"   "bitalu_zext_subst"   "_z" "_noz")
 
 (define_code_iterator ALUOP3 [plus minus and ior xor umin umax ashift 
lshiftrt])
+(define_code_iterator ALUOP3_ZEXT0 [and ior xor umin umax lshiftrt])
 (define_code_iterator ALUOP2 [neg not])
 
 ;; Arithmetic Operations
@@ -130,8 +132,9 @@ (define_insn "setbit__"
   "set\\t%0, %1, %T2"
   [(set_attr "type" "alu")])
 
-; Regular ALU ops
-(define_insn 
"_impl_"
+; Regular ALU ops.  For all of them it is safe to present the result as
+; zero-extended, because there is no carry or shifted-out bits.
+(define_insn 
"_impl_"
   [(set (match_operand:EQD 0 "register_operand" "=r")
(LOGICAL:EQD
  (zero_extend:EQD
@@ -142,14 +145,25 @@ (define_insn 
"_impl_\\t%0, %1, %u2"
   [(set_attr "type" "alu")])
 
-; Shift ALU ops
-(define_insn 
"_impl_"
+; Shift left ALU op.  Cannot present the result as zero-extended because
+; of the shifted-out bits.
+(define_insn 
"ashl_impl_"
   [(set (match_operand:EQD 0 "register_operand" "=r")
-   (SHIFT:EQD
+   (ashift:EQD
 (zero_extend:EQD (match_operand:EQS0 1 "register_operand" "r"))
 (zero_extend:EQD (match_operand:EQS1 2 "shift_operand" "rL"]
   ""
-  "\\t%0, %1, %2"
+  "lsl\\t%0, %1, %2"
+  [(set_attr "type" "alu")])
+
+; Shift right ALU op.  The result can be presented as zero-extended.
+(define_insn 
"lshr_impl_"
+  [(set (match_operand:EQD 0 "register_operand" "=r")
+   (lshiftrt:EQD
+(zero_extend:EQD (match_operand:EQS0 1 "register_operand" "r"))
+(zero_extend:EQD (match_operand:EQS1 2 "shift_operand" "rL"]
+  ""
+  "lsr\\t%0, %1, %2"
   [(set_attr "type" "alu")])
 
 ;; Substitutions
@@ -197,6 +211,18 @@ (define_subst "alu3_zext_op2_subst"
(ALUOP3:EQD (zero_extend:EQD (match_dup 1))
(match_dup 2)))])
 
+;; Some ALU operations with zero-extended inputs are
+;; equivalent to doing the same ALU operation in the
+;; smaller mo

[COMMITTED 5/9] pru: Skip register save if function will not return

[Dimitar Dimitrov]

There is no need to store callee-saved registers in prologue if the
function would never return.  Size optimization is paramount for the
microcontroller-class PRU.

Some backends save some registers for noreturn functions.  But for PRU
debuggability is a less concern because GDB has not been ported yet
for PRU.

gcc/ChangeLog:

* config/pru/pru.cc (prologue_saved_reg_p): Skip saving
if function will not return.

gcc/testsuite/ChangeLog:

* gcc.target/pru/noreturn-prologue-1.c: New test.
* gcc.target/pru/noreturn-prologue-2.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.cc  |  4 
 gcc/testsuite/gcc.target/pru/noreturn-prologue-1.c | 10 ++
 gcc/testsuite/gcc.target/pru/noreturn-prologue-2.c | 11 +++
 3 files changed, 25 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/pru/noreturn-prologue-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/noreturn-prologue-2.c

diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc
index a76451f4223..e5ec398d2db 100644
--- a/gcc/config/pru/pru.cc
+++ b/gcc/config/pru/pru.cc
@@ -443,6 +443,10 @@ prologue_saved_reg_p (int regno)
 {
   gcc_assert (GP_REG_P (regno));
 
+  /* Do not save the register if function will not return.  */
+  if (TREE_THIS_VOLATILE (current_function_decl))
+return false;
+
   if (df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno))
 return true;
 
diff --git a/gcc/testsuite/gcc.target/pru/noreturn-prologue-1.c 
b/gcc/testsuite/gcc.target/pru/noreturn-prologue-1.c
new file mode 100644
index 000..af69e52d925
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/noreturn-prologue-1.c
@@ -0,0 +1,10 @@
+/* Ensure prologues are not generated for noreturn functions.  */
+/* { dg-do assemble } */
+/* { dg-options "-Os" } */
+/* { dg-final { object-size text == 0 } } */
+
+void test(void)
+{
+  asm volatile ("# \n\t" : : : "r5", "r10");
+  __builtin_unreachable ();
+}
diff --git a/gcc/testsuite/gcc.target/pru/noreturn-prologue-2.c 
b/gcc/testsuite/gcc.target/pru/noreturn-prologue-2.c
new file mode 100644
index 000..8d12a9c462b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/noreturn-prologue-2.c
@@ -0,0 +1,11 @@
+/* Ensure prologues are not generated for noreturn functions.  */
+/* { dg-do assemble } */
+/* { dg-options "-Os" } */
+/* { dg-final { object-size text == 4 } } */
+
+void test(void)
+{
+  asm volatile ("# \n\t" : : : "r0", "r9");
+  for (;;)
+;
+}
-- 
2.45.0

[COMMITTED 8/9] pru: Refactor to use passes definition file

[Dimitar Dimitrov]

Switch to using a passes definition file instead of explicitly
registering the PRU-specific passes in pru.cc.  This would make it
cleaner to add new PRU-specific passes.

There are no functional changes.

gcc/ChangeLog:

* config/pru/pru-passes.cc (class pass_tiabi_check): Rename to
add "pru_" prefix.
(class pass_pru_tiabi_check): Ditto.
(pass_tiabi_check::execute): Ditto.
(pass_pru_tiabi_check::execute): Ditto.
(make_pru_tiabi_check): Ditto.
(pru_register_abicheck_pass): Remove.
* config/pru/pru-protos.h (pru_register_abicheck_pass): Remove.
(make_pru_tiabi_check): Add declaration.
* config/pru/pru.cc (pru_option_override): Remove explicit pass
registration.
* config/pru/t-pru: Register PRU passes definition file.
* config/pru/pru-passes.def: New file.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru-passes.cc  | 30 +-
 gcc/config/pru/pru-passes.def | 24 
 gcc/config/pru/pru-protos.h   |  2 +-
 gcc/config/pru/pru.cc |  5 -
 gcc/config/pru/t-pru  |  2 ++
 5 files changed, 36 insertions(+), 27 deletions(-)
 create mode 100644 gcc/config/pru/pru-passes.def

diff --git a/gcc/config/pru/pru-passes.cc b/gcc/config/pru/pru-passes.cc
index a76be8fd528..d2c6ae8737d 100644
--- a/gcc/config/pru/pru-passes.cc
+++ b/gcc/config/pru/pru-passes.cc
@@ -44,10 +44,10 @@ namespace {
 /* Scan the tree to ensure that the compiled code by GCC
conforms to the TI ABI specification.  If GCC cannot
output a conforming code, raise an error.  */
-const pass_data pass_data_tiabi_check =
+const pass_data pass_data_pru_tiabi_check =
 {
   GIMPLE_PASS, /* type */
-  "*tiabi_check", /* name */
+  "*pru_tiabi_check", /* name */
   OPTGROUP_NONE, /* optinfo_flags */
   TV_NONE, /* tv_id */
   PROP_gimple_any, /* properties_required */
@@ -58,11 +58,11 @@ const pass_data pass_data_tiabi_check =
 };
 
 /* Implementation class for the TI ABI compliance-check pass.  */
-class pass_tiabi_check : public gimple_opt_pass
+class pass_pru_tiabi_check : public gimple_opt_pass
 {
 public:
-  pass_tiabi_check (gcc::context *ctxt)
-: gimple_opt_pass (pass_data_tiabi_check, ctxt)
+  pass_pru_tiabi_check (gcc::context *ctxt)
+: gimple_opt_pass (pass_data_pru_tiabi_check, ctxt)
   {}
 
   /* opt_pass methods: */
@@ -73,7 +73,7 @@ public:
 return pru_current_abi == PRU_ABI_TI;
   }
 
-}; // class pass_tiabi_check
+}; // class pass_pru_tiabi_check
 
 /* Return 1 if type TYPE is a pointer to function type or a
structure having a pointer to function type as one of its fields.
@@ -187,7 +187,7 @@ check_op_callback (tree *tp, int *walk_subtrees, void *data)
 
 /* Pass implementation.  */
 unsigned
-pass_tiabi_check::execute (function *fun)
+pass_pru_tiabi_check::execute (function *fun)
 {
   struct walk_stmt_info wi;
   const_tree fntype = TREE_TYPE (fun->decl);
@@ -210,19 +210,7 @@ pass_tiabi_check::execute (function *fun)
 } // anon namespace
 
 gimple_opt_pass *
-make_pass_tiabi_check (gcc::context *ctxt)
+make_pru_tiabi_check (gcc::context *ctxt)
 {
-  return new pass_tiabi_check (ctxt);
-}
-
-/* Register as early as possible.  */
-void
-pru_register_abicheck_pass (void)
-{
-  opt_pass *tiabi_check = make_pass_tiabi_check (g);
-  struct register_pass_info tiabi_check_info
-= { tiabi_check, "*warn_unused_result",
-   1, PASS_POS_INSERT_AFTER
-  };
-  register_pass (_check_info);
+  return new pass_pru_tiabi_check (ctxt);
 }
diff --git a/gcc/config/pru/pru-passes.def b/gcc/config/pru/pru-passes.def
new file mode 100644
index 000..cdef089bd82
--- /dev/null
+++ b/gcc/config/pru/pru-passes.def
@@ -0,0 +1,24 @@
+/* Description of target passes for PRU.
+   Copyright (C) 2024 Free Software Foundation, Inc.  */
+
+/* This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3, or (at your option) any later
+   version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* If strict TI ABI conformance is requested, then this pass would validate
+   that the compiled code by GCC conforms to the TI ABI specification.
+   If GCC cannot output a conforming code, then an error is raised.  */
+
+INSERT_PASS_AFTER (pass_warn_unused_result, 1, pru_tiabi_check);
diff --git a/gcc/config/pru/pru-protos.h b/gcc/config/pru/pru-protos.h
index e8670ad4326..74426bb86ea 100644
--- a/gcc/config/p

[COMMITTED 3/9] pru: Optimize the extzv and insv patterns

[Dimitar Dimitrov]

Optimize the generated code for the bit-field extract and insert
patterns:
  - Use bit-set and bit-clear instructions for 1-bit fields.
  - Expand to SImode operations instead of relying on the default
expansion to word (QI) mode.

gcc/ChangeLog:

* config/pru/pru.md (extzv): Make it an expand pattern,
handle efficiently zero-positioned bit-fields.
(insv): New expand pattern.

gcc/testsuite/ChangeLog:

* gcc.target/pru/ashiftrt.c: Minor update due to new (but
equivalent) generated code sequence.
* gcc.target/pru/extzv-1.c: New test.
* gcc.target/pru/extzv-2.c: New test.
* gcc.target/pru/extzv-3.c: New test.
* gcc.target/pru/insv-1.c: New test.
* gcc.target/pru/insv-2.c: New test.
* gcc.target/pru/insv-3.c: New test.
* gcc.target/pru/insv-4.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.md   | 104 ++--
 gcc/testsuite/gcc.target/pru/ashiftrt.c |   2 +-
 gcc/testsuite/gcc.target/pru/extzv-1.c  |  14 
 gcc/testsuite/gcc.target/pru/extzv-2.c  |  15 
 gcc/testsuite/gcc.target/pru/extzv-3.c  |  13 +++
 gcc/testsuite/gcc.target/pru/insv-1.c   |  14 
 gcc/testsuite/gcc.target/pru/insv-2.c   |  14 
 gcc/testsuite/gcc.target/pru/insv-3.c   |  14 
 gcc/testsuite/gcc.target/pru/insv-4.c   |  14 
 9 files changed, 194 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/extzv-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/extzv-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/extzv-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-4.c

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 0123952aa9e..2ceea2e7b1c 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -486,22 +486,108 @@ (define_expand "extend2"
 })
 
 ;; Bit extraction
-;; We define it solely to allow combine to choose SImode
+;; One reason to define it is to allow combine to choose SImode
 ;; for word mode when trying to match our cbranch_qbbx_* insn.
 ;;
 ;; Check how combine.cc:make_extraction() uses
 ;; get_best_reg_extraction_insn() to select the op size.
-(define_insn "extzv"
-  [(set (match_operand:QISI 0 "register_operand"   "=r")
+(define_expand "extzv"
+  [(set (match_operand:QISI 0 "register_operand")
  (zero_extract:QISI
-  (match_operand:QISI 1 "register_operand" "r")
-  (match_operand:QISI 2 "const_int_operand""i")
-  (match_operand:QISI 3 "const_int_operand""i")))]
+  (match_operand:QISI 1 "register_operand")
+  (match_operand:QISI 2 "const_int_operand")
+  (match_operand:QISI 3 "const_int_operand")))]
   ""
-  "lsl\\t%0, %1, (%S0 * 8 - %2 - %3)\;lsr\\t%0, %0, (%S0 * 8 - %2)"
-  [(set_attr "type" "complex")
-   (set_attr "length" "8")])
+{
+  const int nbits = INTVAL (operands[2]);
+  const int bitpos = INTVAL (operands[3]);
+  const int trailing_bits = GET_MODE_BITSIZE (mode) - nbits - bitpos;
+
+  if (bitpos == 0 && nbits <= 7)
+{
+  emit_insn (gen_and3 (operands[0],
+operands[1],
+gen_int_mode ((HOST_WIDE_INT_1U << nbits) - 1,
+  mode)));
+  DONE;
+}
+
+  rtx src = operands[1];
+  if (trailing_bits != 0)
+{
+  emit_insn (gen_ashl3 (operands[0],
+ operands[1],
+ GEN_INT (trailing_bits)));
+  src = operands[0];
+}
+  emit_insn (gen_lshr3 (operands[0],
+ src,
+ GEN_INT (trailing_bits + bitpos)));
+  DONE;
+})
+
+;; Bit-field insert.
+(define_expand "insv"
+  [(set (zero_extract:QISI
+ (match_operand:QISI 0 "register_operand")
+ (match_operand:QISI 1 "const_int_operand")
+ (match_operand:QISI 2 "const_int_operand"))
+   (match_operand:QISI 3 "reg_or_ubyte_operand"))]
+  ""
+{
+  const int nbits = INTVAL (operands[1]);
+  const int bitpos = INTVAL (operands[2]);
 
+  if (nbits == 1)
+{
+  rtx j;
+  rtx src = gen_reg_rtx (mode);
+  rtx dst = operands[0];
+
+  emit_move_insn (src, operands[3]);
+
+  emit_insn (gen_and3 (dst,
+dst,
+gen_int_mode (~(HOST_WIDE_INT_1U << bitpos),
+  mode)));
+
+  rtx_code_label *skip_set_label = gen_label_rtx ();
+

[COMMITTED 2/9] pru: Implement zero fill for 64-bit registers

[Dimitar Dimitrov]

Loading a constant zero in a 64-bit register now takes one instead of
two instructions.

gcc/ChangeLog:

* config/pru/pru.md: New pattern alternative for zero-filling
64-bit registers.

gcc/testsuite/ChangeLog:

* gcc.target/pru/mov-0.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.md| 18 ++
 gcc/testsuite/gcc.target/pru/mov-0.c | 19 +++
 2 files changed, 29 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/mov-0.c

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 8393d8f9607..0123952aa9e 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -248,8 +248,8 @@ (define_insn "prumov"
 ; Forcing DI reg alignment (akin to microblaze's HARD_REGNO_MODE_OK)
 ; does not seem efficient, and will violate TI ABI.
 (define_insn "mov"
-  [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r")
-   (match_operand:MOV64 1 "general_operand"  "r,m,Um,r,T,J,nF"))]
+  [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r,r")
+   (match_operand:MOV64 1 "general_operand"  "r,m,Z,Um,r,T,J,nF"))]
   ""
 {
   switch (which_alternative)
@@ -259,8 +259,10 @@ (define_insn "mov"
 case 1:
   return "lb%B1o\\t%b0, %1, %S1";
 case 2:
-  return "fill\\t%F0, 8";
+  return "zero\\t%F0, 8";
 case 3:
+  return "fill\\t%F0, 8";
+case 4:
   /* careful with overlapping source and destination regs.  */
   gcc_assert (GP_REG_P (REGNO (operands[0])));
   gcc_assert (GP_REG_P (REGNO (operands[1])));
@@ -268,18 +270,18 @@ (define_insn "mov"
return "mov\\t%N0, %N1\;mov\\t%F0, %F1";
   else
return "mov\\t%F0, %F1\;mov\\t%N0, %N1";
-case 4:
-  return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
 case 5:
-  return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+  return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
 case 6:
+  return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+case 7:
   return "ldi32\\t%F0, %w1\;ldi32\\t%N0, %W1";
 default:
   gcc_unreachable ();
   }
 }
-  [(set_attr "type" "st,ld,alu,alu,alu,alu,alu")
-   (set_attr "length" "4,4,4,8,8,8,16")])
+  [(set_attr "type" "st,ld,alu,alu,alu,alu,alu,alu")
+   (set_attr "length" "4,4,4,4,8,8,8,16")])
 
 ;
 ; load_multiple pattern(s).
diff --git a/gcc/testsuite/gcc.target/pru/mov-0.c 
b/gcc/testsuite/gcc.target/pru/mov-0.c
new file mode 100644
index 000..0190be36fa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/mov-0.c
@@ -0,0 +1,19 @@
+/* Loading a register with constant 0 integer value.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int
+test_set_0_si (void)
+{
+  /* Since zero-extension is free, "zero" fill is not implemented for SI.  */
+  /* { dg-final { scan-assembler "ldi\\tr14(.b0)?, 0" } } */
+  return 0;
+}
+
+long long
+test_set_0_di (void)
+{
+  /* { dg-final { scan-assembler "zero\\tr14(.b0)?, 8" } } */
+  return 0;
+}
-- 
2.45.0

[COMMITTED 0/9] Small cleanups and improvements for PRU backend

[Dimitar Dimitrov]

This patch set includes small cleanups and code generation improvements
I implemented during stages 3 and 4.

All patches have been regression-tested individually for pru-unknown-elf
while being developed.  And the entire set was tested again on GCC 15
mainline.

Dimitar Dimitrov (9):
  pru: Implement TARGET_ADDRESS_COST
  pru: Implement zero fill for 64-bit registers
  pru: Optimize the extzv and insv patterns
  pru: Add pattern variants for zero extending destination
  pru: Skip register save if function will not return
  pru: Drop usage of ATTRIBUTE_UNUSED
  pru: Use HOST_WIDE_INT_1U macro
  pru: Refactor to use passes definition file
  pru: New validation pass for minrt

 gcc/config/pru/alu-zext.md|  38 +-
 gcc/config/pru/pru-passes.cc  |  96 ++---
 gcc/config/pru/pru-passes.def |  29 
 gcc/config/pru/pru-pragma.cc  |   2 +-
 gcc/config/pru/pru-protos.h   |   3 +-
 gcc/config/pru/pru.cc |  58 +---
 gcc/config/pru/pru.md | 128 +++---
 gcc/config/pru/t-pru  |   2 +
 gcc/testsuite/g++.target/pru/minrt-1.cc   |  10 ++
 gcc/testsuite/g++.target/pru/minrt-2.cc   |  10 ++
 gcc/testsuite/g++.target/pru/minrt-3.cc   |   9 ++
 gcc/testsuite/g++.target/pru/pru.exp  |  34 +
 gcc/testsuite/gcc.target/pru/ashiftrt.c   |   2 +-
 gcc/testsuite/gcc.target/pru/extzv-1.c|  14 ++
 gcc/testsuite/gcc.target/pru/extzv-2.c|  15 ++
 gcc/testsuite/gcc.target/pru/extzv-3.c|  13 ++
 gcc/testsuite/gcc.target/pru/insv-1.c |  14 ++
 gcc/testsuite/gcc.target/pru/insv-2.c |  14 ++
 gcc/testsuite/gcc.target/pru/insv-3.c |  14 ++
 gcc/testsuite/gcc.target/pru/insv-4.c |  14 ++
 gcc/testsuite/gcc.target/pru/minrt-1.c|  10 ++
 gcc/testsuite/gcc.target/pru/minrt-2.c|  10 ++
 gcc/testsuite/gcc.target/pru/minrt-3.c|   9 ++
 gcc/testsuite/gcc.target/pru/mov-0.c  |  19 +++
 .../gcc.target/pru/noreturn-prologue-1.c  |  10 ++
 .../gcc.target/pru/noreturn-prologue-2.c  |  11 ++
 .../gcc.target/pru/zero_extend-op0.c  |  28 
 27 files changed, 549 insertions(+), 67 deletions(-)
 create mode 100644 gcc/config/pru/pru-passes.def
 create mode 100644 gcc/testsuite/g++.target/pru/minrt-1.cc
 create mode 100644 gcc/testsuite/g++.target/pru/minrt-2.cc
 create mode 100644 gcc/testsuite/g++.target/pru/minrt-3.cc
 create mode 100644 gcc/testsuite/g++.target/pru/pru.exp
 create mode 100644 gcc/testsuite/gcc.target/pru/extzv-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/extzv-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/extzv-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/insv-4.c
 create mode 100644 gcc/testsuite/gcc.target/pru/minrt-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/minrt-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/minrt-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/mov-0.c
 create mode 100644 gcc/testsuite/gcc.target/pru/noreturn-prologue-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/noreturn-prologue-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/zero_extend-op0.c

-- 
2.45.0

[COMMITTED 1/9] pru: Implement TARGET_ADDRESS_COST

[Dimitar Dimitrov]

Stop relying on the default fallback to TARGET_RTX_COST for PRU's
addressing costs.  Implement TARGET_ADDRESS_COST, in order to allow RTX
cost refactoring in the future without affecting the addressing costs.

No code generation changes are expected by this patch.  No changes were
detected when running embench-iot and building a few real-world firmware
examples.

gcc/ChangeLog:

* config/pru/pru.cc (pru_address_cost): Implement address cost
calculation.
(TARGET_ADDRESS_COST): Define for PRU.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.cc | 25 +
 1 file changed, 25 insertions(+)

diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc
index 270c536d4c7..a76451f4223 100644
--- a/gcc/config/pru/pru.cc
+++ b/gcc/config/pru/pru.cc
@@ -784,6 +784,28 @@ pru_rtx_costs (rtx x, machine_mode mode,
 }
 }
 
+/* Calculate the cost of an addressing mode that contains ADDR.
+   ADDR must be a valid address.  */
+
+static int
+pru_address_cost (rtx addr, machine_mode, addr_space_t as, bool)
+{
+  if (as != ADDR_SPACE_GENERIC)
+/* All currently implemented special address spaces for PRU
+   are much more efficient than generic memory I/O.  */
+return 0;
+  else if (ctable_addr_operand (addr, VOIDmode)
+  || (GET_CODE (addr) == PLUS
+  && ctable_base_operand (XEXP (addr, 1), VOIDmode)))
+/* Using CTABLE instructions reduces register pressure,
+   so give it precedence.  */
+return 1;
+  else
+/* Same two instructions (LBBO/SBBO) are used for any valid
+   addressing mode.  */
+return 2;
+}
+
 /* Insn costs on PRU are straightforward because:
  - Insns emit 0, 1 or more instructions.
  - All instructions are 32-bit length.
@@ -3208,6 +3230,9 @@ pru_unwind_word_mode (void)
 #undef TARGET_RTX_COSTS
 #define TARGET_RTX_COSTS pru_rtx_costs
 
+#undef TARGET_ADDRESS_COST
+#define TARGET_ADDRESS_COST pru_address_cost
+
 #undef TARGET_INSN_COST
 #define TARGET_INSN_COST pru_insn_cost
 
-- 
2.45.0

Re: [PATCH 2/4] df: Add DF_LIVE_SUBREG problem

[Dimitar Dimitrov]

On Wed, Apr 24, 2024 at 06:05:03PM +0800, Lehua Ding wrote:
> This patch add a new DF problem, named DF_LIVE_SUBREG. This problem
> is extended from the DF_LR problem and support track the subreg liveness
> of multireg pseudo if these pseudo satisfy the following conditions:
> 
>   1. the mode size greater than it's REGMODE_NATURAL_SIZE.
>   2. the reg is used in insns via subreg pattern.
> 
> The main methods are as follows:
> 
>   1. split bitmap in/out/def/use fileds to full_in/out/def/use and
>  partial_in/out/def/use. If a pseudo need to be tracked it's subreg
>  liveness, then it is recorded in partial_in/out/def/use fileds.
>  Meantimes, there are range_in/out/def/use fileds which records the live
>  range of the tracked pseudo.
>   2. in the df_live_subreg_finalize function, we move the tracked pseudo from
>  the partial_in/out/def/use to full_in/out/def/use if the pseudo's live
>  range is full.

Hi Lehua,

I'm not familiar with LRA, so my comments bellow could be totally off
point.  Please treat them as mild suggestions.

> 
> gcc/ChangeLog:
> 
>   * Makefile.in: Add subreg-live-range object file.
>   * df-problems.cc (struct df_live_subreg_problem_data): Private struct
>   for DF_LIVE_SUBREG problem.
>   (df_live_subreg_get_bb_info): getting bb regs in/out data.
>   (get_live_subreg_local_bb_info): getting bb regs use/def data.
>   (multireg_p): checking is the regno a pseudo multireg.
>   (need_track_subreg_p): checking is the regno need to be tracked.
>   (init_range): getting the range of subreg rtx.
>   (remove_subreg_range): removing use data for the reg/subreg rtx.
>   (add_subreg_range): adding def/use data for the reg/subreg rtx.
>   (df_live_subreg_free_bb_info): Free basic block df data.
>   (df_live_subreg_alloc): Allocate and init df data.
>   (df_live_subreg_reset): Reset the live in/out df data.
>   (df_live_subreg_bb_local_compute): Compute basic block df data.
>   (df_live_subreg_local_compute): Compute all basic blocks df data.
>   (df_live_subreg_init): Init the in/out df data.
>   (df_live_subreg_check_result): Assert the full and partial df data.
>   (df_live_subreg_confluence_0): Confluence function for infinite loops.
>   (df_live_subreg_confluence_n): Confluence function for normal edge.
>   (df_live_subreg_transfer_function): Transfer function.
>   (df_live_subreg_finalize): Finalize the all_in/all_out df data.
>   (df_live_subreg_free): Free the df data.
>   (df_live_subreg_top_dump): Dump top df data.
>   (df_live_subreg_bottom_dump): Dump bottom df data.
>   (df_live_subreg_add_problem): Add the DF_LIVE_SUBREG problem.
>   * df.h (enum df_problem_id): Add DF_LIVE_SUBREG.
>   (class subregs_live): Simple decalare.
>   (class df_live_subreg_local_bb_info): New class for full/partial def/use
>   df data.
>   (class df_live_subreg_bb_info): New class for full/partial in/out
>   df data.
>   (df_live_subreg): getting the df_live_subreg data.
>   (df_live_subreg_add_problem): Exported.
>   (df_live_subreg_finalize): Ditto.
>   (df_live_subreg_check_result): Ditto.
>   (multireg_p): Ditto.
>   (init_range): Ditto.
>   (add_subreg_range): Ditto.
>   (remove_subreg_range): Ditto.
>   (df_get_subreg_live_in): Accessor the all_in df data.
>   (df_get_subreg_live_out): Accessor the all_out df data.
>   (df_get_subreg_live_full_in): Accessor the full_in df data.
>   (df_get_subreg_live_full_out): Accessor the full_out df data.
>   (df_get_subreg_live_partial_in): Accessor the partial_in df data.
>   (df_get_subreg_live_partial_out): Accessor the partial_out df data.
>   (df_get_subreg_live_range_in): Accessor the range_in df data.
>   (df_get_subreg_live_range_out): Accessor the range_out df data.
>   * regs.h (get_nblocks): Get the blocks of mode.
>   * sbitmap.cc (bitmap_full_p): sbitmap predicator.
>   (bitmap_same_p): sbitmap predicator.
>   (test_full): test bitmap_full_p.
>   (test_same): test bitmap_same_p.
>   (sbitmap_cc_tests): Add test_full and test_same.
>   * sbitmap.h (bitmap_full_p): Exported.
>   (bitmap_same_p): Ditto.
>   * timevar.def (TV_DF_LIVE_SUBREG): add DF_LIVE_SUBREG timevar.
>   * subreg-live-range.cc: New file.
>   * subreg-live-range.h: New file.
> ---
>  gcc/Makefile.in  |   1 +
>  gcc/df-problems.cc   | 855 ++-
>  gcc/df.h | 155 +++
>  gcc/regs.h   |   5 +
>  gcc/sbitmap.cc   |  98 +
>  gcc/sbitmap.h|   2 +
>  gcc/subreg-live-range.cc |  53 +++
>  gcc/subreg-live-range.h  | 206 ++
>  gcc/timevar.def  |   1 +
>  9 files changed, 1375 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/subreg-live-range.cc
>  create mode 100644 gcc/subreg-live-range.h
> 
> diff --git 

[committed] pru: Document how -mmcu option uses MCU specs

[Dimitar Dimitrov]

The plan to maintain PRU hardware-specific specs in newlib tree has been
abandoned in favour of a new distinct GIT project.  Update the
documentation accordingly.

gcc/ChangeLog:

* doc/invoke.texi (-mmcu): Add information about MCU specs.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/doc/invoke.texi | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 69020245b25..d75b28484bb 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30106,8 +30106,14 @@ This is already the norm for most firmware projects.
 
 @opindex mmcu
 @item -mmcu=@var{mcu}
-Specify the PRU MCU variant to use.  Check Newlib for the exact list of
-supported MCUs.
+Specify the PRU hardware variant to use.  A correspondingly named
+spec file would be loaded, passing the memory region sizes to
+the linker and defining hardware-specific C macros.
+
+Newlib provides only the @code{sim} spec, intended for running
+regression tests using a simulator.  Specs for real hardware can be
+obtained by installing the
+@w{@uref{https://github.com/dinuxbg/gnuprumcu/,GnuPruMcu}} package.
 
 @opindex mno-relax
 @item -mno-relax
-- 
2.43.0

[committed] pru: Document that arguments are not passed to main with -minrt

[Dimitar Dimitrov]

The minimal runtime has been documented from the beginning to break some
standard features in order to reduce code size, while keeping
the features required by typical firmware programs.  Document one more
imposed restriction - the main() function must take no arguments.

gcc/ChangeLog:

* doc/invoke.texi (-minrt): Clarify that main
must take no arguments.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/doc/invoke.texi | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e18886e0ac7..69020245b25 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30091,11 +30091,18 @@ These command-line options are defined for PRU target:
 @table @gcctabopt
 @opindex minrt
 @item -minrt
-Link with a minimum runtime environment, with no support for static
-initializers and constructors.  Using this option can significantly reduce
-the size of the final ELF binary.  Beware that the compiler could still
-generate code with static initializers and constructors.  It is up to the
-programmer to ensure that the source program will not use those features.
+Link with a minimum runtime environment.  This can significantly reduce
+the size of the final ELF binary, but some standard C runtime features
+are removed.
+
+This option disables support for static initializers and constructors.
+Beware that the compiler could still generate code with static initializers
+and constructors.  It is up to the programmer to ensure that the source
+program will not use those features.
+
+The minimal startup code would not pass @code{argc} and @code{argv} arguments
+to @code{main}, so the latter must be declared as @code{int main (void)}.
+This is already the norm for most firmware projects.
 
 @opindex mmcu
 @item -mmcu=@var{mcu}
-- 
2.43.0

[PATCH v2] testsuite: Mark non-optimized variants as expensive

[Dimitar Dimitrov]

When not optimized for speed, the test for PR112344 takes several
seconds to execute on native x86_64, and 15 minutes on PRU target
simulator.  Thus mark those variants as expensive.  The -O2 variant
which originally triggered the PR is not expensive, hence it is
still run by default.

Ok for trunk?

PR middle-end/112344

gcc/testsuite/ChangeLog:

* gcc.dg/torture/pr112344.c: Run non-optimized variants only
if expensive tests are allowed.

Signed-off-by: Dimitar Dimitrov 
---
Changes since V1:
  - Mark as expensive instead of outright disabling variants
which are not optimized for speed.

 gcc/testsuite/gcc.dg/torture/pr112344.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/torture/pr112344.c 
b/gcc/testsuite/gcc.dg/torture/pr112344.c
index c52d2c8304b..657322caed0 100644
--- a/gcc/testsuite/gcc.dg/torture/pr112344.c
+++ b/gcc/testsuite/gcc.dg/torture/pr112344.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target int32plus } */
+/* { dg-skip-if "non-optimized code is too slow" { ! run_expensive_tests } { 
"*" } { "-O2" "-O3" } } */
 
 int
 main ()
-- 
2.43.0

Re: [PATCH] testsuite: Disable slow and unneeded test variants

[Dimitar Dimitrov]

On Fri, Feb 16, 2024 at 07:06:57PM +0100, Jakub Jelinek wrote:
> On Fri, Feb 16, 2024 at 07:52:17PM +0200, Dimitar Dimitrov wrote:
> > The issue in PR112344 is triggered only at -O2, so there is little value
> > in running the test at lower optimization levels.  At the same time the
> 
> That is generally not true.
> We had hundreds of cases in the history where a test written for one bug
> let us discover a different bug later on, often at different optimization
> level etc.
> 
> If the test is too slow, perhaps the dg-skip-if should take the
> run_expensive_tests effective target into account, like:
> /* { dg-skip-if "" { ! run_expensive_tests }  { "*" } { "-O0" "-O1" } } */

Thank you, this is reasonable.  I'll send V2 with that change.

Curiously, -Os also needs to be added to the slow variants, along with
-O0 and -O1.

> 
> But guess another question is if the bug can be reproduced with fewer
> iterations...

I could not think of a way to do it.

Regards,
Dimitar

> 
>   Jakub
> 

[PATCH] testsuite: Disable slow and unneeded test variants

[Dimitar Dimitrov]

The issue in PR112344 is triggered only at -O2, so there is little value
in running the test at lower optimization levels.  At the same time the
generated code at low and code-size optimization levels is taking a long
time to execute because it loops a few billion iterations.

On the PRU simulator target the non-optimized test variants take more
than 10 minutes, thus failing due to timeout.  Even a native x86_64
takes a few seconds to run the non-optimized variants.

Let's not waste cycles and run only the test configurations which
triggered the issue described in the PR.

On native x86_64 Linux:
$ time make check-gcc-c -j10 RUNTESTFLAGS="dg-torture.exp=pr112344.c"
--
TimePreviously  With this patch
--
real0m4,786s0m1,694s
user0m7,031s0m4,013s
sys 0m3,300s0m3,234s

With PRU simulator:
$ time make -j10 check-gcc-c RUNTESTFLAGS="--target_board=pru-sim 
dg-torture.exp=pr112344.c"
--
TimePreviously   With this patch
--
real11m32,740s   0m1,897s
user11m34,301s   0m4,012s
sys 0m2,178s 0m2,133s


Ok for trunk?

PR middle-end/112344

gcc/testsuite/ChangeLog:

* gcc.dg/torture/pr112344.c: Run only
for expensive speed optimizations.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/torture/pr112344.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/torture/pr112344.c 
b/gcc/testsuite/gcc.dg/torture/pr112344.c
index c52d2c8304b..abcef51428f 100644
--- a/gcc/testsuite/gcc.dg/torture/pr112344.c
+++ b/gcc/testsuite/gcc.dg/torture/pr112344.c
@@ -1,6 +1,8 @@
 /* { dg-do run } */
 /* { dg-require-effective-target int32plus } */
 
+/* { dg-skip-if "triggered by expensive speed optimizations" { *-*-* } { "-O0" 
"-O1" "-Os" "-Oz" } { "" } } */
+
 int
 main ()
 {
-- 
2.43.0

Re: [RFA] New pass for sign/zero extension elimination

[Dimitar Dimitrov]

On Sun, Nov 19, 2023 at 05:47:56PM -0700, Jeff Law wrote:
...
> +/* Process uses in INSN.  Set appropriate bits in LIVENOW for any chunks of
> +   pseudos that become live, potentially filtering using bits from LIVE_TMP.
> +
> +   If MODIFIED is true, then optimize sign/zero extensions to SUBREGs when
> +   the extended bits are never read and mark pseudos which had extensions
> +   eliminated in CHANGED_PSEUDOS.  */
> +
> +static void
> +ext_dce_process_uses (rtx insn, bitmap livenow, bitmap live_tmp,
> +   bool modify, bitmap changed_pseudos)
> +{
> +  /* A nonlocal goto implicitly uses the frame pointer.  */
> +  if (JUMP_P (insn) && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
> +{
> +  bitmap_set_range (livenow, FRAME_POINTER_REGNUM * 4, 4);
> +  if (!HARD_FRAME_POINTER_IS_FRAME_POINTER)
> + bitmap_set_range (livenow, HARD_FRAME_POINTER_REGNUM * 4, 4);
> +}
> +
> +  subrtx_var_iterator::array_type array_var;
> +  rtx pat = PATTERN (insn);
> +  FOR_EACH_SUBRTX_VAR (iter, array_var, pat, NONCONST)
> +{
> +  /* An EXPR_LIST (from call fusage) ends in NULL_RTX.  */
> +  rtx x = *iter;
> +  if (x == NULL_RTX)
> + continue;
> +
> +  /* So the basic idea in this FOR_EACH_SUBRTX_VAR loop is to
> +  handle SETs explicitly, possibly propagating live information
> +  into the uses.
> +
> +  We may continue the loop at various points which will cause
> +  iteration into the next level of RTL.  Breaking from the loop
> +  is never safe as it can lead us to fail to process some of the
> +  RTL and thus not make objects live when necessary.  */
> +  enum rtx_code xcode = GET_CODE (x);
> +  if (xcode == SET)
> + {
> +   const_rtx dst = SET_DEST (x);
> +   rtx src = SET_SRC (x);
> +   const_rtx y;
> +   unsigned HOST_WIDE_INT bit = 0;
> +
> +   /* The code of the RHS of a SET.  */
> +   enum rtx_code code = GET_CODE (src);
> +
> +   /* ?!? How much of this should mirror SET handling, potentially
> +  being shared?   */
> +   if (SUBREG_BYTE (dst).is_constant () && SUBREG_P (dst))

Shouldn't SUBREG_P be checked first like:
  if (SUBREG_P (dst) && SUBREG_BYTE (dst).is_constant ())

On pru-unknown-elf with RTL checking I get:

conftest.c:16:1: internal compiler error: RTL check: expected code 'subreg', 
have 'reg' in ext_dce_process_uses, at ext-dce.cc:421
   16 | }
  | ^
0x158b39e rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, 
char const*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:770
0x223a486 ext_dce_process_uses
/mnt/nvme/dinux/local-workspace/gcc/gcc/ext-dce.cc:421
0x223b5ba ext_dce_process_bb
/mnt/nvme/dinux/local-workspace/gcc/gcc/ext-dce.cc:651
0x223bdd3 ext_dce
/mnt/nvme/dinux/local-workspace/gcc/gcc/ext-dce.cc:802
0x223c0ac execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/ext-dce.cc:868


Regards,
Dimitar

Re: [PATCH 1/2] gcov: Use unshare_expr() in gen_counter_update()

[Dimitar Dimitrov]

On Mon, Nov 20, 2023 at 03:33:30PM +0100, Sebastian Huber wrote:
> This fixes issues like this:
> 
>   gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c: In function 
> 'main':
>   gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: error: 
> incorrect sharing of tree nodes
>   __gcov0.main[0]
>   # .MEM_12 = VDEF <.MEM_9>
>   __gcov0.main[0] = PROF_edge_counter_4;
>   during IPA pass: profile
>   gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: internal 
> compiler error: verify_gimple failed
> 

Hi Sebastian,

This fixes all the regressions I reported for the pru-unknown-elf
target from commit "gcov: Add gen_counter_update()"

Thanks,
Dimitar

Re: [PATCH 3/4] gcov: Add gen_counter_update()

[Dimitar Dimitrov]

On Tue, Nov 14, 2023 at 11:08:24PM +0100, Sebastian Huber wrote:
> Move the counter update to the new gen_counter_update() helper function.  Use
> it in gimple_gen_edge_profiler() and gimple_gen_time_profiler().  The 
> resulting
> gimple instructions should be identical with the exception of the removed
> unshare_expr() call.  The unshare_expr() call was used in
> gimple_gen_edge_profiler().
> 
> gcc/ChangeLog:
> 
>   * tree-profile.cc (gen_assign_counter_update): New.
>   (gen_counter_update): Likewise.
>   (gimple_gen_edge_profiler): Use gen_counter_update().
>   (gimple_gen_time_profiler): Likewise.
> ---
>  gcc/tree-profile.cc | 133 +---
>  1 file changed, 62 insertions(+), 71 deletions(-)
> 

Hi Sebastian,

This patch caused a bunch of test failures on arm-none-eabi and
pru-unknown-elf targets.  One example:

/home/dinux/projects/pru/testbot-workspace/gcc/gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:
 In function 'main':
/home/dinux/projects/pru/testbot-workspace/gcc/gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1:
 error: incorrect sharing of tree nodes
__gcov0.main[0]
# .MEM_12 = VDEF <.MEM_9>
__gcov0.main[0] = PROF_edge_counter_4;
during IPA pass: profile
/home/dinux/projects/pru/testbot-workspace/gcc/gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1:
 internal compiler error: verify_gimple failed
0xfd9c7d verify_gimple_in_cfg(function*, bool, bool)
/home/dinux/projects/pru/testbot-workspace/gcc/gcc/tree-cfg.cc:5662
0xe586a4 execute_function_todo
/home/dinux/projects/pru/testbot-workspace/gcc/gcc/passes.cc:2088
0xe58ba2 do_per_function
/home/dinux/projects/pru/testbot-workspace/gcc/gcc/passes.cc:1694
0xe58ba2 do_per_function
/home/dinux/projects/pru/testbot-workspace/gcc/gcc/passes.cc:1684
0xe58bfe execute_todo
/home/dinux/projects/pru/testbot-workspace/gcc/gcc/passes.cc:2142
Please submit a full bug report, with preprocessed source (by using 
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.
compiler exited with status 1
FAIL: gcc.dg/no_profile_instrument_function-attr-1.c (internal compiler error: 
verify_gimple failed)
FAIL: gcc.dg/no_profile_instrument_function-attr-1.c (test for excess errors)


I'm using the following script to build and test:
  https://github.com/dinuxbg/gnupru/blob/master/testing/manual-test-pru.sh

Regards,
Dimitar

Re: [PATCH] tree-optimization/112282 - wrong-code with ifcvt hoisting

[Dimitar Dimitrov]

On Wed, Nov 15, 2023 at 12:11:50PM +, Richard Biener wrote:
> The following avoids hoisting of invariants from conditionally
> executed parts of an if-converted loop.  That now makes a difference
> since we perform bitfield lowering even when we do not actually
> if-convert the loop.  if-conversion deals with resetting flow-sensitive
> info when necessary already.
> 
> Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
> 
>   PR tree-optimization/112282
>   * tree-if-conv.cc (ifcvt_hoist_invariants): Only hoist from
>   the loop header.
> 
>   * gcc.dg/torture/pr112282.c: New testcase.
> ---
>  gcc/testsuite/gcc.dg/torture/pr112282.c | 132 
>  gcc/tree-if-conv.cc |  44 
>  2 files changed, 153 insertions(+), 23 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.dg/torture/pr112282.c
> 
> diff --git a/gcc/testsuite/gcc.dg/torture/pr112282.c 
> b/gcc/testsuite/gcc.dg/torture/pr112282.c
> new file mode 100644
> index 000..23e0ed64b82
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/torture/pr112282.c
> @@ -0,0 +1,132 @@
> +/* { dg-do run } */
> +
> +int printf(const char *, ...);
> +void __assert_fail();

This function is glibc-only. Thus the test fails on newlib targets with:

  FAIL: gcc.dg/torture/pr112282.c   -O0  (test for excess errors)
  Excess errors:
  pr112282.c:(.text+0x1944): undefined reference to `__assert_fail'
  pr112282.c:(.text+0x2480): undefined reference to `__assert_fail'

Perhaps __builtin_abort should be used instead?

Regards,
Dimitar

[committed] testsuite: Ignore warning for unsupported option

[Dimitar Dimitrov]

The -w option was used in gcc.dg/20020206-1.c to ignore warnings if the
'-fprefetch-loop-arrays' option is not supported by target.

When commit r14-5380-g5c432b0efab54e removed the -w option, some targets
(arm-none-eabi, pru and possibly others) started failing the test:

  cc1: warning: '-fprefetch-loop-arrays' not supported for this target
  FAIL: gcc.dg/20020206-1.c (test for excess errors)

Fix by instructing DejaGnu to prune the '-fprefetch-loop-arrays'
warning.

Pushed to trunk as an obvious fix.

gcc/testsuite/ChangeLog:

* gcc.dg/20020206-1.c: Prune warning that
-fprefetch-loop-arrays is not supported.

CC: Florian Weimer 
Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/20020206-1.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/20020206-1.c 
b/gcc/testsuite/gcc.dg/20020206-1.c
index c8d8b61937a..a5a9cb038e7 100644
--- a/gcc/testsuite/gcc.dg/20020206-1.c
+++ b/gcc/testsuite/gcc.dg/20020206-1.c
@@ -5,6 +5,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -fprefetch-loop-arrays" } */
 /* { dg-options "-O2 -fprefetch-loop-arrays -mtune=pentium3" { target { { 
i?86-*-* x86_64-*-* } && ia32 } } } */
+/* { dg-prune-output  ".-fprefetch-loop-arrays. not supported for this target" 
} */
 
 
 struct reload
-- 
2.41.0

Re: [PATCH V3 0/7] ira/lra: Support subreg coalesce

[Dimitar Dimitrov]

On Sun, Nov 12, 2023 at 08:08:10PM +0800, Lehua Ding wrote:
> V3 Changes:
>   1. fix three ICE.
>   2. rebase
> 
> Hi,
> 
> These patchs try to support subreg coalesce feature in
> register allocation passes (ira and lra).
> 

Hi Lehua,

V3 indeed fixes the arm-none-eabi build. It's also confirmed by Linaro CI:
  
https://patchwork.sourceware.org/project/gcc/patch/20231112120817.2635864-8-lehua.d...@rivai.ai/

But avr and pru backends are still broken, albeit with different crash
signatures. Both targets are peculiar because they have
UNITS_PER_WORD=1. I'll try building some 16-bit target like msp430.

AVR fails when building libgcc:
/mnt/nvme/dinux/local-workspace/gcc/libgcc/config/avr/lib2funcs.c: In function 
'__roundlr':
/mnt/nvme/dinux/local-workspace/gcc/libgcc/config/avr/lib2funcs.c:115:3: 
internal compiler error: in check_allocation, at ira.cc:2673
  115 |   }
  |   ^
/mnt/nvme/dinux/local-workspace/gcc/libgcc/config/avr/lib2funcs.c:106:3: note: 
in expansion of macro 'ROUND2'
  106 |   ROUND2 (FX)
  |   ^~
/mnt/nvme/dinux/local-workspace/gcc/libgcc/config/avr/lib2funcs.c:117:1: note: 
in expansion of macro 'ROUND1'
  117 | ROUND1(L_LABEL)
  | ^~
0xc80b8d check_allocation
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:2673
0xc89451 ira
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:5873
0xc89451 execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:6104

Script I'm using to build avr: 
https://github.com/dinuxbg/gnupru/blob/master/testing/manual-build-avr.sh



PRU fails building newlib:
/mnt/nvme/dinux/local-workspace/newlib/newlib/libc/stdlib/gdtoa-gdtoa.c:835:9: 
internal compiler error: in lra_create_live_ranges, at lra-lives.cc:1933
  835 | }
  | ^
0x6b951c lra_create_live_ranges(bool, bool)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra-lives.cc:1933
0xd9320c lra(_IO_FILE*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:2638
0xd3e519 do_reload
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:5960
0xd3e519 execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:6148

Script I'm using to build pru: 
https://github.com/dinuxbg/gnupru/blob/master/testing/manual-build-pru.sh

Regards,
Dimitar,

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

[Dimitar Dimitrov]

On Fri, Nov 10, 2023 at 04:53:57PM +0800, Lehua Ding wrote:
> > > The divide by zero error above is interesting. I'm not sure why
> > > ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in
> > > the following rtx:
> > > (debug_insn 168 167 169 19 (var_location:SI encoding (reg/v:SI 168 [
> > > encoding ])) -1
> > >   (nil))
> > 
> > I just cross compiled an arm-none-eabi compiler and didn't encounter
> > this error, can you give me a little more config info about build? For
> > example, flags_for_target, etc. Thanks again.
> > 
> 
> Forgot, please also provide the version information of newlib code.
> 

These are the GIT commit hashes which I tested:
  gcc 39d81b667373b0033f44702a4b532a4618dde9ff
  binutils c96ceed9dce7617f270aa4742645706e535f74b7
  newlib 39f734a857e2692224715b03b99fc7bd83e94a0f

This is the script I'm using to build arm-none-eabi:
   https://github.com/dinuxbg/gnupru/blob/master/testing/manual-build-arm.sh
The build steps and config parameters are easily seen there.

Note that the Linaro CI is also detecting issues. It hits ICEs when
building libgcc:
  
https://patchwork.sourceware.org/project/gcc/patch/20231108034740.834590-8-lehua.d...@rivai.ai/

Regards,
Dimitar

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

[Dimitar Dimitrov]

On Wed, Nov 08, 2023 at 11:47:33AM +0800, Lehua Ding wrote:
> Hi,
> 
> These patchs try to support subreg coalesce feature in
> register allocation passes (ira and lra).

Hi Lehua,

This patch set breaks the build for at least three embedded targets. See
below.

For avr the GCC build fails with:
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira-lives.cc:149:39: error: call of 
overloaded ‘set_subreg_conflict_hard_regs(ira_allocno*&, int&)’ is ambiguous
  149 | set_subreg_conflict_hard_regs (OBJECT_ALLOCNO (obj), regno);


For arm-none-eabi the newlib build fails with:
/mnt/nvme/dinux/local-workspace/newlib/newlib/libm/math/e_jn.c:279:1: internal 
compiler error: Floating point exception
  279 | }
  | ^
0x1176e0f crash_signal
/mnt/nvme/dinux/local-workspace/gcc/gcc/toplev.cc:316
0xf6008d get_range_hard_regs(int, subreg_range const&)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:609
0xf6008d get_range_hard_regs(int, subreg_range const&)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:601
0xf60312 new_insn_reg
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:658
0xf6064d add_regs_to_insn_regno_info
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1623
0xf62909 lra_update_insn_regno_info(rtx_insn*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1769
0xf62e46 lra_update_insn_regno_info(rtx_insn*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1762
0xf62e46 lra_push_insn_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1919
0xf62f2d lra_push_insn(rtx_insn*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1927
0xf62f2d push_insns
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1970
0xf63302 push_insns
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1966
0xf63302 lra(_IO_FILE*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:2511
0xf0e399 do_reload 
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:5960
0xf0e399 execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:6148


For pru-elf the GCC build fails with:
/mnt/nvme/dinux/local-workspace/gcc/libgcc/unwind-dw2-fde.c: In function 
'linear_search_fdes':
/mnt/nvme/dinux/local-workspace/gcc/libgcc/unwind-dw2-fde.c:1035:1: internal 
compiler error: Floating point exception
 1035 | }
  | ^
0x1694f2e crash_signal
/mnt/nvme/dinux/local-workspace/gcc/gcc/toplev.cc:316
0x1313178 get_range_hard_regs(int, subreg_range const&)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:609
0x131343a new_insn_reg
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:658
0x13174f0 add_regs_to_insn_regno_info
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1608
0x1318479 lra_update_insn_regno_info(rtx_insn*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1769
0x13196ab lra_push_insn_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1919
0x13196de lra_push_insn(rtx_insn*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1927
0x13197da push_insns
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:1970
0x131b6dc lra(_IO_FILE*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/lra.cc:2511
0x129f237 do_reload
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:5960
0x129f6c6 execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/ira.cc:6148


The divide by zero error above is interesting. I'm not sure why 
ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in the following 
rtx:
(debug_insn 168 167 169 19 (var_location:SI encoding (reg/v:SI 168 [ encoding 
])) -1
 (nil))

Regards,
Dimitar

[committed] pru: Implement TARGET_INSN_COST

[Dimitar Dimitrov]

This patch slightly improves the embench-iot benchmark score for
PRU code size.  There is also small improvement in a few real-world
firmware programs.

  Embench-iot size
  --
  Benchmark  before   afterdelta
  -    -
  aha-mont64  4.154.15 0
  crc32   6.046.04 0
  cubic  21.64   21.62 -0.02
  edn 6.376.37 0
  huffbench  18.63   18.55 -0.08
  matmult-int 5.445.44 0
  md5sum 25.56   25.43 -0.13
  minver 12.82   12.76 -0.06
  nbody  15.09   14.97 -0.12
  nettle-aes  4.754.75 0
  nettle-sha256   4.674.67 0
  nsichneu3.773.77 0
  picojpeg4.114.11 0
  primecount  7.907.90 0
  qrduino 7.187.16 -0.02
  sglib-combined 13.63   13.59 -0.04
  slre5.195.19 0
  st 14.23   14.12 -0.11
  statemate   2.342.34 0
  tarfind36.85   36.64 -0.21
  ud 10.51   10.46 -0.05
  wikisort7.447.41 -0.03
  -  -   -
  Geometric mean  8.428.40 -0.02
  Geometric SD2.002.00 0
  Geometric range12.68   12.62 -0.06

Reg-tested pru-unknown-elf, and committed to trunk.

gcc/ChangeLog:

* config/pru/pru.cc (pru_insn_cost): New function.
(TARGET_INSN_COST): Define for PRU.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.cc | 36 
 1 file changed, 36 insertions(+)

diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc
index 6e8112be64a..fd1924e38dc 100644
--- a/gcc/config/pru/pru.cc
+++ b/gcc/config/pru/pru.cc
@@ -783,6 +783,39 @@ pru_rtx_costs (rtx x, machine_mode mode,
   }
 }
 }
+
+/* Insn costs on PRU are straightforward because:
+ - Insns emit 0, 1 or more instructions.
+ - All instructions are 32-bit length.
+ - All instructions execute in 1 cycle (sans memory access delays).
+   The "length" attribute maps nicely to the insn cost.  */
+
+static int
+pru_insn_cost (rtx_insn *insn, bool speed)
+{
+  /* Use generic cost calculation for unrecognized insns.  */
+  if (recog_memoized (insn) < 0)
+return pattern_cost (insn, speed);
+
+  unsigned int len = get_attr_length (insn);
+
+  gcc_assert ((len % 4) == 0);
+
+  int cost = COSTS_N_INSNS (len / 4);
+  /* Some insns have zero length (e.g. blockage, pruloop_end).
+ In such cases give the minimum cost, because a return of
+ 0 would incorrectly indicate that the insn cost is unknown.  */
+  if (cost == 0)
+cost = 1;
+
+  /* Writes are usually posted, so they take 1 cycle.  Reads
+ from DMEM usually take 3 cycles.
+ See TI document SPRACE8A, Device-Specific PRU Read Latency Values.  */
+  if (speed && get_attr_type (insn) == TYPE_LD)
+cost += COSTS_N_INSNS (2);
+
+  return cost;
+}
 
 static GTY(()) rtx eqdf_libfunc;
 static GTY(()) rtx nedf_libfunc;
@@ -3175,6 +3208,9 @@ pru_unwind_word_mode (void)
 #undef TARGET_RTX_COSTS
 #define TARGET_RTX_COSTS pru_rtx_costs
 
+#undef TARGET_INSN_COST
+#define TARGET_INSN_COST pru_insn_cost
+
 #undef TARGET_PRINT_OPERAND
 #define TARGET_PRINT_OPERAND pru_print_operand
 
-- 
2.41.0

Re: [PATCH 3/3] [V2] [RISC-V] support cm.mva01s cm.mvsa01 in zcmp

[Dimitar Dimitrov]

Hi,

This patch appears to have caused PR 111259.

Regards,
Dimitar

On Tue, Aug 29, 2023 at 08:37:46AM +, Fei Gao wrote:
> From: Die Li 
> 
> Signed-off-by: Die Li 
> Co-Authored-By: Fei Gao 
> 
> gcc/ChangeLog:
> 
> * config/riscv/peephole.md: New pattern.
> * config/riscv/predicates.md (a0a1_reg_operand): New predicate.
> (zcmp_mv_sreg_operand): New predicate.
> * config/riscv/riscv.md: New predicate.
> * config/riscv/zc.md (*mva01s): New pattern.
> (*mvsa01): New pattern.
> 
> gcc/testsuite/ChangeLog:
> 
> * gcc.target/riscv/cm_mv_rv32.c: New test.
> ---
>  gcc/config/riscv/peephole.md| 28 +
>  gcc/config/riscv/predicates.md  | 11 
>  gcc/config/riscv/riscv.md   |  1 +
>  gcc/config/riscv/zc.md  | 22 
>  gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c | 23 +
>  5 files changed, 85 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c
> 
> diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md
> index 0ef0c04410b..92e57f9a447 100644
> --- a/gcc/config/riscv/peephole.md
> +++ b/gcc/config/riscv/peephole.md
> @@ -38,3 +38,31 @@
>  {
>operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5]));
>  })
> +
> +;; ZCMP
> +(define_peephole2
> +  [(set (match_operand:X 0 "a0a1_reg_operand")
> +(match_operand:X 1 "zcmp_mv_sreg_operand"))
> +   (set (match_operand:X 2 "a0a1_reg_operand")
> +(match_operand:X 3 "zcmp_mv_sreg_operand"))]
> +  "TARGET_ZCMP
> +   && (REGNO (operands[2]) != REGNO (operands[0]))"
> +  [(parallel [(set (match_dup 0)
> +   (match_dup 1))
> +  (set (match_dup 2)
> +   (match_dup 3))])]
> +)
> +
> +(define_peephole2
> +  [(set (match_operand:X 0 "zcmp_mv_sreg_operand")
> +(match_operand:X 1 "a0a1_reg_operand"))
> +   (set (match_operand:X 2 "zcmp_mv_sreg_operand")
> +(match_operand:X 3 "a0a1_reg_operand"))]
> +  "TARGET_ZCMP
> +   && (REGNO (operands[0]) != REGNO (operands[2]))
> +   && (REGNO (operands[1]) != REGNO (operands[3]))"
> +  [(parallel [(set (match_dup 0)
> +   (match_dup 1))
> +  (set (match_dup 2)
> +   (match_dup 3))])]
> +)
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index 3ef09996a85..772f45df65c 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -165,6 +165,17 @@
>(and (match_code "const_int")
> (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 13)")))
>  
> +;; ZCMP predicates
> +(define_predicate "a0a1_reg_operand"
> +  (and (match_operand 0 "register_operand")
> +   (match_test "IN_RANGE (REGNO (op), A0_REGNUM, A1_REGNUM)")))
> +
> +(define_predicate "zcmp_mv_sreg_operand"
> +  (and (match_operand 0 "register_operand")
> +   (match_test "TARGET_RVE ? IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM)
> +: IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM)
> +|| IN_RANGE (REGNO (op), S2_REGNUM, S7_REGNUM)")))
> +
>  ;; Only use branch-on-bit sequences when the mask is not an ANDI immediate.
>  (define_predicate "branch_on_bit_operand"
>(and (match_code "const_int")
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 8e09df6ff63..aa2b5b960dc 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -132,6 +132,7 @@
> (S0_REGNUM8)
> (S1_REGNUM9)
> (A0_REGNUM10)
> +   (A1_REGNUM11)
> (S2_REGNUM18)
> (S3_REGNUM19)
> (S4_REGNUM20)
> diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
> index 8d7de97daad..77b28adde95 100644
> --- a/gcc/config/riscv/zc.md
> +++ b/gcc/config/riscv/zc.md
> @@ -1433,3 +1433,25 @@
>"TARGET_ZCMP"
>"cm.push   {ra, s0-s11}, %0"
>  )
> +
> +;; ZCMP mv
> +(define_insn "*mva01s"
> +  [(set (match_operand:X 0 "a0a1_reg_operand" "=r")
> +(match_operand:X 1 "zcmp_mv_sreg_operand" "r"))
> +   (set (match_operand:X 2 "a0a1_reg_operand" "=r")
> +(match_operand:X 3 "zcmp_mv_sreg_operand" "r"))]
> +  "TARGET_ZCMP
> +   && (REGNO (operands[2]) != REGNO (operands[0]))"
> +  { return (REGNO (operands[0]) == 
> A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; }
> +  [(set_attr "mode" "")])
> +
> +(define_insn "*mvsa01"
> +  [(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r")
> +(match_operand:X 1 "a0a1_reg_operand" "r"))
> +   (set (match_operand:X 2 "zcmp_mv_sreg_operand" "=r")
> +(match_operand:X 3 "a0a1_reg_operand" "r"))]
> +  "TARGET_ZCMP
> +   && (REGNO (operands[0]) != REGNO (operands[2]))
> +   && (REGNO (operands[1]) != REGNO (operands[3]))"
> +  { return (REGNO (operands[1]) == 
> 

[committed] pru: Add cstore expansion patterns

[Dimitar Dimitrov]

Add cstore patterns for the two specific operations which can be
efficiently expanded using the UMIN instruction:
  X != 0
  X == 0
The rest of the operations are rejected, and left to be expanded
by the common expansion code.

Reg-tested pru-unknown-elf.  Pushed to trunk.

PR target/106562

gcc/ChangeLog:

* config/pru/predicates.md (const_0_operand): New predicate.
(pru_cstore_comparison_operator): Ditto.
* config/pru/pru.md (cstore4): New pattern.
(cstoredi4): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/pru/pr106562-10.c: New test.
* gcc.target/pru/pr106562-11.c: New test.
* gcc.target/pru/pr106562-5.c: New test.
* gcc.target/pru/pr106562-6.c: New test.
* gcc.target/pru/pr106562-7.c: New test.
* gcc.target/pru/pr106562-8.c: New test.
* gcc.target/pru/pr106562-9.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/predicates.md   |  8 +++
 gcc/config/pru/pru.md  | 62 ++
 gcc/testsuite/gcc.target/pru/pr106562-10.c |  8 +++
 gcc/testsuite/gcc.target/pru/pr106562-11.c |  8 +++
 gcc/testsuite/gcc.target/pru/pr106562-5.c  |  8 +++
 gcc/testsuite/gcc.target/pru/pr106562-6.c  |  8 +++
 gcc/testsuite/gcc.target/pru/pr106562-7.c  |  8 +++
 gcc/testsuite/gcc.target/pru/pr106562-8.c  |  8 +++
 gcc/testsuite/gcc.target/pru/pr106562-9.c  |  8 +++
 9 files changed, 126 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-10.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-11.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-5.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-6.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-7.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-8.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-9.c

diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index e4a7fcf259b..faa0dbf9fb4 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -22,6 +22,10 @@ (define_predicate "const_1_operand"
   (and (match_code "const_int")
(match_test "INTVAL (op) == 1")))
 
+(define_predicate "const_0_operand"
+  (and (match_code "const_int")
+   (match_test "INTVAL (op) == 0")))
+
 ; Note: Always pass a valid mode!
 (define_predicate "const_ubyte_operand"
   (match_code "const_int")
@@ -49,6 +53,10 @@ (define_predicate "pru_signed_cmp_operator"
 (define_predicate "pru_fp_comparison_operator"
   (match_code "eq,ne,lt,gt,le,ge"))
 
+;; TRUE for comparisons supported by PRU's cstore.
+(define_predicate "pru_cstore_comparison_operator"
+  (match_code "eq,ne,gtu"))
+
 ;; Return true if OP is a constant that contains only one 1 in its
 ;; binary representation.
 (define_predicate "single_one_operand"
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 6deb5ecfecb..93ad7b6ad7e 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -1489,6 +1489,68 @@ (define_expand "cbranchdi4"
 gcc_unreachable ();
 })
 
+;; Emit efficient code for two specific cstore cases:
+;;   X == 0
+;;   X != 0
+;;
+;; These can be efficiently compiled on the PRU using the umin
+;; instruction.
+;;
+;; This expansion does not handle "X > 0 unsigned" and "X >= 1 unsigned"
+;; because it is assumed that those would have been replaced with the
+;; canonical "X != 0".
+(define_expand "cstore4"
+  [(set (match_operand:QISI 0 "register_operand")
+   (match_operator:QISI 1 "pru_cstore_comparison_operator"
+ [(match_operand:QISI 2 "register_operand")
+  (match_operand:QISI 3 "const_0_operand")]))]
+  ""
+{
+  const enum rtx_code op1code = GET_CODE (operands[1]);
+
+  /* Crash if OP1 is GTU.  It would mean that "X > 0 unsigned"
+ had not been canonicalized before calling this expansion.  */
+  gcc_assert (op1code == NE || op1code == EQ);
+  gcc_assert (CONST_INT_P (operands[3]) && INTVAL (operands[3]) == 0);
+
+  if (op1code == NE)
+{
+  emit_insn (gen_umin3 (operands[0], operands[2], const1_rtx));
+  DONE;
+}
+  else if (op1code == EQ)
+{
+  rtx tmpval = gen_reg_rtx (mode);
+  emit_insn (gen_umin3 (tmpval, operands[2], const1_rtx));
+  emit_insn (gen_xor3 (operands[0], tmpval, const1_rtx));
+  DONE;
+}
+
+  gcc_unreachable ();
+})
+
+(define_expand "cstoredi4"
+  [(set (match_operand:SI 0 "register_operand")
+   (match_operator:SI 1 "pru_cstore_comparison_operator"
+ [(match_operand:DI 2 "register_operand")
+  (match_operand:DI 3 "const_0_operand")]))]
+  ""
+{
+  /* Combining the two SImode suboperands with IOR wor

Re: [PATCH] riscv: Fix scope for memory model calculation

[Dimitar Dimitrov]

On Tue, Jun 06, 2023 at 08:38:14PM -0600, Jeff Law wrote:
> 
> 
> > Regression tested for riscv32-none-elf. No changes in gcc.sum and
> > g++.sum.  I don't have setup to test riscv64.
> > 
> > gcc/ChangeLog:
> > 
> > * config/riscv/riscv.cc (riscv_print_operand): Calculate
> > memmodel only when it is valid.
> Good to see you poking around in the RISC-V world Dimitar!  Are you still
> poking at the PRU as well?

Hi Jeff,

Yes, I'm still maintaining the PRU backend.

For this patch I was actually poking at the middle end, trying to
implement a small optimization for PRU (PR 106562).  And I wanted
to test if other targets would also benefit from it.

Thanks,
Dimitar

> 
> Anyway, this is fine for the trunk and for backporting to gcc-13 if the
> problem exists there as well.
> 
> jeff

[PATCH] riscv: Fix scope for memory model calculation

[Dimitar Dimitrov]

During libgcc configure stage for riscv32-none-elf, when
"--enable-checking=yes,rtl" has been activated, the following error
is observed:

  configure:3814: 
/home/dinux/projects/pru/local-workspace/riscv32-gcc-build/./gcc/xgcc 
-B/home/dinux/projects/pru/local-workspace/riscv32-gcc-build/./gcc/ 
-B/mnt/nvme/dinux/local-workspace/riscv32-opt/riscv32-none-elf/bin/ 
-B/mnt/nvme/dinux/local-workspace/riscv32-opt/riscv32-none-elf/lib/ -isystem 
/mnt/nvme/dinux/local-workspace/riscv32-opt/riscv32-none-elf/include -isystem 
/mnt/nvme/dinux/local-workspace/riscv32-opt/riscv32-none-elf/sys-include-c 
-g -O2  conftest.c >&5
  during RTL pass: final
  conftest.c: In function 'main':
  conftest.c:16:1: internal compiler error: RTL check: expected code 
'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4462
 16 | }
| ^
  0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, 
char const*)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916
  0x8ea823 riscv_print_operand
  /mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:4462
  0xde84b5 output_operand(rtx_def*, int)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3632
  0xde8ef8 output_asm_insn(char const*, rtx_def**)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3544
  0xded33b output_asm_insn(char const*, rtx_def**)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3421
  0xded33b final_scan_insn_1
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2841
  0xded6cb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2887
  0xded8b7 final_1
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:1979
  0xdee518 rest_of_handle_final
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4240
  0xdee518 execute
  /mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4318

Fix by moving the calculation of memmodel to the cases where it is used.

Regression tested for riscv32-none-elf. No changes in gcc.sum and
g++.sum.  I don't have setup to test riscv64.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_print_operand): Calculate
memmodel only when it is valid.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/riscv/riscv.cc | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index c15da1d0e30..fa4bc3e1f7e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4459,7 +4459,6 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 }
   machine_mode mode = GET_MODE (op);
   enum rtx_code code = GET_CODE (op);
-  const enum memmodel model = memmodel_base (INTVAL (op));
 
   switch (letter)
 {
@@ -4596,7 +4595,8 @@ riscv_print_operand (FILE *file, rtx op, int letter)
   fputs (GET_RTX_NAME (code), file);
   break;
 
-case 'A':
+case 'A': {
+  const enum memmodel model = memmodel_base (INTVAL (op));
   if (riscv_memmodel_needs_amo_acquire (model)
  && riscv_memmodel_needs_amo_release (model))
fputs (".aqrl", file);
@@ -4605,18 +4605,23 @@ riscv_print_operand (FILE *file, rtx op, int letter)
   else if (riscv_memmodel_needs_amo_release (model))
fputs (".rl", file);
   break;
+}
 
-case 'I':
+case 'I': {
+  const enum memmodel model = memmodel_base (INTVAL (op));
   if (model == MEMMODEL_SEQ_CST)
fputs (".aqrl", file);
   else if (riscv_memmodel_needs_amo_acquire (model))
fputs (".aq", file);
   break;
+}
 
-case 'J':
+case 'J': {
+  const enum memmodel model = memmodel_base (INTVAL (op));
   if (riscv_memmodel_needs_amo_release (model))
fputs (".rl", file);
   break;
+}
 
 case 'i':
   if (code != REG)
-- 
2.40.1

[PATCH] riscv: Fix insn cost calculation

[Dimitar Dimitrov]

When building riscv32-none-elf with "--enable-checking=yes,rtl", the
following ICE is observed:

  cc1: internal compiler error: RTL check: expected code 'const_int', have 
'const_double' in riscv_const_insns, at config/riscv/riscv.cc:1313
  0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, 
char const*)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916
  0x8eab61 riscv_const_insns(rtx_def*)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:1313
  0x15443bb riscv_legitimate_constant_p
  /mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:826
  0xdd3c71 emit_move_insn(rtx_def*, rtx_def*)
  /mnt/nvme/dinux/local-workspace/gcc/gcc/expr.cc:4310
  0x15f28e5 run_const_vector_selftests
  
/mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv-selftests.cc:285
  0x15f37bd selftest::riscv_run_selftests()
  
/mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv-selftests.cc:364
  0x1f6fba9 selftest::run_tests()
  /mnt/nvme/dinux/local-workspace/gcc/gcc/selftest-run-tests.cc:111
  0x11d1f39 toplev::run_self_tests()
  /mnt/nvme/dinux/local-workspace/gcc/gcc/toplev.cc:2185

Fix by following the spirit of the adjacent comment, and using the
dedicated riscv_const_insns() function to calculate cost for loading a
constant element.  Infinite recursion is not possible because the first
invocation is on a CONST_VECTOR, whereas the second is on a single
element of the vector (e.g. CONST_INT or CONST_DOUBLE).

Regression tested for riscv32-none-elf. No changes in gcc.sum and
g++.sum.  I don't have setup to test riscv64.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_const_insns): Recursively call
for constant element of a vector.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3954c89a039..c15da1d0e30 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1310,7 +1310,7 @@ riscv_const_insns (rtx x)
   a general-purpose register.  This means we need as many
   insns as it takes to load the constant into the GPR
   and one vmv.v.x.  */
-   return 1 + riscv_integer_cost (INTVAL (elt));
+   return 1 + riscv_const_insns (elt);
  }
  }
 
-- 
2.40.1

[committed] testsuite: Require trampolines for nestev-vla tests

[Dimitar Dimitrov]

Three recent test cases declare nested C functions, so they fail on
targets lacking support for trampolines. Fix by adding the necessary
filter.

Committed as obvious.

gcc/testsuite/ChangeLog:

* gcc.dg/nested-vla-1.c: Require effective target trampolines.
* gcc.dg/nested-vla-2.c: Ditto.
* gcc.dg/nested-vla-3.c: Ditto.

CC: Martin Uecker 
Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/nested-vla-1.c | 1 +
 gcc/testsuite/gcc.dg/nested-vla-2.c | 1 +
 gcc/testsuite/gcc.dg/nested-vla-3.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/nested-vla-1.c 
b/gcc/testsuite/gcc.dg/nested-vla-1.c
index 5b62c2c213a..d1b3dc3c5f8 100644
--- a/gcc/testsuite/gcc.dg/nested-vla-1.c
+++ b/gcc/testsuite/gcc.dg/nested-vla-1.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-std=gnu99" } */
+/* { dg-require-effective-target trampolines } */
 
 
 int main()
diff --git a/gcc/testsuite/gcc.dg/nested-vla-2.c 
b/gcc/testsuite/gcc.dg/nested-vla-2.c
index d83c90a0b16..294b01d370e 100644
--- a/gcc/testsuite/gcc.dg/nested-vla-2.c
+++ b/gcc/testsuite/gcc.dg/nested-vla-2.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-std=gnu99" } */
+/* { dg-require-effective-target trampolines } */
 
 
 int main()
diff --git a/gcc/testsuite/gcc.dg/nested-vla-3.c 
b/gcc/testsuite/gcc.dg/nested-vla-3.c
index 1ffb482da3b..d2ba04adab8 100644
--- a/gcc/testsuite/gcc.dg/nested-vla-3.c
+++ b/gcc/testsuite/gcc.dg/nested-vla-3.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-std=gnu99" } */
+/* { dg-require-effective-target trampolines } */
 
 
 int main()
-- 
2.40.1

[committed] libgcc pru: Define TARGET_HAS_NO_HW_DIVIDE

[Dimitar Dimitrov]

This patch aligns the configuration to the actual PRU capabilities. It
also reduces the size of the affected libgcc functions.

For a real-world project using integer arithmetics the savings
are significant:

  Before:
 textdata bss dec hex filename
 3688 865 544509713e9 hc-sr04-range-sensor.elf

  With TARGET_HAS_NO_HW_DIVIDE defined:
 textdata bss dec hex filename
 2824 865 54442331089 hc-sr04-range-sensor.elf

Execution speed also appears to have improved. The moddi3 function is
now executed in half the CPU cycles.

Cherry-picked from the recent change for the CRIS port. Pushed to trunk.

libgcc/ChangeLog:

* config/pru/t-pru (HOST_LIBGCC2_CFLAGS): Add
-DTARGET_HAS_NO_HW_DIVIDE.

Signed-off-by: Dimitar Dimitrov 
---
 libgcc/config/pru/t-pru | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/libgcc/config/pru/t-pru b/libgcc/config/pru/t-pru
index a5b1871e52d..7d5f5ee4261 100644
--- a/libgcc/config/pru/t-pru
+++ b/libgcc/config/pru/t-pru
@@ -42,6 +42,9 @@ LIB2ADD += \
 
 HOST_LIBGCC2_CFLAGS += -Os -ffunction-sections -fdata-sections
 
+# Use an appropriate implementation when implementing DImode division.
+HOST_LIBGCC2_CFLAGS += -DTARGET_HAS_NO_HW_DIVIDE
+
 LIB2FUNCS_EXCLUDE = _muldi3
 
 SHLIB_MAPFILES += $(srcdir)/config/pru/libgcc-eabi.ver
-- 
2.40.0

[GCC-11][committed] pru: Fix CLZ expansion for QI and HI modes

[Dimitar Dimitrov]

The recent gcc.dg/tree-ssa/clz-char.c test case failed for PRU target,
exposing a wrong code generation bug in the PRU backend.  The "clz"
pattern did not produce correct output for QI and HI input operand
modes.  SI mode is ok.

The "clz" pattern is expanded to an LMBD instruction to get the
left-most bit position having value "1".  In turn, to get the correct
"clz" value, that bit position must be subtracted from the MSB bit
position of the input operand.  The old behaviour of hard-coding 31
for MSB bit position is wrong.

The LMBD instruction returns 32 if input operand is zero, irrespective
of its register mode.  This maps nicely for SI mode, where the "clz"
pattern outputs -1.  It also leads to peculiar (but valid!) output
values from the "clz" pattern for QI and HI zero-valued inputs.

The corresponding commit in trunk contains two new test cases, which
have been removed here because they depend on r13-5195-g4798080d4a3530.
Regtested for pru-unknown-elf.

gcc/ChangeLog:

* config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Fix value for QI
and HI input modes.
* config/pru/pru.md (clz): Fix generated code for QI and HI
input modes.

Signed-off-by: Dimitar Dimitrov 
(cherry picked from commit c517295940a23db8ca165dfd5d0edea4457eda49)
---
 gcc/config/pru/pru.h  |  5 +++--
 gcc/config/pru/pru.md | 15 ---
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/gcc/config/pru/pru.h b/gcc/config/pru/pru.h
index 4c35a7d7ee3..41260b9450d 100644
--- a/gcc/config/pru/pru.h
+++ b/gcc/config/pru/pru.h
@@ -562,8 +562,9 @@ do {
\
 
 #define CASE_VECTOR_MODE Pmode
 
-/* See definition of clz pattern for rationale of value -1.  */
-#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
+/* See definition of clz pattern for rationale of the value.  */
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+   ((VALUE) = GET_MODE_BITSIZE (MODE) - 1 - 32, 2)
 
 /* Jumps are cheap on PRU.  */
 #define LOGICAL_OP_NON_SHORT_CIRCUIT   0
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index e6cfa8ec3bf..c5661adb6c4 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -1035,8 +1035,16 @@ (define_insn "pru_halt"
   [(set_attr "type" "control")])
 
 ;; Count Leading Zeros implemented using LMBD.
-;; LMBD returns 32 if bit value is not present, and we subtract 31 to get CLZ.
-;; Hence we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO.
+;;
+;; LMBD returns 32 if bit value is not present, for any kind of input MODE.
+;; The LMBD's search result for a "1" bit is subtracted from the
+;; mode bit size minus one, in order to get CLZ.
+;;
+;; Hence for SImode we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO.
+;;
+;; The QImode and HImode defined values for zero inputs end up to be
+;; non-standard (-25 and -17).  But this is considered acceptable in
+;; order to keep the CLZ expansion to only two instructions.
 (define_expand "clz2"
   [(set (match_operand:QISI 0 "register_operand")
(clz:QISI (match_operand:QISI 1 "register_operand")))]
@@ -1047,7 +1055,8 @@ (define_expand "clz2"
   rtx tmpval = gen_reg_rtx (mode);
 
   emit_insn (gen_pru_lmbd (mode, tmpval, src, const1_rtx));
-  emit_insn (gen_sub3_insn (dst, GEN_INT (31), tmpval));
+  int msb_bitn = GET_MODE_BITSIZE (mode) - 1;
+  emit_insn (gen_sub3_insn (dst, GEN_INT (msb_bitn), tmpval));
   DONE;
 })
 
-- 
2.39.1

[GCC-12][committed] pru: Fix CLZ expansion for QI and HI modes

[Dimitar Dimitrov]

The recent gcc.dg/tree-ssa/clz-char.c test case failed for PRU target,
exposing a wrong code generation bug in the PRU backend.  The "clz"
pattern did not produce correct output for QI and HI input operand
modes.  SI mode is ok.

The "clz" pattern is expanded to an LMBD instruction to get the
left-most bit position having value "1".  In turn, to get the correct
"clz" value, that bit position must be subtracted from the MSB bit
position of the input operand.  The old behaviour of hard-coding 31
for MSB bit position is wrong.

The LMBD instruction returns 32 if input operand is zero, irrespective
of its register mode.  This maps nicely for SI mode, where the "clz"
pattern outputs -1.  It also leads to peculiar (but valid!) output
values from the "clz" pattern for QI and HI zero-valued inputs.

The corresponding commit in trunk contains two new test cases, which
have been removed here because they depend on r13-5195-g4798080d4a3530.
Regtested for pru-unknown-elf.

gcc/ChangeLog:

* config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Fix value for QI
and HI input modes.
* config/pru/pru.md (clz): Fix generated code for QI and HI
input modes.

Signed-off-by: Dimitar Dimitrov 
(cherry picked from commit c517295940a23db8ca165dfd5d0edea4457eda49)
---
 gcc/config/pru/pru.h  |  5 +++--
 gcc/config/pru/pru.md | 15 ---
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/gcc/config/pru/pru.h b/gcc/config/pru/pru.h
index 4c35a7d7ee3..41260b9450d 100644
--- a/gcc/config/pru/pru.h
+++ b/gcc/config/pru/pru.h
@@ -562,8 +562,9 @@ do {
\
 
 #define CASE_VECTOR_MODE Pmode
 
-/* See definition of clz pattern for rationale of value -1.  */
-#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
+/* See definition of clz pattern for rationale of the value.  */
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+   ((VALUE) = GET_MODE_BITSIZE (MODE) - 1 - 32, 2)
 
 /* Jumps are cheap on PRU.  */
 #define LOGICAL_OP_NON_SHORT_CIRCUIT   0
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index e6cfa8ec3bf..c5661adb6c4 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -1035,8 +1035,16 @@ (define_insn "pru_halt"
   [(set_attr "type" "control")])
 
 ;; Count Leading Zeros implemented using LMBD.
-;; LMBD returns 32 if bit value is not present, and we subtract 31 to get CLZ.
-;; Hence we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO.
+;;
+;; LMBD returns 32 if bit value is not present, for any kind of input MODE.
+;; The LMBD's search result for a "1" bit is subtracted from the
+;; mode bit size minus one, in order to get CLZ.
+;;
+;; Hence for SImode we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO.
+;;
+;; The QImode and HImode defined values for zero inputs end up to be
+;; non-standard (-25 and -17).  But this is considered acceptable in
+;; order to keep the CLZ expansion to only two instructions.
 (define_expand "clz2"
   [(set (match_operand:QISI 0 "register_operand")
(clz:QISI (match_operand:QISI 1 "register_operand")))]
@@ -1047,7 +1055,8 @@ (define_expand "clz2"
   rtx tmpval = gen_reg_rtx (mode);
 
   emit_insn (gen_pru_lmbd (mode, tmpval, src, const1_rtx));
-  emit_insn (gen_sub3_insn (dst, GEN_INT (31), tmpval));
+  int msb_bitn = GET_MODE_BITSIZE (mode) - 1;
+  emit_insn (gen_sub3_insn (dst, GEN_INT (msb_bitn), tmpval));
   DONE;
 })
 
-- 
2.39.1

[committed] pru: Fix CLZ expansion for QI and HI modes

[Dimitar Dimitrov]

The recent gcc.dg/tree-ssa/clz-char.c test case failed for PRU target,
exposing a wrong code generation bug in the PRU backend.  The "clz"
pattern did not produce correct output for QI and HI input operand
modes.  SI mode is ok.

The "clz" pattern is expanded to an LMBD instruction to get the
left-most bit position having value "1".  In turn, to get the correct
"clz" value, that bit position must be subtracted from the MSB bit
position of the input operand.  The old behaviour of hard-coding 31
for MSB bit position is wrong.

The LMBD instruction returns 32 if input operand is zero, irrespective
of its register mode.  This maps nicely for SI mode, where the "clz"
pattern outputs -1.  It also leads to peculiar (but valid!) output
values from the "clz" pattern for QI and HI zero-valued inputs.

Pushed to trunk. This patch is confined to the PRU backend only,
and is fixing a wrong code generation.  Hence I deem it suitable
for stage 4.

Is it ok to push a backport to gcc-11 and gcc-12 branches?

gcc/ChangeLog:

* config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Fix value for QI
and HI input modes.
* config/pru/pru.md (clz): Fix generated code for QI and HI
input modes.

gcc/testsuite/ChangeLog:

* gcc.target/pru/clz-hi-2.c: New test.
    * gcc.target/pru/clz-hi.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.h|  5 ++--
 gcc/config/pru/pru.md   | 15 ---
 gcc/testsuite/gcc.target/pru/clz-hi-2.c | 24 +
 gcc/testsuite/gcc.target/pru/clz-hi.c   | 35 +
 4 files changed, 74 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/clz-hi-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/clz-hi.c

diff --git a/gcc/config/pru/pru.h b/gcc/config/pru/pru.h
index 3658036cccb..1b5e874bc06 100644
--- a/gcc/config/pru/pru.h
+++ b/gcc/config/pru/pru.h
@@ -566,8 +566,9 @@ do {
\
 
 #define CASE_VECTOR_MODE Pmode
 
-/* See definition of clz pattern for rationale of value -1.  */
-#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
+/* See definition of clz pattern for rationale of the value.  */
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+   ((VALUE) = GET_MODE_BITSIZE (MODE) - 1 - 32, 2)
 
 /* Jumps are cheap on PRU.  */
 #define LOGICAL_OP_NON_SHORT_CIRCUIT   0
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index dfe08071e04..aa8e42a3587 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -1723,8 +1723,16 @@ (define_insn "pru_halt"
   [(set_attr "type" "control")])
 
 ;; Count Leading Zeros implemented using LMBD.
-;; LMBD returns 32 if bit value is not present, and we subtract 31 to get CLZ.
-;; Hence we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO.
+;;
+;; LMBD returns 32 if bit value is not present, for any kind of input MODE.
+;; The LMBD's search result for a "1" bit is subtracted from the
+;; mode bit size minus one, in order to get CLZ.
+;;
+;; Hence for SImode we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO.
+;;
+;; The QImode and HImode defined values for zero inputs end up to be
+;; non-standard (-25 and -17).  But this is considered acceptable in
+;; order to keep the CLZ expansion to only two instructions.
 (define_expand "clz2"
   [(set (match_operand:QISI 0 "register_operand")
(clz:QISI (match_operand:QISI 1 "register_operand")))]
@@ -1735,7 +1743,8 @@ (define_expand "clz2"
   rtx tmpval = gen_reg_rtx (mode);
 
   emit_insn (gen_pru_lmbd (mode, tmpval, src, const1_rtx));
-  emit_insn (gen_sub3_insn (dst, GEN_INT (31), tmpval));
+  int msb_bitn = GET_MODE_BITSIZE (mode) - 1;
+  emit_insn (gen_sub3_insn (dst, GEN_INT (msb_bitn), tmpval));
   DONE;
 })
 
diff --git a/gcc/testsuite/gcc.target/pru/clz-hi-2.c 
b/gcc/testsuite/gcc.target/pru/clz-hi-2.c
new file mode 100644
index 000..af877c7021e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/clz-hi-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-tree-ch" } */
+
+/* This test case is based on gcc.dg/tree-ssa/clz-char.c. */
+
+#define PREC (sizeof(short) * 8)
+
+int
+__attribute__ ((noinline, noclone))
+foo (unsigned short b) {
+int c = 0;
+
+if (b == 0)
+  return PREC;
+
+while (!(b & (1 << (PREC - 1 {
+   b <<= 1;
+   c++;
+}
+
+return c;
+}
+
+/* { dg-final { scan-assembler "lmbd\\tr\[012\]\[0-9\]?.w\[0-2\], 
r\[012\]\[0-9\]?.w\[0-2\], 1" } } */
diff --git a/gcc/testsuite/gcc.target/pru/clz-hi.c 
b/gcc/testsuite/gcc.target/pru/clz-hi.c
new file mode 100644
index 000..9350913b6d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/clz-hi.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options &q

[PATCH] testsuite: Add filter for target socket support

[Dimitar Dimitrov]

The new analyzer tests for sockets are failing on embedded targets.
The newlib and avr-libc C libraries do not support sockets.

At first I considered a coarse filtering on the existing
effective_target_freestanding check.  But seeing how lib/target-supports.exp
is slowly turning into a copy of autotools, I kept the tradition and added
a new fine grained "socket" filter.

I also considered adding effective_target_posix, but could not
figure out a reliable C code to perform the check.

Testing done:
  - No changes in gcc.sum for x86_64-pc-linux-gnu, with or without this
patch.
  - Filtered cases are now UNSUPPORTED instead of failing on AVR and PRU
backends.

Ok for trunk?

gcc/ChangeLog:

* doc/sourcebuild.texi (sockets): Document new check.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/fd-accept.c: Require sockets.
* gcc.dg/analyzer/fd-bind.c: Ditto.
* gcc.dg/analyzer/fd-connect.c: Ditto.
* gcc.dg/analyzer/fd-datagram-socket.c: Ditto.
* gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c:
Ditto.
* gcc.dg/analyzer/fd-glibc-byte-stream-socket.c: Ditto.
* gcc.dg/analyzer/fd-glibc-datagram-client.c: Ditto.
* gcc.dg/analyzer/fd-glibc-datagram-socket.c: Ditto.
* gcc.dg/analyzer/fd-listen.c: Ditto.
* gcc.dg/analyzer/fd-manpage-getaddrinfo-client.c: Ditto.
* gcc.dg/analyzer/fd-mappage-getaddrinfo-server.c: Ditto.
* gcc.dg/analyzer/fd-meaning.c: Ditto.
* gcc.dg/analyzer/fd-socket-meaning.c: Ditto.
* gcc.dg/analyzer/fd-socket-misuse.c: Ditto.
* gcc.dg/analyzer/fd-stream-socket-active-open.c: Ditto.
* gcc.dg/analyzer/fd-stream-socket-passive-open.c: Ditto.
* gcc.dg/analyzer/fd-stream-socket.c: Ditto.
* gcc.dg/analyzer/fd-symbolic-socket.c: Ditto.
* lib/target-supports.exp (check_effective_target_sockets): New
check.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/doc/sourcebuild.texi   |  3 +++
 gcc/testsuite/gcc.dg/analyzer/fd-accept.c  |  2 ++
 gcc/testsuite/gcc.dg/analyzer/fd-bind.c|  2 ++
 gcc/testsuite/gcc.dg/analyzer/fd-connect.c |  2 ++
 gcc/testsuite/gcc.dg/analyzer/fd-datagram-socket.c |  2 ++
 .../fd-glibc-byte-stream-connection-server.c   |  1 +
 .../gcc.dg/analyzer/fd-glibc-byte-stream-socket.c  |  1 +
 .../gcc.dg/analyzer/fd-glibc-datagram-client.c |  1 +
 .../gcc.dg/analyzer/fd-glibc-datagram-socket.c |  1 +
 gcc/testsuite/gcc.dg/analyzer/fd-listen.c  |  2 ++
 .../analyzer/fd-manpage-getaddrinfo-client.c   |  1 +
 .../analyzer/fd-mappage-getaddrinfo-server.c   |  2 ++
 gcc/testsuite/gcc.dg/analyzer/fd-meaning.c |  2 +-
 gcc/testsuite/gcc.dg/analyzer/fd-socket-meaning.c  |  1 +
 gcc/testsuite/gcc.dg/analyzer/fd-socket-misuse.c   |  2 ++
 .../gcc.dg/analyzer/fd-stream-socket-active-open.c |  2 ++
 .../analyzer/fd-stream-socket-passive-open.c   |  2 ++
 gcc/testsuite/gcc.dg/analyzer/fd-stream-socket.c   |  2 ++
 gcc/testsuite/gcc.dg/analyzer/fd-symbolic-socket.c |  2 ++
 gcc/testsuite/lib/target-supports.exp  | 14 ++
 20 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 766266942f9..ffe69d6fcb9 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2666,6 +2666,9 @@ Target can compile using @code{pthread.h} with no errors 
or warnings.
 @item pthread_h
 Target has @code{pthread.h}.
 
+@item sockets
+Target can compile using @code{sys/socket.h} with no errors or warnings.
+
 @item run_expensive_tests
 Expensive testcases (usually those that consume excessive amounts of CPU
 time) should be run on this target.  This can be enabled by setting the
diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-accept.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-accept.c
index 36cc7af7184..5426063f31d 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-accept.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-accept.c
@@ -1,3 +1,5 @@
+/* { dg-require-effective-target sockets } */
+
 #include 
 #include 
 #include 
diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-bind.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-bind.c
index 6f91bc4b794..c34803f1380 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-bind.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-bind.c
@@ -1,3 +1,5 @@
+/* { dg-require-effective-target sockets } */
+
 #include 
 #include 
 #include 
diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-connect.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-connect.c
index 1ab54d01f36..7bf687e2570 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-connect.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-connect.c
@@ -1,3 +1,5 @@
+/* { dg-require-effective-target sockets } */
+
 #include 
 #include 
 #include 
diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-datagram-socket.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-datagram-socket.c
index 045bdfa32d3..58508570a25 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-datagra

[committed] pru: Add cbranchdi4 pattern

[Dimitar Dimitrov]

This patch improves code generation for the PRU backend.  Committed to
trunk.

Manually expanding into 32-bit comparisons is much more efficient than
the default expansion into word-size comparisons.  Note that word for PRU
is 8-bit.

PR target/106562

gcc/ChangeLog:

* config/pru/pru-protos.h (pru_noteq_condition): New
function declaration.
* config/pru/pru.cc (pru_noteq_condition): New function.
* config/pru/pru.md (cbranchdi4): Define new pattern.

gcc/testsuite/ChangeLog:

* gcc.target/pru/pr106562-1.c: New test.
* gcc.target/pru/pr106562-2.c: New test.
* gcc.target/pru/pr106562-3.c: New test.
* gcc.target/pru/pr106562-4.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru-protos.h   |   1 +
 gcc/config/pru/pru.cc |  21 +++
 gcc/config/pru/pru.md | 180 ++
 gcc/testsuite/gcc.target/pru/pr106562-1.c |   9 ++
 gcc/testsuite/gcc.target/pru/pr106562-2.c |   9 ++
 gcc/testsuite/gcc.target/pru/pr106562-3.c |   9 ++
 gcc/testsuite/gcc.target/pru/pr106562-4.c | 159 +++
 7 files changed, 388 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106562-4.c

diff --git a/gcc/config/pru/pru-protos.h b/gcc/config/pru/pru-protos.h
index 4b190c98206..517fa02e272 100644
--- a/gcc/config/pru/pru-protos.h
+++ b/gcc/config/pru/pru-protos.h
@@ -52,6 +52,7 @@ extern const char *pru_output_signed_cbranch (rtx *, bool);
 extern const char *pru_output_signed_cbranch_ubyteop2 (rtx *, bool);
 extern const char *pru_output_signed_cbranch_zeroop2 (rtx *, bool);
 
+extern enum rtx_code pru_noteq_condition (enum rtx_code code);
 extern rtx pru_expand_fp_compare (rtx comparison, machine_mode mode);
 
 extern void pru_emit_doloop (rtx *, int);
diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc
index 04eca90b255..0029dcbc6aa 100644
--- a/gcc/config/pru/pru.cc
+++ b/gcc/config/pru/pru.cc
@@ -895,6 +895,27 @@ pru_init_libfuncs (void)
   set_optab_libfunc (udivmod_optab, DImode, "__pruabi_divremull");
 }
 
+/* Given a comparison CODE, return a similar comparison but without
+   the "equals" condition.  In other words, it strips GE/GEU/LE/LEU
+   and instead returns GT/GTU/LT/LTU.  */
+
+enum rtx_code
+pru_noteq_condition (enum rtx_code code)
+{
+  switch (code)
+{
+case GT: return GT;
+case GTU: return GTU;
+case GE: return GT;
+case GEU: return GTU;
+case LT: return LT;
+case LTU: return LTU;
+case LE: return LT;
+case LEU: return LTU;
+default:
+  gcc_unreachable ();
+}
+}
 
 /* Emit comparison instruction if necessary, returning the expression
that holds the compare result in the proper mode.  Return the comparison
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 5307708..bdc5ad79ba0 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -1309,6 +1309,186 @@ (define_expand "cbranch4"
   operands[2] = XEXP (t, 1);
 })
 
+;; Expand the cbranchdi pattern in order to avoid the default
+;; expansion into word_mode operations, which is not efficient for PRU.
+;; In pseudocode this expansion outputs:
+;;
+;; /* EQ */
+;; if (OP1_hi {reverse_condition (cmp)} OP2_hi)
+;; goto fallthrough
+;; if (OP1_lo {cmp} OP2_lo)
+;; goto label3
+;; fallthrough:
+;;
+;; /* NE */
+;; if (OP1_hi {cmp} OP2_hi)
+;; goto label3
+;; if (OP1_lo {cmp} OP2_lo)
+;; goto label3
+;;
+;; The LT comparisons with zero take one machine instruction to simply
+;; check the sign bit.  The GT comparisons with zero take two - one
+;; to check the sign bit, and one to check for zero.  Hence arrange
+;; the expand such that only LT comparison is used for OP1_HI, because
+;; OP2_HI is const0_rtx.
+;;
+;; The LTU comparisons with zero will be removed by subsequent passes.
+;;
+;;  /* LT/LTU/LE/LEU */
+;;  if (OP1_hi {noteq_condition (cmp)} OP2_hi)
+;; goto label3 /* DI comparison obviously true.  */
+;;  if (OP1_hi != OP2_hi)
+;; goto fallthrough/* DI comparison obviously not true.  */
+;;  if (OP1_lo {unsigned_condition (cmp)} OP2_lo)
+;; goto label3 /* Comparison was deferred to lo parts.  */
+;;  fallthrough:
+
+;;  /* GT/GTU/GE/GEU */
+;;  if (OP1_hi {reverse_condition (noteq_condition (cmp))} OP2_hi)
+;; goto fallthrough/* DI comparison obviously not true.  */
+;;  if (OP1_hi != OP2_hi)
+;; goto label3 /* DI comparison obviously true.  */
+;;  if (OP1_lo {unsigned_condition (cmp)} OP2_lo)
+;; goto label3 /* Comparison was deferred to lo parts.  */
+;;  fallthrough:
+
+(define_expand "cbranchdi4"
+  [(set (pc)
+ (if_then_else
+   (match

[committed] pru: Optimize DI shifts

[Dimitar Dimitrov]

This patch improves code generation for the PRU backend.  Committed to
trunk.

If the number of shift positions is a constant, then the DI shift
operation is expanded to a sequence of 2 to 4 machine instructions.
That is more efficient than the default action to call libgcc.

gcc/ChangeLog:

* config/pru/pru.md (lshrdi3): New expand pattern.
(ashldi3): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/pru/ashiftdi-1.c: New test.
* gcc.target/pru/lshiftrtdi-1.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.md   | 196 
 gcc/testsuite/gcc.target/pru/ashiftdi-1.c   |  53 ++
 gcc/testsuite/gcc.target/pru/lshiftrtdi-1.c |  53 ++
 3 files changed, 302 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/pru/ashiftdi-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/lshiftrtdi-1.c

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 144cd35d809..5307708 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -703,6 +703,202 @@ (define_insn "ashr3_single"
   [(set_attr "type" "alu")
(set_attr "length" "12")])
 
+
+; 64-bit LSHIFTRT with a constant shift count can be expanded into
+; more efficient code sequence than a variable register shift.
+;
+; 1. For shift >= 32:
+;dst_lo = (src_hi >> (shift - 32))
+;dst_hi = 0
+;
+; 2. For shift==1 there is no need for a temporary:
+;dst_lo = (src_lo >> 1)
+;if (src_hi & 1)
+;   dst_lo |= (1 << 31)
+;dst_hi = (src_hi >> 1)
+;
+; 3. For shift < 32:
+;dst_lo = (src_lo >> shift)
+;tmp = (src_hi << (32 - shift)
+;dst_lo |= tmp
+;dst_hi = (src_hi >> shift)
+;
+; 4. For shift in a register:
+;Fall back to calling libgcc.
+(define_expand "lshrdi3"
+  [(set (match_operand:DI 0 "register_operand")
+ (lshiftrt:DI
+   (match_operand:DI 1 "register_operand")
+   (match_operand:QI 2 "const_int_operand")))]
+  ""
+{
+  gcc_assert (CONST_INT_P (operands[2]));
+
+  const int nshifts = INTVAL (operands[2]);
+  rtx dst_lo = simplify_gen_subreg (SImode, operands[0], DImode, 0);
+  rtx dst_hi = simplify_gen_subreg (SImode, operands[0], DImode, 4);
+  rtx src_lo = simplify_gen_subreg (SImode, operands[1], DImode, 0);
+  rtx src_hi = simplify_gen_subreg (SImode, operands[1], DImode, 4);
+
+  if (nshifts >= 32)
+{
+  emit_insn (gen_rtx_SET (dst_lo,
+ gen_rtx_LSHIFTRT (SImode,
+   src_hi,
+   GEN_INT (nshifts - 32;
+  emit_insn (gen_rtx_SET (dst_hi, const0_rtx));
+  DONE;
+}
+
+  gcc_assert (can_create_pseudo_p ());
+
+  /* The expansions which follow are safe only if DST_LO and SRC_HI
+ do not overlap.  If they do, then fix by using a temporary register.
+ Overlapping of DST_HI and SRC_LO is safe because by the time DST_HI
+ is set, SRC_LO is no longer live.  */
+  if (reg_overlap_mentioned_p (dst_lo, src_hi))
+{
+  rtx new_src_hi = gen_reg_rtx (SImode);
+
+  emit_move_insn (new_src_hi, src_hi);
+  src_hi = new_src_hi;
+}
+
+  if (nshifts == 1)
+{
+  rtx_code_label *skip_hiset_label;
+  rtx j;
+
+  emit_insn (gen_rtx_SET (dst_lo,
+ gen_rtx_LSHIFTRT (SImode, src_lo, const1_rtx)));
+
+  /* The code generated by `genemit' would create a LABEL_REF.  */
+  skip_hiset_label = gen_label_rtx ();
+  j = emit_jump_insn (gen_cbranch_qbbx_const (EQ,
+ SImode,
+ src_hi,
+ GEN_INT (0),
+ skip_hiset_label));
+  JUMP_LABEL (j) = skip_hiset_label;
+  LABEL_NUSES (skip_hiset_label)++;
+
+  emit_insn (gen_iorsi3 (dst_lo, dst_lo, GEN_INT (1 << 31)));
+  emit_label (skip_hiset_label);
+  emit_insn (gen_rtx_SET (dst_hi,
+ gen_rtx_LSHIFTRT (SImode, src_hi, const1_rtx)));
+  DONE;
+}
+
+  if (nshifts < 32)
+{
+  rtx tmpval = gen_reg_rtx (SImode);
+
+  emit_insn (gen_rtx_SET (dst_lo,
+ gen_rtx_LSHIFTRT (SImode,
+   src_lo,
+   GEN_INT (nshifts;
+  emit_insn (gen_rtx_SET (tmpval,
+ gen_rtx_ASHIFT (SImode,
+ src_hi,
+ GEN_INT (32 - nshifts;
+  emit_insn (gen_iorsi3 (dst_lo, dst_lo, tmpval));
+  emit_insn (gen_rtx_SET (dst_hi,
+ gen_rtx_LSHIFTRT (SImode,
+   s

Re: [PATCH v4] eliminate mutex in fast path of __register_frame

[Dimitar Dimitrov]

On Fri, Sep 16, 2022 at 12:19:36PM +0200, Thomas Neumann via Gcc-patches wrote:
> The __register_frame/__deregister_frame functions are used to register
> unwinding frames from JITed code in a sorted list. That list itself
> is protected by object_mutex, which leads to terrible performance
> in multi-threaded code and is somewhat expensive even if single-threaded.
> There was already a fast-path that avoided taking the mutex if no
> frame was registered at all.
> 
> This commit eliminates both the mutex and the sorted list from
> the atomic fast path, and replaces it with a btree that uses
> optimistic lock coupling during lookup. This allows for fully parallel
> unwinding and is essential to scale exception handling to large
> core counts.
> 
> Changes since v3:
> - Avoid code duplication by adding query mode to classify_object_over_fdes
> - Adjust all comments as requested
> 
> libgcc/ChangeLog:
> 
> * unwind-dw2-fde.c (release_registered_frames): Cleanup at shutdown.
> (__register_frame_info_table_bases): Use btree in atomic fast path.
> (__deregister_frame_info_bases): Likewise.
> (_Unwind_Find_FDE): Likewise.
> (base_from_object): Make parameter const.
> (classify_object_over_fdes): Add query-only mode.
> (get_pc_range): Compute PC range for lookup.
> * unwind-dw2-fde.h (last_fde): Make parameter const.
> * unwind-dw2-btree.h: New file.
> ---
>  libgcc/unwind-dw2-btree.h | 953 ++
>  libgcc/unwind-dw2-fde.c   | 195 ++--
>  libgcc/unwind-dw2-fde.h   |   2 +-
>  3 files changed, 1098 insertions(+), 52 deletions(-)
>  create mode 100644 libgcc/unwind-dw2-btree.h
> 

Hi Thomas,

This patch broke avr and pru-elf cross builds:
  gcc/libgcc/unwind-dw2-fde.c:680:28: error: unknown type name ‘uintptr_t’
  680 |uintptr_t *range)

Should uintptr_t be replaced with __UINTPTR_TYPE__? Such change fixes the
above broken builds for me. But I'm not sure how valid it is for that
part of libgcc.

Other embedded targets like arm-none-eabi are not broken because they
overwrite LIB2ADDEH, and consequently unwind-dw2-fde.c is not built for
them.

Regards,
Dimitar

[committed] pru: Add mov variants to load const -1

[Dimitar Dimitrov]

Use the FILL instruction to efficiently load -1 constants.

Regression tested on pru-unknown-elf, committed to mainline.

gcc/ChangeLog:

* config/pru/pru.md (prumov, mov): Add
variants for loading -1 consts.

gcc/testsuite/ChangeLog:

* gcc.target/pru/mov-m1.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.md | 25 ++---
 gcc/testsuite/gcc.target/pru/mov-m1.c | 18 ++
 2 files changed, 32 insertions(+), 11 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/mov-m1.c

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 031109236d6..02e11350a4d 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -206,8 +206,8 @@ (define_expand "mov"
 ;;
 ;; Note: Assume that Program Mem (T constraint) can fit in 16 bits!
 (define_insn "prumov"
-  [(set (match_operand:MOV32 0 "nonimmediate_operand" "=m,r,r,r,r,r")
-   (match_operand:MOV32 1 "general_operand"  "r,m,r,T,J,iF"))]
+  [(set (match_operand:MOV32 0 "nonimmediate_operand" "=m,r,r,r,r,r,r")
+   (match_operand:MOV32 1 "general_operand"  "r,m,r,T,J,Um,iF"))]
   ""
   "@
 sb%B0o\\t%b1, %0, %S0
@@ -215,9 +215,10 @@ (define_insn "prumov"
 mov\\t%0, %1
 ldi\\t%0, %%pmem(%1)
 ldi\\t%0, %1
+fill\\t%0, 4
 ldi32\\t%0, %1"
-  [(set_attr "type" "st,ld,alu,alu,alu,alu")
-   (set_attr "length" "4,4,4,4,4,8")])
+  [(set_attr "type" "st,ld,alu,alu,alu,alu,alu")
+   (set_attr "length" "4,4,4,4,4,4,8")])
 
 
 ;; Separate pattern for 8 and 16 bit moves, since LDI32 pseudo instruction
@@ -247,8 +248,8 @@ (define_insn "prumov"
 ; Forcing DI reg alignment (akin to microblaze's HARD_REGNO_MODE_OK)
 ; does not seem efficient, and will violate TI ABI.
 (define_insn "mov"
-  [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r")
-   (match_operand:MOV64 1 "general_operand"  "r,m,r,T,J,nF"))]
+  [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r")
+   (match_operand:MOV64 1 "general_operand"  "r,m,Um,r,T,J,nF"))]
   ""
 {
   switch (which_alternative)
@@ -258,6 +259,8 @@ (define_insn "mov"
 case 1:
   return "lb%B1o\\t%b0, %1, %S1";
 case 2:
+  return "fill\\t%F0, 8";
+case 3:
   /* careful with overlapping source and destination regs.  */
   gcc_assert (GP_REG_P (REGNO (operands[0])));
   gcc_assert (GP_REG_P (REGNO (operands[1])));
@@ -265,18 +268,18 @@ (define_insn "mov"
return "mov\\t%N0, %N1\;mov\\t%F0, %F1";
   else
return "mov\\t%F0, %F1\;mov\\t%N0, %N1";
-case 3:
-  return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
 case 4:
-  return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+  return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
 case 5:
+  return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+case 6:
   return "ldi32\\t%F0, %w1\;ldi32\\t%N0, %W1";
 default:
   gcc_unreachable ();
   }
 }
-  [(set_attr "type" "st,ld,alu,alu,alu,alu")
-   (set_attr "length" "4,4,8,8,8,16")])
+  [(set_attr "type" "st,ld,alu,alu,alu,alu,alu")
+   (set_attr "length" "4,4,4,8,8,8,16")])
 
 ;
 ; load_multiple pattern(s).
diff --git a/gcc/testsuite/gcc.target/pru/mov-m1.c 
b/gcc/testsuite/gcc.target/pru/mov-m1.c
new file mode 100644
index 000..0b31020e101
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/mov-m1.c
@@ -0,0 +1,18 @@
+/* Loading a register with constant -1 integer value.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int
+test_set_m1_si (void)
+{
+  /* { dg-final { scan-assembler "fill\\tr14(.b0)?, 4" } } */
+  return -1;
+}
+
+long long
+test_set_m1_di (void)
+{
+  /* { dg-final { scan-assembler "fill\\tr14(.b0)?, 8" } } */
+  return -1;
+}
-- 
2.37.2

[committed] PR target/106564: pru: Optimize 64-bit sign- and zero-extend

[Dimitar Dimitrov]

Add new patterns to optimize 64-bit sign- and zero-extend operations for
the PRU target.

The new 64-bit zero-extend patterns are straightforward define_insns.

The old 16/32-bit sign-extend pattern has been rewritten from scratch
in order to add 64-bit support.  The new pattern expands into several
optimized insns for filling bytes with zeros or ones, and for
conditional branching on bit-test.  The bulk of this patch is to
implement the patterns for those new optimized insns.

Regression tested on pru-unknown-elf, committed to mainline.

PR target/106564

gcc/ChangeLog:

* config/pru/constraints.md (Um): New constraint for -1.
(Uf): New constraint for IOR fill-bytes constants.
(Uz): New constraint for AND zero-bytes constants.
* config/pru/predicates.md (const_fillbytes_operand): New
predicate for IOR fill-bytes constants.
(const_zerobytes_operand): New predicate for AND zero-bytes
constants.
* config/pru/pru-protos.h (pru_output_sign_extend): Remove.
(struct pru_byterange): New struct to describe a byte range.
(pru_calc_byterange): New declaration.
* config/pru/pru.cc (pru_rtx_costs): Add penalty for
64-bit zero-extend.
(pru_output_sign_extend): Remove.
(pru_calc_byterange): New helper function to extract byte
range info from a constant.
(pru_print_operand): Remove 'y' and 'z' print modifiers.
* config/pru/pru.md (zero_extendqidi2): New pattern.
(zero_extendhidi2): New pattern.
(zero_extendsidi2): New pattern.
(extend2): Rewrite as an expand.
(@pru_ior_fillbytes): New pattern.
(@pru_and_zerobytes): New pattern.
(di3): Rewrite as an expand and handle ZERO and FILL
special cases.
(pru_di3): New name for di3.
(@cbranch_qbbx_const_): New pattern to
handle bit-test for 64-bit registers.

gcc/testsuite/ChangeLog:

* gcc.target/pru/pr106564-1.c: New test.
* gcc.target/pru/pr106564-2.c: New test.
* gcc.target/pru/pr106564-3.c: New test.
* gcc.target/pru/pr106564-4.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/constraints.md |  23 +++
 gcc/config/pru/predicates.md  |  22 +++
 gcc/config/pru/pru-protos.h   |   9 +-
 gcc/config/pru/pru.cc | 100 +--
 gcc/config/pru/pru.md | 210 --
 gcc/testsuite/gcc.target/pru/pr106564-1.c |   9 +
 gcc/testsuite/gcc.target/pru/pr106564-2.c |   9 +
 gcc/testsuite/gcc.target/pru/pr106564-3.c |   9 +
 gcc/testsuite/gcc.target/pru/pr106564-4.c |   9 +
 9 files changed, 338 insertions(+), 62 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106564-1.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106564-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106564-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/pr106564-4.c

diff --git a/gcc/config/pru/constraints.md b/gcc/config/pru/constraints.md
index 26f9adbe9a6..99cf39904b4 100644
--- a/gcc/config/pru/constraints.md
+++ b/gcc/config/pru/constraints.md
@@ -39,6 +39,11 @@
 ;;  N: -32768 to 32767 (16-bit signed integer).
 ;;  O: -128 to 127 (8-bit signed integer).
 ;;  P: 1
+;;  Um: -1 constant.
+;;  Uf: A constant with a single consecutive range of 0xff bytes.  Rest
+;;  of bytes are zeros.
+;;  Uz: A constant with a single consecutive range of 0x00 bytes.  Rest
+;;  of bytes are 0xff.
 
 ;; Register constraints.
 
@@ -111,3 +116,21 @@ (define_constraint "Z"
   "An integer constant zero."
   (and (match_code "const_int")
(match_test "ival == 0")))
+
+(define_constraint "Um"
+  "@internal
+  A constant -1."
+  (and (match_code "const_int")
+   (match_test "ival == -1")))
+
+(define_constraint "Uf"
+  "@internal
+  An integer constant with a consecutive range of 0xff bytes."
+  (and (match_code "const_int")
+   (match_test "const_fillbytes_operand (op, DImode)")))
+
+(define_constraint "Uz"
+  "@internal
+  An integer constant with a consecutive range of 0x00 bytes."
+  (and (match_code "const_int")
+   (match_test "const_zerobytes_operand (op, DImode)")))
diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index b8debeea371..a138f70a360 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -304,3 +304,25 @@ (define_special_predicate "store_multiple_operation"
 }
   return true;
 })
+
+;; Return true if OP is a constant integer with one single consecutive
+;; range of bytes with value 0xff, and the rest of the bytes are 0x00.
+(define_predicate "const_fillbytes_operand"
+  (match_code "const_int")
+{
+  gcc_assert (mode != VOIDmode);
+
+  pru_byterange r = pru_calc_bytera

[committed] pru: Optimize 64-bit logical operations

[Dimitar Dimitrov]

The earlyclobber in the pattern yields inefficient code due to
unnecessarily generated moves.  Optimize by removing the earlyclobber
for two special alternatives:
  - If OP2 is a small constant integer.
  - If the logical bit operation has only two operands.

Regression tested on pru-unknown-elf, committed to mainline.

gcc/ChangeLog:

* config/pru/pru.md (pru_di3): New alternative for
two operands but without earlyclobber.

gcc/testsuite/ChangeLog:

* gcc.target/pru/bitop-di.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.md   | 39 +
 gcc/testsuite/gcc.target/pru/bitop-di.c | 25 
 2 files changed, 58 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/bitop-di.c

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 02e11350a4d..144cd35d809 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -786,15 +786,42 @@ (define_expand "di3"
 operands[2] = force_reg (DImode, operands[2]);
 })
 
+;; 64-bit pattern for logical operations.
 (define_insn "pru_di3"
-  [(set (match_operand:DI 0 "register_operand" "=,")
+  [(set (match_operand:DI 0 "register_operand" "=r,,r")
  (LOGICAL_BITOP:DI
-   (match_operand:DI 1 "register_operand"  "%r,r")
-   (match_operand:DI 2 "reg_or_ubyte_operand"  "r,I")))]
+   (match_operand:DI 1 "register_operand"  "%0,r,r")
+   (match_operand:DI 2 "reg_or_ubyte_operand"  "r,r,I")))]
   ""
-  "@
-   \\t%F0, %F1, %F2\;\\t%N0, %N1, %N2
-   \\t%F0, %F1, %2\;\\t%N0, %N1, 0"
+{
+  switch (which_alternative)
+{
+case 0:
+  if (REGNO (operands[0]) == (REGNO (operands[2]) + 4))
+   return "\\t%N0, %N0, %N2\;"
+  "\\t%F0, %F0, %F2";
+  else
+   return "\\t%F0, %F0, %F2\;"
+  "\\t%N0, %N0, %N2";
+case 1:
+  /* With the three-register variant there is no way to handle the case
+when OP0 overlaps both OP1 and OP2.  Example:
+OP0_lo == OP1_hi
+OP0_hi == OP2_lo
+Hence this variant's OP0 must be marked as an earlyclobber.  */
+  return "\\t%F0, %F1, %F2\;"
+"\\t%N0, %N1, %N2";
+case 2:
+  if (REGNO (operands[0]) == (REGNO (operands[1]) + 4))
+   return "\\t%N0, %N1, 0\;"
+  "\\t%F0, %F1, %2";
+  else
+   return "\\t%F0, %F1, %2\;"
+  "\\t%N0, %N1, 0";
+default:
+  gcc_unreachable ();
+  }
+}
   [(set_attr "type" "alu")
(set_attr "length" "8")])
 
diff --git a/gcc/testsuite/gcc.target/pru/bitop-di.c 
b/gcc/testsuite/gcc.target/pru/bitop-di.c
new file mode 100644
index 000..4290cdbc759
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/bitop-di.c
@@ -0,0 +1,25 @@
+/* 64-bit logical bit operations.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+unsigned long long
+test_xor_di (unsigned long long val1, unsigned long long val2)
+{
+  /* { dg-final { scan-assembler "xor\\tr14, r14, r16" } } */
+  return val1 ^ val2;
+}
+
+unsigned long long
+test_and_di (unsigned long long val1, unsigned long long val2)
+{
+  /* { dg-final { scan-assembler "and\\tr14, r14, r16" } } */
+  return val1 & val2;
+}
+
+unsigned long long
+test_ior_di (unsigned long long val1, unsigned long long val2)
+{
+  /* { dg-final { scan-assembler "or\\tr14, r14, r16" } } */
+  return val1 | val2;
+}
-- 
2.37.2

[committed] testsuite: Require int128 for gcc.dg/pr106063.c

[Dimitar Dimitrov]

Require effective target int128 for gcc.dg/pr106063.c.

Committed as obvious.

PR tree-optimization/106063

gcc/testsuite/ChangeLog:

* gcc.dg/pr106063.c: Require effective target int128.

CC: Tamar Christina 
Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/pr106063.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/pr106063.c b/gcc/testsuite/gcc.dg/pr106063.c
index b23596724f6..467b31dea62 100644
--- a/gcc/testsuite/gcc.dg/pr106063.c
+++ b/gcc/testsuite/gcc.dg/pr106063.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target int128 } } */
 /* { dg-options "-O2 -fno-tree-forwprop --disable-tree-evrp" } */
 typedef __int128 __attribute__((__vector_size__ (16))) V;
 
-- 
2.36.1

[PATCH v2] testsuite: Add new target check for no_alignment_constraints

[Dimitar Dimitrov]

A few testcases were marked for avr target, which has no alignment
requirements.  But those tests in fact should filter for any
target having __BIGGEST_ALIGNMENT__=1.

A new effective target check is introduced: no_alignment_constraints.
It checks whether __BIGGEST_ALIGNMENT__ is declared as 1.

This change fixes the testsuite cases for PRU target.  I don't have
environment to test mm32c and cris targets, which also declare
__BIGGEST_ALIGNMENT__=1.

It was regression-tested on x86_64-pc-linux-gnu.

The following two existing macros were considered, but they check for
subtly different target behaviour:
 1. non_strict_align
If true, non-aligned access is permitted. But it also allows
variables to be naturally aligned, which is not true for
no_alignment_constraints.

 2. default_packed
Whether structures are packed by default is not necessarily
the same as lacking constraints for non-aggregate types.
For example, BIGGEST_FIELD_ALIGNMENT or ADJUST_FIELD_ALIGN
could be defined for a target as something other than
BIGGEST_ALIGNMENT.

gcc/ChangeLog:

* doc/sourcebuild.texi: Document new no_alignment_constraints
effective target check.

gcc/testsuite/ChangeLog:

* c-c++-common/Wcast-align.c: Silence warnings for targets with
no_alignment_constraints.
* gcc.dg/c11-align-4.c: Skip for no_alignment_constraints.
* gcc.dg/strlenopt-10.c: Replace checks for avr with checks for
any target with no_alignment_constraints.
* gcc.dg/strlenopt-11.c: Ditto.
* gcc.dg/strlenopt-13.c: Ditto.
* lib/target-supports.exp
(check_effective_target_no_alignment_constraints): New.


Signed-off-by: Dimitar Dimitrov 
---
Changes since patch V1:
  - Documented the new check in gcc/doc/sourcebuild.texi.

 gcc/doc/sourcebuild.texi |  9 +
 gcc/testsuite/c-c++-common/Wcast-align.c |  4 ++--
 gcc/testsuite/gcc.dg/c11-align-4.c   |  2 +-
 gcc/testsuite/gcc.dg/strlenopt-10.c  |  6 +++---
 gcc/testsuite/gcc.dg/strlenopt-11.c  | 14 +++---
 gcc/testsuite/gcc.dg/strlenopt-13.c  | 16 
 gcc/testsuite/lib/target-supports.exp| 13 +
 7 files changed, 43 insertions(+), 21 deletions(-)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 3696a58fbf2..760ff9559a6 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2716,6 +2716,7 @@ Target supports @option{-branch-cost=N}.
 Target uses @code{__cxa_atexit}.
 
 @item default_packed
+@anchor{default_packed}
 Target has packed layout of structure members by default.
 
 @item exceptions
@@ -2786,6 +2787,14 @@ Target uses natural alignment (aligned to type size) for 
types of
 Target uses natural alignment (aligned to type size) for types of
 64 bits or less.
 
+@item no_alignment_constraints
+Target defines __BIGGEST_ALIGNMENT__=1.  Hence target imposes
+no alignment constraints.  This is similar, but not necessarily
+the same as @ref{default_packed}.  Although @code{BIGGEST_FIELD_ALIGNMENT}
+defaults to @code{BIGGEST_ALIGNMENT} for most targets, it is possible
+for a target to set those two with different values and have different
+alignment constraints for aggregate and non-aggregate types.
+
 @item noinit
 Target supports the @code{noinit} variable attribute.
 
diff --git a/gcc/testsuite/c-c++-common/Wcast-align.c 
b/gcc/testsuite/c-c++-common/Wcast-align.c
index c296c7fd249..1087b10fd99 100644
--- a/gcc/testsuite/c-c++-common/Wcast-align.c
+++ b/gcc/testsuite/c-c++-common/Wcast-align.c
@@ -16,8 +16,8 @@ struct t { double x; } *q;
 void
 foo (void)
 {
-  y = (c *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" } */
-  z = (d *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" } */
+  y = (c *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" "" { target { ! no_alignment_constraints } } } */
+  z = (d *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" "" { target { ! no_alignment_constraints } } } */
   (long long *) p;  /* { dg-bogus "alignment" } */
   (double *) q; /* { dg-bogus "alignment" } */
 }
diff --git a/gcc/testsuite/gcc.dg/c11-align-4.c 
b/gcc/testsuite/gcc.dg/c11-align-4.c
index 57f93ff05fc..eb9071b9149 100644
--- a/gcc/testsuite/gcc.dg/c11-align-4.c
+++ b/gcc/testsuite/gcc.dg/c11-align-4.c
@@ -2,7 +2,7 @@
are at least some alignment constraints).  */
 /* { dg-do compile } */
 /* { dg-options "-std=c11 -pedantic-errors" } */
-/* { dg-skip-if "no alignment constraints" { "avr-*-*" } } */
+/* { dg-skip-if "no alignment constraints" { no_alignment_constraints } } */
 
 #include 
 
diff --git a/gcc/testsuite/gcc.dg/strlenopt-10.c 
b/gcc/testsuite/gcc.dg/strlenopt-10.c
index ce959c34a80..6e2c2597b27 100644
--- a/gcc/testsuite/gcc.dg/strleno

Re: [PATCH] testsuite: Add new target check for no_alignment_constraints

[Dimitar Dimitrov]

On Fri, Jun 24, 2022 at 08:58:49AM +0200, Richard Biener wrote:
> On Fri, Jun 24, 2022 at 2:34 AM Andrew Pinski via Gcc-patches
>  wrote:
> >
> > On Thu, Jun 23, 2022 at 2:24 PM Dimitar Dimitrov  wrote:
> > >
> > > A few testcases were marked for avr target, which has no alignment
> > > requirements.  But those tests in fact should filter for any
> > > target having __BIGGEST_ALIGNMENT__=1.
> > >
> > > A new effective target check is introduced: no_alignment_constraints.
> > > It checks whether __BIGGEST_ALIGNMENT__ is declared as 1.
> > >
> > > Alternative names I considered for the new macro are:
> > >   - !natural_alignment_16
> > >   - biggest_alignment_1
> > >
> > > This change fixes the testsuite cases for PRU target.  I don't have
> > > environment to test mm32c and cris targets, which also declare
> > > __BIGGEST_ALIGNMENT__=1.
> > >
> > > It was regression-tested on x86_64-pc-linux-gnu.
> > >
> > > The following two existing macros were considered, but they check for
> > > subtly different target behaviour:
> > >  1. non_strict_align
> > > If true, non-aligned access is permitted. But it also allows
> > > variables to be naturally aligned, which is not true for
> > > no_alignment_constraints.
> > >
> > >  2. default_packed
> > > Whether structures are packed by default is not necessarily
> > > the same as lacking constraints for any variable alignment.
> > > For example, BIGGEST_FIELD_ALIGNMENT or ADJUST_FIELD_ALIGN
> > > could be defined for a target.
> > >
> > > Ok for trunk?
> >
> > How is no_alignment_constraints different from default_packed? I
> > suspect they have the same effect really.
> 
> Different when non-aggregates are involved?  Does default_packed
> also apply to scalar types?

It is my understanding that aggregates and scalars could have
different alignment constraints.

For example, consider the following target settings combination, which I
found in the vax backend:

#define BIGGEST_ALIGNMENT 32
#define BIGGEST_FIELD_ALIGNMENT 8

I made an experiment and hacked pru-unknonwn-elf with the above change.
This resulted in:

  default_packed=1
  no_alignment_constraints=0

> 
> Btw, new effective targets should be documented in sourcebuild.texi

I'll fix and post a new version.

Thanks,
Dimitar

> 
> Richard.
> 
> > Thanks,
> > Andrew
> >
> > >
> > > Signed-off-by: Dimitar Dimitrov 
> > > ---
> > >  gcc/testsuite/c-c++-common/Wcast-align.c |  4 ++--
> > >  gcc/testsuite/gcc.dg/c11-align-4.c   |  2 +-
> > >  gcc/testsuite/gcc.dg/strlenopt-10.c  |  6 +++---
> > >  gcc/testsuite/gcc.dg/strlenopt-11.c  | 14 +++---
> > >  gcc/testsuite/gcc.dg/strlenopt-13.c  | 16 
> > >  gcc/testsuite/lib/target-supports.exp| 13 +
> > >  6 files changed, 34 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/gcc/testsuite/c-c++-common/Wcast-align.c 
> > > b/gcc/testsuite/c-c++-common/Wcast-align.c
> > > index c296c7fd249..1087b10fd99 100644
> > > --- a/gcc/testsuite/c-c++-common/Wcast-align.c
> > > +++ b/gcc/testsuite/c-c++-common/Wcast-align.c
> > > @@ -16,8 +16,8 @@ struct t { double x; } *q;
> > >  void
> > >  foo (void)
> > >  {
> > > -  y = (c *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of 
> > > target type" } */
> > > -  z = (d *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of 
> > > target type" } */
> > > +  y = (c *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of 
> > > target type" "" { target { ! no_alignment_constraints } } } */
> > > +  z = (d *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of 
> > > target type" "" { target { ! no_alignment_constraints } } } */
> > >(long long *) p;  /* { dg-bogus "alignment" } */
> > >(double *) q; /* { dg-bogus "alignment" } */
> > >  }
> > > diff --git a/gcc/testsuite/gcc.dg/c11-align-4.c 
> > > b/gcc/testsuite/gcc.dg/c11-align-4.c
> > > index 57f93ff05fc..eb9071b9149 100644
> > > --- a/gcc/testsuite/gcc.dg/c11-align-4.c
> > > +++ b/gcc/testsuite/gcc.dg/c11-align-4.c
> > > @@ -2,7 +2,7 @@
> > > are at least some alignment constraints).  */
> > >  /* { dg-do compile } */
> > >  /* { dg-option

[PATCH] testsuite: Add new target check for no_alignment_constraints

[Dimitar Dimitrov]

A few testcases were marked for avr target, which has no alignment
requirements.  But those tests in fact should filter for any
target having __BIGGEST_ALIGNMENT__=1.

A new effective target check is introduced: no_alignment_constraints.
It checks whether __BIGGEST_ALIGNMENT__ is declared as 1.

Alternative names I considered for the new macro are:
  - !natural_alignment_16
  - biggest_alignment_1

This change fixes the testsuite cases for PRU target.  I don't have
environment to test mm32c and cris targets, which also declare
__BIGGEST_ALIGNMENT__=1.

It was regression-tested on x86_64-pc-linux-gnu.

The following two existing macros were considered, but they check for
subtly different target behaviour:
 1. non_strict_align
If true, non-aligned access is permitted. But it also allows
variables to be naturally aligned, which is not true for
no_alignment_constraints.

 2. default_packed
Whether structures are packed by default is not necessarily
the same as lacking constraints for any variable alignment.
For example, BIGGEST_FIELD_ALIGNMENT or ADJUST_FIELD_ALIGN
could be defined for a target.

Ok for trunk?

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/c-c++-common/Wcast-align.c |  4 ++--
 gcc/testsuite/gcc.dg/c11-align-4.c   |  2 +-
 gcc/testsuite/gcc.dg/strlenopt-10.c  |  6 +++---
 gcc/testsuite/gcc.dg/strlenopt-11.c  | 14 +++---
 gcc/testsuite/gcc.dg/strlenopt-13.c  | 16 
 gcc/testsuite/lib/target-supports.exp| 13 +
 6 files changed, 34 insertions(+), 21 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/Wcast-align.c 
b/gcc/testsuite/c-c++-common/Wcast-align.c
index c296c7fd249..1087b10fd99 100644
--- a/gcc/testsuite/c-c++-common/Wcast-align.c
+++ b/gcc/testsuite/c-c++-common/Wcast-align.c
@@ -16,8 +16,8 @@ struct t { double x; } *q;
 void
 foo (void)
 {
-  y = (c *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" } */
-  z = (d *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" } */
+  y = (c *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" "" { target { ! no_alignment_constraints } } } */
+  z = (d *) x;  /* { dg-warning "7:cast \[^\n\r]* required alignment of target 
type" "" { target { ! no_alignment_constraints } } } */
   (long long *) p;  /* { dg-bogus "alignment" } */
   (double *) q; /* { dg-bogus "alignment" } */
 }
diff --git a/gcc/testsuite/gcc.dg/c11-align-4.c 
b/gcc/testsuite/gcc.dg/c11-align-4.c
index 57f93ff05fc..eb9071b9149 100644
--- a/gcc/testsuite/gcc.dg/c11-align-4.c
+++ b/gcc/testsuite/gcc.dg/c11-align-4.c
@@ -2,7 +2,7 @@
are at least some alignment constraints).  */
 /* { dg-do compile } */
 /* { dg-options "-std=c11 -pedantic-errors" } */
-/* { dg-skip-if "no alignment constraints" { "avr-*-*" } } */
+/* { dg-skip-if "no alignment constraints" { no_alignment_constraints } } */
 
 #include 
 
diff --git a/gcc/testsuite/gcc.dg/strlenopt-10.c 
b/gcc/testsuite/gcc.dg/strlenopt-10.c
index ce959c34a80..6e2c2597b27 100644
--- a/gcc/testsuite/gcc.dg/strlenopt-10.c
+++ b/gcc/testsuite/gcc.dg/strlenopt-10.c
@@ -70,10 +70,10 @@ main ()
 }
 
 /* { dg-final { scan-tree-dump-times "strlen \\(" 2 "strlen1" } } */
-/* avr has BIGGEST_ALIGNMENT 8, allowing fold_builtin_memory_op
+/* Some targets have BIGGEST_ALIGNMENT 8-bits, allowing fold_builtin_memory_op
to expand the memcpy call at the end of fn2.  */
-/* { dg-final { scan-tree-dump-times "memcpy \\(" 8 "strlen1" { target { ! 
avr-*-* } } } } */
-/* { dg-final { scan-tree-dump-times "memcpy \\(" 7 "strlen1" { target { 
avr-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "memcpy \\(" 8 "strlen1" { target { ! 
no_alignment_constraints } } } } */
+/* { dg-final { scan-tree-dump-times "memcpy \\(" 7 "strlen1" { target { 
no_alignment_constraints} } } } */
 /* { dg-final { scan-tree-dump-times "strcpy \\(" 0 "strlen1" } } */
 /* { dg-final { scan-tree-dump-times "strcat \\(" 0 "strlen1" } } */
 /* { dg-final { scan-tree-dump-times "strchr \\(" 0 "strlen1" } } */
diff --git a/gcc/testsuite/gcc.dg/strlenopt-11.c 
b/gcc/testsuite/gcc.dg/strlenopt-11.c
index abd9faebed6..952de0730f1 100644
--- a/gcc/testsuite/gcc.dg/strlenopt-11.c
+++ b/gcc/testsuite/gcc.dg/strlenopt-11.c
@@ -59,17 +59,17 @@ main ()
 }
 
 /* { dg-final { scan-tree-dump-times "strlen \\(" 3 "strlen1" } } */
-/* avr has BIGGEST_ALIGNMENT 8, allowing fold_builtin_memory_op
+/* Some targets have BIGGEST_ALIGNMENT 8-bits, allowing fold_builtin_memory_op
to expand the memcpy call at the end of fn1.  */
-/* { dg-final { scan-tree-dump-times "memcpy \\(" 7 "strlen1" { target { ! 
avr-*

[PATCH] testsuite: Handle default_packed for gcc.dg/builtin-object-size-20.c

[Dimitar Dimitrov]

The gcc.dg/builtin-object-size-20.c test case assumes that the target
inserts padding between structure members.  Obviously it fails for
targets which pack structures by default.

Split the cases into two tests, so that the ones requiring structure
padding can be skipped for default_packed targets.

Ok for trunk?

gcc/testsuite/ChangeLog:

* gcc.dg/builtin-object-size-20.c: Remove cases which
work on default_packed targets.
* gcc.dg/builtin-object-size-22.c: New test with the cases
removed above.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/builtin-object-size-20.c | 64 +--
 gcc/testsuite/gcc.dg/builtin-object-size-22.c | 79 +++
 2 files changed, 81 insertions(+), 62 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-22.c

diff --git a/gcc/testsuite/gcc.dg/builtin-object-size-20.c 
b/gcc/testsuite/gcc.dg/builtin-object-size-20.c
index bed973c2c77..f40e3dcc1a9 100644
--- a/gcc/testsuite/gcc.dg/builtin-object-size-20.c
+++ b/gcc/testsuite/gcc.dg/builtin-object-size-20.c
@@ -1,7 +1,8 @@
 /* PR middle-end/92815 - spurious -Wstringop-overflow writing into
a flexible array of an extern struct
{ dg-do compile }
-   { dg-options "-O -Wall -fdump-tree-optimized" } */
+   { dg-options "-O -Wall -fdump-tree-optimized" }
+   { dg-skip-if "test assumes that structs have padding" { default_packed } } 
*/
 
 #define ASSERT(expr) ((expr) ? (void)0 : fail (__LINE__))
 #define bos0(expr) __builtin_object_size (expr, 1)
@@ -18,44 +19,6 @@ typedef __SIZE_TYPE__  size_t;
 extern void fail (int);
 
 
-/* Verify sizes of a struct with a flexible array member and no padding.  */
-
-struct ACX { char n, a[]; };
-
-struct ACX ac0 = { };
-struct ACX ac1 = { 1, { 1 } };
-struct ACX ac2 = { 2, { 1, 2 } };
-struct ACX ac3 = { 3, { 1, 2, 3 } };
-
-extern struct ACX eacx;
-
-void facx (void)
-{
-  ASSERT (bos0 () == sizeof ac0);
-  ASSERT (bos0 () == 2);
-  ASSERT (bos0 () == 3);
-  ASSERT (bos0 () == 4);
-  ASSERT (bos0 () == (size_t)-1);
-
-  ASSERT (bos1 () == sizeof ac0);
-  ASSERT (bos1 () == 2);
-  ASSERT (bos1 () == 3);
-  ASSERT (bos1 () == 4);
-  ASSERT (bos1 () == (size_t)-1);
-
-  ASSERT (bos2 () == sizeof ac0);
-  ASSERT (bos2 () == 2);
-  ASSERT (bos2 () == 3);
-  ASSERT (bos2 () == 4);
-  ASSERT (bos2 () == sizeof eacx);
-
-  ASSERT (bos3 () == sizeof ac0);
-  ASSERT (bos3 () == 2);
-  ASSERT (bos3 () == 3);
-  ASSERT (bos3 () == 4);
-  ASSERT (bos3 () == sizeof eacx);
-}
-
 
 
 /* Verify sizes of a struct with a flexible array member and 1 byte
@@ -289,27 +252,4 @@ void fai64cx (void)
   ASSERT (bos3 () == sizeof eai64cx);
 }
 
-
-/* Also verify sizes of a struct with a zero length array member.  */
-
-struct A0C0 { char n, a[0]; };
-
-struct A0C0 a0c0 = { };
-extern struct A0C0 ea0c0;
-
-void fa0c0 (void)
-{
-  ASSERT (bos0 () == sizeof a0c0);
-  ASSERT (bos0 () == sizeof ea0c0);
-
-  ASSERT (bos1 () == sizeof a0c0);
-  ASSERT (bos1 () == sizeof ea0c0);
-
-  ASSERT (bos2 () == sizeof a0c0);
-  ASSERT (bos2 () == sizeof ea0c0);
-
-  ASSERT (bos3 () == sizeof a0c0);
-  ASSERT (bos3 () == sizeof ea0c0);
-}
-
 /* { dg-final { scan-tree-dump-not "fail" "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/builtin-object-size-22.c 
b/gcc/testsuite/gcc.dg/builtin-object-size-22.c
new file mode 100644
index 000..1e55229c949
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/builtin-object-size-22.c
@@ -0,0 +1,79 @@
+/* PR middle-end/92815 - a variant of gcc.dg/builtin-object-size-20.c
+   prepared for all targets, irregardless if they pack or not
+   the structs by default.
+   { dg-do compile }
+   { dg-options "-O -Wall -fdump-tree-optimized" } */
+
+#define ASSERT(expr) ((expr) ? (void)0 : fail (__LINE__))
+#define bos0(expr) __builtin_object_size (expr, 1)
+#define bos1(expr) __builtin_object_size (expr, 1)
+#define bos2(expr) __builtin_object_size (expr, 2)
+#define bos3(expr) __builtin_object_size (expr, 3)
+
+typedef __SIZE_TYPE__  size_t;
+
+
+extern void fail (int);
+
+
+/* Verify sizes of a struct with a flexible array member and no padding.  */
+
+struct ACX { char n, a[]; };
+
+struct ACX ac0 = { };
+struct ACX ac1 = { 1, { 1 } };
+struct ACX ac2 = { 2, { 1, 2 } };
+struct ACX ac3 = { 3, { 1, 2, 3 } };
+
+extern struct ACX eacx;
+
+void facx (void)
+{
+  ASSERT (bos0 () == sizeof ac0);
+  ASSERT (bos0 () == 2);
+  ASSERT (bos0 () == 3);
+  ASSERT (bos0 () == 4);
+  ASSERT (bos0 () == (size_t)-1);
+
+  ASSERT (bos1 () == sizeof ac0);
+  ASSERT (bos1 () == 2);
+  ASSERT (bos1 () == 3);
+  ASSERT (bos1 () == 4);
+  ASSERT (bos1 () == (size_t)-1);
+
+  ASSERT (bos2 () == sizeof ac0);
+  ASSERT (bos2 () == 2);
+  ASSERT (bos2 () == 3);
+  ASSERT (bos2 () == 4);
+  ASSERT (bos2 () == sizeof eacx);
+
+  ASSERT (bos3 () == sizeof ac0);
+  ASSERT (bos3 () == 2);
+  ASSERT (bos3 () == 3);
+  ASSERT (bos3 () == 4);
+  ASSERT (bos3 () == sizeof eacx);
+}
+
+/* A

[PATCH] testsuite: Rename test-defined macros

[Dimitar Dimitrov]

Epiphany, PRU, ARC and NDS32 may predefine __big_endian__ and
__little_endian__ macros.  This leads to spurious warnings like:
  gcc.dg/sso/memcpy-1.c:7: warning: "__little_endian__" redefined

Fix by renaming the macros in the test.

Ok for trunk?

gcc/testsuite/ChangeLog:

* gcc.dg/sso/memcpy-1.c (__big_endian__, __little_endian__):
Rename macros to avoid conflicts with predefined ones.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/sso/memcpy-1.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/sso/memcpy-1.c 
b/gcc/testsuite/gcc.dg/sso/memcpy-1.c
index b4e1c8786d9..0dea955cbaf 100644
--- a/gcc/testsuite/gcc.dg/sso/memcpy-1.c
+++ b/gcc/testsuite/gcc.dg/sso/memcpy-1.c
@@ -3,20 +3,20 @@
 typedef unsigned char uint8_t;
 typedef unsigned int uint32_t;
 
-#define __big_endian__ scalar_storage_order("big-endian")
-#define __little_endian__ scalar_storage_order("little-endian")
+#define __big_endian_attr__ scalar_storage_order("big-endian")
+#define __little_endian_attr__ scalar_storage_order("little-endian")
 
 typedef union
 {
   uint32_t val;
   uint8_t v[4];
-} __attribute__((__big_endian__)) upal_u32be_t;
+} __attribute__((__big_endian_attr__)) upal_u32be_t;
 
 typedef union
 {
   uint32_t val;
   uint8_t v[4];
-} __attribute__((__little_endian__)) upal_u32le_t;
+} __attribute__((__little_endian_attr__)) upal_u32le_t;
 
 static inline uint32_t native_to_big_endian(uint32_t t)
 {
-- 
2.36.1

[PATCH] testsuite: Remove reliance on argc in lto/pr101868_0.c

[Dimitar Dimitrov]

Some embedded targets do not pass any argv arguments.  When argc is
zero, this causes spurious failures for lto/pr101868_0.c.  Fix by
following the strategy in r0-114701-g2c49569ecea56d.  Use a volatile
variable instead of argc to inject a runtime value into the test.

I validated the following:
  - No changes in testresults for x86_64-pc-linux-gnu.
  - The spurious failures are fixed for PRU target.
  - lto/pr101868_0.c still fails on x86_64-pc-linux-gnu, if
the PR/101868 fix (r12-2254-gfedcf3c476aff7) is reverted.

Ok for trunk?

PR tree-optimization/101868

gcc/testsuite/ChangeLog:

* gcc.dg/lto/pr101868_0.c (zero): New volatile variable.
(main): Use it instead of argc.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/lto/pr101868_0.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/lto/pr101868_0.c 
b/gcc/testsuite/gcc.dg/lto/pr101868_0.c
index c84d19b0267..03124308267 100644
--- a/gcc/testsuite/gcc.dg/lto/pr101868_0.c
+++ b/gcc/testsuite/gcc.dg/lto/pr101868_0.c
@@ -22,12 +22,13 @@ repro(VALUE dummy, VALUE hash)
 
 static VALUE (*that)(VALUE dummy, VALUE hash) = repro;
 
+volatile int zero = 0;
+
 int
 main(int argc, char **argv)
 {
-argc--;
-that(0, argc);
+that(0, zero);
 
-rb_check_type(argc, argc);
+rb_check_type(zero, zero);
 
 }
-- 
2.36.1

[PATCH] testsuite: Skip btf-bitfields-1.c if int is less than 32-bits

[Dimitar Dimitrov]

This test spuriously fails on AVR with:
   error: width of 'bitfield_c' exceeds its type

8-bit and 16-bit microcontrollers do not seem to be the target audience
for BTF file format.  So the least intrusive fix is to simply skip the
test for them.

Ok for trunk?

gcc/testsuite/ChangeLog:

* gcc.dg/debug/btf/btf-bitfields-1.c: Skip if int is less than
32-bits.

CC: Jose E. Marchesi 
Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c 
b/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c
index 4cb7ee84f83..793b4c8db82 100644
--- a/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c
+++ b/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c
@@ -10,6 +10,7 @@
 
 /* { dg-do compile )  */
 /* { dg-options "-O0 -gbtf -dA" } */
+/* { dg-require-effective-target int32plus } */
 
 /* { dg-final { scan-assembler-times "\[\t \]0x8404\[\t 
\]+\[^\n\]*btt_info" 1 } } */
 
-- 
2.36.1

[PATCH] testsuite: Adjust btf-bitfields-1.c for default_packed

[Dimitar Dimitrov]

If target packs structures by default, the bitfield offset which the
tests validates must be adjusted to not include padding.

Ok for trunk?

gcc/testsuite/ChangeLog:

* gcc.dg/debug/btf/btf-bitfields-1.c: Adjust the checked offsets
for targets which pack structures by default.

CC: Jose E. Marchesi 
Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c 
b/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c
index c6bf52130dc..4cb7ee84f83 100644
--- a/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c
+++ b/gcc/testsuite/gcc.dg/debug/btf/btf-bitfields-1.c
@@ -5,7 +5,8 @@
  (bit_size << 24) | bit_offset
  - (0xa  << 24) | 0x20
  - (0x7  << 24) | 0x2a
- - (0x13 << 24) | 0x40 - note that this is aligned to 0x40.  */
+ - (0x13 << 24) | 0x40 - note that this is aligned to 0x40.
+ - (0x13 << 24) | 0x31 - in case structures are packed.  */
 
 /* { dg-do compile )  */
 /* { dg-options "-O0 -gbtf -dA" } */
@@ -14,7 +15,8 @@
 
 /* { dg-final { scan-assembler-times "\[\t \]0xa20\[\t 
\]+\[^\n\]*btm_offset" 1 } } */
 /* { dg-final { scan-assembler-times "\[\t \]0x72a\[\t 
\]+\[^\n\]*btm_offset" 1 } } */
-/* { dg-final { scan-assembler-times "\[\t \]0x1340\[\t 
\]+\[^\n\]*btm_offset" 1 } } */
+/* { dg-final { scan-assembler-times "\[\t \]0x1340\[\t 
\]+\[^\n\]*btm_offset" 1 { target { ! default_packed } } } } */
+/* { dg-final { scan-assembler-times "\[\t \]0x1331\[\t 
\]+\[^\n\]*btm_offset" 1 { target { default_packed } } } } */
 
 struct bitt {
   int a;
-- 
2.36.1

[committed] testsuite: Skip vectorize tests for PRU

[Dimitar Dimitrov]

PRU has single-cycle constant cost for any jump, and it cannot
vectorise.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/gen-vect-11.c: For PRU target, skip the
vectorizing checks in tree dumps.
* gcc.dg/tree-ssa/gen-vect-11a.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-2.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-25.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-26.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-28.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-32.c: Ditto.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c  | 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c | 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c   | 4 ++--
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c  | 4 ++--
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c  | 6 +++---
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c  | 6 +++---
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c  | 4 ++--
 7 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c 
b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c
index dd1c0ac3eba..6916843f397 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c
@@ -34,4 +34,4 @@ int main ()
 }
 
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! { avr-*-* msp430-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! { avr-*-* msp430-*-* pru-*-* } } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c 
b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c
index e2fb3623614..6326bf75ab0 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c
@@ -38,4 +38,4 @@ int main ()
 }
 
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! avr-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! { avr-*-* pru-*-* } } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c 
b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c
index 42171a2fbf3..b84f3184427 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c
@@ -36,5 +36,5 @@ int main ()
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! avr-*-* } } } } */
-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 
"vect" { target { ! avr-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! { avr-*-* pru-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 
"vect" { target { ! { avr-*-* pru-*-* } } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c 
b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c
index 60ec27054b6..18fe1aa1502 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c
@@ -54,5 +54,5 @@ int main (void)
   return main_1 (n + 2, (int *) );
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { 
! { avr-*-* msp430-*-* } } } } } */
-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 
"vect" { target { ! { avr-*-* msp430-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { 
! { avr-*-* msp430-*-* pru-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 
"vect" { target { ! { avr-*-* msp430-*-* pru-*-* } } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c 
b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c
index 6f3c2b7d88a..710696198bb 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c
@@ -29,7 +29,7 @@ int main ()
 }
 
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! avr-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { 
! { avr-*-* pru-*-* } } } } } */
 /* IBM Z does not require special alignment for vectorization.  */
-/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 
"vect" { target { ! { avr-*-* s390*-*-* } } } } } */
-/* { dg-final { scan-tree-dump-times "Alignment of access forced using 
peeling" 1 "vect" { target { ! { avr-*-* s390*-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 
"vect" { target { ! { avr-*-* pru-*-* s390*-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using 
peeling" 1 "vect" { target { ! { avr-*-* pru-*

[committed] testsuite: Adjust pr91088.c for default_packed targets

[Dimitar Dimitrov]

Committed as obvious.

PR ipa/91088

gcc/testsuite/ChangeLog:

* gcc.dg/ipa/pr91088.c: Adjust member offset checks to
accommodate targets which pack structures by default.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/ipa/pr91088.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/ipa/pr91088.c 
b/gcc/testsuite/gcc.dg/ipa/pr91088.c
index cc146a88134..f8b3c49b973 100644
--- a/gcc/testsuite/gcc.dg/ipa/pr91088.c
+++ b/gcc/testsuite/gcc.dg/ipa/pr91088.c
@@ -115,6 +115,7 @@ int caller ()
 /* { dg-final { scan-ipa-dump-times "Creating a specialized node of callee1" 1 
"cp" } } */
 /* { dg-final { scan-ipa-dump-times "Creating a specialized node of callee2" 1 
"cp" } } */
 /* { dg-final { scan-ipa-dump-times "Creating a specialized node of callee3" 1 
"cp" } } */
-/* { dg-final { scan-ipa-dump "op0\\\[offset: 32],\\(\\(short int\\) 
#\\),\\(\\(int\\) #\\),\\(1300 / #\\) == 19" "cp" } } */
+/* { dg-final { scan-ipa-dump "op0\\\[offset: 16],\\(\\(short int\\) 
#\\),\\(\\(int\\) #\\),\\(1300 / #\\) == 19" "cp" { target default_packed } } } 
*/
+/* { dg-final { scan-ipa-dump "op0\\\[offset: 32],\\(\\(short int\\) 
#\\),\\(\\(int\\) #\\),\\(1300 / #\\) == 19" "cp" { target { ! default_packed } 
} } } */
 /* { dg-final { scan-ipa-dump "op0\\\[ref offset: 0],\\(# \\^ 1\\) <" "cp" } } 
*/
 /* { dg-final { scan-ipa-dump "op0,\\(# & 255\\),\\(1 - #\\),\\(# \\* 
3\\),\\(27 % #\\) <" "cp" } } */
-- 
2.36.1

[committed] testsuite: Skip gcc.dg/pr46647.c for PRU

[Dimitar Dimitrov]

Like AVR and Cris, PRU has no alignment requirements.  Thus it is
also affected by PR53535.

PR middle-end/53535

gcc/testsuite/ChangeLog:

* gcc.dg/pr46647.c: Skip for pru target.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/pr46647.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/pr46647.c b/gcc/testsuite/gcc.dg/pr46647.c
index 7eefc6e336a..a903273fc9d 100644
--- a/gcc/testsuite/gcc.dg/pr46647.c
+++ b/gcc/testsuite/gcc.dg/pr46647.c
@@ -25,5 +25,5 @@ func3 (void)
   return 0;
 }
 
-/* The xfail for avr and cris-* is due to PR53535.  */
-/* { dg-final { scan-tree-dump-not "memset" "optimized" { xfail avr-*-* 
cris-*-* } } } */
+/* The xfail for avr, cris-* and pru is due to PR53535.  */
+/* { dg-final { scan-tree-dump-not "memset" "optimized" { xfail avr-*-* 
cris-*-* pru-*-* } } } */
-- 
2.36.1

[committed] testsuite: Skip ifcvt-4.c for PRU

[Dimitar Dimitrov]

PRU has no condition code and conditional moves.

gcc/testsuite/ChangeLog:

* gcc.dg/ifcvt-4.c: Skip for PRU.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/ifcvt-4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/ifcvt-4.c b/gcc/testsuite/gcc.dg/ifcvt-4.c
index 37aa76a0d1b..46245f0d069 100644
--- a/gcc/testsuite/gcc.dg/ifcvt-4.c
+++ b/gcc/testsuite/gcc.dg/ifcvt-4.c
@@ -2,7 +2,7 @@
 /* { dg-additional-options "-misel" { target { powerpc*-*-* } } } */
 /* { dg-additional-options "-march=z196" { target { s390x-*-* } } } */
 /* { dg-additional-options "-mtune-ctrl=^one_if_conv_insn" { target { i?86-*-* 
x86_64-*-* } } } */
-/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" 
{ "arm*-*-* avr-*-* hppa*64*-*-* visium-*-*" riscv*-*-* msp430-*-* nios2-*-*} } 
 */
+/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" 
{ "arm*-*-* avr-*-* hppa*64*-*-* visium-*-*" riscv*-*-* msp430-*-* nios2-*-* 
pru-*-* } }  */
 /* { dg-skip-if "" { "s390x-*-*" } { "-m31" } }  */
 
 typedef int word __attribute__((mode(word)));
-- 
2.36.1

[committed] testsuite: Mark extra warnings for default_packed

[Dimitar Dimitrov]

If the target uses packed structs by default, there are no trailing
padding bytes allocated.  Hence extra warnings are emitted.

Committed as obvious.

gcc/testsuite/ChangeLog:

* gcc.dg/Warray-bounds-48-novec.c: Add expected warnings
if target packs the structs by default.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/Warray-bounds-48-novec.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/Warray-bounds-48-novec.c 
b/gcc/testsuite/gcc.dg/Warray-bounds-48-novec.c
index da179a2c0f5..5cae8566209 100644
--- a/gcc/testsuite/gcc.dg/Warray-bounds-48-novec.c
+++ b/gcc/testsuite/gcc.dg/Warray-bounds-48-novec.c
@@ -238,15 +238,17 @@ static void warn_a1_init (struct A1 *p)
 
 static void warn_a1_local_buf (struct A1 *p)
 {
-  p->a1[0] = 0; p->a1[1] = 1; p->a1[2] = 2; p->a1[3] = 3;
+  p->a1[0] = 0; p->a1[1] = 1; p->a1[2] = 2;
 
+  p->a1[3] = 3;// { dg-warning "\\\[-Warray-bounds" "" { target 
default_packed } }
   p->a1[4] = 4; // { dg-warning "\\\[-Warray-bounds" }
 }
 
 static void warn_a1_extern_buf (struct A1 *p)
 {
-  p->a1[0] = 0; p->a1[1] = 1; p->a1[2] = 2; p->a1[3] = 3; p->a1[4] = 4;
+  p->a1[0] = 0; p->a1[1] = 1; p->a1[2] = 2; p->a1[3] = 3;
 
+  p->a1[4] = 4;// { dg-warning "\\\[-Warray-bounds" "" { target 
default_packed } }
   p->a1[5] = 5; // { dg-warning "\\\[-Warray-bounds" }
 }
 
-- 
2.36.1

Re: [PATCH] testsuite: mallign: Handle word size of 1 byte

[Dimitar Dimitrov]

On Sun, May 08, 2022 at 10:31:04AM +0300, Dimitar Dimitrov wrote:
> This patch fixes a spurious warning for pru-unknown-elf target:
>   gcc/testsuite/gcc.dg/mallign.c:12:27: warning: ignoring return value of 
> 'malloc' declared with attribute 'warn_unused_result' [-Wunused-result]
> 
> For 8-bit targets the resulting mask ignores all bits in the value
> returned by malloc.  Fix by first checking the target word size.
> 
> Sanity checked that there are no new failures on x86_64-pc-linux-gnu.
> 
> Ok for trunk?

Ping. Does this count as an obvious fix?

> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.dg/mallign.c: Skip check if sizeof(word)==1.
> 
> Signed-off-by: Dimitar Dimitrov 
> ---
>  gcc/testsuite/gcc.dg/mallign.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/testsuite/gcc.dg/mallign.c b/gcc/testsuite/gcc.dg/mallign.c
> index 349cdaa343f..9a18a00c3b0 100644
> --- a/gcc/testsuite/gcc.dg/mallign.c
> +++ b/gcc/testsuite/gcc.dg/mallign.c
> @@ -9,7 +9,7 @@ typedef int word __attribute__((mode(word)));
>  
>  int main()
>  {
> -if ((__UINTPTR_TYPE__)malloc (1) & (sizeof(word)-1))
> +if ((sizeof(word)>1) && ((__UINTPTR_TYPE__)malloc (1) & 
> (sizeof(word)-1)))
>   abort ();
>  return 0;
>  }
>   
> -- 
> 2.35.1
> 

[PATCH] testsuite: mallign: Handle word size of 1 byte

[Dimitar Dimitrov]

This patch fixes a spurious warning for pru-unknown-elf target:
  gcc/testsuite/gcc.dg/mallign.c:12:27: warning: ignoring return value of 
'malloc' declared with attribute 'warn_unused_result' [-Wunused-result]

For 8-bit targets the resulting mask ignores all bits in the value
returned by malloc.  Fix by first checking the target word size.

Sanity checked that there are no new failures on x86_64-pc-linux-gnu.

Ok for trunk?

gcc/testsuite/ChangeLog:

* gcc.dg/mallign.c: Skip check if sizeof(word)==1.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/mallign.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/mallign.c b/gcc/testsuite/gcc.dg/mallign.c
index 349cdaa343f..9a18a00c3b0 100644
--- a/gcc/testsuite/gcc.dg/mallign.c
+++ b/gcc/testsuite/gcc.dg/mallign.c
@@ -9,7 +9,7 @@ typedef int word __attribute__((mode(word)));
 
 int main()
 {
-if ((__UINTPTR_TYPE__)malloc (1) & (sizeof(word)-1))
+if ((sizeof(word)>1) && ((__UINTPTR_TYPE__)malloc (1) & (sizeof(word)-1)))
abort ();
 return 0;
 }  
-- 
2.35.1

[PATCH] testsuite: Silence analyzer/pr51628-30.c for default_packed

[Dimitar Dimitrov]

On default_packed targets like PRU, a warning in the file included from
analyzer/pr51628-30.c is reported as spurious one, even though it has been
annotated there:

  Excess errors:
  
gcc/gcc/testsuite/gcc.dg/analyzer/torture/../../../c-c++-common/pr51628-30.c:7:19:
 warning: 'packed' attribute ignored for field of type 'struct B' [-Wattributes]

DejaGnu does not preprocess the C test case sources.  Hence the "dg-*"
statements in included files are ignored.

Mark that gcc.dg/analyzer/torture/pr51628-30.c generates excess warnings
for default_packed targets.  This is safe because the original test case
covered an ICE, not a diagnostic error.

Ok for trunk?

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/torture/pr51628-30.c: Test can spill excess
errors for default_packed targets.

CC: David Malcolm 
Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/analyzer/torture/pr51628-30.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/analyzer/torture/pr51628-30.c 
b/gcc/testsuite/gcc.dg/analyzer/torture/pr51628-30.c
index 4513e0f890c..abc13413f2b 100644
--- a/gcc/testsuite/gcc.dg/analyzer/torture/pr51628-30.c
+++ b/gcc/testsuite/gcc.dg/analyzer/torture/pr51628-30.c
@@ -1,3 +1,4 @@
 /* { dg-additional-options "-Wno-address-of-packed-member" } */
+/* { dg-excess-errors "warnings about ignored 'packed' attribute" { target 
default_packed } } */
 
 #include "../../../c-c++-common/pr51628-30.c"
-- 
2.35.1

[PATCH][committed] testsuite: libgcc function name for PRU

[Dimitar Dimitrov]

Update the match rules to accommodate the non-standard libgcc function
names for PRU backend.  The C6x target also seems to be affected, and
should be fixed with this change, but there is no free simulator for me
to check.

Sanity checked that there are no new failures on x86_64-pc-linux-gnu.

gcc/testsuite/ChangeLog:

* gcc.c-torture/compile/attr-complex-method-2.c: Accept both __divdc3
and __gnu_divdc3 as valid libgcc function names.
* gcc.dg/complex-6.c: Ditto for __mulsc3.
* gcc.dg/complex-7.c: Ditto for __muldc3.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.c-torture/compile/attr-complex-method-2.c | 2 +-
 gcc/testsuite/gcc.dg/complex-6.c| 2 +-
 gcc/testsuite/gcc.dg/complex-7.c| 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.c-torture/compile/attr-complex-method-2.c 
b/gcc/testsuite/gcc.c-torture/compile/attr-complex-method-2.c
index 121ae17f64b..0c5311ec675 100644
--- a/gcc/testsuite/gcc.c-torture/compile/attr-complex-method-2.c
+++ b/gcc/testsuite/gcc.c-torture/compile/attr-complex-method-2.c
@@ -8,4 +8,4 @@ void do_div (_Complex double *a, _Complex double *b)
   *a = *b / (4.0 - 5.0fi);
 }
 
-/* { dg-final { scan-tree-dump "__divdc3" "optimized" } } */
+/* { dg-final { scan-tree-dump "__(?:gnu_)?divdc3" "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/complex-6.c b/gcc/testsuite/gcc.dg/complex-6.c
index a7eae1e2513..cfbfc07d610 100644
--- a/gcc/testsuite/gcc.dg/complex-6.c
+++ b/gcc/testsuite/gcc.dg/complex-6.c
@@ -10,4 +10,4 @@ foo (__complex float a, __complex float b)
 }
 
 /* { dg-final { scan-tree-dump-times "unord" 1 "cplxlower1" { target { ! 
rx*-*-* } } } } */
-/* { dg-final { scan-tree-dump-times "__mulsc3" 1 "cplxlower1" { target { ! 
rx*-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "__(?:gnu_)?mulsc3" 1 "cplxlower1" { 
target { ! rx*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.dg/complex-7.c b/gcc/testsuite/gcc.dg/complex-7.c
index a1f136ce9a2..659ae40afa2 100644
--- a/gcc/testsuite/gcc.dg/complex-7.c
+++ b/gcc/testsuite/gcc.dg/complex-7.c
@@ -11,4 +11,4 @@ foo (__complex double a, __complex double b)
 }
 
 /* { dg-final { scan-tree-dump-times "unord" 1 "cplxlower1" } } */
-/* { dg-final { scan-tree-dump-times "__muldc3" 1 "cplxlower1" } } */
+/* { dg-final { scan-tree-dump-times "__(?:gnu_)?muldc3" 1 "cplxlower1" } } */
-- 
2.35.1

[PATCH][committed] testsuite: Skip cases for default_packed targets

[Dimitar Dimitrov]

The memchr test cases expect padding to be present in structures.  But
this is not true for targets which pack by default.  Skip these test
cases in order to avoid static assert errors when checking field offsets.

The following asserts are triggered due to assumptions for structure
field alignment:
memcmp-3.c: _Static_assert (sizeof (struct S8_16_32) == 8);
memchr.c: _Static_assert (__builtin_offsetof (struct SX, a) == 6);
  

Committed as obvious.

gcc/testsuite/ChangeLog:

* gcc.dg/memchr.c: Skip for default_packed targets.
* gcc.dg/memcmp-3.c: Ditto.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/memchr.c   | 3 ++-
 gcc/testsuite/gcc.dg/memcmp-3.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/memchr.c b/gcc/testsuite/gcc.dg/memchr.c
index fb21d58b476..27524b82520 100644
--- a/gcc/testsuite/gcc.dg/memchr.c
+++ b/gcc/testsuite/gcc.dg/memchr.c
@@ -1,6 +1,7 @@
 /* PR middle-end/78257 - missing memcmp optimization with constant arrays
{ dg-do compile }
-   { dg-options "-O -Wall -fdump-tree-optimized" } */
+   { dg-options "-O -Wall -fdump-tree-optimized" }
+   { dg-skip-if "test assumes structs are not packed" { default_packed } } */
 
 typedef __INT8_TYPE__  int8_t;
 typedef __INT16_TYPE__ int16_t;
diff --git a/gcc/testsuite/gcc.dg/memcmp-3.c b/gcc/testsuite/gcc.dg/memcmp-3.c
index b5b8ac1209f..8ddde996c2f 100644
--- a/gcc/testsuite/gcc.dg/memcmp-3.c
+++ b/gcc/testsuite/gcc.dg/memcmp-3.c
@@ -1,7 +1,8 @@
 /* PR middle-end/78257 - missing memcmp optimization with constant arrays
{ dg-do compile }
{ dg-options "-O -Wall -fdump-tree-optimized" }
-   { dg-skip-if "missing data representation" { "pdp11-*-*" } } */
+   { dg-skip-if "missing data representation" { "pdp11-*-*" } }
+   { dg-skip-if "test assumes structs are not packed" { default_packed } } */
 
 #define offsetof(T, m) __builtin_offsetof (T, m)
 
-- 
2.35.1

[PATCH][committed] testsuite: Annotate Wattributes-8.c for default_packed

[Dimitar Dimitrov]

Place markers in test case to handle targets which pack structures by
default. Validated on pru-none-elf.

Committed as obvious.

gcc/testsuite/ChangeLog:

* gcc.dg/Wattributes-8.c: Add annotations for default_packed
targets.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/Wattributes-8.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/Wattributes-8.c 
b/gcc/testsuite/gcc.dg/Wattributes-8.c
index a4b4c00c08f..8f5483e2d7a 100644
--- a/gcc/testsuite/gcc.dg/Wattributes-8.c
+++ b/gcc/testsuite/gcc.dg/Wattributes-8.c
@@ -24,8 +24,10 @@ int c ATTR ((aligned (2)));   // okay (reduces 
alignment)
 ASSERT (_Alignof (c) == 2);
 
 struct {
-  int a ATTR ((packed, aligned (2)));   /* { dg-bogus "\\\[-Wattributes" } */
-  int b ATTR ((aligned (2), packed));   /* { dg-bogus "\\\[-Wattributes" } */
+  int a ATTR ((packed, aligned (2)));   /* { dg-bogus "\\\[-Wattributes" "" { 
target { ! default_packed } } } */
+  /* { dg-warning "attribute ignored" "" { target { default_packed } } .-1 } */
+  int b ATTR ((aligned (2), packed));   /* { dg-bogus "\\\[-Wattributes" "" { 
target { ! default_packed } } } */
+  /* { dg-warning "attribute ignored" "" { target { default_packed } } .-1 } */
 
   /* Avoid exercising this since the attribute has no effect yet
  there is no warning.
-- 
2.35.1

[PATCH][committed] testsuite: Mark that PRU lowers DI alu ops by itself

[Dimitar Dimitrov]

PRU target defines DI patterns for logical ALU operations.

gcc/testsuite/ChangeLog:

* gcc.dg/lower-subreg-1.c: Skip for PRU.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/lower-subreg-1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/lower-subreg-1.c 
b/gcc/testsuite/gcc.dg/lower-subreg-1.c
index 8462992c7b9..595938acdcc 100644
--- a/gcc/testsuite/gcc.dg/lower-subreg-1.c
+++ b/gcc/testsuite/gcc.dg/lower-subreg-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* i?86-*-* 
ia64-*-* sparc*-*-* tilegx-*-* x86_64-*-* } } } } } */
+/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* i?86-*-* 
ia64-*-* pru-*-* sparc*-*-* tilegx-*-* x86_64-*-* } } } } } */
 /* { dg-options "-O -fdump-rtl-subreg1" } */
 /* { dg-require-effective-target ilp32 } */
 
-- 
2.35.1

[PATCH][committed] testsuite: Skip gcc.dg/Wno-frame-address.c for PRU

[Dimitar Dimitrov]

Access to arbitrary stack frames is not supported on PRU.

gcc/testsuite/ChangeLog:

* gcc.dg/Wno-frame-address.c: Skip for PRU target.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/Wno-frame-address.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/Wno-frame-address.c 
b/gcc/testsuite/gcc.dg/Wno-frame-address.c
index 13c42b255e9..a97ec402b4a 100644
--- a/gcc/testsuite/gcc.dg/Wno-frame-address.c
+++ b/gcc/testsuite/gcc.dg/Wno-frame-address.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "Cannot access arbitrary stack frames" { arm*-*-* amdgpu-*-* 
avr-*-* hppa*-*-* ia64-*-* visium-*-* csky-*-* msp430-*-* cris-*-* mmix-*-* } } 
*/
+/* { dg-skip-if "Cannot access arbitrary stack frames" { arm*-*-* amdgpu-*-* 
avr-*-* hppa*-*-* ia64-*-* visium-*-* csky-*-* msp430-*-* cris-*-* mmix-*-* 
pru-*-* } } */
 /* { dg-options "-Werror" } */
 /* { dg-additional-options "-mbackchain" { target { s390*-*-* } } } */
 
-- 
2.35.1

Re: [PATCH] libstdc++: Decouple HAVE_FCNTL_H from HAVE_DIRENT_H check

[Dimitar Dimitrov]

On Mon, Feb 07, 2022 at 09:05:45PM +, Jonathan Wakely wrote:
> On Mon, 7 Feb 2022 at 21:01, Jonathan Wakely  wrote:
> 
> >
> >
> > On Mon, 7 Feb 2022 at 20:12, Dimitar Dimitrov  wrote:
> >
> >> On PRU target with newlib, we have the following combination in config.h:
> >>   /* #undef HAVE_DIRENT_H */
> >>   #define HAVE_FCNTL_H 1
> >>   #define HAVE_UNLINKAT 1
> >>
> >> In newlib, targets which do not define dirent.h, get a build error when
> >> including :
> >>
> >> https://sourceware.org/git/?p=newlib-cygwin.git;a=blob;f=newlib/libc/include/sys/dirent.h;hb=HEAD
> >>
> >> While fs_dir.cc correctly checks for HAVE_FCNTL_H, dir-common.h doesn't,
> >> and instead uses HAVE_DIRENT_H. This results in unlinkat() function call
> >> in fs_dir.cc without the needed  include in dir-common.h. Thus
> >> a build failure:
> >>   .../gcc/libstdc++-v3/src/c++17/fs_dir.cc:151:11: error: ‘::unlinkat’
> >> has not been declared; did you mean ‘unlink’?
> >>
> >> Fix by encapsulating  include with the correct check.
> >>
> >
> > But there's no point doing anything in that file if we don't have
> > , the whole thing is unusable. There's no point making the
> > members using unlinkat compile if you can't ever construct the type.
> >
> > So I think we want a different fix.
> >
> 
> 
> Maybe something like:
> 
> --- a/libstdc++-v3/src/filesystem/dir-common.h
> +++ b/libstdc++-v3/src/filesystem/dir-common.h
> @@ -70,6 +70,8 @@ struct DIR { };
> inline DIR* opendir(const char*) { return nullptr; }
> inline dirent* readdir(DIR*) { return nullptr; }
> inline int closedir(DIR*) { return -1; }
> +#undef _GLIBCXX_HAVE_DIRFD
> +#undef _GLIBCXX_HAVE_UNLINKAT
> #endif
> } // namespace __gnu_posix
Yes, this fixes the PRU target, and does not regress
x86_64-pc-linux-gnu.

Regards,
Dimitar

[PATCH] libstdc++: Decouple HAVE_FCNTL_H from HAVE_DIRENT_H check

[Dimitar Dimitrov]

On PRU target with newlib, we have the following combination in config.h:
  /* #undef HAVE_DIRENT_H */
  #define HAVE_FCNTL_H 1
  #define HAVE_UNLINKAT 1

In newlib, targets which do not define dirent.h, get a build error when
including :
  
https://sourceware.org/git/?p=newlib-cygwin.git;a=blob;f=newlib/libc/include/sys/dirent.h;hb=HEAD

While fs_dir.cc correctly checks for HAVE_FCNTL_H, dir-common.h doesn't,
and instead uses HAVE_DIRENT_H. This results in unlinkat() function call
in fs_dir.cc without the needed  include in dir-common.h. Thus
a build failure:
  .../gcc/libstdc++-v3/src/c++17/fs_dir.cc:151:11: error: ‘::unlinkat’ has not 
been declared; did you mean ‘unlink’?

Fix by encapsulating  include with the correct check.

Regtested x86_64-pc-linux-gnu and no new failures detected.

Fixes commit r12-7062-gebf61754647689 (libstdc++: Fix filesystem::remove_all 
races).

libstdc++-v3/ChangeLog:

* src/filesystem/dir-common.h (_GLIBCXX_HAVE_FCNTL_H): Move the
check outside the HAVE_DIRENT_H check.

Signed-off-by: Dimitar Dimitrov 
---
 libstdc++-v3/src/filesystem/dir-common.h | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/libstdc++-v3/src/filesystem/dir-common.h 
b/libstdc++-v3/src/filesystem/dir-common.h
index 0b7665a3f70..cfce4fae9a4 100644
--- a/libstdc++-v3/src/filesystem/dir-common.h
+++ b/libstdc++-v3/src/filesystem/dir-common.h
@@ -35,10 +35,11 @@
 #  include 
 # endif
 # include  // opendir, readdir, fdopendir, dirfd
-# ifdef _GLIBCXX_HAVE_FCNTL_H
-#  include   // open, openat, fcntl, AT_FDCWD, O_NOFOLLOW etc.
-#  include  // close, unlinkat
-# endif
+#endif
+
+#ifdef _GLIBCXX_HAVE_FCNTL_H
+# include   // open, openat, fcntl, AT_FDCWD, O_NOFOLLOW etc.
+# include  // close, unlinkat
 #endif
 
 namespace std _GLIBCXX_VISIBILITY(default)
-- 
2.34.1

Re: [committed] libstdc++: Avoid symlink race in filesystem::remove_all [PR104161]

[Dimitar Dimitrov]

On Tue, Jan 25, 2022 at 09:09:51PM +, Jonathan Wakely via Gcc-patches wrote:
> Tested x86_64-linux, pushed to trunk. Backports to follow.
> 
> 
> This adds a new internal flag to the filesystem::directory_iterator
> constructor that makes it fail if the path is a symlink that resolves to
> a directory. This prevents filesystem::remove_all from following a
> symlink to a directory, rather than deleting the symlink itself.
> 
> We can also use that new flag in recursive_directory_iterator to ensure
> that we don't follow symlinks if the follow_directory_symlink option is
> not set.
> 
> This also moves an error check in filesystem::remove_all after the while
> loop, so that errors from the directory_iterator constructor are
> reproted, instead of continuing to the filesystem::remove call below.
> 
> libstdc++-v3/ChangeLog:
> 
>   PR libstdc++/104161
>   * acinclude.m4 (GLIBCXX_CHECK_FILESYSTEM_DEPS): Check for
>   fdopendir.
>   * config.h.in: Regenerate.
>   * configure: Regenerate.
>   * src/c++17/fs_dir.cc (_Dir): Add nofollow flag to constructor
>   and pass it to base class constructor.
>   (directory_iterator): Pass nofollow flag to _Dir constructor.
>   (fs::recursive_directory_iterator::increment): Likewise.
>   * src/c++17/fs_ops.cc (do_remove_all): Use nofollow option for
>   directory_iterator constructor. Move error check outside loop.
>   * src/filesystem/dir-common.h (_Dir_base): Add nofollow flag to
>   constructor and when it's set use ::open with O_NOFOLLOW and
>   O_DIRECTORY.
>   * src/filesystem/dir.cc (_Dir): Add nofollow flag to constructor
>   and pass it to base class constructor.
>   (directory_iterator): Pass nofollow flag to _Dir constructor.
>   (fs::recursive_directory_iterator::increment): Likewise.
>   * src/filesystem/ops.cc (remove_all): Use nofollow option for
>   directory_iterator constructor. Move error check outside loop.
> ---
>  libstdc++-v3/acinclude.m4| 12 ++
>  libstdc++-v3/config.h.in |  3 ++
>  libstdc++-v3/configure   | 55 
>  libstdc++-v3/src/c++17/fs_dir.cc | 13 --
>  libstdc++-v3/src/c++17/fs_ops.cc | 12 +++---
>  libstdc++-v3/src/filesystem/dir-common.h | 48 -
>  libstdc++-v3/src/filesystem/dir.cc   | 13 --
>  libstdc++-v3/src/filesystem/ops.cc   |  6 +--
>  8 files changed, 134 insertions(+), 28 deletions(-)
> 
> diff --git a/libstdc++-v3/acinclude.m4 b/libstdc++-v3/acinclude.m4
> index d996477254c..7b6b807114a 100644
> --- a/libstdc++-v3/acinclude.m4
> +++ b/libstdc++-v3/acinclude.m4
> @@ -4735,6 +4735,18 @@ dnl
>if test $glibcxx_cv_truncate = yes; then
>  AC_DEFINE(HAVE_TRUNCATE, 1, [Define if truncate is available in 
> .])
>fi
> +dnl
> +  AC_CACHE_CHECK([for fdopendir],
> +glibcxx_cv_fdopendir, [dnl
> +GCC_TRY_COMPILE_OR_LINK(
> +  [#include ],
> +  [::fdopendir(1);],
> +  [glibcxx_cv_fdopendir=yes],
> +  [glibcxx_cv_fdopendir=no])
> +  ])
> +  if test $glibcxx_cv_truncate = yes; then

This is a typo. Should check glibcxx_cv_fdopendir.

Regards,
Dimitar

Re: [PATCH] pru: Fixup flags for .pru_irq_map section

[Dimitar Dimitrov]

On Fri, Dec 03, 2021 at 11:33:48PM +0200, Dimitar Dimitrov wrote:
> I intend to merge this patch next week, unless I hear objections.  I
> consider it a bug fix which fits the Stage 3 criteria.  It fixes the
> RPMSG firmware examples in the latest version 6.0 of TI's PRU Software
> Package.
> 
> The .pru_irq_map section has been introduced by Linux kernel 5.10:
>   
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c75c9fdac66efd8b54773368254ef330c276171b
> This section must not be loaded into target memory.
> 
> Binutils already includes the corresponding fix in the linker script:
>   
> https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=44b357eb9aefc77a8385e631d8e3035a664f2333
> 
> gcc/ChangeLog:
> 
>   * config/pru/pru.c (pru_section_type_flags): New function.
>   (TARGET_SECTION_TYPE_FLAGS): Wire it.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.target/pru/pru_irq_map.c: New test.
> 
> Signed-off-by: Dimitar Dimitrov 


Committed.

[PATCH] pru: Fixup flags for .pru_irq_map section

[Dimitar Dimitrov]

I intend to merge this patch next week, unless I hear objections.  I
consider it a bug fix which fits the Stage 3 criteria.  It fixes the
RPMSG firmware examples in the latest version 6.0 of TI's PRU Software
Package.

The .pru_irq_map section has been introduced by Linux kernel 5.10:
  
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c75c9fdac66efd8b54773368254ef330c276171b
This section must not be loaded into target memory.

Binutils already includes the corresponding fix in the linker script:
  
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=44b357eb9aefc77a8385e631d8e3035a664f2333

gcc/ChangeLog:

* config/pru/pru.c (pru_section_type_flags): New function.
(TARGET_SECTION_TYPE_FLAGS): Wire it.

gcc/testsuite/ChangeLog:

* gcc.target/pru/pru_irq_map.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/pru.c   | 19 +++
 gcc/testsuite/gcc.target/pru/pru_irq_map.c |  8 
 2 files changed, 27 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/pru/pru_irq_map.c

diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index 9f264b4698d..01d283fd9e7 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -2022,6 +2022,23 @@ pru_assemble_integer (rtx x, unsigned int size, int 
aligned_p)
 }
 }
 
+/* Implement TARGET_SECTION_TYPE_FLAGS.  */
+
+static unsigned int
+pru_section_type_flags (tree decl, const char *name, int reloc)
+{
+  unsigned int flags = default_section_type_flags (decl, name, reloc);
+
+  /* The .pru_irq_map section is not meant to be loaded into the target
+ memory.  Instead its contents are read by the host remoteproc loader.
+ To prevent being marked as a loadable (allocated) section, the
+ .pru_irq_map section is intercepted and marked as a debug section.  */
+  if (!strcmp (name, ".pru_irq_map"))
+flags = SECTION_DEBUG | SECTION_RETAIN;
+
+  return flags;
+}
+
 /* Implement TARGET_ASM_FILE_START.  */
 
 static void
@@ -3071,6 +3088,8 @@ pru_unwind_word_mode (void)
 #define TARGET_ASM_FUNCTION_PROLOGUE pru_asm_function_prologue
 #undef TARGET_ASM_INTEGER
 #define TARGET_ASM_INTEGER pru_assemble_integer
+#undef TARGET_SECTION_TYPE_FLAGS
+#define TARGET_SECTION_TYPE_FLAGS pru_section_type_flags
 
 #undef TARGET_ASM_FILE_START
 #define TARGET_ASM_FILE_START pru_file_start
diff --git a/gcc/testsuite/gcc.target/pru/pru_irq_map.c 
b/gcc/testsuite/gcc.target/pru/pru_irq_map.c
new file mode 100644
index 000..4f9a5e71b01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/pru_irq_map.c
@@ -0,0 +1,8 @@
+/* Test the special handling of .pru_irq_map section.  */
+
+/* { dg-do compile } */
+
+int my_int_map __attribute__((section(".pru_irq_map")));
+
+/* Section must not have the allocated flag.  */
+/* { dg-final { scan-assembler "\.section\[ \t\]+.pru_irq_map,\[ \]*\"\",[ 
]*@progbits" } } */
-- 
2.33.1

[committed] wwwdocs: gcc-12/changes.html (PRU): Document __regio_symbol

[Dimitar Dimitrov]

Document the new __regio_symbol variable qualifier for PRU target.

Pushed.

Signed-off-by: Dimitar Dimitrov 
---
 htdocs/gcc-12/changes.html | 9 +
 1 file changed, 9 insertions(+)

diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
index 4f7bbd33..22839f2d 100644
--- a/htdocs/gcc-12/changes.html
+++ b/htdocs/gcc-12/changes.html
@@ -203,6 +203,15 @@ a work-in-progress.
 
 
 
+PRU
+
+  The https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html#PRU-Named-Address-Spaces;
+  >__regio_symbol variable qualifier has been added.
+  It allows easier access in C programs to the __R30 and
+  __R31 CPU I/O registers.
+  
+
 
 
 
-- 
2.31.1

[COMMITTED][PATCH v2] pru: Named address space for R30/R31 I/O access

[Dimitar Dimitrov]

I have committed the below patch. I've made only cosmetic updates since
version 1 
(https://gcc.gnu.org/pipermail/gcc-patches/2021-September/579420.html).

The PRU architecture provides single-cycle access to GPIO pins via
special designated CPU registers - R30 and R31. These two registers can
of course be accessed in C code using inline assembly, but that can be
intimidating to users.

The TI proprietary compiler [1] can expose these I/O registers as global
volatile registers:
  volatile register unsigned int __R31;

Consequently, accessing them in user programs is as straightforward as
using a regular global variable:
  __R31 |= (1 << 2);

Unfortunately, global volatile registers are not supported by GCC [2].
I decided to implement convenient access to __R30 and __R31 using a new
named address space:
  extern volatile __regio_symbol unsigned int __R30;
Unlike global registers, volatile global memory variables are well
supported in GCC.  Memory writes and reads to the __regio_symbol address
space are converted to writes and reads to R30 and R31 CPU registers.
The declared variable name determines which of the two registers it is
representing.

With an ifdef for the __R30/__R31 declarations, user programs can now
be source-compatible with both TI and GCC toolchains.

[1] https://www.ti.com/lit/ug/spruhv7c/spruhv7c.pdf , "Global Register 
Variables"
[2] https://gcc.gnu.org/ml/gcc-patches/2015-01/msg02241.html

gcc/ChangeLog:

* config/pru/constraints.md (Rrio): New constraint.
* config/pru/predicates.md (regio_operand): New predicate.
* config/pru/pru-pragma.c (pru_register_pragmas): Register
the __regio_symbol address space.
* config/pru/pru-protos.h (pru_symref2ioregno): Declaration.
* config/pru/pru.c (pru_symref2ioregno): New helper function.
(pru_legitimate_address_p): Remove.
(pru_addr_space_legitimate_address_p): Use the address space
aware hook variant.
(pru_nongeneric_pointer_addrspace): New helper function.
(pru_insert_attributes): New function to validate __regio_symbol
usage.
(TARGET_INSERT_ATTRIBUTES): New macro.
(TARGET_LEGITIMATE_ADDRESS_P): Remove.
(TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P): New macro.
* config/pru/pru.h (enum reg_class): Add REGIO_REGS class.
* config/pru/pru.md (*regio_readsi): New pattern to read I/O
registers.
(*regio_nozext_writesi): New pattern to write to I/O registers.
(*regio_zext_write_r30): Ditto.
* doc/extend.texi: Document the new PRU Named Address Space.

gcc/testsuite/ChangeLog:

* gcc.target/pru/regio-as-pointer.c: New negative test.
* gcc.target/pru/regio-as-pointer-2.c: New negative test.
* gcc.target/pru/regio-decl-2.c: New negative test.
* gcc.target/pru/regio-decl-3.c: New negative test.
* gcc.target/pru/regio-decl-4.c: New negative test.
* gcc.target/pru/regio-decl.c: New negative test.
* gcc.target/pru/regio-di.c: New negative test.
* gcc.target/pru/regio-hi.c: New negative test.
* gcc.target/pru/regio-qi.c: New negative test.
* gcc.target/pru/regio.c: New test.
* gcc.target/pru/regio.h: New helper header.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/constraints.md |   5 +
 gcc/config/pru/predicates.md  |  19 +++
 gcc/config/pru/pru-pragma.c   |   2 +
 gcc/config/pru/pru-protos.h   |   3 +
 gcc/config/pru/pru.c  | 156 +-
 gcc/config/pru/pru.h  |   5 +
 gcc/config/pru/pru.md | 102 +++-
 gcc/doc/extend.texi   |  19 ++-
 .../gcc.target/pru/regio-as-pointer-2.c   |  11 ++
 .../gcc.target/pru/regio-as-pointer.c |  11 ++
 gcc/testsuite/gcc.target/pru/regio-decl-2.c   |  13 ++
 gcc/testsuite/gcc.target/pru/regio-decl-3.c   |  19 +++
 gcc/testsuite/gcc.target/pru/regio-decl-4.c   |  17 ++
 gcc/testsuite/gcc.target/pru/regio-decl.c |  15 ++
 gcc/testsuite/gcc.target/pru/regio-di.c   |   9 +
 gcc/testsuite/gcc.target/pru/regio-hi.c   |   9 +
 gcc/testsuite/gcc.target/pru/regio-qi.c   |   9 +
 gcc/testsuite/gcc.target/pru/regio.c  |  58 +++
 gcc/testsuite/gcc.target/pru/regio.h  |   7 +
 19 files changed, 478 insertions(+), 11 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-as-pointer-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-as-pointer.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl-4.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-di.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-hi.c
 create mode 1006

Re: [PATCH][RFC] pru: Named address space for R30/R31 I/O access

[Dimitar Dimitrov]

On Wed, Sep 15, 2021 at 11:12:18AM +0200, Richard Biener wrote:
> On Tue, Sep 14, 2021 at 11:13 PM Dimitar Dimitrov  wrote:
> >
> > Hi,
> >
> > I'm sending this patch to get feedback for a new PRU CPU port feature.
> > My intention is to push it to master by end of September, so that it gets
> > included in GCC 12.
> >
> > The PRU architecture provides single-cycle access to GPIO pins via
> > special designated CPU registers - R30 and R31. These two registers can
> > of course be accessed in C code using inline assembly, but that can be
> > intimidating to users.
> >
> > The TI proprietary compiler [1] can expose these I/O registers as global
> > volatile registers:
> >   volatile register unsigned int __R31;
> >
> > Consequently, accessing them in user programs is as straightforward as
> > using a regular global variable:
> >   __R31 |= (1 << 2);
> >
> > Unfortunately, global volatile registers are not supported by GCC [2].
> 
> Yes, a "register" write or read does not follow volatile semantics, so
> exposing those as registers isn't supported (I consider the GPIO regs
> similar to MSRs on other CPUs?).

Yes, they are a lot like MSRs.

> 
> > I decided to implement convenient access to __R30 and __R31 using a new
> > named address space:
> >   extern volatile __regio_symbol unsigned int __R30;
> >
> > Unlike global registers, volatile global memory variables are well
> > supported in GCC.  Memory writes and reads to the __regio_symbol address
> > space are converted to writes and reads to R30 and R31 CPU registers.
> > The declared variable name determines which of the two registers it is
> > representing.
> 
> I think that's reasonable.  I do wonder whether it's possible to prevent
> taking the address of __R30 though - otherwise I guess the backend
> will crash or do weird things on such code?

I believe I have handled those cases, and suitable error messages are
emitted by the compiler.  See the negative test cases added in
regio-as-pointer*.c and regio-decl*.c.

Thanks,
Dimitar

> 
> > With an ifdef for the __R30/__R31 declarations, user programs can now
> > be source-compatible with both TI and GCC toolchains.
> >
> > [1] https://www.ti.com/lit/ug/spruhv7c/spruhv7c.pdf , "Global Register 
> > Variables"
> > [2] https://gcc.gnu.org/ml/gcc-patches/2015-01/msg02241.html
> >
> > gcc/ChangeLog:
> >
> > * config/pru/constraints.md (Rrio): New constraint.
> > * config/pru/predicates.md (regio_operand): New predicate.
> > * config/pru/pru-pragma.c (pru_register_pragmas): Register
> > the __regio_symbol address space.
> > * config/pru/pru-protos.h (pru_symref2ioregno): Declaration.
> > * config/pru/pru.c (pru_symref2ioregno): New helper function.
> > (pru_legitimate_address_p): Remove.
> > (pru_addr_space_legitimate_address_p): Use the address space
> > aware hook variant.
> > (pru_nongeneric_pointer_addrspace): New helper function.
> > (pru_insert_attributes): New function to validate __regio_symbol
> > usage.
> > (TARGET_INSERT_ATTRIBUTES): New macro.
> > (TARGET_LEGITIMATE_ADDRESS_P): Remove.
> > (TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P): New macro.
> > * config/pru/pru.h (enum reg_class): Add REGIO_REGS class.
> > * config/pru/pru.md (*regio_readsi): New pattern to read I/O
> > registers.
> > (*regio_nozext_writesi): New pattern to write to I/O registers.
> > (*regio_zext_write_r30): Ditto.
> > * doc/extend.texi: Document the new PRU Named Address Space.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/pru/regio-as-pointer.c: New negative test.
> > * gcc.target/pru/regio-as-pointer2.c: New negative test.
> > * gcc.target/pru/regio-decl-2.c: New negative test.
> > * gcc.target/pru/regio-decl-3.c: New negative test.
> > * gcc.target/pru/regio-decl-4.c: New negative test.
> > * gcc.target/pru/regio-decl.c: New negative test.
> > * gcc.target/pru/regio-di.c: New negative test.
> > * gcc.target/pru/regio-hi.c: New negative test.
> > * gcc.target/pru/regio-qi.c: New negative test.
> > * gcc.target/pru/regio.c: New test.
> > * gcc.target/pru/regio.h: New helper header.
> >
> > Signed-off-by: Dimitar Dimitrov 
> > ---
> >  gcc/config/pru/constraints.md |   5 +
> >  gcc/config/pru/predicates.md 

[PATCH][RFC] pru: Named address space for R30/R31 I/O access

[Dimitar Dimitrov]

Hi,

I'm sending this patch to get feedback for a new PRU CPU port feature.
My intention is to push it to master by end of September, so that it gets
included in GCC 12.

The PRU architecture provides single-cycle access to GPIO pins via
special designated CPU registers - R30 and R31. These two registers can
of course be accessed in C code using inline assembly, but that can be
intimidating to users.

The TI proprietary compiler [1] can expose these I/O registers as global
volatile registers:
  volatile register unsigned int __R31;

Consequently, accessing them in user programs is as straightforward as
using a regular global variable:
  __R31 |= (1 << 2);

Unfortunately, global volatile registers are not supported by GCC [2].
I decided to implement convenient access to __R30 and __R31 using a new
named address space:
  extern volatile __regio_symbol unsigned int __R30;

Unlike global registers, volatile global memory variables are well
supported in GCC.  Memory writes and reads to the __regio_symbol address
space are converted to writes and reads to R30 and R31 CPU registers.
The declared variable name determines which of the two registers it is
representing.

With an ifdef for the __R30/__R31 declarations, user programs can now
be source-compatible with both TI and GCC toolchains.

[1] https://www.ti.com/lit/ug/spruhv7c/spruhv7c.pdf , "Global Register 
Variables"
[2] https://gcc.gnu.org/ml/gcc-patches/2015-01/msg02241.html

gcc/ChangeLog:

* config/pru/constraints.md (Rrio): New constraint.
* config/pru/predicates.md (regio_operand): New predicate.
* config/pru/pru-pragma.c (pru_register_pragmas): Register
the __regio_symbol address space.
* config/pru/pru-protos.h (pru_symref2ioregno): Declaration.
* config/pru/pru.c (pru_symref2ioregno): New helper function.
(pru_legitimate_address_p): Remove.
(pru_addr_space_legitimate_address_p): Use the address space
aware hook variant.
(pru_nongeneric_pointer_addrspace): New helper function.
(pru_insert_attributes): New function to validate __regio_symbol
usage.
(TARGET_INSERT_ATTRIBUTES): New macro.
(TARGET_LEGITIMATE_ADDRESS_P): Remove.
(TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P): New macro.
* config/pru/pru.h (enum reg_class): Add REGIO_REGS class.
* config/pru/pru.md (*regio_readsi): New pattern to read I/O
registers.
(*regio_nozext_writesi): New pattern to write to I/O registers.
(*regio_zext_write_r30): Ditto.
* doc/extend.texi: Document the new PRU Named Address Space.

gcc/testsuite/ChangeLog:

* gcc.target/pru/regio-as-pointer.c: New negative test.
* gcc.target/pru/regio-as-pointer2.c: New negative test.
* gcc.target/pru/regio-decl-2.c: New negative test.
* gcc.target/pru/regio-decl-3.c: New negative test.
* gcc.target/pru/regio-decl-4.c: New negative test.
* gcc.target/pru/regio-decl.c: New negative test.
* gcc.target/pru/regio-di.c: New negative test.
* gcc.target/pru/regio-hi.c: New negative test.
* gcc.target/pru/regio-qi.c: New negative test.
* gcc.target/pru/regio.c: New test.
* gcc.target/pru/regio.h: New helper header.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/constraints.md |   5 +
 gcc/config/pru/predicates.md  |  19 +++
 gcc/config/pru/pru-pragma.c   |   2 +
 gcc/config/pru/pru-protos.h   |   3 +
 gcc/config/pru/pru.c  | 155 +-
 gcc/config/pru/pru.h  |   5 +
 gcc/config/pru/pru.md | 102 +++-
 gcc/doc/extend.texi   |  19 ++-
 .../gcc.target/pru/regio-as-pointer.c |  11 ++
 .../gcc.target/pru/regio-as-pointer2.c|  11 ++
 gcc/testsuite/gcc.target/pru/regio-decl-2.c   |  13 ++
 gcc/testsuite/gcc.target/pru/regio-decl-3.c   |  19 +++
 gcc/testsuite/gcc.target/pru/regio-decl-4.c   |  17 ++
 gcc/testsuite/gcc.target/pru/regio-decl.c |  15 ++
 gcc/testsuite/gcc.target/pru/regio-di.c   |   9 +
 gcc/testsuite/gcc.target/pru/regio-hi.c   |   9 +
 gcc/testsuite/gcc.target/pru/regio-qi.c   |   9 +
 gcc/testsuite/gcc.target/pru/regio.c  |  58 +++
 gcc/testsuite/gcc.target/pru/regio.h  |   7 +
 19 files changed, 477 insertions(+), 11 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-as-pointer.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-as-pointer2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl-2.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl-3.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl-4.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-decl.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-di.c
 create mode 100644 gcc/testsuite/gcc.target/pru/regio-hi.c
 cr

Re: disable -Warray-bounds in libgo (PR 101374)

[Dimitar Dimitrov]

On Fri, Jul 09, 2021 at 08:16:24AM +0200, Richard Biener via Gcc-patches wrote:
> On Thu, Jul 8, 2021 at 8:02 PM Martin Sebor via Gcc-patches
>  wrote:
> >
> > Hi Ian,
> >
> > Yesterday's enhancement to -Warray-bounds has exposed a couple of
> > issues in libgo where the code writes into an invalid constant
> > address that the warning is designed to flag.
> >
> > On the assumption that those invalid addresses are deliberate,
> > the attached patch suppresses these instances by using #pragma
> > GCC diagnostic but I don't think I'm supposed to commit it (at
> > least Git won't let me).  To avoid Go bootstrap failures please
> > either apply the patch or otherwise suppress the warning (e.g.,
> > by using a volatile pointer temporary).
> 
> Btw, I don't think we should diagnose things like
> 
> *(int*)0x21 = 0x21;
> 
> when somebody literally writes that he'll be just annoyed by diagnostics.
I agree. This will raise a lot of noise for embedded targets.

Similar constructs are used extensively in pretty much any microcontroller
project to define macros to access I/O special-function addresses.
A few random examples:

http://svn.savannah.gnu.org/viewvc/avr-libc/trunk/avr-libc/include/avr/sfr_defs.h?view=markup#l128
https://sourceforge.net/p/mspgcc/msp430mcu/ci/master/tree/upstream/cc430f5123.h#l2141
https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/RTOS/RTX/SRC/rt_HAL_CM.h#L138

Regards,
Dimitar

> 
> Of course the above might be able to use __builtin_trap (); - it looks
> like it is placed where control flow should never end, kind of a
> __builtin_unreachable (), which means abort () might do as well.
> 
> Richard.
> 
> > Thanks
> > Martin

[committed] [PATCH v2] doc/lto.texi: List slim object format as the default

[Dimitar Dimitrov]

On Mon, Jun 21, 2021 at 08:09:20AM +0200, Richard Biener wrote:
> On Sun, 20 Jun 2021, Dimitar Dimitrov wrote:
> 
> > Slim LTO object files have been the default for quite a while, since:
> >   commit e9f67e625c2a4225a7169d7220dcb85b6fdd7ca9
> >   Author: Jan Hubicka 
> >   common.opt (ffat-lto-objects): Disable by default.
> > 
> > That commit did not update lto.texi, so do it now.
> 
> LGTM.  Btw, on targets where linker plugin support is not detected
> by configury fat objects are still the default.
> 

Thanks. I added a comment about fat objects being default if ar/nm
plugin is not detected when GCC is configured.  I committed the
following:


[PATCH v2] doc/lto.texi: List slim object format as the default

Slim LTO object files have been the default for quite a while, since:
  commit e9f67e625c2a4225a7169d7220dcb85b6fdd7ca9
  Author: Jan Hubicka 
  common.opt (ffat-lto-objects): Disable by default.

That commit did not update lto.texi, so do it now.

gcc/ChangeLog:

* doc/lto.texi (Design Overview): Update that slim objects are
the default.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/doc/lto.texi | 25 -
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/gcc/doc/lto.texi b/gcc/doc/lto.texi
index 1f55216328a..3c5de2144d0 100644
--- a/gcc/doc/lto.texi
+++ b/gcc/doc/lto.texi
@@ -36,11 +36,18 @@ bytecode representation of GIMPLE that is emitted in 
special sections
 of @code{.o} files.  Currently, LTO support is enabled in most
 ELF-based systems, as well as darwin, cygwin and mingw systems.
 
-Since GIMPLE bytecode is saved alongside final object code, object
-files generated with LTO support are larger than regular object files.
-This ``fat'' object format makes it easy to integrate LTO into
-existing build systems, as one can, for instance, produce archives of
-the files.  Additionally, one might be able to ship one set of fat
+By default, object files generated with LTO support contain only GIMPLE
+bytecode.  Such objects are called ``slim'', and they require that
+tools like @code{ar} and @code{nm} understand symbol tables of LTO
+sections.  For most targets these tools have been extended to use the
+plugin infrastructure, so GCC can support ``slim'' objects consisting
+of the intermediate code alone.
+
+GIMPLE bytecode could also be saved alongside final object code if
+the @option{-ffat-lto-objects} option is passed, or if no plugin support
+is detected for @code{ar} and @code{nm} when GCC is configured.  It makes
+the object files generated with LTO support larger than regular object
+files.  This ``fat'' object format allows to ship one set of fat
 objects which could be used both for development and the production of
 optimized builds.  A, perhaps surprising, side effect of this feature
 is that any mistake in the toolchain leads to LTO information not
@@ -49,14 +56,6 @@ This is both an advantage, as the system is more robust, and 
a
 disadvantage, as the user is not informed that the optimization has
 been disabled.
 
-The current implementation only produces ``fat'' objects, effectively
-doubling compilation time and increasing file sizes up to 5x the
-original size.  This hides the problem that some tools, such as
-@code{ar} and @code{nm}, need to understand symbol tables of LTO
-sections.  These tools were extended to use the plugin infrastructure,
-and with these problems solved, GCC will also support ``slim'' objects
-consisting of the intermediate code alone.
-
 At the highest level, LTO splits the compiler in two.  The first half
 (the ``writer'') produces a streaming representation of all the
 internal data structures needed to optimize and generate code.  This
-- 
2.31.1

[PATCH] doc/lto.texi: List slim object format as the default

[Dimitar Dimitrov]

Slim LTO object files have been the default for quite a while, since:
  commit e9f67e625c2a4225a7169d7220dcb85b6fdd7ca9
  Author: Jan Hubicka 
  common.opt (ffat-lto-objects): Disable by default.

That commit did not update lto.texi, so do it now.

gcc/ChangeLog:

* doc/lto.texi (Design Overview): Update that slim objects are
the default.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/doc/lto.texi | 23 ++-
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/gcc/doc/lto.texi b/gcc/doc/lto.texi
index 1f55216328a..755258ccb2b 100644
--- a/gcc/doc/lto.texi
+++ b/gcc/doc/lto.texi
@@ -36,11 +36,16 @@ bytecode representation of GIMPLE that is emitted in 
special sections
 of @code{.o} files.  Currently, LTO support is enabled in most
 ELF-based systems, as well as darwin, cygwin and mingw systems.
 
-Since GIMPLE bytecode is saved alongside final object code, object
-files generated with LTO support are larger than regular object files.
-This ``fat'' object format makes it easy to integrate LTO into
-existing build systems, as one can, for instance, produce archives of
-the files.  Additionally, one might be able to ship one set of fat
+Object files generated with LTO support contain only GIMPLE bytecode.
+Such objects are called ``slim'', and they require that tools like
+@code{ar} and @code{nm} understand symbol tables of LTO sections.  These tools
+have been extended to use the plugin infrastructure, so GCC can support
+``slim'' objects consisting of the intermediate code alone.
+
+GIMPLE bytecode could also be saved alongside final object code if the
+@option{-ffat-lto-objects} option is passed.  But this would make the
+object files generated with LTO support larger than regular object
+files.  This ``fat'' object format allows to ship one set of fat
 objects which could be used both for development and the production of
 optimized builds.  A, perhaps surprising, side effect of this feature
 is that any mistake in the toolchain leads to LTO information not
@@ -49,14 +54,6 @@ This is both an advantage, as the system is more robust, and 
a
 disadvantage, as the user is not informed that the optimization has
 been disabled.
 
-The current implementation only produces ``fat'' objects, effectively
-doubling compilation time and increasing file sizes up to 5x the
-original size.  This hides the problem that some tools, such as
-@code{ar} and @code{nm}, need to understand symbol tables of LTO
-sections.  These tools were extended to use the plugin infrastructure,
-and with these problems solved, GCC will also support ``slim'' objects
-consisting of the intermediate code alone.
-
 At the highest level, LTO splits the compiler in two.  The first half
 (the ``writer'') produces a streaming representation of all the
 internal data structures needed to optimize and generate code.  This
-- 
2.31.1

[committed] wwwdocs: readings: Add PRU documents reference

[Dimitar Dimitrov]

On Mon, Jun 14, 2021 at 09:56:12AM +0200, Gerald Pfeifer wrote:
> On Sun, 13 Jun 2021, Dimitar Dimitrov wrote:
> >> TI's server has been telling us that "The PRU-ICSS wiki is in the
> >> process of being migrated to software-dl.ti.com" for five months.
> >> Time to pull the plug.
> > Could you please consider the following replacement?
> >   https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571766.html
> 
> Ah, yes, this is fine - I actually thought you were going to commit
> this directly. ;-)
> 
> Just one little ask: can you please make the links
> 
>   https://www.ti.com/lit/ug/spruij2/spruij2.pdf
> 
> and the like to avoid redirection (which runs afoul of link checkers
> and leads to, hmm, unwielding, URLs)?
> 
> Gerald


Thanks. Committed the change below.


With TI official wiki gone, let's put stable links to their proprietary
toolchain documents, which happen to describe ABI and instruction set.

Signed-off-by: Dimitar Dimitrov 
---
 htdocs/readings.html | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/htdocs/readings.html b/htdocs/readings.html
index 33ed5822..e75bfc49 100644
--- a/htdocs/readings.html
+++ b/htdocs/readings.html
@@ -256,6 +256,8 @@ names.

  pru
Manufacturer: Texas Instruments
+   https://www.ti.com/lit/ug/spruij2/spruij2.pdf;>PRU Assembly 
Instruction User Guide.
+   https://www.ti.com/lit/ug/spruhv7c/spruhv7c.pdf;>TI ABI 
Specification (see chapter 6).
https://elinux.org/Category:PRU;>Community PRU 
Documentation
  

Re: [committed] wwwdocs: readings: Remove PRU-ICSS documentation reference

[Dimitar Dimitrov]

On Mon, May 31, 2021 at 12:20:21AM +0200, Gerald Pfeifer wrote:
> TI's server has been telling us that "The PRU-ICSS wiki is in the
> process of being migrated to software-dl.ti.com" for five months.
> Time to pull the plug.
> ---
>  htdocs/readings.html | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/htdocs/readings.html b/htdocs/readings.html
> index c4c0618a..33ed5822 100644
> --- a/htdocs/readings.html
> +++ b/htdocs/readings.html
> @@ -256,7 +256,6 @@ names.
>  
>   pru
> Manufacturer: Texas Instruments
> -href="https://processors.wiki.ti.com/index.php/PRU-ICSS;>Official PRU 
> Documentation
> https://elinux.org/Category:PRU;>Community PRU 
> Documentation
>   
>  
Hi,

Could you please consider the following replacement?
  https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571766.html

Regards,
Dimitar

[PATCH] wwwdocs: readings: Add PRU documents

[Dimitar Dimitrov]

With TI official wiki gone, let's put stable links to their proprietary
toolchain documents, which happen to describe ABI and instruction set.

Signed-off-by: Dimitar Dimitrov 
---
 htdocs/readings.html | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/htdocs/readings.html b/htdocs/readings.html
index 33ed5822..b3ffbe51 100644
--- a/htdocs/readings.html
+++ b/htdocs/readings.html
@@ -256,6 +256,8 @@ names.
 
  pru
Manufacturer: Texas Instruments
+   https://www.ti.com/lit/pdf/spruij2;>PRU Assembly Instruction 
User Guide.
+   https://www.ti.com/lit/pdf/spruhv7;>TI ABI Specification 
(see chapter 6).
https://elinux.org/Category:PRU;>Community PRU 
Documentation
  
 
-- 
2.31.1

[committed] libgcc: pru: Place mpyll into its own section

[Dimitar Dimitrov]

Pushed as obvious.

This should help LD's --gc-sections feature to reduce final ELF size.

libgcc/ChangeLog:

* config/pru/mpyll.S (__pruabi_mpyll): Place into own section.

Signed-off-by: Dimitar Dimitrov 
---
 libgcc/config/pru/mpyll.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libgcc/config/pru/mpyll.S b/libgcc/config/pru/mpyll.S
index 1aa12a63b2c..cd093bb6b72 100644
--- a/libgcc/config/pru/mpyll.S
+++ b/libgcc/config/pru/mpyll.S
@@ -29,6 +29,8 @@
 
 #include "pru-asm.h"
 
+   .section .text.__pruabi_mpyll, "ax"
+
.global SYM(__pruabi_mpyll)
FUNC(__pruabi_mpyll)
 SYM(__pruabi_mpyll):
-- 
2.20.1

[committed] MAINTAINERS: Add myself as pru port maintainer

[Dimitar Dimitrov]

ChangeLog:

* MAINTAINERS: Add myself as pru port maintainer.
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1722f0aa8fc..0fbbc0519d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -96,6 +96,7 @@ nvptx portTom de Vries

 or1k port  Stafford Horne  
 pdp11 port Paul Koning 
 powerpcspe portAndrew Jenner   

+pru port   Dimitar Dimitrov
 riscv port Kito Cheng  
 riscv port Palmer Dabbelt  
 riscv port Andrew Waterman 
@@ -372,7 +373,6 @@ Bud Davis   

 Chris Demetriou
 Sameera Deshpande  
 Wilco Dijkstra 
-Dimitar Dimitrov   
 Benoit Dupont de Dinechin  

 Jason Eckhardt 
 Bernd Edlinger 
-- 
2.20.1

Re: Dimitar Dimitrov as TI PRU maintainer

[Dimitar Dimitrov]

On петък, 26 март 2021 г. 18:29:23 EET Jeff Law wrote:
> I am pleased to announce that the GCC Steering Committee has appointed
> Dimitar Dimitrov as maintainer of the TI PRU port in GCC.
> 
> 
> Dimitar, please update your listing in the MAINTAINERS file. Sorry it's
> taken so long to make this happen.  It just kept slipping off my radar.
> 
> 
> Thanks,
> 
> Jeff

Thank you for the honour. I have pushed the following as 
c314741a539244a947b94ac045611746c0f072e0

ChangeLog:

* MAINTAINERS: Add myself as pru port maintainer.
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1722f0aa8fc..0fbbc0519d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -96,6 +96,7 @@ nvptx portTom de Vries

 or1k port  Stafford Horne  
 pdp11 port Paul Koning 
 powerpcspe portAndrew Jenner   

+pru port   Dimitar Dimitrov
 riscv port Kito Cheng  
 riscv port Palmer Dabbelt  
 riscv port Andrew Waterman 
@@ -372,7 +373,6 @@ Bud Davis   

 Chris Demetriou
 Sameera Deshpande  
 Wilco Dijkstra         
-Dimitar Dimitrov   
 Benoit Dupont de Dinechin  

 Jason Eckhardt 
 Bernd Edlinger 

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

[Dimitar Dimitrov]

On понеделник, 14 декември 2020 г. 20:53:36 EET Dimitar Dimitrov wrote:
> On петък, 11 декември 2020 г. 19:00:35 EET abebeos wrote:
> > After "digesting" a bit more your review, I need to thank you for opening
> > my eyes re "cherrypick" suggestion and... the missing g++ summaries. I
> > need
> > to update my setup to provide the g++ test-deltas, too. Note that in my
> > test-setup, more c++ tests pass than in yours, not exactly sure why. It's
> > in the "unresovled testcases".
> 
> Regarding the additional "unresolved testcases" in my results. I traced it
> to a bug in my setup. I did not prepare $HOME/.dejagnurc properly for AVR.
> I'll rerun the tests and post the results.
> 
> I'm using stock avr-libc, while I see you are using the avr-libc3 fork.
> Hopefully the main differences are in HW support, not core libc.
> 
> Regards,
> Dimitar

Here are the tests results with my environment fixes. Outcome is the same - 
saaadhu has no regressions.


=
baseline beb9afcaf1466996a301c778596c5df209e7913c
=== gcc Summary ===

# of expected passes105527
# of unexpected failures584
# of unexpected successes   16
# of expected failures  582
# of untested testcases 2
# of unresolved testcases   33
# of unsupported tests  5031

=== g++ Summary ===

# of expected passes146432
# of unexpected failures8012
# of unexpected successes   21
# of expected failures  624
# of untested testcases 10
# of unresolved testcases   3174
# of unsupported tests  2


=
pipcet/avr-ccmode
=== gcc Summary ===

# of expected passes105431
# of unexpected failures709
# of unexpected successes   16
# of expected failures  582
# of untested testcases 2
# of unresolved testcases   69
# of unsupported tests  5032

=== g++ Summary ===

# of expected passes146229
# of unexpected failures8291
# of unexpected successes   21
# of expected failures  624
# of untested testcases 10
# of unresolved testcases   3236
# of unsupported tests  2

=
saadhu/avr-cc0
=== gcc Summary ===

# of expected passes105527
# of unexpected failures584
# of unexpected successes   16
# of expected failures  582
# of untested testcases 2
# of unresolved testcases   33
# of unsupported tests  5031

=== g++ Summary ===

# of expected passes146432
# of unexpected failures8012
# of unexpected successes   21
# of expected failures  624
# of untested testcases 10
# of unresolved testcases   3174
# of unsupported tests  2

Regards,
Dimitar

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

[Dimitar Dimitrov]

On четвъртък, 10 декември 2020 г. 10:24:50 EET Richard Biener wrote:
> On Thu, Dec 10, 2020 at 6:42 AM Dimitar Dimitrov  wrote:
> > On сряда, 9 декември 2020 г. 15:12:49 EET abebeos via Gcc-patches wrote:
> > > Essence:
> > > 
> > > I need a confirmation that the testsuite setup as presented in:
> > > 
> > > https://github.com/abebeos/avr-gnu
> > > 
> > > works fine.
> > > 
> > > The problem with the avr target is that the testsuite cannot be run
> > > easily,
> > > mainly because of the need for a special simulated-target setup, which
> > > does
> > > not work for avr as documented. This led developers to a dead-end with
> > > their non-cc0-avr-backends (the non-cc0 backend is needed thus avr is
> > > not
> > > dropped from gcc11).
> > > 
> > > I integrated a toolchain/testsetup to be able to run the gcc testsuite
> > > against a simulated avr target.
> > > 
> > > I then used this toolchain to test 2 different existent
> > > non-cc0-avr-backends (from pipcet and saaadhu, both github).
> > > 
> > > The result is that saaadhu's backend seems to be working 100%. It has
> > > identical testsuite results with the existing (but deprecated)
> > > cc0-backend,
> > > which means that it can be used "as-is" for inclusion in gcc11.
> > > 
> > > Please note that I did this work in context of a bounty @ bountysouce,
> > > more
> > > information within the issue:
> > > 
> > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92729#c35
> > 
> > Hi,
> > 
> > I tested the trees you have given with my own AVR test setup [1]. I
> > confirm
> > 
> > your results:
> >   - saaadhu's tree does not introduce any regressions.
> >   - pipcet's tree has 142 gcc and 299 g++ regressions (although many of
> >   them
> >   
> > are duplicates, e.g. same test case with different optimization
> > levels).
> > 
> > It's a bit awkward to copy gcc/config/avr into a mainline tree. Looking at
> > their github history, both authors made some small changes in other areas.
> > I would have prefered to cherry-pick or apply patches.
> > 
> > =
> > baseline beb9afcaf1466996a301c778596c5df209e7913c
> > 
> > === gcc Summary ===
> > 
> > # of expected passes87504
> > # of unexpected failures1105
> > # of unexpected successes   15
> > # of expected failures  581
> > # of unresolved testcases   16786
> > # of unsupported tests  5370
> > 
> > === g++ Summary ===
> > 
> > # of expected passes140663
> > # of unexpected failures7932
> > # of unexpected successes   21
> > # of expected failures  620
> > # of unresolved testcases   8603
> > # of unsupported tests  11305
> > 
> > =
> > pipcet/avr-ccmode
> > 
> > === gcc Summary ===
> > 
> > # of expected passes87463
> > # of unexpected failures1221
> > # of unexpected successes   15
> > # of expected failures  581
> > # of unresolved testcases   16799
> > # of unsupported tests  5359
> > 
> > === g++ Summary ===
> > 
> > # of expected passes140529
> > # of unexpected failures8205
> > # of unexpected successes   21
> > # of expected failures  620
> > # of unresolved testcases   8607
> > # of unsupported tests  11301
> > 
> > =
> > saadhu/avr-cc0
> > 
> > === gcc Summary ===
> > 
> > # of expected passes87504
> > # of unexpected failures1105
> > # of unexpected successes   15
> > # of expected failures  581
> > # of unresolved testcases   16786
> > # of unsupported tests  5370
> > 
> > === g++ Summary ===
> > 
> > # of expected passes140663
> > # of unexpected failures7932
> > # of unexpected successes   21
> > # of expected failures  620
> > # of unresolved testcases   8603
> > # of unsupported tests  11305
> > 
> > On a side note, I build and test AVR backend in mainline everyday. If
> > there is interest from 

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

[Dimitar Dimitrov]

On петък, 11 декември 2020 г. 19:00:35 EET abebeos wrote:
> After "digesting" a bit more your review, I need to thank you for opening
> my eyes re "cherrypick" suggestion and... the missing g++ summaries. I need
> to update my setup to provide the g++ test-deltas, too. Note that in my
> test-setup, more c++ tests pass than in yours, not exactly sure why. It's
> in the "unresovled testcases".

Regarding the additional "unresolved testcases" in my results. I traced it to 
a bug in my setup. I did not prepare $HOME/.dejagnurc properly for AVR. I'll 
rerun the tests and post the results.

I'm using stock avr-libc, while I see you are using the avr-libc3 fork. 
Hopefully the main differences are in HW support, not core libc.

Regards,
Dimitar

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

[Dimitar Dimitrov]

On сряда, 9 декември 2020 г. 15:12:49 EET abebeos via Gcc-patches wrote:
> Essence:
> 
> I need a confirmation that the testsuite setup as presented in:
> 
> https://github.com/abebeos/avr-gnu
> 
> works fine.
> 
> The problem with the avr target is that the testsuite cannot be run easily,
> mainly because of the need for a special simulated-target setup, which does
> not work for avr as documented. This led developers to a dead-end with
> their non-cc0-avr-backends (the non-cc0 backend is needed thus avr is not
> dropped from gcc11).
> 
> I integrated a toolchain/testsetup to be able to run the gcc testsuite
> against a simulated avr target.
> 
> I then used this toolchain to test 2 different existent
> non-cc0-avr-backends (from pipcet and saaadhu, both github).
> 
> The result is that saaadhu's backend seems to be working 100%. It has
> identical testsuite results with the existing (but deprecated) cc0-backend,
> which means that it can be used "as-is" for inclusion in gcc11.
> 
> Please note that I did this work in context of a bounty @ bountysouce, more
> information within the issue:
> 
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92729#c35
Hi,

I tested the trees you have given with my own AVR test setup [1]. I confirm 
your results:
  - saaadhu's tree does not introduce any regressions.
  - pipcet's tree has 142 gcc and 299 g++ regressions (although many of them
are duplicates, e.g. same test case with different optimization levels).

It's a bit awkward to copy gcc/config/avr into a mainline tree. Looking at 
their github history, both authors made some small changes in other areas. I 
would have prefered to cherry-pick or apply patches.

=
baseline beb9afcaf1466996a301c778596c5df209e7913c

=== gcc Summary ===

# of expected passes87504
# of unexpected failures1105
# of unexpected successes   15
# of expected failures  581
# of unresolved testcases   16786
# of unsupported tests  5370

=== g++ Summary ===

# of expected passes140663
# of unexpected failures7932
# of unexpected successes   21
# of expected failures  620
# of unresolved testcases   8603
# of unsupported tests  11305

=
pipcet/avr-ccmode

=== gcc Summary ===

# of expected passes87463
# of unexpected failures1221
# of unexpected successes   15
# of expected failures  581
# of unresolved testcases   16799
# of unsupported tests  5359

=== g++ Summary ===

# of expected passes140529
# of unexpected failures8205
# of unexpected successes   21
# of expected failures  620
# of unresolved testcases   8607
# of unsupported tests  11301

=
saadhu/avr-cc0
=== gcc Summary ===

# of expected passes87504
# of unexpected failures1105
# of unexpected successes   15
# of expected failures  581
# of unresolved testcases   16786
# of unsupported tests  5370

=== g++ Summary ===

# of expected passes140663
# of unexpected failures7932
# of unexpected successes   21
# of expected failures  620
# of unresolved testcases   8603
# of unsupported tests  11305

On a side note, I build and test AVR backend in mainline everyday. If there is 
interest from AVR maintainers I can post daily results to gcc-testresults@ 
mailing list.

Regards,
Dimitar

[1] https://github.com/dinuxbg/gnupru/blob/master/testing/buildbot-avr.sh

Re: [PATCH] pru: Add builtins for HALT and LMBD

[Dimitar Dimitrov]

On четвъртък, 19 ноември 2020 г. 2:07:59 EET Jeff Law wrote:
> On 11/13/20 1:07 PM, Dimitar Dimitrov wrote:
> > Add builtins for HALT and LMBD, per Texas Instruments document
> > SPRUHV7C.  Use the new LMBD pattern to define an expand for clz.
> > 
> > Binutils [1] and sim [2] support for LMBD instruction are merged now.
> > 
> > [1] https://sourceware.org/pipermail/binutils/2020-October/113901.html
> > [2] https://sourceware.org/pipermail/gdb-patches/2020-November/173141.html
> > 
> > gcc/ChangeLog:
> > * config/pru/alu-zext.md: Add lmbd patterns for zero_extend
> > variants.
> > * config/pru/pru.c (enum pru_builtin): Add HALT and LMBD.
> > (pru_init_builtins): Ditto.
> > (pru_builtin_decl): Ditto.
> > (pru_expand_builtin): Ditto.
> > * config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Define PRU
> > value for CLZ with zero value parameter.
> > * config/pru/pru.md: Add halt, lmbd and clz patterns.
> > * doc/extend.texi: Document PRU builtins.
> > 
> > gcc/testsuite/ChangeLog:
> > * gcc.target/pru/halt.c: New test.
> > * gcc.target/pru/lmbd.c: New test.
> 
> OK.  Please commit if you haven't already.

Thank you. Pushed as 5ace1776b88d4b0fc371414d0b3983015e22fead .

Regards,
Dimitar

[PATCH] pru: Add builtins for HALT and LMBD

[Dimitar Dimitrov]

Add builtins for HALT and LMBD, per Texas Instruments document
SPRUHV7C.  Use the new LMBD pattern to define an expand for clz.

Binutils [1] and sim [2] support for LMBD instruction are merged now.

[1] https://sourceware.org/pipermail/binutils/2020-October/113901.html
[2] https://sourceware.org/pipermail/gdb-patches/2020-November/173141.html

gcc/ChangeLog:

* config/pru/alu-zext.md: Add lmbd patterns for zero_extend
variants.
* config/pru/pru.c (enum pru_builtin): Add HALT and LMBD.
(pru_init_builtins): Ditto.
(pru_builtin_decl): Ditto.
(pru_expand_builtin): Ditto.
* config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Define PRU
value for CLZ with zero value parameter.
* config/pru/pru.md: Add halt, lmbd and clz patterns.
* doc/extend.texi: Document PRU builtins.

gcc/testsuite/ChangeLog:

* gcc.target/pru/halt.c: New test.
* gcc.target/pru/lmbd.c: New test.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/config/pru/alu-zext.md  | 51 
 gcc/config/pru/pru.c| 62 ++---
 gcc/config/pru/pru.h|  3 ++
 gcc/config/pru/pru.md   | 40 +++
 gcc/doc/extend.texi | 28 +
 gcc/testsuite/gcc.target/pru/halt.c |  9 +
 gcc/testsuite/gcc.target/pru/lmbd.c | 14 +++
 7 files changed, 201 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/pru/halt.c
 create mode 100644 gcc/testsuite/gcc.target/pru/lmbd.c

diff --git a/gcc/config/pru/alu-zext.md b/gcc/config/pru/alu-zext.md
index 65916c70d65..35a6dbdda79 100644
--- a/gcc/config/pru/alu-zext.md
+++ b/gcc/config/pru/alu-zext.md
@@ -37,6 +37,10 @@ (define_subst_attr "alu3_zext_op1" "alu3_zext_op1_subst" 
"_z1" "_noz1")
 (define_subst_attr "alu3_zext_op2" "alu3_zext_op2_subst" "_z2" "_noz2")
 (define_subst_attr "alu3_zext" "alu3_zext_subst" "_z" "_noz")
 
+(define_subst_attr "lmbd_zext_op1" "lmbd_zext_op1_subst" "_z1" "_noz1")
+(define_subst_attr "lmbd_zext_op2" "lmbd_zext_op2_subst" "_z2" "_noz2")
+(define_subst_attr "lmbd_zext" "lmbd_zext_subst" "_z"  "_noz")
+
 (define_subst_attr "bitalu_zext"   "bitalu_zext_subst"   "_z" "_noz")
 
 (define_code_iterator ALUOP3 [plus minus and ior xor umin umax ashift 
lshiftrt])
@@ -72,6 +76,19 @@ (define_insn 
"sub_impl__"
+  [(set (match_operand:EQD 0 "register_operand" "=r")
+   (unspec:EQD
+ [(zero_extend:EQD
+(match_operand:EQS0 1 "register_operand" "r"))
+  (zero_extend:EQD
+(match_operand:EQS1 2 "reg_or_ubyte_operand" 
"r"))]
+ UNSPEC_LMBD))]
+  ""
+  "lmbd\t%0, %1, %2"
+  [(set_attr "type" "alu")])
+
 (define_insn "neg_impl_"
   [(set (match_operand:EQD 0 "register_operand" "=r")
(neg:EQD
@@ -179,3 +196,37 @@ (define_subst "alu3_zext_op2_subst"
   [(set (match_dup 0)
(ALUOP3:EQD (zero_extend:EQD (match_dup 1))
(match_dup 2)))])
+
+
+(define_subst "lmbd_zext_subst"
+  [(set (match_operand:EQD 0)
+   (unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
+(zero_extend:EQD (match_operand:EQD 2))]
+   UNSPEC_LMBD))]
+  ""
+  [(set (match_dup 0)
+   (unspec:EQD [(match_dup 1)
+(match_dup 2)]
+   UNSPEC_LMBD))])
+
+(define_subst "lmbd_zext_op1_subst"
+  [(set (match_operand:EQD 0)
+   (unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
+(zero_extend:EQD (match_operand:EQS1 2))]
+   UNSPEC_LMBD))]
+  ""
+  [(set (match_dup 0)
+   (unspec:EQD [(match_dup 1)
+(zero_extend:EQD (match_dup 2))]
+   UNSPEC_LMBD))])
+
+(define_subst "lmbd_zext_op2_subst"
+  [(set (match_operand:EQD 0)
+   (unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
+(zero_extend:EQD (match_operand:EQD 2))]
+   UNSPEC_LMBD))]
+  ""
+  [(set (match_dup 0)
+   (unspec:EQD [(zero_extend:EQD (match_dup 1))
+(match_dup 2)]
+   UNSPEC_LMBD))])
diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index 39104e5f9cd..65ad6878a12 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -2705,6 +2705,8 @@ pru_reorg (void)
 enum pru_builtin
 {
   PRU_BUILTIN_DELAY_CYCLES,
+  PRU_BUILTIN_HALT,
+  PRU_BUILTIN_LMBD,
   PRU_BUILTIN_max
 };
 
@@ -2719,11 +2721,31 @@ pru_init_builtins (void)
 

Re: [PATCH] Add TARGET_LOWER_LOCAL_DECL_ALIGNMENT [PR95237]

[Dimitar Dimitrov]

On сряда, 22 юли 2020 г. 2:04:35 EEST Sunil Pandey via Gcc-patches wrote:
> On Tue, Jul 21, 2020 at 12:50 AM Richard Biener
> 
>  wrote:
> > On Tue, Jul 21, 2020 at 7:16 AM Sunil Pandey  wrote:
> > > On Mon, Jul 20, 2020 at 5:06 AM Richard Biener
> > > 
> > >  wrote:
> > > > On Sat, Jul 18, 2020 at 7:57 AM Sunil Pandey  
wrote:
> > > > > On Fri, Jul 17, 2020 at 1:22 AM Richard Biener
> > > > > 
> > > > >  wrote:
> > > > > > On Fri, Jul 17, 2020 at 7:15 AM Sunil Pandey  
wrote:
> > > > > > > Any comment on revised patch? At least,  in finish_decl, decl
> > > > > > > global attributes are populated.> > > > > 
> > > > > > +static void
> > > > > > +ix86_lower_local_decl_alignment (tree decl)
> > > > > > +{
> > > > > > +  unsigned new_align = LOCAL_DECL_ALIGNMENT (decl);
> > > > > > 
> > > > > > please use the macro-expanded call here since we want to amend
> > > > > > ix86_local_alignment to _not_ return a lower alignment when
> > > > > > called as LOCAL_DECL_ALIGNMENT (by adding a new parameter
> > > > > > to ix86_local_alignment).  Can you also amend the patch in this
> > > > > > way?
> > > > > > 
> > > > > > +  if (new_align < DECL_ALIGN (decl))
> > > > > > +SET_DECL_ALIGN (decl, new_align);
> > > > > > 
> > > > > > diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c
> > > > > > index 81bd2ee94f0..1ae99e30ed1 100644
> > > > > > --- a/gcc/c/c-decl.c
> > > > > > +++ b/gcc/c/c-decl.c
> > > > > > @@ -5601,6 +5601,8 @@ finish_decl (tree decl, location_t init_loc,
> > > > > > tree init,> > > > > 
> > > > > >  }
> > > > > >
> > > > > >invoke_plugin_callbacks (PLUGIN_FINISH_DECL, decl);
> > > > > > 
> > > > > > +  /* Lower local decl alignment.  */
> > > > > > +  lower_decl_alignment (decl);
> > > > > > 
> > > > > >  }
> > > > > > 
> > > > > > should come before plugin hook invocation, likewise for the
> > > > > > cp_finish_decl case.
> > > > > > 
> > > > > > +/* Lower DECL alignment.  */
> > > > > > +
> > > > > > +void
> > > > > > +lower_decl_alignment (tree decl)
> > > > > > +{
> > > > > > +  if (VAR_P (decl)
> > > > > > +  && !is_global_var (decl)
> > > > > > +  && !DECL_HARD_REGISTER (decl))
> > > > > > +targetm.lower_local_decl_alignment (decl);
> > > > > > +}
> > > > > > 
> > > > > > please avoid this function, it's name sounds too generic and it's
> > > > > > not worth
> > > > > > adding a public API for two calls.
> > > > > > 
> > > > > > Alltogether this should avoid the x86 issue leaving left-overs
> > > > > > (your identified inliner case) as missed optimization [for the
> > > > > > linux kernel which appearantly decided that
> > > > > > -mpreferred-stack-boundary=2 is a good ABI to use].
> > > > > > 
> > > > > > Richard.
> > > > > 
> > > > > Revised patch attached.
> > > > 
> > > > @@ -16776,7 +16783,7 @@ ix86_data_alignment (tree type, unsigned int
> > > > align, bool opt)
> > > > 
> > > >  unsigned int
> > > >  ix86_local_alignment (tree exp, machine_mode mode,
> > > > 
> > > > - unsigned int align)
> > > > + unsigned int align, bool setalign)
> > > > 
> > > >  {
> > > >  
> > > >tree type, decl;
> > > > 
> > > > @@ -16801,6 +16808,10 @@ ix86_local_alignment (tree exp, machine_mode
> > > > mode,
> > > > 
> > > >&& (!decl || !DECL_USER_ALIGN (decl)))
> > > >  
> > > >  align = 32;
> > > > 
> > > > +  /* Lower decl alignment.  */
> > > > +  if (setalign && align < DECL_ALIGN (decl))
> > > > +SET_DECL_ALIGN (decl, align);
> > > > +
> > > > 
> > > >/* If TYPE is NULL, we are allocating a stack slot for caller-save
> > > >
> > > >   register in MODE.  We will return the largest alignment of XF
> > > >   and DF.  */
> > > > 
> > > > sorry for not being clear - the parameter should indicate whether an
> > > > alignment lower
> > > > than natural alignment is OK to return thus sth like
> > > > 
> > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > > index 31757b044c8..19703cbceb9 100644
> > > > --- a/gcc/config/i386/i386.c
> > > > +++ b/gcc/config/i386/i386.c
> > > > @@ -16641,7 +16641,7 @@ ix86_data_alignment (tree type, unsigned int
> > > > align, bool opt)
> > > > 
> > > >  unsigned int
> > > >  ix86_local_alignment (tree exp, machine_mode mode,
> > > > 
> > > > - unsigned int align)
> > > > + unsigned int align, bool may_lower)
> > > > 
> > > >  {
> > > >  
> > > >tree type, decl;
> > > > 
> > > > @@ -16658,7 +16658,8 @@ ix86_local_alignment (tree exp, machine_mode
> > > > mode,
> > > > 
> > > >/* Don't do dynamic stack realignment for long long objects with
> > > >
> > > >   -mpreferred-stack-boundary=2.  */
> > > > 
> > > > -  if (!TARGET_64BIT
> > > > +  if (may_lower
> > > > +  && !TARGET_64BIT
> > > > 
> > > >&& align == 64
> > > >&& ix86_preferred_stack_boundary < 64
> > > >&& (mode == DImode || (type && TYPE_MODE (type) == DImode))
> > > > 
> > > > I also believe that spill_slot_alignment () 

Re: [PATCH 0/4] testsuite: Add markers for default_packed targets

[Dimitar Dimitrov]

On Mon, 20 July 2020 г. 19:31:02 EEST Dimitar Dimitrov wrote:
> Hi,
> 
> I'm sending a few minor testsuite updates to add markers for targets using
> packed structures by default. From those targets, I tested AVR and PRU. I
> don't have setup to test cris and m32c.
> 
> I also tested x86_64 to ensure there are neither dropped nor newly failing
> tests.
> 
> Regards,
> Dimitar
> 
> Dimitar Dimitrov (4):
>   testsuite: Filter unaligned pointer value warning
>   testsuite: Add expected warning for packed attribute
>   testsuite: Relax pattern to include "packed" targets
>   testsuite: Add default_packed filters
> 
>  .../Waddress-of-packed-member-1.c | 48 +--
>  .../Waddress-of-packed-member-2.c | 37 +++---
>  gcc/testsuite/c-c++-common/Wattributes.c  |  2 +-
>  gcc/testsuite/c-c++-common/attr-copy.c|  1 +
>  .../c-c++-common/builtin-has-attribute-4.c|  2 +-
>  gcc/testsuite/c-c++-common/pr51628-13.c   |  2 +-
>  gcc/testsuite/c-c++-common/pr51628-15.c   |  2 +-
>  gcc/testsuite/c-c++-common/pr51628-16.c   |  4 +-
>  gcc/testsuite/c-c++-common/pr51628-26.c   |  6 +--
>  gcc/testsuite/c-c++-common/pr51628-27.c   |  2 +-
>  gcc/testsuite/c-c++-common/pr51628-28.c   | 10 ++--
>  gcc/testsuite/c-c++-common/pr51628-29.c   |  3 +-
>  gcc/testsuite/c-c++-common/pr51628-3.c| 12 ++---
>  gcc/testsuite/c-c++-common/pr51628-30.c   |  5 +-
>  gcc/testsuite/c-c++-common/pr51628-31.c   |  2 +-
>  gcc/testsuite/c-c++-common/pr51628-32.c   |  3 +-
>  gcc/testsuite/c-c++-common/pr51628-33.c   |  2 +-
>  gcc/testsuite/c-c++-common/pr51628-35.c   |  4 +-
>  gcc/testsuite/c-c++-common/pr51628-4.c| 12 ++---
>  gcc/testsuite/c-c++-common/pr51628-5.c| 12 ++---
>  gcc/testsuite/c-c++-common/pr51628-6.c| 12 ++---
>  gcc/testsuite/c-c++-common/pr51628-8.c| 14 +++---
>  gcc/testsuite/c-c++-common/pr51628-9.c| 14 +++---
>  gcc/testsuite/c-c++-common/pr88664-2.c|  4 +-
>  gcc/testsuite/gcc.dg/Wattributes-6.c  |  2 +-
>  gcc/testsuite/gcc.dg/attr-copy-4.c|  4 +-
>  gcc/testsuite/gcc.dg/attr-copy-8.c| 25 ++
>  gcc/testsuite/gcc.dg/c11-align-9.c|  4 +-
>  gcc/testsuite/gcc.dg/pr51628-17.c |  2 +-
>  gcc/testsuite/gcc.dg/pr51628-19.c |  6 +--
>  gcc/testsuite/gcc.dg/pr51628-20.c |  2 +-
>  gcc/testsuite/gcc.dg/pr51628-21.c |  2 +-
>  gcc/testsuite/gcc.dg/pr51628-22.c |  2 +-
>  gcc/testsuite/gcc.dg/pr51628-24.c |  2 +-
>  gcc/testsuite/gcc.dg/pr51628-25.c |  2 +-
>  gcc/testsuite/gcc.dg/pr51628-34.c |  8 ++--
>  gcc/testsuite/gcc.dg/pr53037-1.c  |  4 +-
>  gcc/testsuite/gcc.dg/pr88928.c|  2 +-
>  38 files changed, 157 insertions(+), 125 deletions(-)

I pushed all 4 changes, with the pattern and quoting update suggested by 
Richard for the third patch.


Thanks,
Dimitar

[PATCH 0/4] testsuite: Add markers for default_packed targets

[Dimitar Dimitrov]

Hi,

I'm sending a few minor testsuite updates to add markers for targets using 
packed structures by default. From those targets, I tested AVR and PRU. I don't 
have setup to test cris and m32c.

I also tested x86_64 to ensure there are neither dropped nor newly failing 
tests.

Regards,
Dimitar

Dimitar Dimitrov (4):
  testsuite: Filter unaligned pointer value warning
  testsuite: Add expected warning for packed attribute
  testsuite: Relax pattern to include "packed" targets
  testsuite: Add default_packed filters

 .../Waddress-of-packed-member-1.c | 48 +--
 .../Waddress-of-packed-member-2.c | 37 +++---
 gcc/testsuite/c-c++-common/Wattributes.c  |  2 +-
 gcc/testsuite/c-c++-common/attr-copy.c|  1 +
 .../c-c++-common/builtin-has-attribute-4.c|  2 +-
 gcc/testsuite/c-c++-common/pr51628-13.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-15.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-16.c   |  4 +-
 gcc/testsuite/c-c++-common/pr51628-26.c   |  6 +--
 gcc/testsuite/c-c++-common/pr51628-27.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-28.c   | 10 ++--
 gcc/testsuite/c-c++-common/pr51628-29.c   |  3 +-
 gcc/testsuite/c-c++-common/pr51628-3.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-30.c   |  5 +-
 gcc/testsuite/c-c++-common/pr51628-31.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-32.c   |  3 +-
 gcc/testsuite/c-c++-common/pr51628-33.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-35.c   |  4 +-
 gcc/testsuite/c-c++-common/pr51628-4.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-5.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-6.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-8.c| 14 +++---
 gcc/testsuite/c-c++-common/pr51628-9.c| 14 +++---
 gcc/testsuite/c-c++-common/pr88664-2.c|  4 +-
 gcc/testsuite/gcc.dg/Wattributes-6.c  |  2 +-
 gcc/testsuite/gcc.dg/attr-copy-4.c|  4 +-
 gcc/testsuite/gcc.dg/attr-copy-8.c| 25 ++
 gcc/testsuite/gcc.dg/c11-align-9.c|  4 +-
 gcc/testsuite/gcc.dg/pr51628-17.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-19.c |  6 +--
 gcc/testsuite/gcc.dg/pr51628-20.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-21.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-22.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-24.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-25.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-34.c |  8 ++--
 gcc/testsuite/gcc.dg/pr53037-1.c  |  4 +-
 gcc/testsuite/gcc.dg/pr88928.c|  2 +-
 38 files changed, 157 insertions(+), 125 deletions(-)

-- 
2.20.1

[PATCH 4/4] testsuite: Add default_packed filters

[Dimitar Dimitrov]

Fix test cases assumptions that target has alignment constraints.

gcc/testsuite/ChangeLog:

* gcc.dg/attr-copy-4.c: Unpacked may still have alignment of 1
on targets with default_packed.
* gcc.dg/c11-align-9.c: Remove AVR target filter and replace
with default_packed filter.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/attr-copy-4.c | 1 +
 gcc/testsuite/gcc.dg/c11-align-9.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/attr-copy-4.c 
b/gcc/testsuite/gcc.dg/attr-copy-4.c
index 796724bb950..01fae3f78d4 100644
--- a/gcc/testsuite/gcc.dg/attr-copy-4.c
+++ b/gcc/testsuite/gcc.dg/attr-copy-4.c
@@ -32,6 +32,7 @@ extern const struct PackedA packed;
 
 struct Unpacked { int i; char c; };
 Assert (__alignof (struct Unpacked) > 1);
+/* { dg-error "size of array .* is negative" "" { target default_packed } .-1 
} */
 
 /* Verify that copying the packed attribute to the declaration
of an object is ignored with a warning.  (There should be
diff --git a/gcc/testsuite/gcc.dg/c11-align-9.c 
b/gcc/testsuite/gcc.dg/c11-align-9.c
index 3c9cf55756e..6a0d4248f1b 100644
--- a/gcc/testsuite/gcc.dg/c11-align-9.c
+++ b/gcc/testsuite/gcc.dg/c11-align-9.c
@@ -2,8 +2,8 @@
are at least some alignment constraints), case of compound literals.  */
 /* { dg-do compile } */
 /* { dg-options "-std=c11 -pedantic-errors" } */
-/* { dg-skip-if "no alignment constraints" { "avr-*-*" } } */
 
 #include 
 
-max_align_t *p = &(_Alignas (_Alignof (char)) max_align_t) { 1 }; /* { 
dg-error "reduce alignment" } */
+max_align_t *p = &(_Alignas (_Alignof (char)) max_align_t) { 1 };
+/* { dg-error "reduce alignment" "" { target { ! default_packed } } .-1 } */
-- 
2.20.1

[PATCH 2/4] testsuite: Add expected warning for packed attribute

[Dimitar Dimitrov]

Targets which pack structures by default get warnings for packed structure
attributes. This is expected, so add markers in the test cases.

gcc/testsuite/ChangeLog:

* c-c++-common/Waddress-of-packed-member-2.c: Add dg-warning for
ignored attribute if target is default_packed.
* c-c++-common/Wattributes.c: Ditto.
* c-c++-common/attr-copy.c: Ditto.
* c-c++-common/builtin-has-attribute-4.c: Ditto.
* c-c++-common/pr51628-29.c: Ditto.
* c-c++-common/pr51628-30.c: Ditto.
* c-c++-common/pr51628-32.c: Ditto.
* gcc.dg/Wattributes-6.c: Ditto.
* gcc.dg/attr-copy-4.c: Ditto.
* gcc.dg/attr-copy-8.c: Ditto.

Signed-off-by: Dimitar Dimitrov 
---
 .../Waddress-of-packed-member-2.c |  1 +
 gcc/testsuite/c-c++-common/Wattributes.c  |  2 +-
 gcc/testsuite/c-c++-common/attr-copy.c|  1 +
 .../c-c++-common/builtin-has-attribute-4.c|  2 +-
 gcc/testsuite/c-c++-common/pr51628-29.c   |  1 +
 gcc/testsuite/c-c++-common/pr51628-30.c   |  1 +
 gcc/testsuite/c-c++-common/pr51628-32.c   |  1 +
 gcc/testsuite/gcc.dg/Wattributes-6.c  |  2 +-
 gcc/testsuite/gcc.dg/attr-copy-4.c|  3 ++-
 gcc/testsuite/gcc.dg/attr-copy-8.c| 25 +++
 10 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/Waddress-of-packed-member-2.c 
b/gcc/testsuite/c-c++-common/Waddress-of-packed-member-2.c
index 5dbcb89ffbc..802dd8156cb 100644
--- a/gcc/testsuite/c-c++-common/Waddress-of-packed-member-2.c
+++ b/gcc/testsuite/c-c++-common/Waddress-of-packed-member-2.c
@@ -15,6 +15,7 @@ struct s {
 struct t {
   char c;
   struct r p __attribute__((packed));
+  /* { dg-warning "attribute ignored" "" { target default_packed } .-1 } */
   struct r u;
 };
 
diff --git a/gcc/testsuite/c-c++-common/Wattributes.c 
b/gcc/testsuite/c-c++-common/Wattributes.c
index 3f176a04660..4ad90441b4d 100644
--- a/gcc/testsuite/c-c++-common/Wattributes.c
+++ b/gcc/testsuite/c-c++-common/Wattributes.c
@@ -21,7 +21,7 @@ PackedAligned { int i; };
 struct ATTR ((aligned (2)))
 AlignedMemberPacked
 {
-  int ATTR ((packed)) i;
+  int ATTR ((packed)) i; // { dg-warning "attribute ignored" "" { target 
default_packed } }
 };
 
 struct ATTR ((packed))
diff --git a/gcc/testsuite/c-c++-common/attr-copy.c 
b/gcc/testsuite/c-c++-common/attr-copy.c
index 284088a8b97..f0db0fd1a27 100644
--- a/gcc/testsuite/c-c++-common/attr-copy.c
+++ b/gcc/testsuite/c-c++-common/attr-copy.c
@@ -21,6 +21,7 @@ struct C
 {
   char c;
   ATTR (copy ((bar (), ((struct A *)(0))[0]))) int i;
+  /* { dg-warning "attribute ignored" "" { target default_packed } .-1 } */
 };
 
 /* Verify the attribute has been copied.  */
diff --git a/gcc/testsuite/c-c++-common/builtin-has-attribute-4.c 
b/gcc/testsuite/c-c++-common/builtin-has-attribute-4.c
index ec3127794b5..3a960aae2ff 100644
--- a/gcc/testsuite/c-c++-common/builtin-has-attribute-4.c
+++ b/gcc/testsuite/c-c++-common/builtin-has-attribute-4.c
@@ -130,7 +130,7 @@ struct PackedMember
   char c;
   short s;
   int i;
-  ATTR (packed) int a[2];
+  ATTR (packed) int a[2]; /* { dg-warning "attribute ignored" "" { target 
default_packed } } */
 } gpak[2];
 
 void test_packed (struct PackedMember *p)
diff --git a/gcc/testsuite/c-c++-common/pr51628-29.c 
b/gcc/testsuite/c-c++-common/pr51628-29.c
index a3e77455b6b..1ad9a7d2d9f 100644
--- a/gcc/testsuite/c-c++-common/pr51628-29.c
+++ b/gcc/testsuite/c-c++-common/pr51628-29.c
@@ -5,6 +5,7 @@
 struct A { int i; };
 struct B { struct A a; };
 struct C { struct B b __attribute__ ((packed)); };
+/* { dg-warning "attribute ignored" "" { target default_packed } .-1 } */
 
 extern struct C *p;
 
diff --git a/gcc/testsuite/c-c++-common/pr51628-30.c 
b/gcc/testsuite/c-c++-common/pr51628-30.c
index b31e73ec036..387fc71db13 100644
--- a/gcc/testsuite/c-c++-common/pr51628-30.c
+++ b/gcc/testsuite/c-c++-common/pr51628-30.c
@@ -5,6 +5,7 @@
 struct A { __complex int i; };
 struct B { struct A a; };
 struct C { struct B b __attribute__ ((packed)); };
+/* { dg-warning "attribute ignored" "" { target default_packed } .-1 } */
 
 extern struct C *p;
 
diff --git a/gcc/testsuite/c-c++-common/pr51628-32.c 
b/gcc/testsuite/c-c++-common/pr51628-32.c
index 52f5e543ab7..908c0b8cbf4 100644
--- a/gcc/testsuite/c-c++-common/pr51628-32.c
+++ b/gcc/testsuite/c-c++-common/pr51628-32.c
@@ -11,6 +11,7 @@ struct B
 {
char c;
__attribute ((packed)) struct A ar[4];
+   /* { dg-warning "attribute ignored" "" { target default_packed } .-1 } */
 };
 
 struct B b;
diff --git a/gcc/testsuite/gcc.dg/Wattributes-6.c 
b/gcc/testsuite/gcc.dg/Wattributes-6.c
index d3dd22d85b9..4ba59bf2806 100644
--- a/gcc/testsuite/gcc.dg/Wattributes-6.c
+++ b/gcc/testsuite/gcc.dg/Wattributes-6.c
@@ -21,7 +21,7 @@ PackedAligned { int i; };
 struct ATTR

[PATCH 3/4] testsuite: Relax pattern to include "packed" targets

[Dimitar Dimitrov]

The actual warning message depends on the default alignment of the
target. With this update the test correctly passes on AVR and PRU
targets.

gcc/testsuite/ChangeLog:

* gcc.dg/pr53037-1.c: Relax warning pattern.

Signed-off-by: Dimitar Dimitrov 
---
 gcc/testsuite/gcc.dg/pr53037-1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/pr53037-1.c b/gcc/testsuite/gcc.dg/pr53037-1.c
index 3ea5ae6a34e..b4e9049c746 100644
--- a/gcc/testsuite/gcc.dg/pr53037-1.c
+++ b/gcc/testsuite/gcc.dg/pr53037-1.c
@@ -40,7 +40,7 @@ struct foo5
 {
   int i1;
   int x __attribute__((warn_if_not_aligned(16))); /* { dg-warning "'x' offset 
4 in 'struct foo5' isn't aligned to 16" } */
-}; /* { dg-warning "alignment 4 of 'struct foo5' is less than 16" } */
+}; /* { dg-warning "alignment .* of 'struct foo5' is less than 16" } */
 
 struct foo6
 {
@@ -73,7 +73,7 @@ union bar3
 {
   int i1;
   int x __attribute__((warn_if_not_aligned(16))); 
-}; /* { dg-warning "alignment 4 of 'union bar3' is less than 16" } */
+}; /* { dg-warning "alignment .* of 'union bar3' is less than 16" } */
 
 union bar4
 {
-- 
2.20.1

[PATCH 1/4] testsuite: Filter unaligned pointer value warning

[Dimitar Dimitrov]

Targets which pack structures by default will not get warnings about
unaligned access to structure members.

gcc/testsuite/ChangeLog:

* c-c++-common/Waddress-of-packed-member-1.c: Filter dg-warning
for targets who pack by default.
* c-c++-common/Waddress-of-packed-member-2.c: Ditto.
* c-c++-common/pr51628-13.c: Ditto.
* c-c++-common/pr51628-15.c: Ditto.
* c-c++-common/pr51628-16.c: Ditto.
* c-c++-common/pr51628-26.c: Ditto.
* c-c++-common/pr51628-27.c: Ditto.
* c-c++-common/pr51628-28.c: Ditto.
* c-c++-common/pr51628-29.c: Ditto.
* c-c++-common/pr51628-3.c: Ditto.
* c-c++-common/pr51628-30.c: Ditto.
* c-c++-common/pr51628-31.c: Ditto.
* c-c++-common/pr51628-32.c: Ditto.
* c-c++-common/pr51628-33.c: Ditto.
* c-c++-common/pr51628-35.c: Ditto.
* c-c++-common/pr51628-4.c: Ditto.
* c-c++-common/pr51628-5.c: Ditto.
* c-c++-common/pr51628-6.c: Ditto.
* c-c++-common/pr51628-8.c: Ditto.
* c-c++-common/pr51628-9.c: Ditto.
* c-c++-common/pr88664-2.c: Ditto.
* gcc.dg/pr51628-17.c: Ditto.
* gcc.dg/pr51628-19.c: Ditto.
* gcc.dg/pr51628-20.c: Ditto.
* gcc.dg/pr51628-21.c: Ditto.
* gcc.dg/pr51628-22.c: Ditto.
* gcc.dg/pr51628-24.c: Ditto.
* gcc.dg/pr51628-25.c: Ditto.
* gcc.dg/pr51628-34.c: Ditto.
* gcc.dg/pr88928.c: Ditto.

Signed-off-by: Dimitar Dimitrov 
---
 .../Waddress-of-packed-member-1.c | 48 +--
 .../Waddress-of-packed-member-2.c | 36 +++---
 gcc/testsuite/c-c++-common/pr51628-13.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-15.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-16.c   |  4 +-
 gcc/testsuite/c-c++-common/pr51628-26.c   |  6 +--
 gcc/testsuite/c-c++-common/pr51628-27.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-28.c   | 10 ++--
 gcc/testsuite/c-c++-common/pr51628-29.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-3.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-30.c   |  4 +-
 gcc/testsuite/c-c++-common/pr51628-31.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-32.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-33.c   |  2 +-
 gcc/testsuite/c-c++-common/pr51628-35.c   |  4 +-
 gcc/testsuite/c-c++-common/pr51628-4.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-5.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-6.c| 12 ++---
 gcc/testsuite/c-c++-common/pr51628-8.c| 14 +++---
 gcc/testsuite/c-c++-common/pr51628-9.c| 14 +++---
 gcc/testsuite/c-c++-common/pr88664-2.c|  4 +-
 gcc/testsuite/gcc.dg/pr51628-17.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-19.c |  6 +--
 gcc/testsuite/gcc.dg/pr51628-20.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-21.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-22.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-24.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-25.c |  2 +-
 gcc/testsuite/gcc.dg/pr51628-34.c |  8 ++--
 gcc/testsuite/gcc.dg/pr88928.c|  2 +-
 30 files changed, 117 insertions(+), 117 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/Waddress-of-packed-member-1.c 
b/gcc/testsuite/c-c++-common/Waddress-of-packed-member-1.c
index afad603dfa2..95a376664da 100644
--- a/gcc/testsuite/c-c++-common/Waddress-of-packed-member-1.c
+++ b/gcc/testsuite/c-c++-common/Waddress-of-packed-member-1.c
@@ -52,28 +52,28 @@ void foo (void)
   f0 = *&__real__ t0.f;/* { dg-bogus "may result in an unaligned 
pointer value" } */
   f0 = *&__imag__ t0.f;/* { dg-bogus "may result in an unaligned 
pointer value" } */
   i1 = (, (int*) 0);  /* { dg-bogus "may result in an unaligned 
pointer value" } */
-  t2 = (struct t**) t10; /* { dg-warning "may result in an unaligned 
pointer value" } */
-  t2 = (struct t**) t100;/* { dg-warning "may result in an unaligned 
pointer value" } */
-  t2 = (struct t**) t1;  /* { dg-warning "may result in an unaligned 
pointer value" } */
-  t2 = (struct t**) bar();   /* { dg-warning "may result in an unaligned 
pointer value" } */
-  t2 = (struct t**) baz();   /* { dg-warning "may result in an unaligned 
pointer value" } */
-  t2 = (struct t**) bazz();  /* { dg-warning "may result in an unaligned 
pointer value" } */
-  i1 = /* { dg-warning "may result in an unaligned 
pointer value" } */
-  i1 = >b;   /* { dg-warning "may result in an unaligned 
pointer value" } */
-  i1 = [0].b;/* { dg-warning "may result in an unaligned 
pointer value" } */
-  i1 = t0.d; /* { dg-warning "may result in an unaligned 
pointer value" } */
-  i1 = t1->d;  

Re: [PATCH 3/6] contrib: Add pru-elf to config-list.mk

[Dimitar Dimitrov]

On неделя, 31 май 2020 г. 13:17:21 EEST Iain Buclaw wrote:
> Support for the TI PRU target was added in SVN r272202.
> 
> Judging from the testsuite results posted at the time[1], the only
> supported target is pru-elf.
> 
> OK?
> 
> Regards
> Iain.
> 
> [1]: http://dinux.eu/gnupru/testresults/index.html
> 
> ---
Thank you. I confirm that pru-elf is the only supported target.

My bot also posts daily to gcc-testresults [1].

Regards,
Dimitar

[1]  https://gcc.gnu.org/pipermail/gcc-testresults/2020-May/560070.html

Re: [PATCH v2 0/5] Updates for PRU backend

[Dimitar Dimitrov]

On вторник, 5 май 2020 г. 19:00:29 EEST Jeff Law wrote:
> On Sun, 2020-05-03 at 19:11 +0300, Dimitar Dimitrov wrote:
> > One of the changes frees a previously fixed register, per
> > ABI clarification from TI, for local usage from function.
> > The change is backwards compatible.
> > 
> > Rest of changes are cleanups.
> > 
> > Testsuite did not reveal any regressions.
> > 
> > Dimitar Dimitrov (5):
> >   PRU: Fix comment to avoid fall through warning
> >   PRU: Simplify machine description
> >   PRU: Fix R3.w0 register class
> >   testsuite: pru: Add clobber test
> >   PRU: Remove TARGET_HARD_REGNO_CALL_PART_CLOBBERED
> 
> These are all OK for the trunk.  Your call if you want to backport any of
> these changes.

Committed to master.

I don't think it's worth bothering the release team with those cleanups.

Thanks,
Dimitar