Re: [PATCH v2] configure: define TARGET_LIBC_GNUSTACK on musl

[Dragan Mladjenovic]

Hi,

Looks fine to me. If possible, maybe it should even be back-ported to 
stable branches.


Not sure if MIPS assembly sources (if any) in musl would need explicit 
.note.GNU-stack


to complement this?

Best regards,

Dragan

On 16-Nov-21 06:13, Ilya Lipnitskiy wrote:

musl only uses PT_GNU_STACK to set default thread stack size and has no
executable stack support[0], so there is no reason not to emit the
.note.GNU-stack section on musl builds.

[0]: 
https://lore.kernel.org/all/20190423192534.gn23...@brightrain.aerifal.cx/T/#u

gcc/ChangeLog:

* configure: Regenerate.
* configure.ac: define TARGET_LIBC_GNUSTACK on musl

Signed-off-by: Ilya Lipnitskiy 
---
  gcc/configure| 3 +++
  gcc/configure.ac | 3 +++
  2 files changed, 6 insertions(+)

diff --git a/gcc/configure b/gcc/configure
index 74b9d9be4c85..7091a838aefa 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -31275,6 +31275,9 @@ fi
  # Check if the target LIBC handles PT_GNU_STACK.
  gcc_cv_libc_gnustack=unknown
  case "$target" in
+  mips*-*-linux-musl*)
+gcc_cv_libc_gnustack=yes
+;;
mips*-*-linux*)
  
  if test $glibc_version_major -gt 2 \

diff --git a/gcc/configure.ac b/gcc/configure.ac
index c9ee1fb8919e..8a2d34179a75 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -6961,6 +6961,9 @@ fi
  # Check if the target LIBC handles PT_GNU_STACK.
  gcc_cv_libc_gnustack=unknown
  case "$target" in
+  mips*-*-linux-musl*)
+gcc_cv_libc_gnustack=yes
+;;
mips*-*-linux*)
  GCC_GLIBC_VERSION_GTE_IFELSE([2], [31], [gcc_cv_libc_gnustack=yes], )
  ;;

[RFC 6/7] Enable MIPS DSP rev3 ASE for nanoMIPS

[Dragan Mladjenovic via Gcc-patches]

gcc/ChangeLog:

* config/mips/mips-dsp.md (mips_bposge):
Output bposgec for TARGET_DSPR3.
* config/mips/mips.c (mips_output_move):
Use $ac0 for $lo if base isa doesn't have md registers.
(mips_option_override) [TARGET_DSPR3]:
Enable TARGET_DSP and TARGET_DSPR2.
(mips_conditional_register_usage) [ISA_HAS_DSP]:
Don't disable md registers.
* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS)
[TARGET_DSPR3]: Define __mips_dsp_rev=3 and __mips_dspr3.
(ASM_SPEC): Forward mdspr3 and mno-dspr3.
* config/mips/mips.md (mulsidi3_32bit):
Enable for ISA_HAS_DSP.
(mfhi_,
mthi_):
Use $ac0 for $lo if base isa doesn't have md registers.
* config/mips/mips.opt (mdspr3): New option.
Enabled for TARGET_NANOMIPS.
(mdspr2): Disabled for TARGET_NANOMIPS.

gcc/testsuite/ChangeLog:

* gcc.target/nanomips/dpaq_sa_l_w.c: New test.
* gcc.target/nanomips/dpsq_sa_l_w.c: New test.
* gcc.target/nanomips/dsp-ctrl.c: New test.
* gcc.target/nanomips/dsp-lhxs.c: New test.
* gcc.target/nanomips/dsp-no-lhx.c: New test.
* gcc.target/nanomips/fixed-scalar-type.c: New test.
* gcc.target/nanomips/fixed-vector-type.c: New test.
* gcc.target/nanomips/madd-4.c: New test.
* gcc.target/nanomips/maddu-3.c: New test.
* gcc.target/nanomips/maddu-4.c: New test.
* gcc.target/nanomips/mips-prepend-1.c: New test.
* gcc.target/nanomips/mips32-dsp-run.c: New test.
* gcc.target/nanomips/mips32-dspr2.c: New test.
* gcc.target/nanomips/msub-4.c: New test.
* gcc.target/nanomips/msubu-4.c: New test.
* gcc.target/nanomips/nanomips-dsp-accinit-2.c: New test.
* gcc.target/nanomips/nanomips-dsp.c: New test.
* gcc.target/nanomips/nanomips-dspr3-type-1.c: New test.
* gcc.target/nanomips/nanomips-dspr3-type-2.c: New test.
---
 gcc/config/mips/mips-dsp.md   |   17 +-
 gcc/config/mips/mips.c|   22 +-
 gcc/config/mips/mips.h|6 +
 gcc/config/mips/mips.md   |   12 +-
 gcc/config/mips/mips.opt  |6 +-
 .../gcc.target/nanomips/dpaq_sa_l_w.c (new)   |   51 +
 .../gcc.target/nanomips/dpsq_sa_l_w.c (new)   |   37 +
 .../gcc.target/nanomips/dsp-ctrl.c (new)  |   69 +
 .../gcc.target/nanomips/dsp-lhxs.c (new)  |   11 +
 .../gcc.target/nanomips/dsp-no-lhx.c (new)|   11 +
 .../nanomips/fixed-scalar-type.c (new)|  218 
 .../nanomips/fixed-vector-type.c (new)|  133 ++
 .../gcc.target/nanomips/madd-4.c (new)|   27 +
 .../gcc.target/nanomips/maddu-3.c (new)   |   30 +
 .../gcc.target/nanomips/maddu-4.c (new)   |   30 +
 .../nanomips/mips-prepend-1.c (new)   |8 +
 .../nanomips/mips32-dsp-run.c (new)   | 1063 +++
 .../gcc.target/nanomips/mips32-dspr2.c (new)  |  541 
 .../gcc.target/nanomips/msub-4.c (new)|   21 +
 .../gcc.target/nanomips/msubu-4.c (new)   |   24 +
 .../nanomips/nanomips-dsp-accinit-2.c (new)   |   23 +
 .../gcc.target/nanomips/nanomips-dsp.c (new)  | 1160 +
 .../nanomips/nanomips-dspr3-type-1.c (new)|   30 +
 .../nanomips/nanomips-dspr3-type-2.c (new)|   12 +
 24 files changed, 3552 insertions(+), 10 deletions(-)
 24 files changed, 3552 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dpaq_sa_l_w.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dpsq_sa_l_w.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dsp-ctrl.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dsp-lhxs.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/dsp-no-lhx.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/fixed-scalar-type.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/fixed-vector-type.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/madd-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/maddu-3.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/maddu-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/mips-prepend-1.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/mips32-dsp-run.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/mips32-dspr2.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/msub-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/msubu-4.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dsp-accinit-2.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dsp.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dspr3-type-1.c
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-dspr3-type-2.c

diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md
index 5a5694f3f9e..d71ad95aa40 100644
--- a/gcc/config/mips/mips-dsp.md
+++ b/gcc/config/mips/mips-dsp.md
@@ -1152,8 +1152,21 

[RFC 7/7] Add documentation for nanoMIPS

[Dragan Mladjenovic via Gcc-patches]

gcc/ChangeLog:

* doc/extend.texi: Add nanoMIPS Function Attributes,
nanoMIPS Built-in Functions and nanoMIPS DSP Built-in Functions.
* doc/invoke.texi: Add nanoMIPS Options.
* doc/md.texi: Add nanoMIPS constraints.
---
 gcc/doc/extend.texi | 124 +++
 gcc/doc/invoke.texi | 367 
 gcc/doc/md.texi |  71 +
 3 files changed, 562 insertions(+)
 3 files changed, 562 insertions(+)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 6d8b9856eea..5bfea4cd7b6 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -2484,6 +2484,7 @@ GCC plugins may provide their own attributes.
 * Microsoft Windows Function Attributes::
 * MIPS Function Attributes::
 * MSP430 Function Attributes::
+* nanoMIPS Function Attributes::
 * NDS32 Function Attributes::
 * Nios II Function Attributes::
 * Nvidia PTX Function Attributes::
@@ -5673,6 +5674,99 @@ options can help the packing, however, since they 
produce smaller,
 easier to pack regions.
 @end table
 
+@node nanoMIPS Function Attributes
+@subsection nanoMIPS Function Attributes
+
+These function attributes are supported by the nanoMIPS back end:
+
+@table @code
+@item cmodel ("@var{model}")
+@cindex @code{cmodel} function attribute, nanoMIPS
+Use this attribute to indicate what code should be generated for a particular
+code and data model for this function.  The behavior and permissible arguments
+are the same as for the command line option @option{-mcmodel=}.
+@end table
+
+@table @code
+@item interrupt
+@cindex @code{interrupt} function attribute, nanoMIPS
+Use this attribute to indicate that the specified function is an interrupt
+handler.  The compiler generates function entry and exit sequences suitable
+for use in an interrupt handler when this attribute is present.
+An optional argument is supported for the interrupt attribute which allows
+the interrupt mode to be described.  By default GCC assumes the external
+interrupt controller (EIC) mode is in use, this can be explicitly set using
+@code{eic}.  When interrupts are non-masked then the requested Interrupt
+Priority Level (IPL) is copied to the current IPL which has the effect of only
+enabling higher priority interrupts.  To use vectored interrupt mode use
+the argument @code{vector=[sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5]}, this will change
+the behavior of the non-masked interrupt support and GCC will arrange to mask
+all interrupts from sw0 up to and including the specified interrupt vector.
+
+You can use the following attributes to modify the behavior
+of an interrupt handler:
+@table @code
+@item use_shadow_register_set
+@cindex @code{use_shadow_register_set} function attribute, nanoMIPS
+Assume that the handler uses a shadow register set, instead of
+the main general-purpose registers.  An optional argument @code{intstack} is
+supported to indicate that the shadow register set contains a valid stack
+pointer.
+
+@item keep_interrupts_masked
+@cindex @code{keep_interrupts_masked} function attribute, nanoMIPS
+Keep interrupts masked for the whole function.  Without this attribute,
+GCC tries to reenable interrupts for as much of the function as it can.
+
+@item use_debug_exception_return
+@cindex @code{use_debug_exception_return} function attribute, nanoMIPS
+Return using the @code{deret} instruction.  Interrupt handlers that don't
+have this attribute return using @code{eret} instead.
+@end table
+
+You can use any combination of these attributes, as shown below:
+@smallexample
+void __attribute__ ((interrupt)) v0 ();
+void __attribute__ ((interrupt, use_shadow_register_set)) v1 ();
+void __attribute__ ((interrupt, keep_interrupts_masked)) v2 ();
+void __attribute__ ((interrupt, use_debug_exception_return)) v3 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ keep_interrupts_masked)) v4 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ use_debug_exception_return)) v5 ();
+void __attribute__ ((interrupt, keep_interrupts_masked,
+ use_debug_exception_return)) v6 ();
+void __attribute__ ((interrupt, use_shadow_register_set,
+ keep_interrupts_masked,
+ use_debug_exception_return)) v7 ();
+void __attribute__ ((interrupt("eic"))) v8 ();
+void __attribute__ ((interrupt("vector=hw3"))) v9 ();
+@end smallexample
+
+@item long_call
+@itemx near
+@itemx far
+@cindex indirect calls, nanoMIPS
+@cindex @code{long_call} function attribute, nanoMIPS
+@cindex @code{near} function attribute, nanoMIPS
+@cindex @code{far} function attribute, nanoMIPS
+These attributes specify how a particular function is called on nanoMIPS@.
+The attributes override the @option{-mlong-calls} (@pxref{nanoMIPS Options})
+command-line switch.  The @code{long_call} and @code{far} attributes are
+synonyms, and cause the compiler to always call
+the function by first loading its address into a register, and then using

[RFC 5/7] Fix unhelpful messages for disabled options.

[Dragan Mladjenovic via Gcc-patches]

Firstly, the option handling was building suggestions without checking
if an option is disabled.  This could have caused other unhelpful
messages for other mistyped options.

Secondly, the key issue here appears to be the lack of CL_JOINED flag
for the false 'Condition' i.e. an option is disabled but other flags are
zeroed out too.  This caused find_opt() not to return the right index
to an option e.g. for -mabi= we would expect OPT_mabi_ rather than
OPT_SPECIAL_unknown, hence, the option did not appear to be correctly
marked as disabled.  The patch aims to retain the extra flag but to keep
an option as disabled.  I do not see any fallout with this, -m=
are now rejected on the command line and not printed with --target-help.

gcc/ChangeLog:

* opt-suggestions.c (option_proposer::build_option_suggestions):
Ignore disabled options.
* opts.c (print_filtered_help): Likewise.
* optc-gen.awk: Preserve flags in both cases.

gcc/testsuite/ChangeLog:

* gcc.target/nanomips/nanomips-err-mabi32.c: New test.
---
 gcc/opt-suggestions.c| 3 +++
 gcc/optc-gen.awk | 5 +++--
 gcc/opts.c   | 4 
 .../gcc.target/nanomips/nanomips-err-mabi32.c (new)  | 4 
 4 files changed, 14 insertions(+), 2 deletions(-)
 4 files changed, 14 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c

diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
index 5c36fc8cc8c..03bccd5379f 100644
--- a/gcc/opt-suggestions.c
+++ b/gcc/opt-suggestions.c
@@ -108,6 +108,9 @@ option_proposer::build_option_suggestions (const char 
*prefix)
   switch (i)
{
default:
+/* We don't want to suggest disabled options.  */
+if (option->cl_disabled)
+  continue;
  if (option->var_type == CLVC_ENUM)
{
  const struct cl_enum *e = _enums[option->var_enum];
diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
index 77e598efd60..eb725fdb8ce 100644
--- a/gcc/optc-gen.awk
+++ b/gcc/optc-gen.awk
@@ -412,10 +412,11 @@ for (i = 0; i < n_opts; i++) {
   "%s,\n" \
   "0, %s,\n" \
   "#else\n" \
-  "0,\n" \
+  "%s,\n" \
   "1 /* Disabled.  */, %s,\n" \
   "#endif\n",
-  condition, cl_flags, cl_bit_fields, cl_zero_bit_fields)
+  condition, cl_flags, cl_bit_fields,
+  cl_flags, cl_zero_bit_fields)
else
printf("%s,\n" \
   "0, %s,\n",
diff --git a/gcc/opts.c b/gcc/opts.c
index 1d2d22d7a3f..d85fc2adf8a 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1435,6 +1435,10 @@ print_filtered_help (unsigned int include_flags,
continue;
}
 
+  /* Skip disabled options.  */
+  if (option->cl_disabled)
+   continue;
+
   /* Skip unwanted switches.  */
   if ((option->flags & exclude_flags) != 0)
continue;
diff --git a/gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c 
b/gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c
new file mode 100644
index 000..1bf233a36e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/nanomips/nanomips-err-mabi32.c
@@ -0,0 +1,4 @@
+/* Verify that we get an error for unsupported -mabi=32 option.  */
+/* { dg-additional-options "-mabi=32" } */
+/* { dg-error "not supported by this configuration" "" { target *-*-* } 0 } */
+void foo (void) {}
-- 
2.17.1

[RFC 2/7] Make mips-classic.md entry point for mips*-*-* targets

[Dragan Mladjenovic via Gcc-patches]

Make parts of the code and options conditional on compile-time defines.

gcc/ChangeLog:

* config/mips/mips.h
(MIPS_SUPPORT_DSP, MIPS_SUPPORT_PS_3D,
MIPS_SUPPORT_MSA, MIPS_SUPPORT_LOONGSON
MIPS_SUPPORT_MICROMIPS, MIPS_SUPPORT_LEGACY
MIPS_SUPPORT_FRAME_HEADER_OPT): New defines.
* config/mips/mips.c (MIPS_BUILTIN_MOVF,
MIPS_BUILTIN_MOVT, mips_expand_vcondv2sf,
pll_ps, pul_ps, plu_ps, mips_expand_builtin_movtf,
mips_expand_builtin_compare):
Make conditional on MIPS_SUPPORT_PS_3D.
(MIPS_BUILTIN_BPOSGE32, mips_emit_compare,
dspalu_bypass_table, CODE_FOR_mips_sqrt_ps,
... CODE_FOR_mips_multu, addq_ph ...
dpsqx_sa_w_ph, mips_expand_builtin_bposge):
Make conditional on MIPS_SUPPORT_DSP.
(mips_split_move_p, mips_split_move,
CODE_FOR_msa_adds_s_b ... CODE_FOR_msa_ldi_d,
mips_builtin_vectorized_function,
mips_expand_builtin_insn,
mips_expand_msa_shuffle,
mips_msa_vec_parallel_const_half,
mips_expand_vector_init,
mips_expand_vec_reduc):
Make conditional on MIPS_SUPPORT_MSA.
(struct mips_ls2,
mips_ls2_init_dfa_post_cycle_insn,
mips_sched_init, mips_ls2_variable_issue,
mips_variable_issue,
CODE_FOR_loongson_packsswh ...
CODE_FOR_loongson_psubusb,
mips_expand_vpc_loongson_even_odd
mips_expand_vec_perm_const_1,
mips_expand_vi_broadcast,
mips_expand_vi_loongson_one_pinsrh,
mips_expand_vector_init,
TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN,
TARGET_SCHED_DFA_POST_ADVANCE_CYCLE):
Make conditional on MIPS_SUPPORT_LOONGSON.
(vr4130_reorder, mips_sched_init,
mips_sched_reorder_1, mips_variable_issue):
Make conditional on MIPS_SUPPORT_LEGACY.
(mips_expand_epilogue):
Make conditional on MIPS_SUPPORT_MICROMIPS.
(mips_compute_frame_info, mips_option_override):
Make conditional on MIPS_SUPPORT_FRAME_HEADER_OPT.
* config/mips/mips.md (processor):
(unspec): Move into ...
* config/mips/mips-classic.md: ... here.
* config.gcc [mips*-*-*]: Use mips-classic.md.
* config/mips/mips.opt: Conditionalize options.
---
 gcc/config.gcc|   1 +
 gcc/config/mips/mips-classic.md (new) | 142 
 gcc/config/mips/mips.c| 154 ++
 gcc/config/mips/mips.h|   8 ++
 gcc/config/mips/mips.md   | 117 ---
 gcc/config/mips/mips.opt  | 122 ++--
 6 files changed, 346 insertions(+), 198 deletions(-)
 6 files changed, 346 insertions(+), 198 deletions(-)
 create mode 100644 gcc/config/mips/mips-classic.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 498c51e619d..58e38f70aa6 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -448,6 +448,7 @@ microblaze*-*-*)
 ;;
 mips*-*-*)
cpu_type=mips
+   md_file=mips/mips-classic.md
d_target_objs="mips-d.o"
extra_headers="loongson.h loongson-mmiintrin.h msa.h"
extra_objs="frame-header-opt.o"
diff --git a/gcc/config/mips/mips-classic.md b/gcc/config/mips/mips-classic.md
new file mode 100644
index 000..0f7efc4d5d8
--- /dev/null
+++ b/gcc/config/mips/mips-classic.md
@@ -0,0 +1,142 @@
+;;  Mips.md Machine Description for MIPS based processors
+;;  Copyright (C) 1989-2021 Free Software Foundation, Inc.
+;;  Contributed by   A. Lichnewsky, l...@inria.inria.fr
+;;  Changes by   Michael Meissner, meiss...@osf.org
+;;  64-bit r4000 support by Ian Lance Taylor, i...@cygnus.com, and
+;;  Brendan Eich, bren...@microunity.com.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_enum "processor" [
+  r3000
+  4kc
+  4kp
+  5kc
+  5kf
+  20kc
+  24kc
+  24kf2_1
+  24kf1_1
+  74kc
+  74kf2_1
+  74kf1_1
+  74kf3_2
+  loongson_2e
+  loongson_2f
+  gs464
+  gs464e
+  gs264e
+  m4k
+  octeon
+  octeon2
+  octeon3
+  r3900
+  r6000
+  r4000
+  r4100
+  r4111
+  r4120
+  r4130
+  r4300
+  r4600
+  r4650
+  r4700
+  r5000
+  r5400
+  r5500
+  r5900
+  r7000
+  r8000
+  r9000
+  r1
+  sb1
+  sb1a
+  sr71000
+  xlr
+  xlp
+  p5600
+  m5100
+  i6400
+  p6600
+])
+
+(include "mips.md")
+
+(include "i6400.md")
+(include 

[RFC 1/7] Avoid references to register names in instruction output patterns.

[Dragan Mladjenovic via Gcc-patches]

This allows us to choose the different names if needed in the future.

gcc/ChangeLog:

* config/mips/mips.c (mips_print_operand_punctuation):
Handle '&' punctuation.
(mips_output_probe_stack_range): Use '%.' instead of $0.
* config/mips/mips.h (GLOBAL_POINTER_REGNUM): Move to ...
* config/mips/mips.md (GLOBAL_POINTER_REGNUM): ... here.
(trap, *conditional_trap_reg, *msac, *muls,
*muls_di, msubsidi4): Use '%.' instead of $0.
(clear_hazard_): Use '%&' instead of $31.
---
 gcc/config/mips/mips.c  |  9 +++--
 gcc/config/mips/mips.h  |  4 
 gcc/config/mips/mips.md | 17 +
 3 files changed, 16 insertions(+), 14 deletions(-)
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ce60c5500b7..ab63575eb26 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8816,6 +8816,7 @@ mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
'^' Print the name of the pic call-through register (t9 or $25).
'+' Print the name of the gp register (usually gp or $28).
'$' Print the name of the stack pointer register (sp or $29).
+   '&' Print the name of the return register (ra or $31).
':'  Print "c" to use the compact version if the delay slot is a nop.
'!'  Print "s" to use the short version if the delay slot contains a
16-bit instruction.
@@ -8902,6 +8903,10 @@ mips_print_operand_punctuation (FILE *file, int ch)
   fputs (reg_names[STACK_POINTER_REGNUM], file);
   break;
 
+case '&':
+  fputs (reg_names[RETURN_ADDR_REGNUM], file);
+  break;
+
 case ':':
   /* When final_sequence is 0, the delay slot will be a nop.  We can
 use the compact version where available.  The %: formatter will
@@ -12133,9 +12138,9 @@ mips_output_probe_stack_range (rtx reg1, rtx reg2)
   strcpy (tmp, "%(%"
@@ -1860,7 +1861,7 @@
   else if (TARGET_MIPS5500)
 return "msub\t%2,%3";
   else
-return "msac\t$0,%2,%3";
+return "msac\t%.,%2,%3";
 }
   [(set_attr "type" "imadd")
(set_attr "accum_in""1")
@@ -2060,7 +2061,7 @@
(clobber (match_scratch:SI 3 "=X,l"))]
   "ISA_HAS_MULS"
   "@
-   muls\t$0,%1,%2
+   muls\t%.,%1,%2
muls\t%0,%1,%2"
   [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
@@ -2243,7 +2244,7 @@
  (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
  (any_extend:DI (match_operand:SI 2 "register_operand" "d")]
   "!TARGET_64BIT && ISA_HAS_MULS"
-  "muls\t$0,%1,%2"
+  "muls\t%.,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
 
@@ -2268,7 +2269,7 @@
   else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
 return "msub\t%1,%2";
   else
-return "msac\t$0,%1,%2";
+return "msac\t%.,%1,%2";
 }
   [(set_attr "type" "imadd")
(set_attr "accum_in""3")
@@ -5622,8 +5623,8 @@
 {
   return "%(%addiu\t$31,$31,12\n"
- "\tjr.hb\t$31\n"
+ "1:\taddiu\t%&,%&,12\n"
+ "\tjr.hb\t%&\n"
  "\tnop%>%)";
 }

[RFC 0/7] nanoMIPS port

[Dragan Mladjenovic via Gcc-patches]

Hi all,


This is somewhat a continuation of the previous effort [1] to bring nanoMIPS 
support upstream.
We would like to move our toolchain releases [2] to something more closer to 
the upstream GCC.
As part of that, we are interested in feedback from the community if the 
current approach of
code sharing between nanoMIPS and MIPS backend is viable for future upstream 
inclusion?

The RFC presented here contains enough to produce the nanomips-elf toolchain 
when paired
with [3], [4], [5]. It targets a little-endian bare metal environment using p32 
ABI with soft-float.
Any feedback on it will be appreciated.

Best regards,

Dragan


References:

[1] https://gcc.gnu.org/legacy-ml/gcc/2018-05/msg00012.html
[2] 
https://github.com/MediaTek-Labs/nanomips-gnu-toolchain/releases/tag/nanoMIPS-2021.07-01
[3] https://github.com/MediaTek-Labs/newlib/tree/mtk/newlib250
[4] https://github.com/MediaTek-Labs/binutils-gdb/tree/mtk/binutils_v9
[5] https://github.com/MediaTek-Labs/binutils-gdb/tree/mtk/gold_v7


  (Robert Suchanek)
  (Toma Tabacu)
  (Matthew Fortune)
  (Zoran Jovanovic)
  (Prachi Godbole)
  (Faraz Shahbazker)
  (Steve Ellcey)
  (Jack Romo)
  (Stefan Markovic)
  (Sara Popadic)
  (Mihailo Stojanovic)
  (Dragan Mladjenovic)
  Avoid references to register names in instruction output patterns
  Make mips-classic.md entry point for mips*-*-* targets
  Add nanoMIPS support
  Add test cases for nanoMIPS
  Fix unhelpful messages for disabled options
  Enable MIPS DSP rev3 ASE for nanoMIPS
  Add documentation for nanoMIPS


 config.sub|3 +-
 config/mt-nanomips (new)  |6 +
 configure |9 +-
 configure.ac  |9 +-
 contrib/test_installed|3 +-
 gcc/config.gcc|   65 +
 gcc/config/mips/constraints.md|   57 +-
 gcc/config/mips/genopt-nanomips.sh (new +x)   |   74 +
 gcc/config/mips/i7200.md (new)|  142 +
 gcc/config/mips/micromips.md  |   12 +-
 gcc/config/mips/mips-classic.md (new) |  142 +
 gcc/config/mips/mips-dsp.md   |   17 +-
 gcc/config/mips/mips-ftypes.def   |1 +
 gcc/config/mips/mips-opts.h   |8 +
 gcc/config/mips/mips-protos.h |   81 +-
 gcc/config/mips/mips.c| 3697 +++--
 gcc/config/mips/mips.h|  456 +-
 gcc/config/mips/mips.md   | 1043 +++--
 gcc/config/mips/mips.opt  |  126 +-
 gcc/config/mips/nanomips-cpus.def (new)   |   41 +
 gcc/config/mips/nanomips-tables.opt (new) |   40 +
 gcc/config/mips/nanomips.h (new)  |  349 ++
 gcc/config/mips/nanomips.md (new) |  285 ++
 gcc/config/mips/nanomips.opt (new)|   60 +
 gcc/config/mips/predicates.md |  246 +-
 gcc/config/mips/t-nanomips (new)  |   23 +
 gcc/config/mips/t-nanomips-elf (new)  |   36 +
 gcc/configure |8 +
 gcc/configure.ac  |6 +
 gcc/doc/extend.texi   |  124 +
 gcc/doc/invoke.texi   |  367 ++
 gcc/doc/md.texi   |   71 +
 gcc/opt-suggestions.c |3 +
 gcc/optc-gen.awk  |5 +-
 gcc/opts.c|4 +
 .../gcc.target/nanomips/addiu48-1.c (new) |   12 +
 .../gcc.target/nanomips/addiu48-2.c (new) |   12 +
 .../gcc.target/nanomips/beqic-1.c (new)   |   13 +
 .../gcc.target/nanomips/bgeiuc-1.c (new)  |   31 +
 .../gcc.target/nanomips/bltc-1.c (new)|   28 +
 .../gcc.target/nanomips/bltic-1.c (new)   |   11 +
 .../gcc.target/nanomips/bltiuc-1.c (new)  |   19 +
 .../gcc.target/nanomips/bnec-1.c (new)|   11 +
 .../gcc.target/nanomips/bneic-1.c (new)   |   11 +
 .../gcc.target/nanomips/bnezc-1.c (new)   |   18 +
 .../gcc.target/nanomips/branch-2.c (new)  |   13 +
 .../gcc.target/nanomips/branch-3.c (new)  |   12 +
 .../gcc.target/nanomips/branch-4.c (new)  |   12 +
 .../gcc.target/nanomips/branch-5.c (new)  |   11 +
 .../gcc.target/nanomips/branch-helper.h (new) |  107 +
 .../gcc.target/nanomips/bswap-1.c (new)   |   10 +
 .../gcc.target/nanomips/bswap-2.c (new)   |9 +
 .../gcc.target/nanomips/bswap-3.c (new)   |   13 +
 .../gcc.target/nanomips/bswap-4.c (new)   |9 +
 .../gcc.target/nanomips/cache-1.c (new)   |   31 +
 .../gcc.target/nanomips/call-saved-1.c (new)  |   14 +
 .../gcc.target/nanomips/clear-cache-1.c (new) |   13 +
 .../gcc.target/nanomips/constraint-m.c (new)  |9 +
 .../gcc.target/nanomips/dpaq_sa_l_w.c (new)   |   51 +
 .../gcc.target/nanomips/dpsq_sa_l_w.c (new)   |   37 +
 .../gcc.target/nanomips/dsp-ctrl.c (new)  |   69

RE: [PATCH] [MIPS] Hazard barrier return support

[Dragan Mladjenovic via Gcc-patches]

> -Original Message-
> From: Dragan Mladjenovic
> Sent: 17 August 2021 17:59
> To: 'Andrew Pinski' 
> Cc: 'gcc-patches@gcc.gnu.org' 
> Subject: RE: [PATCH] [MIPS] Hazard barrier return support
> 
> 
> 
> > -Original Message-
> > From: Dragan Mladjenovic
> > Sent: 16 August 2021 22:40
> > To: 'Andrew Pinski' 
> > Cc: gcc-patches@gcc.gnu.org
> > Subject: RE: [PATCH] [MIPS] Hazard barrier return support
> >
> >
> >
> > > -Original Message-
> > > From: Andrew Pinski [mailto:pins...@gmail.com]
> > > Sent: 16 August 2021 21:17
> > > To: Dragan Mladjenovic 
> > > Cc: gcc-patches@gcc.gnu.org
> > > Subject: Re: [PATCH] [MIPS] Hazard barrier return support
> > >
> > > On Mon, Aug 16, 2021 at 7:43 AM Dragan Mladjenovic via Gcc-patches
> > >  wrote:
> > > >
> > > > This patch allows a function to request clearing of all
> > > > instruction and execution hazards upon normal return via
> > > > __attribute__
> > > ((use_hazard_barrier_return)).
> > > >
> > > > 2017-04-25  Prachi Godbole  
> > > >
> > > > gcc/
> > > > * config/mips/mips.h (machine_function): New variable
> > > > use_hazard_barrier_return_p.
> > > > * config/mips/mips.md (UNSPEC_JRHB): New unspec.
> > > > (mips_hb_return_internal): New insn pattern.
> > > > * config/mips/mips.c (mips_attribute_table): Add attribute
> > > > use_hazard_barrier_return.
> > > > (mips_use_hazard_barrier_return_p): New static function.
> > > > (mips_function_attr_inlinable_p): Likewise.
> > > > (mips_compute_frame_info): Set use_hazard_barrier_return_p.
> > > > Emit error for unsupported architecture choice.
> > > > (mips_function_ok_for_sibcall, mips_can_use_return_insn):
> > > > Return false for use_hazard_barrier_return.
> > > > (mips_expand_epilogue): Emit hazard barrier return.
> > > > * doc/extend.texi: Document use_hazard_barrier_return.
> > > >
> > > > gcc/testsuite/
> > > > * gcc.target/mips/hazard-barrier-return-attribute.c: New test.
> > > > ---
> > > > Rehash of original patch posted by Prachi with minimal changes.
> > > > Tested against mips-mti-elf with mips32r2/-EB and mips32r2/-EB/-
> > micromips.
> > > >
> > > >  gcc/config/mips/mips.c| 58 +--
> > > >  gcc/config/mips/mips.h|  3 +
> > > >  gcc/config/mips/mips.md   | 15 +
> > > >  gcc/doc/extend.texi   |  6 ++
> > > >  .../mips/hazard-barrier-return-attribute.c| 20 +++
> > > >  5 files changed, 98 insertions(+), 4 deletions(-)  create mode
> > > > 100644
> > > > gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c
> > > >
> > > > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
> > > > 89d1be6cea6..6ce12fce52e 100644
> > > > --- a/gcc/config/mips/mips.c
> > > > +++ b/gcc/config/mips/mips.c
> > > > @@ -630,6 +630,7 @@ static const struct attribute_spec
> > > mips_attribute_table[] = {
> > > >  mips_handle_use_shadow_register_set_attr, NULL },
> > > >{ "keep_interrupts_masked",  0, 0, false, true,  true, false, NULL,
> NULL },
> > > >{ "use_debug_exception_return", 0, 0, false, true, true, false,
> > > > NULL, NULL },
> > > > +  { "use_hazard_barrier_return", 0, 0, true, false, false, false,
> > > > + NULL, NULL },
> > > >{ NULL, 0, 0, false, false, false, false, NULL, NULL }
> > > >  };
> > > >
> > > > @@ -1309,6 +1310,16 @@ mips_use_debug_exception_return_p (tree
> > > type)
> > > >TYPE_ATTRIBUTES (type)) != NULL;  }
> > > >
> > > > +/* Check if the attribute to use hazard barrier return is set for
> > > > +   the function declaration DECL.  */
> > > > +
> > > > +static bool
> > > > +mips_use_hazard_barrier_return_p (const_tree decl) {
> > > > +  return lookup_attribute ("use_hazard_barrier_return",
> > > > +  DECL_ATTRIBUTES (decl)) != NULL; }
> > > > +
> > > >

[COMMITTED] MAINTAINERS: Add myself for write after approval

[Dragan Mladjenovic via Gcc-patches]

2021-08-21  Dragan Mladjenovic  

ChangeLog:

* MAINTAINERS: Add myself for write after approval.
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7b03fc25f4d..b8d5f16f85f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -531,6 +531,7 @@ Bingfeng Mei

 Jim Meyering   
 Martin Michlmayr   
 Lee Millward   
+Dragan Mladjenovic 
 Alan Modra 
 Catherine Moore
 James A. Morrison  
-- 
2.17.1

RE: [PATCH][MIPS] Remove TARGET_ASM_FUNCTION_RODATA_SECTION

[Dragan Mladjenovic via Gcc-patches]

From: Jeff Law [mailto:jeffreya...@gmail.com] 
Sent: 19 August 2021 18:03
To: Dragan Mladjenovic ; 
gcc-patches@gcc.gnu.org
Cc: Andrew Pinski 
Subject: Re: [PATCH][MIPS] Remove TARGET_ASM_FUNCTION_RODATA_SECTION


> On 8/19/2021 6:11 AM, Dragan Mladjenovic wrote:
> > Since 'Remove obsolete IRIX 6.5 support' [1] we only use
> > gp-relative jump-tables for PIC code. We can fall back to
> > default behaviour for asm_function_rodata_section.
> >
> > [1] https://gcc.gnu.org/ml/libstdc++/2012-03/msg00067.html
> >
> > 2018-06-04 Dragan Mladjenovic 
> > gcc/
> >
> > * config/mips/mips.c (mips_function_rodata_section,
> > TARGET_ASM_FUNCTION_RODATA_SECTION): Removed.
> OK
> jeff

Thanks,

Committed as 304ec0d1d9f177e059e695fbe11d93f99f6f14e0.

Dragan

[PATCH][MIPS] Remove TARGET_ASM_FUNCTION_RODATA_SECTION

[Dragan Mladjenovic via Gcc-patches]

Since 'Remove obsolete IRIX 6.5 support' [1] we only use
gp-relative jump-tables for PIC code. We can fall back to
default behaviour for asm_function_rodata_section.

[1] https://gcc.gnu.org/ml/libstdc++/2012-03/msg00067.html

2018-06-04 Dragan Mladjenovic 
gcc/

* config/mips/mips.c (mips_function_rodata_section,
TARGET_ASM_FUNCTION_RODATA_SECTION): Removed.
---
Tested against mips64-linux-gnu with -mabi=64|32|n32 and
mips-mti-elf with mips32r2.

 gcc/config/mips/mips.c | 38 --
 1 file changed, 38 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 89d1be6cea6..39666d6973f 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9306,42 +9306,6 @@ mips_select_rtx_section (machine_mode mode, rtx x,
   return default_elf_select_rtx_section (mode, x, align);
 }
 
-/* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
-
-   The complication here is that, with the combination TARGET_ABICALLS
-   && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
-   absolute addresses, and should therefore not be included in the
-   read-only part of a DSO.  Handle such cases by selecting a normal
-   data section instead of a read-only one.  The logic apes that in
-   default_function_rodata_section.  */
-
-static section *
-mips_function_rodata_section (tree decl, bool)
-{
-  if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
-return default_function_rodata_section (decl, false);
-
-  if (decl && DECL_SECTION_NAME (decl))
-{
-  const char *name = DECL_SECTION_NAME (decl);
-  if (DECL_COMDAT_GROUP (decl) && startswith (name, ".gnu.linkonce.t."))
-   {
- char *rname = ASTRDUP (name);
- rname[14] = 'd';
- return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
-   }
-  else if (flag_function_sections
-  && flag_data_sections
-  && startswith (name, ".text."))
-   {
- char *rname = ASTRDUP (name);
- memcpy (rname + 1, "data", 4);
- return get_section (rname, SECTION_WRITE, decl);
-   }
-}
-  return data_section;
-}
-
 /* Implement TARGET_IN_SMALL_DATA_P.  */
 
 static bool
@@ -22606,8 +22570,6 @@ mips_asm_file_end (void)
 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
 #undef TARGET_ASM_SELECT_RTX_SECTION
 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
-#undef TARGET_ASM_FUNCTION_RODATA_SECTION
-#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
 
 #undef TARGET_SCHED_INIT
 #define TARGET_SCHED_INIT mips_sched_init
-- 
2.17.1

RE: [PATCH] [MIPS] Hazard barrier return support

[Dragan Mladjenovic via Gcc-patches]

> -Original Message-
> From: Dragan Mladjenovic
> Sent: 16 August 2021 22:40
> To: 'Andrew Pinski' 
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] [MIPS] Hazard barrier return support
> 
> 
> 
> > -Original Message-
> > From: Andrew Pinski [mailto:pins...@gmail.com]
> > Sent: 16 August 2021 21:17
> > To: Dragan Mladjenovic 
> > Cc: gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH] [MIPS] Hazard barrier return support
> >
> > On Mon, Aug 16, 2021 at 7:43 AM Dragan Mladjenovic via Gcc-patches
> >  wrote:
> > >
> > > This patch allows a function to request clearing of all instruction
> > > and execution hazards upon normal return via __attribute__
> > ((use_hazard_barrier_return)).
> > >
> > > 2017-04-25  Prachi Godbole  
> > >
> > > gcc/
> > > * config/mips/mips.h (machine_function): New variable
> > > use_hazard_barrier_return_p.
> > > * config/mips/mips.md (UNSPEC_JRHB): New unspec.
> > > (mips_hb_return_internal): New insn pattern.
> > > * config/mips/mips.c (mips_attribute_table): Add attribute
> > > use_hazard_barrier_return.
> > > (mips_use_hazard_barrier_return_p): New static function.
> > > (mips_function_attr_inlinable_p): Likewise.
> > > (mips_compute_frame_info): Set use_hazard_barrier_return_p.
> > > Emit error for unsupported architecture choice.
> > > (mips_function_ok_for_sibcall, mips_can_use_return_insn):
> > > Return false for use_hazard_barrier_return.
> > > (mips_expand_epilogue): Emit hazard barrier return.
> > > * doc/extend.texi: Document use_hazard_barrier_return.
> > >
> > > gcc/testsuite/
> > > * gcc.target/mips/hazard-barrier-return-attribute.c: New test.
> > > ---
> > > Rehash of original patch posted by Prachi with minimal changes.
> > > Tested against mips-mti-elf with mips32r2/-EB and mips32r2/-EB/-
> micromips.
> > >
> > >  gcc/config/mips/mips.c| 58 +--
> > >  gcc/config/mips/mips.h|  3 +
> > >  gcc/config/mips/mips.md   | 15 +
> > >  gcc/doc/extend.texi   |  6 ++
> > >  .../mips/hazard-barrier-return-attribute.c| 20 +++
> > >  5 files changed, 98 insertions(+), 4 deletions(-)  create mode
> > > 100644
> > > gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c
> > >
> > > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
> > > 89d1be6cea6..6ce12fce52e 100644
> > > --- a/gcc/config/mips/mips.c
> > > +++ b/gcc/config/mips/mips.c
> > > @@ -630,6 +630,7 @@ static const struct attribute_spec
> > mips_attribute_table[] = {
> > >  mips_handle_use_shadow_register_set_attr, NULL },
> > >{ "keep_interrupts_masked",  0, 0, false, true,  true, false, NULL, 
> > > NULL },
> > >{ "use_debug_exception_return", 0, 0, false, true, true, false,
> > > NULL, NULL },
> > > +  { "use_hazard_barrier_return", 0, 0, true, false, false, false,
> > > + NULL, NULL },
> > >{ NULL, 0, 0, false, false, false, false, NULL, NULL }
> > >  };
> > >
> > > @@ -1309,6 +1310,16 @@ mips_use_debug_exception_return_p (tree
> > type)
> > >TYPE_ATTRIBUTES (type)) != NULL;  }
> > >
> > > +/* Check if the attribute to use hazard barrier return is set for
> > > +   the function declaration DECL.  */
> > > +
> > > +static bool
> > > +mips_use_hazard_barrier_return_p (const_tree decl) {
> > > +  return lookup_attribute ("use_hazard_barrier_return",
> > > +  DECL_ATTRIBUTES (decl)) != NULL; }
> > > +
> > >  /* Return the set of compression modes that are explicitly required
> > > by the attributes in ATTRIBUTES.  */
> > >
> > > @@ -1494,6 +1505,19 @@ mips_can_inline_p (tree caller, tree callee)
> > >return default_target_can_inline_p (caller, callee);  }
> > >
> > > +/* Implement TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P.
> > > +
> > > +   A function requesting clearing of all instruction and execution 
> > > hazards
> > > +   before returning cannot be inlined - thereby not clearing any hazards.
> > > +   All our other function attributes are relate

RE: [PATCH] [MIPS] Hazard barrier return support

[Dragan Mladjenovic via Gcc-patches]

> -Original Message-
> From: Andrew Pinski [mailto:pins...@gmail.com]
> Sent: 16 August 2021 21:17
> To: Dragan Mladjenovic 
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [MIPS] Hazard barrier return support
> 
> On Mon, Aug 16, 2021 at 7:43 AM Dragan Mladjenovic via Gcc-patches  patc...@gcc.gnu.org> wrote:
> >
> > This patch allows a function to request clearing of all instruction
> > and execution hazards upon normal return via __attribute__
> ((use_hazard_barrier_return)).
> >
> > 2017-04-25  Prachi Godbole  
> >
> > gcc/
> > * config/mips/mips.h (machine_function): New variable
> > use_hazard_barrier_return_p.
> > * config/mips/mips.md (UNSPEC_JRHB): New unspec.
> > (mips_hb_return_internal): New insn pattern.
> > * config/mips/mips.c (mips_attribute_table): Add attribute
> > use_hazard_barrier_return.
> > (mips_use_hazard_barrier_return_p): New static function.
> > (mips_function_attr_inlinable_p): Likewise.
> > (mips_compute_frame_info): Set use_hazard_barrier_return_p.
> > Emit error for unsupported architecture choice.
> > (mips_function_ok_for_sibcall, mips_can_use_return_insn):
> > Return false for use_hazard_barrier_return.
> > (mips_expand_epilogue): Emit hazard barrier return.
> > * doc/extend.texi: Document use_hazard_barrier_return.
> >
> > gcc/testsuite/
> > * gcc.target/mips/hazard-barrier-return-attribute.c: New test.
> > ---
> > Rehash of original patch posted by Prachi with minimal changes. Tested
> > against mips-mti-elf with mips32r2/-EB and mips32r2/-EB/-micromips.
> >
> >  gcc/config/mips/mips.c| 58 +--
> >  gcc/config/mips/mips.h|  3 +
> >  gcc/config/mips/mips.md   | 15 +
> >  gcc/doc/extend.texi   |  6 ++
> >  .../mips/hazard-barrier-return-attribute.c| 20 +++
> >  5 files changed, 98 insertions(+), 4 deletions(-)  create mode 100644
> > gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c
> >
> > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index
> > 89d1be6cea6..6ce12fce52e 100644
> > --- a/gcc/config/mips/mips.c
> > +++ b/gcc/config/mips/mips.c
> > @@ -630,6 +630,7 @@ static const struct attribute_spec
> mips_attribute_table[] = {
> >  mips_handle_use_shadow_register_set_attr, NULL },
> >{ "keep_interrupts_masked",  0, 0, false, true,  true, false, NULL, NULL 
> > },
> >{ "use_debug_exception_return", 0, 0, false, true, true, false,
> > NULL, NULL },
> > +  { "use_hazard_barrier_return", 0, 0, true, false, false, false,
> > + NULL, NULL },
> >{ NULL, 0, 0, false, false, false, false, NULL, NULL }
> >  };
> >
> > @@ -1309,6 +1310,16 @@ mips_use_debug_exception_return_p (tree
> type)
> >TYPE_ATTRIBUTES (type)) != NULL;  }
> >
> > +/* Check if the attribute to use hazard barrier return is set for
> > +   the function declaration DECL.  */
> > +
> > +static bool
> > +mips_use_hazard_barrier_return_p (const_tree decl) {
> > +  return lookup_attribute ("use_hazard_barrier_return",
> > +  DECL_ATTRIBUTES (decl)) != NULL; }
> > +
> >  /* Return the set of compression modes that are explicitly required
> > by the attributes in ATTRIBUTES.  */
> >
> > @@ -1494,6 +1505,19 @@ mips_can_inline_p (tree caller, tree callee)
> >return default_target_can_inline_p (caller, callee);  }
> >
> > +/* Implement TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P.
> > +
> > +   A function requesting clearing of all instruction and execution hazards
> > +   before returning cannot be inlined - thereby not clearing any hazards.
> > +   All our other function attributes are related to how out-of-line copies
> > +   should be compiled or called.  They don't in themselves prevent
> > + inlining.  */
> > +
> > +static bool
> > +mips_function_attr_inlinable_p (const_tree decl) {
> > +  return !mips_use_hazard_barrier_return_p (decl); }
> > +
> >  /* Handle an "interrupt" attribute with an optional argument.  */
> >
> >  static tree
> > @@ -7921,6 +7945,11 @@ mips_function_ok_for_sibcall (tree decl, tree
> exp ATTRIBUTE_UNUSED)
> >&& !targetm.binds_local_p (decl))
> >  return false;
> >
> > +  /* Can't generate sibling calls if returni

[PATCH] [MIPS] Hazard barrier return support

[Dragan Mladjenovic via Gcc-patches]

This patch allows a function to request clearing of all instruction and 
execution
hazards upon normal return via __attribute__ ((use_hazard_barrier_return)).

2017-04-25  Prachi Godbole  

gcc/
* config/mips/mips.h (machine_function): New variable
use_hazard_barrier_return_p.
* config/mips/mips.md (UNSPEC_JRHB): New unspec.
(mips_hb_return_internal): New insn pattern.
* config/mips/mips.c (mips_attribute_table): Add attribute
use_hazard_barrier_return.
(mips_use_hazard_barrier_return_p): New static function.
(mips_function_attr_inlinable_p): Likewise.
(mips_compute_frame_info): Set use_hazard_barrier_return_p.
Emit error for unsupported architecture choice.
(mips_function_ok_for_sibcall, mips_can_use_return_insn):
Return false for use_hazard_barrier_return.
(mips_expand_epilogue): Emit hazard barrier return.
* doc/extend.texi: Document use_hazard_barrier_return.

gcc/testsuite/
* gcc.target/mips/hazard-barrier-return-attribute.c: New test.
---
Rehash of original patch posted by Prachi with minimal changes. Tested against
mips-mti-elf with mips32r2/-EB and mips32r2/-EB/-micromips.

 gcc/config/mips/mips.c| 58 +--
 gcc/config/mips/mips.h|  3 +
 gcc/config/mips/mips.md   | 15 +
 gcc/doc/extend.texi   |  6 ++
 .../mips/hazard-barrier-return-attribute.c| 20 +++
 5 files changed, 98 insertions(+), 4 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 89d1be6cea6..6ce12fce52e 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -630,6 +630,7 @@ static const struct attribute_spec mips_attribute_table[] = 
{
 mips_handle_use_shadow_register_set_attr, NULL },
   { "keep_interrupts_masked",  0, 0, false, true,  true, false, NULL, NULL },
   { "use_debug_exception_return", 0, 0, false, true, true, false, NULL, NULL },
+  { "use_hazard_barrier_return", 0, 0, true, false, false, false, NULL, NULL },
   { NULL, 0, 0, false, false, false, false, NULL, NULL }
 };
 
@@ -1309,6 +1310,16 @@ mips_use_debug_exception_return_p (tree type)
   TYPE_ATTRIBUTES (type)) != NULL;
 }
 
+/* Check if the attribute to use hazard barrier return is set for
+   the function declaration DECL.  */
+
+static bool
+mips_use_hazard_barrier_return_p (const_tree decl)
+{
+  return lookup_attribute ("use_hazard_barrier_return",
+  DECL_ATTRIBUTES (decl)) != NULL;
+}
+
 /* Return the set of compression modes that are explicitly required
by the attributes in ATTRIBUTES.  */
 
@@ -1494,6 +1505,19 @@ mips_can_inline_p (tree caller, tree callee)
   return default_target_can_inline_p (caller, callee);
 }
 
+/* Implement TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P.
+
+   A function requesting clearing of all instruction and execution hazards
+   before returning cannot be inlined - thereby not clearing any hazards.
+   All our other function attributes are related to how out-of-line copies
+   should be compiled or called.  They don't in themselves prevent inlining.  
*/
+
+static bool
+mips_function_attr_inlinable_p (const_tree decl)
+{
+  return !mips_use_hazard_barrier_return_p (decl);
+}
+
 /* Handle an "interrupt" attribute with an optional argument.  */
 
 static tree
@@ -7921,6 +7945,11 @@ mips_function_ok_for_sibcall (tree decl, tree exp 
ATTRIBUTE_UNUSED)
   && !targetm.binds_local_p (decl))
 return false;
 
+  /* Can't generate sibling calls if returning from current function using
+ hazard barrier return.  */
+  if (mips_use_hazard_barrier_return_p (current_function_decl))
+return false;
+
   /* Otherwise OK.  */
   return true;
 }
@@ -11008,6 +11037,17 @@ mips_compute_frame_info (void)
}
 }
 
+  /* Determine whether to use hazard barrier return or not.  */
+  if (mips_use_hazard_barrier_return_p (current_function_decl))
+{
+  if (mips_isa_rev < 2)
+   error ("hazard barrier returns require a MIPS32r2 processor or 
greater");
+  else if (TARGET_MIPS16)
+   error ("hazard barrier returns are not supported for MIPS16 functions");
+  else
+   cfun->machine->use_hazard_barrier_return_p = true;
+}
+
   frame = >machine->frame;
   memset (frame, 0, sizeof (*frame));
   size = get_frame_size ();
@@ -12671,7 +12711,8 @@ mips_expand_epilogue (bool sibcall_p)
   && !crtl->calls_eh_return
   && !sibcall_p
   && step2 > 0
-  && mips_unsigned_immediate_p (step2, 5, 2))
+  && mips_unsigned_immediate_p (step2, 5, 2)
+  && !cfun->machine->use_hazard_barrier_return_p)
use_jraddiusp_p = true;
   else
/* Deallocate the final bit of the frame.  */
@@ -12712,6 +12753,11 @@ mips_expand_epilogue 

Re: [PATCH V2][wwwdocs] Document GNU-stack support added to GCC 10 for MIPS

[Dragan Mladjenovic]

On 3/30/2020 17:39, Jeff Law wrote:


On Sun, 2020-03-29 at 22:33 +0200, Dragan Mladjenovic wrote:

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index b5cbcebf..1e1eaf43 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -692,7 +692,17 @@ a work-in-progress.
  
  
  
-

+ MIPS
+ 
+The mips*-*-linux* targets now mark object files with
+  appropriate GNU-stack note, facilitating use of non-executable stack
+  hardening on GNU/Linux.
+  The soft-float targets have this feature enabled by default, while
+  for hard-float targets it is required for GCC to be configured with
+  --with-glibc-version=2.31
+  against glibc 2.31 or later.
+   
+ 

OK
jeff


Thanks. I forgot to mention. I would need someone to commit this for me.

I won't be able to access to my sourceware account for some time.

Thanks in advance.

[PATCH V2][wwwdocs] Document GNU-stack support added to GCC 10 for MIPS

[Dragan Mladjenovic]

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index b5cbcebf..1e1eaf43 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -692,7 +692,17 @@ a work-in-progress.
 
 
 
-
+ MIPS
+ 
+The mips*-*-linux* targets now mark object files with
+  appropriate GNU-stack note, facilitating use of non-executable stack
+  hardening on GNU/Linux.
+  The soft-float targets have this feature enabled by default, while
+  for hard-float targets it is required for GCC to be configured with
+  --with-glibc-version=2.31
+  against glibc 2.31 or later.
+   
+ 
 
 
 
-- 
2.17.1

Re: [PATCH][wwwdocs] Document GNU-stack support added to GCC 10 for MIPS

[Dragan Mladjenovic]

On 22.02.2020. 13:25, Gerald Pfeifer wrote:

On Fri, 24 Jan 2020, Dragan Mladjenovic wrote:

From: "Dragan Mladjenovic" 

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index ef27c9b..7736990 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -623,7 +623,14 @@ a work-in-progress.

  

-
+MIPS
+
+  The mips*-*-linux* targets now mark object files with 
appropriate GNU-stack note,
+facilitating use of non-executable stack hardening on GNU/Linux.
+The soft-float targets have this feature enabled by default, while
+for hard-float targets it requires use of glibc 2.31 or later.
+  
+


Thanksfor preparing this!  I did not see any response, but now
noticed the designated MIPS maintainer Matthew Fortune (per
gcc/MAINTAINERS) was not on copy.


Thanks for the replay. Sorry for the late response.



The first line is a bit long; can you please wrap?


Will do.



The note on hard-float targets does not seem completely clear to me:
I understand it requires glibc 2.31, but per the language it still
may not enabled by default even if in that case?  What is the
situation on the default in the hard-float case?


It retains the original behavior of not using GNU-stack notes at all.
You have to use --with-glibc-version=2.31 in all stages of gcc build
to enable GNU-stack note usage.



If believe you do not have commit access, but if you share an updated
patch I can apply for you.

Geral

Re: [PATCH 2/2][MIPS][RFC] Emit .note.GNU-stack for hard-float linux targets.

[Dragan Mladjenovic]

On 29.01.2020. 22:57, Dragan Mladjenovic wrote:


On 29.01.2020. 12:06, Tobias Burnus wrote:

Hi Dragan,

I think your committed patch was incomplete – at least I see the
following bits when running --enable-maintainer-mode (see attachment,
line numbers wrong as I edited my changes out).

Can you re-check?

(The other change in gcc/configure seems to be due to Andrew Burgess's
e7c26e04b2dd6266d62d5a5825ff7eb44d1cf14e )

Tobias

PS: The following was committed as
54b3d52c3cca836c7c4c08cc9c02eda6c096372a

On 1/23/20 11:58 AM, Dragan Mladjenovic wrote: […]

2019-08-05  Dragan Mladjenovic  

  * config.in: Regenerated.
  * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define
to 1
  for TARGET_LIBC_GNUSTACK.
  * configure: Regenerated.
  * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc
version is
  found 2.31 or greater.


Thank you for letting me know.

Your change looks fine. How should I handle this? Do I just commit the
portion related to my change or perhaps you wish to commit everything
altogether?


Ok, I now see that that e7c26e04b2dd6266d62d5a5825ff7eb44d1cf14e 
mentions that files will be regenerated later. So I went ahead and

committed this as e0332517f900c7947f03c15fd27e7f71ace98629.

Best regards,
Dragan

[committed, obvious] Regenerate configure for 54b3d52

[Dragan Mladjenovic]

From: Dragan Mladjenovic 

Commit 54b3d52 ("Emit .note.GNU-stack for hard-float linux targets.")
was missing generated files.  Add them now.

gcc/ChangeLog:

2020-01-30  Dragan Mladjenovic  

* config.in: Regenerated.
* configure: Regenerated.
---
 gcc/ChangeLog |  5 +
 gcc/config.in |  6 ++
 gcc/configure | 21 +++--
 3 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c9fbdac..a36e732 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-30  Dragan Mladjenovic  
+
+   * config.in: Regenerated.
+   * configure: Regenerated.
+
 2020-01-29  Tobias Burnus  
 
PR bootstrap/93409
diff --git a/gcc/config.in b/gcc/config.in
index ec5c46a..1110492 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -2185,6 +2185,12 @@
 #endif
 
 
+/* Define if your target C Library properly handles PT_GNU_STACK */
+#ifndef USED_FOR_TARGET
+#undef TARGET_LIBC_GNUSTACK
+#endif
+
+
 /* Define if your target C Library provides the AT_HWCAP value in the TCB */
 #ifndef USED_FOR_TARGET
 #undef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
diff --git a/gcc/configure b/gcc/configure
index 490fe6a..e2c8fc7 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -18957,7 +18957,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 18960 "configure"
+#line 18977 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -19063,7 +19063,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 19066 "configure"
+#line 19083 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -29800,6 +29800,23 @@ $as_echo "#define TARGET_LIBC_PROVIDES_HWCAP_IN_TCB 1" 
>>confdefs.h
 
 fi
 
+# Check if the target LIBC handles PT_GNU_STACK.
+gcc_cv_libc_gnustack=unknown
+case "$target" in
+  mips*-*-linux*)
+
+if test $glibc_version_major -gt 2 \
+  || ( test $glibc_version_major -eq 2 && test $glibc_version_minor -ge 31 ); 
then :
+  gcc_cv_libc_gnustack=yes
+fi
+;;
+esac
+if test x$gcc_cv_libc_gnustack = xyes; then
+
+$as_echo "#define TARGET_LIBC_GNUSTACK 1" >>confdefs.h
+
+fi
+
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking dl_iterate_phdr in target C 
library" >&5
 $as_echo_n "checking dl_iterate_phdr in target C library... " >&6; }
 gcc_cv_target_dl_iterate_phdr=unknown
-- 
1.9.1

Re: [EXTERNAL]Re: [PATCH 2/2][MIPS][RFC] Emit .note.GNU-stack for hard-float linux targets.

[Dragan Mladjenovic]

On 29.01.2020. 12:06, Tobias Burnus wrote:
> Hi Dragan,
>
> I think your committed patch was incomplete – at least I see the
> following bits when running --enable-maintainer-mode (see attachment,
> line numbers wrong as I edited my changes out).
>
> Can you re-check?
>
> (The other change in gcc/configure seems to be due to Andrew Burgess's
> e7c26e04b2dd6266d62d5a5825ff7eb44d1cf14e )
>
> Tobias
>
> PS: The following was committed as 54b3d52c3cca836c7c4c08cc9c02eda6c096372a
>
> On 1/23/20 11:58 AM, Dragan Mladjenovic wrote: […]
>>>>>>>> 2019-08-05  Dragan Mladjenovic  
>>>>>>>>
>>>>>>>>   * config.in: Regenerated.
>>>>>>>>   * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define
>>>>>>>> to 1
>>>>>>>>   for TARGET_LIBC_GNUSTACK.
>>>>>>>>   * configure: Regenerated.
>>>>>>>>   * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc
>>>>>>>> version is
>>>>>>>>   found 2.31 or greater.

Thank you for letting me know.

Your change looks fine. How should I handle this? Do I just commit the 
portion related to my change or perhaps you wish to commit everything
altogether?


Best regards,
Dragan

[PATCH][wwwdocs] Document GNU-stack support added to GCC 10 for MIPS

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index ef27c9b..7736990 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -623,7 +623,14 @@ a work-in-progress.
   
 
 
-
+MIPS
+
+  The mips*-*-linux* targets now mark object files with 
appropriate GNU-stack note,
+facilitating use of non-executable stack hardening on GNU/Linux.
+The soft-float targets have this feature enabled by default, while
+for hard-float targets it requires use of glibc 2.31 or later.
+  
+
 
 
 
-- 
1.9.1

Re: [PATCH 2/2][MIPS][RFC] Emit .note.GNU-stack for hard-float linux targets.

[Dragan Mladjenovic]

On 07.12.2019. 19:33, Jeff Law wrote:
> On Thu, 2019-11-07 at 17:05 +0000, Dragan Mladjenovic wrote:
>> On 01.11.2019. 11:32, Dragan Mladjenovic wrote:
>>> On 10.08.2019. 00:15, Joseph Myers wrote:
>>>> On Fri, 9 Aug 2019, Jeff Law wrote:
>>>>
>>>>>> 2019-08-05  Dragan Mladjenovic  
>>>>>>
>>>>>>  * config.in: Regenerated.
>>>>>>  * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define
>>>>>> to 1
>>>>>>  for TARGET_LIBC_GNUSTACK.
>>>>>>  * configure: Regenerated.
>>>>>>  * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc
>>>>>> version is
>>>>>>  found 2.31 or greater.
>>>>> My only concern here is the configure bits.  So for example,
>>>>> will it do
>>>>> the right thing if you're cross-compiling to a MIPS linux
>>>>> target?  If
>>>>> so, how?  If not, do we need to make it a first class configure
>>>>> option
>>>>> so that it can be specified when building cross MIPS linux
>>>>> toolchains?
>>>>
>>>> The key point of using GCC_GLIBC_VERSION_GTE_IFELSE is that (a)
>>>> it checks
>>>> the target glibc headers if available when GCC is built and (b)
>>>> if not
>>>> available, you can still use --with-glibc-version when
>>>> configuring
>>>> GCC, to
>>>> get the right configuration in a bootstrap compiler built before
>>>> glibc is
>>>> built (the latter is necessary on some architectures to get the
>>>> right
>>>> stack-protector configuration for bootstrapping glibc, but may be
>>>> useful
>>>> in other cases as well).
>>>>
>>>> My main concern about this patch is the one I gave in
>>>> <https://sourceware.org/ml/libc-alpha/2019-08/msg00086.html>
>>>> about what
>>>> the configuration mechanism should be, on a whole-toolchain
>>>> level, to say
>>>> whether you are OK with a requirement for a 4.8 or later kernel.
>>>>
>>>
>>> Sorry for the late reply.
>>>
>>> I was waiting to backport [1] to most of the glibc release branches
>>> in
>>> use, but I got sidetracked along the way.
>>>
>>> After this patch lands the preferred way to configure gcc would be
>>> using
>>> --with-glibc-version=2.31 and to use said glibc.
>>> If the user/distribution can live with minimal kernel requirement
>>> of 4.8
>>> the glibc used should be configured with --enable-kernel=4.8.
>>> I also plan to backport the [1] to limit the opportunity for
>>> building
>>> the possibly broken glibc with the gcc w/ enabled .note.GNU-stack.
>>>
>>> This is all tedious and user has to be aware of all of it to make
>>> it
>>> work, but hopefully over time the distributions will default to
>>> --with-glibc-version=2.31 and --enable-kernel=4.8. I guess
>>> providing the
>>> detailed NEWS entry for this change would help a bit.
>>>
>>> Is there any objections to getting this on the trunk before the end
>>> of
>>> stage1?
>>>
>>> [1] https://sourceware.org/ml/libc-alpha/2019-08/msg00639.html
>>>
>>
>> Small update and gentle ping. The glibc change was backported all
>> the
>> way back to 2.24.
> I think this is fine.  And yes, we'd like to get it mentioned in the
> release notes since I suspect folks will want the GNU-stack ELF notes.
>
> jeff
>
>

I left this to fall through the cracks once again. In light of [1], is 
there any leeway for me to push this now?

[1] https://gcc.gnu.org/ml/gcc/2020-01/msg00199.html

[PING] Re: [PATCH 2/2][MIPS][RFC] Emit .note.GNU-stack for hard-float linux targets.

[Dragan Mladjenovic]

On 07.11.2019. 18:05, Dragan Mladjenovic wrote:
> On 01.11.2019. 11:32, Dragan Mladjenovic wrote:
>> On 10.08.2019. 00:15, Joseph Myers wrote:
>>> On Fri, 9 Aug 2019, Jeff Law wrote:
>>>
>>>>> 2019-08-05  Dragan Mladjenovic  
>>>>>
>>>>> * config.in: Regenerated.
>>>>> * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
>>>>> for TARGET_LIBC_GNUSTACK.
>>>>> * configure: Regenerated.
>>>>> * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
>>>>> found 2.31 or greater.
>>>> My only concern here is the configure bits.  So for example, will it do
>>>> the right thing if you're cross-compiling to a MIPS linux target?  If
>>>> so, how?  If not, do we need to make it a first class configure option
>>>> so that it can be specified when building cross MIPS linux toolchains?
>>>
>>> The key point of using GCC_GLIBC_VERSION_GTE_IFELSE is that (a) it
>>> checks
>>> the target glibc headers if available when GCC is built and (b) if not
>>> available, you can still use --with-glibc-version when configuring
>>> GCC, to
>>> get the right configuration in a bootstrap compiler built before
>>> glibc is
>>> built (the latter is necessary on some architectures to get the right
>>> stack-protector configuration for bootstrapping glibc, but may be useful
>>> in other cases as well).
>>>
>>> My main concern about this patch is the one I gave in
>>> <https://sourceware.org/ml/libc-alpha/2019-08/msg00086.html> about what
>>> the configuration mechanism should be, on a whole-toolchain level, to
>>> say
>>> whether you are OK with a requirement for a 4.8 or later kernel.
>>>
>>
>> Sorry for the late reply.
>>
>> I was waiting to backport [1] to most of the glibc release branches in
>> use, but I got sidetracked along the way.
>>
>> After this patch lands the preferred way to configure gcc would be using
>> --with-glibc-version=2.31 and to use said glibc.
>> If the user/distribution can live with minimal kernel requirement of 4.8
>> the glibc used should be configured with --enable-kernel=4.8.
>> I also plan to backport the [1] to limit the opportunity for building
>> the possibly broken glibc with the gcc w/ enabled .note.GNU-stack.
>>
>> This is all tedious and user has to be aware of all of it to make it
>> work, but hopefully over time the distributions will default to
>> --with-glibc-version=2.31 and --enable-kernel=4.8. I guess providing the
>> detailed NEWS entry for this change would help a bit.
>>
>> Is there any objections to getting this on the trunk before the end of
>> stage1?
>>
>> [1] https://sourceware.org/ml/libc-alpha/2019-08/msg00639.html
>>
>
> Small update and gentle ping. The glibc change was backported all the
> way back to 2.24.
>
> Best regards,
> Dragan
>

Ping.

Re: [PATCH] [MIPS] Prevent MSA branches from being put into delay slots

[Dragan Mladjenovic]

On 16.11.2019. 00:33, Jeff Law wrote:
> On 11/15/19 10:27 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic" 
>>
>>   This patch tightens the instruction definitions to make sure
>>   that MSA branch instructions cannot be put into delay slots and have their
>>   delay slots eligible for being filled. Also, MSA *div*3 patterns use MSA
>>   branches for zero checks but are not marked as being multi instruction and
>>   thus could be put into delay slots. This patch fixes that.
>>
>>   Testcase only covers if MSA branch delay slot is being filled.
>>
>> gcc/ChangeLog:
>>
>> 2019-11-15  Zoran Jovanovic 
>>  Dragan Mladjenovic  
>>
>>  * config/mips/mips-msa.md (msa__, 
>> msa__v_):
>>  Mark as not having "likely" version.
>>  * config/mips/mips.md (insn_count): The simd_div instruction with
>>  TARGET_CHECK_ZERO_DIV consists of 3 instructions.
>>  (can_delay): Exclude simd_branch.
>>  (defile_delay *): Add simd_branch instructions.
>>  They have one regular delay slot.
> OK
> jeff
>

Thanks, committed as r278458.

Dragan

[PATCH] [MIPS] Prevent MSA branches from being put into delay slots

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

 This patch tightens the instruction definitions to make sure
 that MSA branch instructions cannot be put into delay slots and have their
 delay slots eligible for being filled. Also, MSA *div*3 patterns use MSA
 branches for zero checks but are not marked as being multi instruction and
 thus could be put into delay slots. This patch fixes that.

 Testcase only covers if MSA branch delay slot is being filled.

gcc/ChangeLog:

2019-11-15  Zoran Jovanovic 
        Dragan Mladjenovic  

* config/mips/mips-msa.md (msa__, 
msa__v_):
Mark as not having "likely" version.
* config/mips/mips.md (insn_count): The simd_div instruction with
TARGET_CHECK_ZERO_DIV consists of 3 instructions.
(can_delay): Exclude simd_branch.
(defile_delay *): Add simd_branch instructions.
They have one regular delay slot.

gcc/testsuite/ChangeLog:

2019-11-15  Dragan Mladjenovic  

* gcc.target/mips/msa-ds.c: New test.
---
 gcc/config/mips/mips-msa.md|  6 --
 gcc/config/mips/mips.md| 10 --
 gcc/testsuite/gcc.target/mips/msa-ds.c | 31 +++
 3 files changed, 43 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/msa-ds.c

diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
index 628423d..100cf99 100644
--- a/gcc/config/mips/mips-msa.md
+++ b/gcc/config/mips/mips-msa.md
@@ -2719,7 +2719,8 @@
 }
  [(set_attr "type" "simd_branch")
   (set_attr "mode" "")
-  (set_attr "compact_form" "never")])
+  (set_attr "compact_form" "never")
+  (set_attr "branch_likely" "no")])
 
 (define_insn "msa__v_"
  [(set (pc) (if_then_else
@@ -2738,4 +2739,5 @@
 }
  [(set_attr "type" "simd_branch")
   (set_attr "mode" "TI")
-  (set_attr "compact_form" "never")])
+  (set_attr "compact_form" "never")
+  (set_attr "branch_likely" "no")])
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 4de9731..929e368 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -560,6 +560,12 @@
 (eq_attr "type" "idiv,idiv3")
 (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))")
 
+;; simd div have 3 instruction if TARGET_CHECK_ZERO_DIV is true.
+(eq_attr "type" "simd_div")
+(if_then_else (match_test "TARGET_CHECK_ZERO_DIV")
+  (const_int 3)
+  (const_int 1))
+
 (not (eq_attr "sync_mem" "none"))
 (symbol_ref "mips_sync_loop_insns (insn, operands)")]
(const_int 1)))
@@ -759,7 +765,7 @@
 
 ;; Can the instruction be put into a delay slot?
 (define_attr "can_delay" "no,yes"
-  (if_then_else (and (eq_attr "type" "!branch,call,jump")
+  (if_then_else (and (eq_attr "type" "!branch,call,jump,simd_branch")
 (eq_attr "hazard" "none")
 (match_test "get_attr_insn_count (insn) == 1"))
(const_string "yes")
@@ -1098,7 +1104,7 @@
 
 ;; Branches that have delay slots and don't have likely variants do
 ;; not annul on false.
-(define_delay (and (eq_attr "type" "branch")
+(define_delay (and (eq_attr "type" "branch,simd_branch")
   (not (match_test "TARGET_MIPS16"))
   (ior (match_test "TARGET_CB_NEVER")
(and (eq_attr "compact_form" "maybe")
diff --git a/gcc/testsuite/gcc.target/mips/msa-ds.c 
b/gcc/testsuite/gcc.target/mips/msa-ds.c
new file mode 100644
index 000..c6932b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-ds.c
@@ -0,0 +1,31 @@
+/* { dg-options "-mmsa -mfp64 -mhard-float" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* Check that delay slots for MSA branches are filled. */
+
+typedef unsigned v4si __attribute__ ((vector_size (16)));
+
+int __attribute__ ((cold)) foo (v4si v , int a, int b)
+{
+  int c = 0xf0f0f0f0;
+  int f = __builtin_msa_bnz_w (v);
+
+  if (f)
+   return a + c;
+  else
+   return b + c;
+}
+
+int __attribute__ ((cold)) bar (v4si v , int a, int b)
+{
+  int c = 0xf0f0f0f0;
+  int f = __builtin_msa_bz_w (v);
+
+  if (f)
+   return a + c;
+  else
+   return b + c;
+}
+
+/* { dg-final { scan-assembler-not "foo:.*nop.*jr.*foo," } } */
+/* { dg-final { scan-assembler-not "bar:.*nop.*jr.*bar," } } */
-- 
1.9.1

Re: [PATCH] [MIPS] Sanitize the constant argument for rotr3

[Dragan Mladjenovic]

On 12.11.2019. 16:29, Jeff Law wrote:
> On 11/12/19 7:56 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic" 
>>
>> This was dormant for quite some time, but it started happening for me
>> on gcc.c-torture/compile/pr65153.c sometime after r276645 for -mabi=32 linux 
>> runs.
>>
>> The pattern accepts any SMALL_OPERAND constant value while it asserts during 
>> the final
>> that the value is in the mode size range. I this case it happens that 
>> combine_and_move_insns
>> during ira makes a pattern with negative "shift count" which fails at final 
>> stage.
>>
>> This simple fix just truncates the constant operand to mode size the same as 
>> shift patterns.
>>
>> gcc/ChangeLog:
>>
>> 2019-11-12  Dragan Mladjenovic  
>>
>>  * config/mips/mips.md (rotr3): Sanitize the constant argument
>>  instead of asserting its value.
>> ---
>>
>> Ok, for trunk and backport to gcc 9 and 8 branches?
> OK.  But I'm not sure the formatting is right.  The bit-and operator
> should be indented so that it lines up with the start of INTVAL (...).
>

Thanks. Now I see it. Committed with fixed indention on trunk, gcc-9 and 
gcc-8 as r278152, r278154 and r278155 respectively.

Best regards,
Dragan

[PATCH] [MIPS] Sanitize the constant argument for rotr3

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

This was dormant for quite some time, but it started happening for me
on gcc.c-torture/compile/pr65153.c sometime after r276645 for -mabi=32 linux 
runs.

The pattern accepts any SMALL_OPERAND constant value while it asserts during 
the final
that the value is in the mode size range. I this case it happens that 
combine_and_move_insns
during ira makes a pattern with negative "shift count" which fails at final 
stage.

This simple fix just truncates the constant operand to mode size the same as 
shift patterns.

gcc/ChangeLog:

2019-11-12  Dragan Mladjenovic  

* config/mips/mips.md (rotr3): Sanitize the constant argument
instead of asserting its value.
---

Ok, for trunk and backport to gcc 9 and 8 branches?

 gcc/config/mips/mips.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 658f5e6..1d63aca 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -5845,8 +5845,8 @@
   "ISA_HAS_ROR"
 {
   if (CONST_INT_P (operands[2]))
-gcc_assert (INTVAL (operands[2]) >= 0
-   && INTVAL (operands[2]) < GET_MODE_BITSIZE (mode));
+operands[2] = GEN_INT (INTVAL (operands[2])
+ & (GET_MODE_BITSIZE (mode) - 1));
 
   return "ror\t%0,%1,%2";
 }
-- 
1.9.1

Re: [PATCH 2/2][MIPS][RFC] Emit .note.GNU-stack for hard-float linux targets.

[Dragan Mladjenovic]

On 01.11.2019. 11:32, Dragan Mladjenovic wrote:
> On 10.08.2019. 00:15, Joseph Myers wrote:
>> On Fri, 9 Aug 2019, Jeff Law wrote:
>>
>>>> 2019-08-05  Dragan Mladjenovic  
>>>>
>>>> * config.in: Regenerated.
>>>> * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
>>>> for TARGET_LIBC_GNUSTACK.
>>>> * configure: Regenerated.
>>>> * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
>>>> found 2.31 or greater.
>>> My only concern here is the configure bits.  So for example, will it do
>>> the right thing if you're cross-compiling to a MIPS linux target?  If
>>> so, how?  If not, do we need to make it a first class configure option
>>> so that it can be specified when building cross MIPS linux toolchains?
>>
>> The key point of using GCC_GLIBC_VERSION_GTE_IFELSE is that (a) it checks
>> the target glibc headers if available when GCC is built and (b) if not
>> available, you can still use --with-glibc-version when configuring
>> GCC, to
>> get the right configuration in a bootstrap compiler built before glibc is
>> built (the latter is necessary on some architectures to get the right
>> stack-protector configuration for bootstrapping glibc, but may be useful
>> in other cases as well).
>>
>> My main concern about this patch is the one I gave in
>> <https://sourceware.org/ml/libc-alpha/2019-08/msg00086.html> about what
>> the configuration mechanism should be, on a whole-toolchain level, to say
>> whether you are OK with a requirement for a 4.8 or later kernel.
>>
>
> Sorry for the late reply.
>
> I was waiting to backport [1] to most of the glibc release branches in
> use, but I got sidetracked along the way.
>
> After this patch lands the preferred way to configure gcc would be using
> --with-glibc-version=2.31 and to use said glibc.
> If the user/distribution can live with minimal kernel requirement of 4.8
> the glibc used should be configured with --enable-kernel=4.8.
> I also plan to backport the [1] to limit the opportunity for building
> the possibly broken glibc with the gcc w/ enabled .note.GNU-stack.
>
> This is all tedious and user has to be aware of all of it to make it
> work, but hopefully over time the distributions will default to
> --with-glibc-version=2.31 and --enable-kernel=4.8. I guess providing the
> detailed NEWS entry for this change would help a bit.
>
> Is there any objections to getting this on the trunk before the end of
> stage1?
>
> [1] https://sourceware.org/ml/libc-alpha/2019-08/msg00639.html
>

Small update and gentle ping. The glibc change was backported all the 
way back to 2.24.

Best regards,
Dragan

Re: [PATCH 2/2][MIPS][RFC] Emit .note.GNU-stack for hard-float linux targets.

[Dragan Mladjenovic]

On 10.08.2019. 00:15, Joseph Myers wrote:
> On Fri, 9 Aug 2019, Jeff Law wrote:
>
>>> 2019-08-05  Dragan Mladjenovic  
>>>
>>> * config.in: Regenerated.
>>> * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
>>> for TARGET_LIBC_GNUSTACK.
>>> * configure: Regenerated.
>>> * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
>>> found 2.31 or greater.
>> My only concern here is the configure bits.  So for example, will it do
>> the right thing if you're cross-compiling to a MIPS linux target?  If
>> so, how?  If not, do we need to make it a first class configure option
>> so that it can be specified when building cross MIPS linux toolchains?
>
> The key point of using GCC_GLIBC_VERSION_GTE_IFELSE is that (a) it checks
> the target glibc headers if available when GCC is built and (b) if not
> available, you can still use --with-glibc-version when configuring GCC, to
> get the right configuration in a bootstrap compiler built before glibc is
> built (the latter is necessary on some architectures to get the right
> stack-protector configuration for bootstrapping glibc, but may be useful
> in other cases as well).
>
> My main concern about this patch is the one I gave in
> <https://sourceware.org/ml/libc-alpha/2019-08/msg00086.html> about what
> the configuration mechanism should be, on a whole-toolchain level, to say
> whether you are OK with a requirement for a 4.8 or later kernel.
>

Sorry for the late reply.

I was waiting to backport [1] to most of the glibc release branches in 
use, but I got sidetracked along the way.

After this patch lands the preferred way to configure gcc would be using 
--with-glibc-version=2.31 and to use said glibc.
If the user/distribution can live with minimal kernel requirement of 4.8
the glibc used should be configured with --enable-kernel=4.8.
I also plan to backport the [1] to limit the opportunity for building 
the possibly broken glibc with the gcc w/ enabled .note.GNU-stack.

This is all tedious and user has to be aware of all of it to make it 
work, but hopefully over time the distributions will default to 
--with-glibc-version=2.31 and --enable-kernel=4.8. I guess providing the 
detailed NEWS entry for this change would help a bit.

Is there any objections to getting this on the trunk before the end of
stage1?

[1] https://sourceware.org/ml/libc-alpha/2019-08/msg00639.html

Best regards,
Dragan

Re: Re: [RFC/PATCH v2][PR89245] Check REG_CALL_DECL note during the tail-merging

[Dragan Mladjenovic]

On 01.10.2019. 21:35, Jeff Law wrote:
> On 9/6/19 4:23 AM, Dragan Mladjenovic wrote:
>> On 24.07.2019. 20:57, Jeff Law wrote:
>>> On 7/17/19 2:29 AM, Dragan Mladjenovic wrote:
>>>>
>>>>
>>>> On 09.07.2019. 23:21, Jeff Law wrote:
>>>>> On 7/9/19 2:06 PM, Dragan Mladjenovic wrote:
>>>>>> This patch prevents merging of CALL instructions that that have different
>>>>>> REG_CALL_DECL notes attached to them.
>>>>>>
>>>>>> On most architectures this is not an important distinction. Usually 
>>>>>> instruction patterns
>>>>>> for calls to different functions reference different SYMBOL_REF-s, so 
>>>>>> they won't match.
>>>>>> On MIPS PIC calls get split into an got_load/*call_internal pair where 
>>>>>> the latter represents
>>>>>> indirect register call w/o SYMBOL_REF attached (until machine_reorg 
>>>>>> pass). The bugzilla issue
>>>>>> had such two internal_call-s merged despite the fact that they had 
>>>>>> different register usage
>>>>>> information assigned by ipa-ra.
>>>>>>
>>>>>> As per comment form Richard Sandiford, this version compares reg usage 
>>>>>> for both call
>>>>>> instruction instead of shallow comparing the notes. Tests updated 
>>>>>> accordingly.
>>>>>>
>>>>>> gcc/ChangeLog:
>>>>>>
>>>>>> 2019-07-09  Dragan Mladjenovic  
>>>>>>
>>>>>>  * cfgcleanup.c (old_insns_match_p): Check if used hard regs set is equal
>>>>>>  for both call instructions.
>>>>>>
>>>>>> gcc/testsuite/ChangeLog:
>>>>>>
>>>>>> 2019-07-09  Dragan Mladjenovic  
>>>>>>
>>>>>>  * gcc.target/mips/cfgcleanup-jalr1.c: New test.
>>>>>>  * gcc.target/mips/cfgcleanup-jalr2.c: New test.
>>>>>>  * gcc.target/mips/cfgcleanup-jalr3.c: New test.
>>>>> THanks.  I've installed this on the trunk.
>>>>>
>>>>> jeff
>>>> Thanks. Can this be back-ported to active branches also. This issue
>>>> seems to be there > since gcc6 if not gcc5.
>>> I've asked Matthew to handle the backport.  I'm going to be on PTO the
>>> next couple weeks.
>>>
>>> jeff
>>>
>>
>> Hi,
>>
>> Sorry, I forgot to check up on this patch. Is it still ok for me to try
>> to backport it to gcc 9 and gcc 8 branches?
> Yes, this would be fine to backport to gcc-8 and gcc-9 branches.  I'd
> expect it to be pretty easy as I don't think old_insns_match_p has
> changed much.

Thanks and sorry for the delay.
Backported as r277625 and r277626 to gcc-9 and gcc-8 branch respectively.

Best regards,
Dragan

Re: [EXTERNAL]Re: Re: [PATCH] [MIPS] Fix PR target/91769

[Dragan Mladjenovic]

On 06.10.2019. 08:43, Paul Hua wrote:
> Hi:
>
> The testsuite has a typo in "dg-final scan-assembler", s/mthc1/mtc1/.
>


Hi,

I think I know what is happening here. My testing setup defaults to 
-mfpxx and yours probably to -mfp32. I should have probably tightened 
the test up to require R2 isa as well.
Does adding isa_rev=2 and -mfpxx to dg-options fix the fallout form this 
test? I cannot check it right now, but I can send the fix for this 
tomorrow. Sorry for the inconvenience.

Best regards,
Dragan

Re: Re: [PATCH] [MIPS] Fix PR target/91769

[Dragan Mladjenovic]

On 01.10.2019. 21:37, Jeff Law wrote:
> On 9/25/19 1:16 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic" 
>>
>> This fixes the issue by checking that addr's base reg is not part of dest
>> multiword reg instead just checking the first reg of dest.
>>
>> gcc/ChangeLog:
>>
>> 2019-09-25  Dragan Mladjenovic  
>>
>>  PR target/91769
>>  * config/mips/mips.c (mips_split_move): Use reg_overlap_mentioned_p
>>  instead of REGNO equality check on addr.reg.
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2019-09-25  Dragan Mladjenovic  
>>
>>  PR target/91769
>>  * gcc.target/mips/pr91769.c: New test.
> OK.  This would seem fine to backport to gcc-9 as well.  I don't think
> gcc-8 had this code.

Committed on trunk as r276525.
Committed on gcc-9-branch as r276570 along with the r273174 as r276569.

Best regards,
Dragan

Re: [PATCH] [MIPS] Fix PR target/91769

[Dragan Mladjenovic]

CC: YunQiang Su

On 25.09.2019. 09:16, Dragan Mladjenovic wrote:
> From: "Dragan Mladjenovic" 
>
> This fixes the issue by checking that addr's base reg is not part of dest
> multiword reg instead just checking the first reg of dest.
>
> gcc/ChangeLog:
>
> 2019-09-25  Dragan Mladjenovic  
>
>   PR target/91769
>   * config/mips/mips.c (mips_split_move): Use reg_overlap_mentioned_p
>   instead of REGNO equality check on addr.reg.
>
> gcc/testsuite/ChangeLog:
>
> 2019-09-25  Dragan Mladjenovic  
>
>   PR target/91769
>   * gcc.target/mips/pr91769.c: New test.
> ---
>
> Hi all,
>
> Is this OK for trunk?
>
> The test case is a bit crude, but I guess that is better than having none.
>
> On top of that, I would like to backport this along with r273174 onto gcc 9 
> branch.
> That should fix BZ91702 and BZ91474 reported against gcc 9.2.
>
> Tested on mips-mti-linux-gnu.
>
> Best regards,
> Dragan
>
>   gcc/config/mips/mips.c  |  2 +-
>   gcc/testsuite/gcc.target/mips/pr91769.c | 19 +++
>   2 files changed, 20 insertions(+), 1 deletion(-)
>   create mode 100644 gcc/testsuite/gcc.target/mips/pr91769.c
>
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index c682ebd..aa527b4 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -4862,7 +4862,7 @@ mips_split_move (rtx dest, rtx src, enum 
> mips_split_type split_type, rtx insn_)
>   {
> rtx tmp = XEXP (src, 0);
> mips_classify_address (, tmp, GET_MODE (tmp), true);
> -   if (addr.reg && REGNO (addr.reg) != REGNO (dest))
> +   if (addr.reg && !reg_overlap_mentioned_p (dest, addr.reg))
>   validate_change (next, _SRC (set), src, false);
>   }
> else
> diff --git a/gcc/testsuite/gcc.target/mips/pr91769.c 
> b/gcc/testsuite/gcc.target/mips/pr91769.c
> new file mode 100644
> index 000..b856183
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/mips/pr91769.c
> @@ -0,0 +1,19 @@
> +/* PR target/91769 */
> +/* { dg-do compile } */
> +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } 
> { "-O0" "-g" } { "" } } */
> +/* { dg-options "-EL -mgp32 -mhard-float" } */
> +
> +NOCOMPRESSION double
> +foo (void)
> +{
> +  register double* pf __asm__ ("$a1");
> +  __asm__ __volatile__ ("":"=r"(pf));
> +  double f = *pf;
> +
> +  if (f != f)
> +f = -f;
> +  return f;
> +}
> +
> +/* { dg-final { scan-assembler-not 
> "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tldc1\t\\\$.*,0\\(\\\$5\\)"
>  } } */
> +/* { dg-final { scan-assembler 
> "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tmtc1\t\\\$4,\\\$.*\n\tmthc1\t\\\$5,\\\$.*"
>  } } */
>

[PATCH] [MIPS] Fix PR target/91769

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

This fixes the issue by checking that addr's base reg is not part of dest
multiword reg instead just checking the first reg of dest.

gcc/ChangeLog:

2019-09-25  Dragan Mladjenovic  

PR target/91769
* config/mips/mips.c (mips_split_move): Use reg_overlap_mentioned_p
instead of REGNO equality check on addr.reg.

gcc/testsuite/ChangeLog:

2019-09-25  Dragan Mladjenovic  

PR target/91769
* gcc.target/mips/pr91769.c: New test.
---

Hi all,

Is this OK for trunk?

The test case is a bit crude, but I guess that is better than having none.

On top of that, I would like to backport this along with r273174 onto gcc 9 
branch.
That should fix BZ91702 and BZ91474 reported against gcc 9.2.

Tested on mips-mti-linux-gnu.

Best regards,
Dragan

 gcc/config/mips/mips.c  |  2 +-
 gcc/testsuite/gcc.target/mips/pr91769.c | 19 +++
 2 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/pr91769.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index c682ebd..aa527b4 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4862,7 +4862,7 @@ mips_split_move (rtx dest, rtx src, enum mips_split_type 
split_type, rtx insn_)
{
  rtx tmp = XEXP (src, 0);
  mips_classify_address (, tmp, GET_MODE (tmp), true);
- if (addr.reg && REGNO (addr.reg) != REGNO (dest))
+ if (addr.reg && !reg_overlap_mentioned_p (dest, addr.reg))
validate_change (next, _SRC (set), src, false);
}
  else
diff --git a/gcc/testsuite/gcc.target/mips/pr91769.c 
b/gcc/testsuite/gcc.target/mips/pr91769.c
new file mode 100644
index 000..b856183
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr91769.c
@@ -0,0 +1,19 @@
+/* PR target/91769 */
+/* { dg-do compile } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { 
"-O0" "-g" } { "" } } */
+/* { dg-options "-EL -mgp32 -mhard-float" } */
+
+NOCOMPRESSION double
+foo (void)
+{
+  register double* pf __asm__ ("$a1");
+  __asm__ __volatile__ ("":"=r"(pf));
+  double f = *pf;
+
+  if (f != f)
+f = -f;
+  return f;
+}
+
+/* { dg-final { scan-assembler-not 
"lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tldc1\t\\\$.*,0\\(\\\$5\\)" 
} } */
+/* { dg-final { scan-assembler 
"lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tmtc1\t\\\$4,\\\$.*\n\tmthc1\t\\\$5,\\\$.*"
 } } */
-- 
1.9.1

Re: [EXTERNAL]Re: [RFC/PATCH v2][PR89245] Check REG_CALL_DECL note during the tail-merging

[Dragan Mladjenovic]

On 24.07.2019. 20:57, Jeff Law wrote:
> On 7/17/19 2:29 AM, Dragan Mladjenovic wrote:
>>
>>
>> On 09.07.2019. 23:21, Jeff Law wrote:
>>> On 7/9/19 2:06 PM, Dragan Mladjenovic wrote:
>>>> This patch prevents merging of CALL instructions that that have different
>>>> REG_CALL_DECL notes attached to them.
>>>>
>>>> On most architectures this is not an important distinction. Usually 
>>>> instruction patterns
>>>> for calls to different functions reference different SYMBOL_REF-s, so they 
>>>> won't match.
>>>> On MIPS PIC calls get split into an got_load/*call_internal pair where the 
>>>> latter represents
>>>> indirect register call w/o SYMBOL_REF attached (until machine_reorg pass). 
>>>> The bugzilla issue
>>>> had such two internal_call-s merged despite the fact that they had 
>>>> different register usage
>>>> information assigned by ipa-ra.
>>>>
>>>> As per comment form Richard Sandiford, this version compares reg usage for 
>>>> both call
>>>> instruction instead of shallow comparing the notes. Tests updated 
>>>> accordingly.
>>>>
>>>> gcc/ChangeLog:
>>>>
>>>> 2019-07-09  Dragan Mladjenovic  
>>>>
>>>>* cfgcleanup.c (old_insns_match_p): Check if used hard regs set is equal
>>>>for both call instructions.
>>>>
>>>> gcc/testsuite/ChangeLog:
>>>>
>>>> 2019-07-09  Dragan Mladjenovic  
>>>>
>>>>* gcc.target/mips/cfgcleanup-jalr1.c: New test.
>>>>* gcc.target/mips/cfgcleanup-jalr2.c: New test.
>>>>* gcc.target/mips/cfgcleanup-jalr3.c: New test.
>>> THanks.  I've installed this on the trunk.
>>>
>>> jeff
>> Thanks. Can this be back-ported to active branches also. This issue
>> seems to be there > since gcc6 if not gcc5.
> I've asked Matthew to handle the backport.  I'm going to be on PTO the
> next couple weeks.
>
> jeff
>

Hi,

Sorry, I forgot to check up on this patch. Is it still ok for me to try 
to backport it to gcc 9 and gcc 8 branches?

Best regards,
Dragan

Re: [EXTERNAL]Re: [PATCH 1/2][MIPS] Emit .note.GNU-stack for soft-float linux targets.

[Dragan Mladjenovic]

On 09.08.2019. 23:31, Jeff Law wrote:
> On 8/5/19 4:47 AM, Dragan Mladjenovic wrote:
>> From: "Dragan Mladjenovic" 
>>
>> gcc/ChangeLog:
>>
>> 2019-08-05  Dragan Mladjenovic  
>>
>>  * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
>>  TARGET_SOFT_FLOAT.
>>  * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
>>  (mips_asm_file_end): New function. Delegate to
>>  file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
>>  * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
>>
>> libgcc/ChangeLog:
>>
>> 2019-08-05  Dragan Mladjenovic  
>>
>>  * config/mips/gnustack.h: New file.
>>  * config/mips/crti.S: Include gnustack.h.
>>  * config/mips/crtn.S: Likewise.
>>  * config/mips/mips16.S: Likewise.
>>  * config/mips/vr4120-div.S: Likewise.
> Seems reasonable.  What testing has been done for this patch?  I don't
> doubt it works for the MIPS linux targets, I'm more interested in making
> sure it doesn't do the wrong thing for the embedded mips targets.

I've built a cross mips-mti-elf toolchain, albeit with reduced multilib, 
but still there were not .note.GNU-stack in sysroot.
Is this enough?

 >
 > Do you have write access to the repository?
 >

I do not have write access to the repository.

Best regards,
Dragan

[PATCH 2/2][MIPS][RFC] Emit .note.GNU-stack for hard-float linux targets.

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

libgcc/ChangeLog:

2019-08-05  Dragan Mladjenovic  

* config/mips/gnustack.h: Check for TARGET_LIBC_GNUSTACK also.

gcc/ChangeLog:

2019-08-05  Dragan Mladjenovic  

* config.in: Regenerated.
* config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
for TARGET_LIBC_GNUSTACK.
* configure: Regenerated.
* configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
found 2.31 or greater.
---
 gcc/config/mips/linux.h   |  4 
 gcc/configure.ac  | 12 
 libgcc/config/mips/gnustack.h |  2 +-
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
index 1fa72ef..30b22e7 100644
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
@@ -53,4 +53,8 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef NEED_INDICATE_EXEC_STACK
 
+#ifdef TARGET_LIBC_GNUSTACK
+#define NEED_INDICATE_EXEC_STACK 1
+#else
 #define NEED_INDICATE_EXEC_STACK TARGET_SOFT_FLOAT
+#endif
diff --git a/gcc/configure.ac b/gcc/configure.ac
index c620dd2..ab080c8 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -6143,6 +6143,18 @@ if test x$gcc_cv_libc_provides_hwcap_in_tcb = xyes; then
[Define if your target C Library provides the AT_HWCAP value in the 
TCB])
 fi
 
+# Check if the target LIBC handles PT_GNU_STACK.
+gcc_cv_libc_gnustack=unknown
+case "$target" in
+  mips*-*-linux*)
+GCC_GLIBC_VERSION_GTE_IFELSE([2], [31], [gcc_cv_libc_gnustack=yes], )
+;;
+esac
+if test x$gcc_cv_libc_gnustack = xyes; then
+  AC_DEFINE(TARGET_LIBC_GNUSTACK, 1,
+[Define if your target C Library properly handles PT_GNU_STACK])
+fi
+
 AC_MSG_CHECKING(dl_iterate_phdr in target C library)
 gcc_cv_target_dl_iterate_phdr=unknown
 case "$target" in
diff --git a/libgcc/config/mips/gnustack.h b/libgcc/config/mips/gnustack.h
index 6d5f618..a67c4b2 100644
--- a/libgcc/config/mips/gnustack.h
+++ b/libgcc/config/mips/gnustack.h
@@ -1,6 +1,6 @@
 #include "config.h"
 #if defined(__ELF__) && defined(__linux__)
-#if defined (__mips_soft_float)
+#if defined (TARGET_LIBC_GNUSTACK) || defined (__mips_soft_float)
 .section .note.GNU-stack,"",%progbits
 .previous
 #endif
-- 
1.9.1

[PATCH 1/2][MIPS] Emit .note.GNU-stack for soft-float linux targets.

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

gcc/ChangeLog:

2019-08-05  Dragan Mladjenovic  

* config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
TARGET_SOFT_FLOAT.
* config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
(mips_asm_file_end): New function. Delegate to
file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
* config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.

libgcc/ChangeLog:

2019-08-05  Dragan Mladjenovic  

* config/mips/gnustack.h: New file.
* config/mips/crti.S: Include gnustack.h.
* config/mips/crtn.S: Likewise.
* config/mips/mips16.S: Likewise.
* config/mips/vr4120-div.S: Likewise.
---
 gcc/config/mips/linux.h |  4 
 gcc/config/mips/mips.c  | 11 +++
 gcc/config/mips/mips.h  |  2 ++
 libgcc/config/mips/crti.S   |  3 +++
 libgcc/config/mips/crtn.S   |  3 +++
 libgcc/config/mips/gnustack.h   |  7 +++
 libgcc/config/mips/mips16.S |  3 +++
 libgcc/config/mips/vr4120-div.S |  3 +++
 8 files changed, 36 insertions(+)
 create mode 100644 libgcc/config/mips/gnustack.h

diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
index 6f79ac9..1fa72ef 100644
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
@@ -50,3 +50,7 @@ along with GCC; see the file COPYING3.  If not see
 #define GNU_USER_DYNAMIC_LINKERN32 \
   CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
  BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
+
+#undef NEED_INDICATE_EXEC_STACK
+
+#define NEED_INDICATE_EXEC_STACK TARGET_SOFT_FLOAT
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index e0535b1..66ef23a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -22522,6 +22522,13 @@ mips_starting_frame_offset (void)
 return 0;
   return crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE;
 }
+
+static void
+mips_asm_file_end (void)
+{
+  if (NEED_INDICATE_EXEC_STACK)
+file_end_indicate_exec_stack ();
+}
 
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
@@ -22829,6 +22836,10 @@ mips_starting_frame_offset (void)
 #undef TARGET_STARTING_FRAME_OFFSET
 #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset
 
+#undef TARGET_ASM_FILE_END
+#define TARGET_ASM_FILE_END mips_asm_file_end
+
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-mips.h"
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index a5be7fa3..22a1b3c 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3461,3 +3461,5 @@ struct GTY(())  machine_function {
   (TARGET_LOAD_STORE_PAIRS \
&& (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \
&& !TARGET_MICROMIPS && !TARGET_FIX_24K)
+
+#define NEED_INDICATE_EXEC_STACK 0
diff --git a/libgcc/config/mips/crti.S b/libgcc/config/mips/crti.S
index 44409c7..8733415 100644
--- a/libgcc/config/mips/crti.S
+++ b/libgcc/config/mips/crti.S
@@ -21,6 +21,9 @@ a copy of the GCC Runtime Library Exception along with this 
program;
 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 <http://www.gnu.org/licenses/>.  */
 
+/* An executable stack is *not* required for these functions.  */
+#include "gnustack.h"
+
 /* 4 slots for argument spill area.  1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20.  Aligned to 16 bytes for n32.  */
 
diff --git a/libgcc/config/mips/crtn.S b/libgcc/config/mips/crtn.S
index b56d77c..f897906 100644
--- a/libgcc/config/mips/crtn.S
+++ b/libgcc/config/mips/crtn.S
@@ -21,6 +21,9 @@ a copy of the GCC Runtime Library Exception along with this 
program;
 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 <http://www.gnu.org/licenses/>.  */
 
+/* An executable stack is *not* required for these functions.  */
+#include "gnustack.h"
+
 /* 4 slots for argument spill area.  1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20.  Aligned to 16 bytes for n32.  */
 
diff --git a/libgcc/config/mips/gnustack.h b/libgcc/config/mips/gnustack.h
new file mode 100644
index 000..6d5f618
--- /dev/null
+++ b/libgcc/config/mips/gnustack.h
@@ -0,0 +1,7 @@
+#include "config.h"
+#if defined(__ELF__) && defined(__linux__)
+#if defined (__mips_soft_float)
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+#endif
diff --git a/libgcc/config/mips/mips16.S b/libgcc/config/mips/mips16.S
index 8cfd9e4..1f4df43 100644
--- a/libgcc/config/mips/mips16.S
+++ b/libgcc/config/mips/mips16.S
@@ -21,6 +21,9 @@ a copy of the GCC Runtime Library Exception along with this 
program;
 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 <http://www.gnu.org/licenses/>.  */
 
+/* An executable stack is *not* required for these functions.  */
+#include "gnustack.h"
+
 #include "auto-host.h"
 
 #

[PATCH 0/2] [MIPS] Emit .note.GNU-stack for linux targets.

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

Greetings,

These patches enable emitting .note.GNU-stack by default on mips linux targets.
First one enables it unconditionally for soft-float builds while the second one
enables it for hard-float build if gcc is configured against the future version
of glibc that should enable safe usage of PT_GNU_STACK [1].


[1] https://sourceware.org/ml/libc-alpha/2019-08/msg00065.html

Best regards,

Dragan

Dragan Mladjenovic (2):
  Emit .note.GNU-stack for soft-float linux targets.
  Emit .note.GNU-stack for hard-float linux targets.

 gcc/config.in   |  6 ++
 gcc/config/mips/linux.h |  8 +++
 gcc/config/mips/mips.c  | 11 ++
 gcc/config/mips/mips.h  |  2 ++
 gcc/configure   | 47 +
 gcc/configure.ac| 12 +++
 libgcc/config/mips/crti.S   |  3 +++
 libgcc/config/mips/crtn.S   |  3 +++
 libgcc/config/mips/gnustack.h   |  7 ++
 libgcc/config/mips/mips16.S |  3 +++
 libgcc/config/mips/vr4120-div.S |  3 +++
 11 files changed, 96 insertions(+), 9 deletions(-)
 create mode 100644 libgcc/config/mips/gnustack.h

-- 
1.9.1

Re: [RFC/PATCH v2][PR89245] Check REG_CALL_DECL note during the tail-merging

[Dragan Mladjenovic]

On 09.07.2019. 23:21, Jeff Law wrote:
> On 7/9/19 2:06 PM, Dragan Mladjenovic wrote:
>> This patch prevents merging of CALL instructions that that have different
>> REG_CALL_DECL notes attached to them.
>>
>> On most architectures this is not an important distinction. Usually 
>> instruction patterns
>> for calls to different functions reference different SYMBOL_REF-s, so they 
>> won't match.
>> On MIPS PIC calls get split into an got_load/*call_internal pair where the 
>> latter represents
>> indirect register call w/o SYMBOL_REF attached (until machine_reorg pass). 
>> The bugzilla issue
>> had such two internal_call-s merged despite the fact that they had different 
>> register usage
>> information assigned by ipa-ra.
>>
>> As per comment form Richard Sandiford, this version compares reg usage for 
>> both call
>> instruction instead of shallow comparing the notes. Tests updated 
>> accordingly.
>>
>> gcc/ChangeLog:
>>
>> 2019-07-09  Dragan Mladjenovic  
>>
>>  * cfgcleanup.c (old_insns_match_p): Check if used hard regs set is equal
>>  for both call instructions.
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2019-07-09  Dragan Mladjenovic  
>>
>>  * gcc.target/mips/cfgcleanup-jalr1.c: New test.
>>  * gcc.target/mips/cfgcleanup-jalr2.c: New test.
>>  * gcc.target/mips/cfgcleanup-jalr3.c: New test.
> THanks.  I've installed this on the trunk.
>
> jeff
Thanks. Can this be back-ported to active branches also. This issue 
seems to be there
since gcc6 if not gcc5.

Thanks in advance,

Dragan

[RFC/PATCH v2][PR89245] Check REG_CALL_DECL note during the tail-merging

[Dragan Mladjenovic]

This patch prevents merging of CALL instructions that that have different
REG_CALL_DECL notes attached to them.

On most architectures this is not an important distinction. Usually instruction 
patterns
for calls to different functions reference different SYMBOL_REF-s, so they 
won't match.
On MIPS PIC calls get split into an got_load/*call_internal pair where the 
latter represents
indirect register call w/o SYMBOL_REF attached (until machine_reorg pass). The 
bugzilla issue
had such two internal_call-s merged despite the fact that they had different 
register usage
information assigned by ipa-ra.

As per comment form Richard Sandiford, this version compares reg usage for both 
call
instruction instead of shallow comparing the notes. Tests updated accordingly.

gcc/ChangeLog:

2019-07-09  Dragan Mladjenovic  

* cfgcleanup.c (old_insns_match_p): Check if used hard regs set is equal
for both call instructions.

gcc/testsuite/ChangeLog:

2019-07-09  Dragan Mladjenovic  

* gcc.target/mips/cfgcleanup-jalr1.c: New test.
* gcc.target/mips/cfgcleanup-jalr2.c: New test.
* gcc.target/mips/cfgcleanup-jalr3.c: New test.
---
 gcc/cfgcleanup.c |  9 +
 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c | 19 +++
 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c | 23 +++
 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c | 23 +++
 4 files changed, 74 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c
 create mode 100644 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c
 create mode 100644 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c

diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c
index 992912c..fca3a08 100644
--- a/gcc/cfgcleanup.c
+++ b/gcc/cfgcleanup.c
@@ -53,6 +53,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "dce.h"
 #include "dbgcnt.h"
 #include "rtl-iter.h"
+#include "regs.h"
 
 #define FORWARDER_BLOCK_P(BB) ((BB)->flags & BB_FORWARDER_BLOCK)
 
@@ -1224,6 +1225,14 @@ old_insns_match_p (int mode ATTRIBUTE_UNUSED, rtx_insn 
*i1, rtx_insn *i2)
}
}
}
+
+  HARD_REG_SET i1_used, i2_used;
+
+  get_call_reg_set_usage (i1, _used, call_used_reg_set);
+  get_call_reg_set_usage (i2, _used, call_used_reg_set);
+
+  if (!hard_reg_set_equal_p (i1_used, i2_used))
+return dir_none;
 }
 
   /* If both i1 and i2 are frame related, verify all the CFA notes
diff --git a/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c 
b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c
new file mode 100644
index 000..24c1826
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mabicalls -fpic -mno-mips16 -mno-micromips" } */
+/* { dg-skip-if "needs codesize optimization" { *-*-* } { "-O0" "-O1" "-O2" 
"-O3" } { "" } } */
+
+extern void foo (void*);
+
+extern void bar (void*);
+
+void
+test (void* p)
+{
+   if (!p)
+   foo(p);
+   else
+   bar(p);
+}
+
+/* { dg-final { scan-assembler-not "\\\.reloc\t1f,R_MIPS_JALR,foo" } } */
+/* { dg-final { scan-assembler-not "\\\.reloc\t1f,R_MIPS_JALR,bar" } } */
diff --git a/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c 
b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c
new file mode 100644
index 000..9fd75c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-mabicalls -fpic -mno-mips16 -mno-micromips" } */
+/* { dg-additional-options "-fno-inline -fipa-ra -mcompact-branches=never" } */
+/* { dg-skip-if "needs codesize optimization" { *-*-* } { "-O0" "-O1" "-O2" 
"-O3" } { "" } } */
+
+static int foo (void* p) { __asm__ (""::"r"(p):"$t0"); return 0; }
+
+static int bar (void* p) { return 1; }
+
+int
+test (void* p)
+{
+  int res = !p ? foo(p) : bar(p);
+
+  register int tmp __asm__("$t0") = -1;
+  __asm__ (""::"r"(tmp));
+
+  return res;
+}
+
+/* { dg-final { scan-assembler "\\\.reloc\t1f,R_MIPS_JALR,foo" } } */
+/* { dg-final { scan-assembler "\\\.reloc\t1f,R_MIPS_JALR,bar" } } */
+/* { dg-final { scan-assembler-not "\\.set\tnomacro\n\tjalr\t\\\$25" } } */
diff --git a/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c 
b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c
new file mode 100644
index 000..580c6ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-mabicalls -fpic -mno-mips16 -mno-micromips" } */
+/* { dg-additional-options "-fno-inline -fipa-ra -mcompact-branches=never" } */
+

[RFC][PR89245] Check REG_CALL_DECL note during the tail-merging

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 

This patch prevents merging of CALL instructions that that have different
REG_CALL_DECL notes attached to them.

On most architectures this is not an important distinction. Usually instruction 
patterns
for calls to different functions reference different SYMBOL_REF-s, so they 
won't match.
On MIPS PIC calls get split into an got_load/*call_internal pair where the 
latter represents
indirect register call w/o SYMBOL_REF attached (until machine_reorg pass). The 
bugzilla issue
had such two internal_call-s merged despite the fact that they had different 
register usage
information assigned by ipa-ra.

The check could be improved by checking if ipa-ra has actually assigned two 
different
register sets for two functions involved, but I chose to only do a quick 
rtx_equal check.

gcc/ChangeLog:

2019-07-07  Dragan Mladjenovic  

* cfgcleanup.c (old_insns_match_p): Check for equal REG_CALL_DECL notes
on call instructions.

gcc/testsuite/ChangeLog:

2019-07-07  Dragan Mladjenovic  

* gcc.target/mips/cfgcleanup-jalr.c: New test.
---
 gcc/cfgcleanup.c|  9 +
 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr.c | 17 +
 2 files changed, 26 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/cfgcleanup-jalr.c

diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c
index 992912c..9903249 100644
--- a/gcc/cfgcleanup.c
+++ b/gcc/cfgcleanup.c
@@ -1224,6 +1224,15 @@ old_insns_match_p (int mode ATTRIBUTE_UNUSED, rtx_insn 
*i1, rtx_insn *i2)
}
}
}
+
+  n1 = find_reg_note (i1, REG_CALL_DECL, 0);
+  n2 = find_reg_note (i2, REG_CALL_DECL, 0);
+
+  if (!n1 && n2)
+return dir_none;
+
+  if (n1 && (!n2 || !rtx_equal_p (XEXP (n1, 0), XEXP (n2, 0
+return dir_none;
 }
 
   /* If both i1 and i2 are frame related, verify all the CFA notes
diff --git a/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr.c 
b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr.c
new file mode 100644
index 000..a4c0c47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mabicalls -fpic" } */
+
+extern void foo (void*);
+
+extern void bar (void*);
+
+void test (void* p)
+{
+   if (!p)
+   foo(p);
+   else
+   bar(p);
+}
+
+/* { dg-final { scan-assembler "\\\.reloc\t1f,R_MIPS_JALR,foo" } } */
+/* { dg-final { scan-assembler "\\\.reloc\t1f,R_MIPS_JALR,bar" } } */
-- 
1.9.1

Re: [MIPS] Fix for the wrong argument sequence in MSA builtin for FMADD/MADDV family.

[Dragan Mladjenovic]

Sorry for the late response.


I've checked the patch on gcc-9 and gcc-8 branches with mips{el}-linux-gnu.

There are no new regressions, as expected.


Is this change still eligible for back-port ?



From: Jeff Law 
Sent: Friday, May 31, 2019 11:41:35 PM
To: Dragan Mladjenovic; gcc-patches@gcc.gnu.org
Cc: Matthew Fortune
Subject: Re: [MIPS] Fix for the wrong argument sequence in MSA builtin for 
FMADD/MADDV family.

On 5/22/19 12:13 AM, Dragan Mladjenovic wrote:
> Hi all,
>
> This patch makes the behavior of __builtin_msa_ fmadd/fmsub/maddv match the
> expected one. While not a recent regression, it would be nice if this can
> be back-ported in order to minimize the fragmentation.
>
> Best regards,
>
> Dragan
>
> gcc/ChangeLog:
>
> 2019-05-20  Prachi Godbole  
> Robert Suchanek  
>
>* gcc/config/mips/mips.c (mips_expand_builtin_insn): Swap the 1st
>and 3rd operands of the fmadd/fmsub/maddv builtin.
>
> gcc/testsuite/ChangeLog:
>
> 2019-05-20  Dragan Mladjenovic  
>
>* gcc.target/mips/msa-fmadd.c: New.
THanks.  I've installed this one the trunk.

Out of an abundance of caution I have not installed it on any of the
release branches.  Feel free to ping me in a week or so and if there
haven't been any issues I'll back port it.

jeff

[MIPS] Fix for the wrong argument sequence in MSA builtin for FMADD/MADDV family.

[Dragan Mladjenovic]

Hi all,

This patch makes the behavior of __builtin_msa_ fmadd/fmsub/maddv match the
expected one. While not a recent regression, it would be nice if this can
be back-ported in order to minimize the fragmentation.

Best regards,

Dragan

gcc/ChangeLog:

2019-05-20  Prachi Godbole  
Robert Suchanek  

* gcc/config/mips/mips.c (mips_expand_builtin_insn): Swap the 1st
and 3rd operands of the fmadd/fmsub/maddv builtin.

gcc/testsuite/ChangeLog:

2019-05-20  Dragan Mladjenovic  

* gcc.target/mips/msa-fmadd.c: New.
---
 gcc/config/mips/mips.c|  13 
 gcc/testsuite/gcc.target/mips/msa-fmadd.c | 101 ++
 2 files changed, 114 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/msa-fmadd.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index bcfffbb..29335a4 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -18467,6 +18467,19 @@ mips_expand_builtin_insn (enum insn_code icode, 
unsigned int nops,
   std::swap (ops[1], ops[2]);
   break;
 
+case CODE_FOR_msa_maddv_b:
+case CODE_FOR_msa_maddv_h:
+case CODE_FOR_msa_maddv_w:
+case CODE_FOR_msa_maddv_d:
+case CODE_FOR_msa_fmadd_w:
+case CODE_FOR_msa_fmadd_d:
+case CODE_FOR_msa_fmsub_w:
+case CODE_FOR_msa_fmsub_d:
+  /* fma(a, b, c) results into (a * b + c), however builtin_msa_fmadd 
expects
+it to be (a + b * c).  Swap the 1st and 3rd operands.  */
+  std::swap (ops[1], ops[3]);
+  break;
+
 case CODE_FOR_msa_slli_b:
 case CODE_FOR_msa_slli_h:
 case CODE_FOR_msa_slli_w:
diff --git a/gcc/testsuite/gcc.target/mips/msa-fmadd.c 
b/gcc/testsuite/gcc.target/mips/msa-fmadd.c
new file mode 100644
index 000..9265c04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-fmadd.c
@@ -0,0 +1,101 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp64 -mhard-float -mmsa -EL -flax-vector-conversions" } */
+/* { dg-skip-if "uses global registers" { *-*-* } { "-O0" } { "" } } */
+
+typedef int v4i32 __attribute__ ((vector_size(16)));
+typedef float v4f32 __attribute__ ((vector_size(16)));
+typedef double v2f64 __attribute__ ((vector_size(16)));
+
+/* Test that MSA FMADD-like intrinsics do not use first operand for 
multiplication.  */
+
+register v4i32 a __asm__("$f20");
+register v4i32 b __asm__("$f22");
+register v4f32 c __asm__("$f24");
+register v4f32 d __asm__("$f26");
+register v2f64 e __asm__("$f28");
+register v2f64 f __asm__("$f30");
+
+void
+maddv_b_msa (void)
+{
+  a = __builtin_msa_maddv_b (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.b\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+maddv_h_msa (void)
+{
+  a = __builtin_msa_maddv_h (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.h\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+maddv_w_msa (void)
+{
+  a = __builtin_msa_maddv_w (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.w\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+maddv_d_msa (void)
+{
+  a = __builtin_msa_maddv_d (a, b, b);
+}
+/* { dg-final { scan-assembler "maddv\\\.d\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+msubv_b_msa (void)
+{
+  a = __builtin_msa_msubv_b (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.b\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+msubv_h_msa (void)
+{
+  a = __builtin_msa_msubv_h (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.h\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+msubv_w_msa (void)
+{
+  a = __builtin_msa_msubv_w (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.w\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+msubv_d_msa (void)
+{
+  a = __builtin_msa_msubv_d (a, b, b);
+}
+/* { dg-final { scan-assembler "msubv\\\.d\t\\\$w20,\\\$w22,\\\$w22" } }  */
+
+void
+fmadd_w_msa (void)
+{
+  c = __builtin_msa_fmadd_w (c, d, d);
+}
+/* { dg-final { scan-assembler "fmadd\\\.w\t\\\$w24,\\\$w26,\\\$w26" } }  */
+
+void
+fmadd_d_msa (void)
+{
+  e = __builtin_msa_fmadd_d (e, f, f);
+}
+/* { dg-final { scan-assembler "fmadd\\\.d\t\\\$w28,\\\$w30,\\\$w30" } }  */
+
+void
+fmsub_w_msa (void)
+{
+  c = __builtin_msa_fmsub_w (c, d, d);
+}
+/* { dg-final { scan-assembler "fmsub\\\.w\t\\\$w24,\\\$w26,\\\$w26" } }  */
+
+void
+fmsub_d_msa (void)
+{
+  e = __builtin_msa_fmsub_d (e, f, f);
+}
+/* { dg-final { scan-assembler "fmsub\\\.d\t\\\$w28,\\\$w30,\\\$w30" } }  */
+
-- 
1.9.1

Re: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with -mfpxx

[Dragan Mladjenovic]

Thank you.



From: Jeff Law 
Sent: Monday, May 20, 2019 9:13 PM
To: Dragan Mladjenovic; gcc-patches@gcc.gnu.org
Cc: Jakub Jelinek; Matthew Fortune
Subject: Re: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with 
-mfpxx

On 5/19/19 4:18 AM, Dragan Mladjenovic wrote:
> Thank you.
>
>
> What can I do to ensure this gets back-ported as further back as possible? I 
> assume that it can go all the way back to gcc 7 branch.Technically it's not a 
> regression fix, but I went ahead and backported
to gcc-9 and gcc-8 branches.  Not really planning to go further back
than that.

jeff
>

Re: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with -mfpxx

[Dragan Mladjenovic]

Thank you.


What can I do to ensure this gets back-ported as further back as possible? I 
assume that it can go all the way back to gcc 7 branch.


Best regards,

Dragan



From: Jeff Law 
Sent: Friday, May 17, 2019 6:28 PM
To: Dragan Mladjenovic; gcc-patches@gcc.gnu.org
Cc: Jakub Jelinek; Matthew Fortune
Subject: Re: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with 
-mfpxx

On 5/16/19 7:15 AM, Dragan Mladjenovic wrote:
> Ping.
>
>
> ____
> From: Dragan Mladjenovic
> Sent: Thursday, May 9, 2019 12:29 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Dragan Mladjenovic; Jakub Jelinek; Matthew Fortune
> Subject: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with 
> -mfpxx
>
> From: "Dragan Mladjenovic" 
>
>
> Hi all,
>
> For TARGET_FLOATXX the odd-numbered FP registers in SFmode are
> HARD_REGNO_CALL_PART_CLOBBERED. This causes dwarf_frame_reg_mode to fall
> back to VOIDmode and for __builtin_init_dwarf_reg_size_table to fill them
> as zero sized.
>
> This prevents libgcc's unwinder form ever restoring high parts of
> calle-saved double precision registers.
>
> This patch fixes the issue by forcing dwarf_frame_reg_mode to use SImode
> for FP registers.
>
> Bootstrapped and done regression tests on mipsel-unknown-linux-gnu -
> no new failures found.
>
>
> Best regards,
> Dragan
>
>
> gcc/ChangeLog:
>
> 2019-04-23  Dragan Mladjenovic  
>
>   * gcc/config/mips/mips.c(mips_dwarf_frame_reg_mode): Replace TARGET_FLOAT64
>   with !TARGET_FLOAT32, thus handling both fp64 and fpxx modes.
>
> gcc/testsuite/ChangeLog:
>
> 2019-04-23  Dragan Mladjenovic  
>
>   * g++.dg/eh/o32-fp.C: New.
>   * gcc.target/mips/dwarfregtable-1.c: New.
>   * gcc.target/mips/dwarfregtable-2.c: New.
>   * gcc.target/mips/dwarfregtable-3.c: New.
>   * gcc.target/mips/dwarfregtable-4.c: New.
>   * gcc.target/mips/dwarfregtable.h: New.
THanks.  I've installed this on the trunk.
jeff

Re: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with -mfpxx

[Dragan Mladjenovic]

Ping.



From: Dragan Mladjenovic
Sent: Thursday, May 9, 2019 12:29 PM
To: gcc-patches@gcc.gnu.org
Cc: Dragan Mladjenovic; Jakub Jelinek; Matthew Fortune
Subject: [PATCH] Fix __builtin_init_dwarf_reg_size_table when built with -mfpxx

From: "Dragan Mladjenovic" 


Hi all,

For TARGET_FLOATXX the odd-numbered FP registers in SFmode are
HARD_REGNO_CALL_PART_CLOBBERED. This causes dwarf_frame_reg_mode to fall
back to VOIDmode and for __builtin_init_dwarf_reg_size_table to fill them
as zero sized.

This prevents libgcc's unwinder form ever restoring high parts of
calle-saved double precision registers.

This patch fixes the issue by forcing dwarf_frame_reg_mode to use SImode
for FP registers.

Bootstrapped and done regression tests on mipsel-unknown-linux-gnu -
no new failures found.


Best regards,
Dragan


gcc/ChangeLog:

2019-04-23  Dragan Mladjenovic  

  * gcc/config/mips/mips.c(mips_dwarf_frame_reg_mode): Replace TARGET_FLOAT64
  with !TARGET_FLOAT32, thus handling both fp64 and fpxx modes.

gcc/testsuite/ChangeLog:

2019-04-23  Dragan Mladjenovic  

  * g++.dg/eh/o32-fp.C: New.
  * gcc.target/mips/dwarfregtable-1.c: New.
  * gcc.target/mips/dwarfregtable-2.c: New.
  * gcc.target/mips/dwarfregtable-3.c: New.
  * gcc.target/mips/dwarfregtable-4.c: New.
  * gcc.target/mips/dwarfregtable.h: New.

---
 gcc/config/mips/mips.c  |  2 +-
 gcc/testsuite/g++.dg/eh/o32-fp.C| 47 +
 gcc/testsuite/gcc.target/mips/dwarfregtable-1.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable-2.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable-3.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable-4.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable.h   | 22 
 7 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/g++.dg/eh/o32-fp.C
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-1.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-2.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-3.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-4.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable.h

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 1de33b2..c0c995a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9577,7 +9577,7 @@ mips_dwarf_frame_reg_mode (int regno)
 {
   machine_mode mode = default_dwarf_frame_reg_mode (regno);

-  if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64)
+  if (FP_REG_P (regno) && mips_abi == ABI_32 && !TARGET_FLOAT32)
 mode = SImode;

   return mode;
diff --git a/gcc/testsuite/g++.dg/eh/o32-fp.C b/gcc/testsuite/g++.dg/eh/o32-fp.C
new file mode 100644
index 000..08fa51b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/eh/o32-fp.C
@@ -0,0 +1,47 @@
+// Test whether call saved float are restored properly for O32 ABI
+// { dg-do run { target { { { mips*-*-linux* } && hard_float } && { ! mips64 } 
} } }
+// { dg-options "-O2" }
+
+void __attribute__((noinline))
+bar (void)
+{
+  throw 1;
+}
+
+void __attribute__((noinline))
+foo (void)
+{
+  register double f20 __asm__ ("f20") = 0.0;
+  register double f22 __asm__ ("f22") = 0.0;
+  register double f24 __asm__ ("f24") = 0.0;
+  register double f26 __asm__ ("f26") = 0.0;
+  register double f28 __asm__ ("f28") = 0.0;
+  register double f30 __asm__ ("f30") = 0.0;
+  __asm__ __volatile__("":"+f"(f20),"+f"(f22),"+f"(f24),"+f"(f26),"+f"(f30));
+  bar ();
+}
+
+int
+main (void)
+{
+  register double f20 __asm__ ("f20") = 12.0;
+  register double f22 __asm__ ("f22") = 13.0;
+  register double f24 __asm__ ("f24") = 14.0;
+  register double f26 __asm__ ("f26") = 15.0;
+  register double f28 __asm__ ("f28") = 16.0;
+  register double f30 __asm__ ("f30") = 17.0;
+
+  try
+{
+  foo ();
+}
+  catch (...)
+{
+  __asm__ ("":"+f"(f20),"+f"(f22),"+f"(f24),"+f"(f26),"+f"(f30));
+}
+
+  if (f20 != 12.0 || f22 != 13.0 || f24 != 14.0
+  || f26 != 15.0 || f28 != 16.0 || f30 != 17.0)
+__builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/mips/dwarfregtable-1.c 
b/gcc/testsuite/gcc.target/mips/dwarfregtable-1.c
new file mode 100644
index 000..93d0844
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/dwarfregtable-1.c
@@ -0,0 +1,5 @@
+/* Check if content of dwarf reg size table matches the expected.  */
+/* { dg-do run } */
+/* { dg-options "-mabi=32 -mfp32" } */
+
+#include "dwarfregtable.h"
diff --git a/gcc/testsuite/gcc.target/mips/dwarfregtable-2.c 
b/gcc/testsuite/gcc.target/mips/dwarfregtable-2.c
new file mode 100644
index 00

[PATCH] Fix __builtin_init_dwarf_reg_size_table when built with -mfpxx

[Dragan Mladjenovic]

From: "Dragan Mladjenovic" 


Hi all,

For TARGET_FLOATXX the odd-numbered FP registers in SFmode are
HARD_REGNO_CALL_PART_CLOBBERED. This causes dwarf_frame_reg_mode to fall
back to VOIDmode and for __builtin_init_dwarf_reg_size_table to fill them
as zero sized.

This prevents libgcc's unwinder form ever restoring high parts of
calle-saved double precision registers.

This patch fixes the issue by forcing dwarf_frame_reg_mode to use SImode
for FP registers.

Bootstrapped and done regression tests on mipsel-unknown-linux-gnu -
no new failures found.


Best regards,
Dragan


gcc/ChangeLog:

2019-04-23  Dragan Mladjenovic  

  * gcc/config/mips/mips.c(mips_dwarf_frame_reg_mode): Replace TARGET_FLOAT64
  with !TARGET_FLOAT32, thus handling both fp64 and fpxx modes.

gcc/testsuite/ChangeLog:

2019-04-23  Dragan Mladjenovic  

  * g++.dg/eh/o32-fp.C: New.
  * gcc.target/mips/dwarfregtable-1.c: New.
  * gcc.target/mips/dwarfregtable-2.c: New.
  * gcc.target/mips/dwarfregtable-3.c: New.
  * gcc.target/mips/dwarfregtable-4.c: New.
  * gcc.target/mips/dwarfregtable.h: New.

---
 gcc/config/mips/mips.c  |  2 +-
 gcc/testsuite/g++.dg/eh/o32-fp.C| 47 +
 gcc/testsuite/gcc.target/mips/dwarfregtable-1.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable-2.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable-3.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable-4.c |  5 +++
 gcc/testsuite/gcc.target/mips/dwarfregtable.h   | 22 
 7 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/g++.dg/eh/o32-fp.C
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-1.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-2.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-3.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable-4.c
 create mode 100644 gcc/testsuite/gcc.target/mips/dwarfregtable.h

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 1de33b2..c0c995a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9577,7 +9577,7 @@ mips_dwarf_frame_reg_mode (int regno)
 {
   machine_mode mode = default_dwarf_frame_reg_mode (regno);
 
-  if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64)
+  if (FP_REG_P (regno) && mips_abi == ABI_32 && !TARGET_FLOAT32)
 mode = SImode;
 
   return mode;
diff --git a/gcc/testsuite/g++.dg/eh/o32-fp.C b/gcc/testsuite/g++.dg/eh/o32-fp.C
new file mode 100644
index 000..08fa51b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/eh/o32-fp.C
@@ -0,0 +1,47 @@
+// Test whether call saved float are restored properly for O32 ABI
+// { dg-do run { target { { { mips*-*-linux* } && hard_float } && { ! mips64 } 
} } }
+// { dg-options "-O2" }
+
+void __attribute__((noinline))
+bar (void)
+{
+  throw 1;
+}
+
+void __attribute__((noinline))
+foo (void)
+{
+  register double f20 __asm__ ("f20") = 0.0;
+  register double f22 __asm__ ("f22") = 0.0;
+  register double f24 __asm__ ("f24") = 0.0;
+  register double f26 __asm__ ("f26") = 0.0;
+  register double f28 __asm__ ("f28") = 0.0;
+  register double f30 __asm__ ("f30") = 0.0;
+  __asm__ __volatile__("":"+f"(f20),"+f"(f22),"+f"(f24),"+f"(f26),"+f"(f30));
+  bar ();
+}
+
+int
+main (void)
+{
+  register double f20 __asm__ ("f20") = 12.0;
+  register double f22 __asm__ ("f22") = 13.0;
+  register double f24 __asm__ ("f24") = 14.0;
+  register double f26 __asm__ ("f26") = 15.0;
+  register double f28 __asm__ ("f28") = 16.0;
+  register double f30 __asm__ ("f30") = 17.0;
+
+  try
+{
+  foo ();
+}
+  catch (...)
+{
+  __asm__ ("":"+f"(f20),"+f"(f22),"+f"(f24),"+f"(f26),"+f"(f30));
+}
+
+  if (f20 != 12.0 || f22 != 13.0 || f24 != 14.0
+  || f26 != 15.0 || f28 != 16.0 || f30 != 17.0)
+__builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/mips/dwarfregtable-1.c 
b/gcc/testsuite/gcc.target/mips/dwarfregtable-1.c
new file mode 100644
index 000..93d0844
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/dwarfregtable-1.c
@@ -0,0 +1,5 @@
+/* Check if content of dwarf reg size table matches the expected.  */
+/* { dg-do run } */
+/* { dg-options "-mabi=32 -mfp32" } */
+
+#include "dwarfregtable.h"
diff --git a/gcc/testsuite/gcc.target/mips/dwarfregtable-2.c 
b/gcc/testsuite/gcc.target/mips/dwarfregtable-2.c
new file mode 100644
index 000..c6dea94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/dwarfregtable-2.c
@@ -0,0 +1,5 @@
+/* Check if content of dwarf reg size table matches the expected.  */
+/* { dg-do run } */
+/* { dg-options "-mabi=32 -mfpxx" } */
+
+#include "dwarfregtable.