RE: [PATCH] Set default to -fomit-frame-pointer
Andreas Schwab wrote: >> Joseph Myers wrote: >>> On Fri, 3 Nov 2017, Wilco Dijkstra wrote: >>> >>> > Almost all targets add an explict -fomit-frame-pointer in the target >>> > specific >>> > options. Rather than doing this in a target-specific way, do this in the >>> >>> Which targets do not? You should explicitly list them and CC their >>> maintainers and seek confirmation that such a change is appropriate for >>> them. >> >> The targets that don't explicitly enable -fomit-frame-pointer in the target >> options or force it internally are bfin, ft32, h8300, m68k - I've CCd the >> maintainers (it seems there is no-one for h8300). > >For m68k, adding -fomit-frame-pointer by default is ok. For ft32, adding -fomit-frame-pointer by default is ok. James.
[patch committed FT32] Add FT32B support
FT32B is a new FT32 architecture type. Ft32B has a code compression
scheme which uses linker relaxations. It also has a security option to
prevent reads from program memory.
[gcc]
2017-11-02 James Bowman <james.bow...@ftdichip.com>
* config/ft32/ft32.c (ft32_addr_space_legitimate_address_p): increase
offset range for FT32B.
* config/ft32/ft32.h: option "mcompress" enables relaxation.
* config/ft32/ft32.md: Add TARGET_NOPM.
* config/ft32/ft32.opt: Add mft32b, mcompress, mnopm.
* gcc/doc/invoke.texi: Add mft32b, mcompress, mnopm.
Index: gcc/config/ft32/ft32.c
===
--- gcc/config/ft32/ft32.c (revision 254348)
+++ gcc/config/ft32/ft32.c (working copy)
@@ -866,6 +866,8 @@
ft32_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
addr_space_t as ATTRIBUTE_UNUSED)
{
+ int max_offset = TARGET_FT32B ? 16384 : 128;
+
if (mode != BLKmode)
{
if (GET_CODE (x) == PLUS)
@@ -875,8 +877,9 @@
op2 = XEXP (x, 1);
if (GET_CODE (op1) == REG
&& CONST_INT_P (op2)
- && INTVAL (op2) >= -128
- && INTVAL (op2) < 128 && reg_ok_for_base_p (op1, strict))
+ && (-max_offset <= INTVAL (op2))
+ && (INTVAL (op2) < max_offset)
+ && reg_ok_for_base_p (op1, strict))
goto yes;
if (GET_CODE (op1) == SYMBOL_REF && CONST_INT_P (op2))
goto yes;
Index: gcc/config/ft32/ft32.h
===
--- gcc/config/ft32/ft32.h (revision 254348)
+++ gcc/config/ft32/ft32.h (working copy)
@@ -39,6 +39,7 @@
#undef LIB_SPEC
#define LIB_SPEC "%{!shared:%{!symbolic:-lc}} \
+ %{mcompress:--relax} \
%{msim:-Tsim.ld}"
#undef LINK_SPEC
@@ -199,12 +200,12 @@
#define GLOBAL_ASM_OP "\t.global\t"
-#define JUMP_TABLES_IN_TEXT_SECTION 1
+#define JUMP_TABLES_IN_TEXT_SECTION (TARGET_NOPM ? 0 : 1)
/* This is how to output an element of a case-vector that is absolute. */
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-fprintf (FILE, "\tjmp\t.L%d\n", VALUE);\
+fprintf (FILE, "\t.long\t.L%d\n", VALUE); \
/* Passing Arguments in Registers */
@@ -469,7 +470,7 @@
#define ADDR_SPACE_PM 1
#define REGISTER_TARGET_PRAGMAS() do { \
- c_register_addr_space ("__flash__", ADDR_SPACE_PM); \
+ c_register_addr_space ("__flash__", TARGET_NOPM ? 0 : ADDR_SPACE_PM); \
} while (0);
extern int ft32_is_mem_pm(rtx o);
Index: gcc/config/ft32/ft32.md
===
--- gcc/config/ft32/ft32.md (revision 254348)
+++ gcc/config/ft32/ft32.md (working copy)
@@ -777,8 +777,12 @@
(clobber (match_scratch:SI 2 "="))
]
""
- "ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;jmpi\t%2"
- )
+ {
+if (TARGET_NOPM)
+ return
\"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;ldi.l\t%2,%2,0\;jmpi\t%2\";
+else
+ return
\"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;lpmi.l\t%2,%2,0\;jmpi\t%2\";
+ })
;; -
;; Atomic exchange instruction
Index: gcc/config/ft32/ft32.opt
===
--- gcc/config/ft32/ft32.opt(revision 254348)
+++ gcc/config/ft32/ft32.opt(working copy)
@@ -29,3 +29,15 @@
mnodiv
Target Report Mask(NODIV)
Avoid use of the DIV and MOD instructions
+
+mft32b
+Target Report Mask(FT32B)
+target the FT32B architecture
+
+mcompress
+Target Report Mask(COMPRESS)
+enable FT32B code compression
+
+mnopm
+Target Report Mask(NOPM)
+Avoid placing any readable data in program memory
Index: gcc/doc/invoke.texi
===
--- gcc/doc/invoke.texi (revision 254348)
+++ gcc/doc/invoke.texi (working copy)
@@ -743,7 +743,7 @@
@gccoptlist{-msmall-model -mno-lsim}
@emph{FT32 Options}
-@gccoptlist{-msim -mlra -mnodiv}
+@gccoptlist{-msim -mlra -mnodiv -mft32b -mcompress -mnopm}
@emph{FRV Options}
@gccoptlist{-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 @gol
@@ -17768,6 +17768,18 @@
@opindex mnodiv
Do not use div and mod instructions.
+@item -mft32b
+@opindex mft32b
+Enable use of the extended instructions of the FT32B processor.
+
+@item -mcompress
+@opindex mcompress
+Compress all code using the Ft32B code compression scheme.
+
+@item -mnopm
+@opindex mnopm
+Do not generate code that reads program memory.
+
@end table
@node FRV Options
[patch committed FT32] Add watchdog vector and FT930 support
The attached patch adds a watchdog reset vector and FT930 support to the base interrupt code. [libgcc] 2017-09-28 James Bowman <james.bow...@ftdichip.com> * config/ft32/crti-hw.S: Add watchdog vector, FT930 IRQ support. Index: libgcc/config/ft32/crti-hw.S === --- libgcc/config/ft32/crti-hw.S(revision 253084) +++ libgcc/config/ft32/crti-hw.S(working copy) @@ -1,8 +1,8 @@ .global _start _start: # START Interrupt Vector Table [[ -jmp __PMSIZE-4 -jmp watchdog_init +jmp __PMSIZE-4 # RESET Vector +jmp interrupt_33 # Watchdog reset vector jmp interrupt_0 jmp interrupt_1 jmp interrupt_2 @@ -35,24 +35,29 @@ jmp interrupt_29 jmp interrupt_30 jmp interrupt_31 -jmp __PMSIZE-8 +jmp __PMSIZE-8 # Interrupt vector 32 (NMI) # ]] END Interrupt Vector Table codestart: jmpinit - + .global _exithook _exithook: # Debugger uses '_exithook' at 0x90 to catch program exit return - -watchdog_init: -ldk$r0,1 + init: ldk $sp,__RAMSIZE # Disable all interrupts -ldk $r4,0x80 -sta.b 0x100e3,$r4 - +lda $r1,0x1 +lshr $r1,$r1,20 +cmp $r1,0x90 +ldk $r1,0x100e3 # FT900 IRQ Control Register +jmpc z,1f +ldk $r1,0x10123 # FT930 IRQ Control Register +1: +ldk $r4,0x80 +sti.b $r1,0,$r4 + # Initialize DATA by copying from program memory ldk.l $r4,__data_load_start ldk.l $r1,__data_load_end @@ -139,6 +144,7 @@ inth30 inth31 inth32 +inth33 # On entry: r0, already saved, holds the handler function interrupt_common: @@ -182,7 +188,7 @@ .section .data .global vector_table vector_table: -.rept 33 +.rept 34 .long nullvector .endr
[PATCH FT32]: apply unbias to references to RAM symbols
The FT32 binutils use a bias to distinguish between RAM and flash
addresses.
This fix adds an ASM_OUTPUT_SYMBOL_REF() that unbiases references to
RAM symbols.
Only references to RAM objects have the bias applied. Flash objects
(that is, objects in ADDR SPACE 1) are not biased, so for these no bias
should be applied. Likewise references in the gdb section need to use
the biased address, so references in debug sections are not unbiased.
gcc/ChangeLog:
2016-07-08 James Bowman <james.bow...@ftdichip.com>
* config/ft32/ft32.c (ft32_elf_encode_section_info): New function.
* config/ft32/ft32.h (ASM_OUTPUT_SYMBOL_REF): New function.
Index: gcc/config/ft32/ft32.c
===
--- gcc/config/ft32/ft32.c (revision 237998)
+++ gcc/config/ft32/ft32.c (working copy)
@@ -35,6 +35,7 @@
#include "calls.h"
#include "expr.h"
#include "builtins.h"
+#include "print-tree.h"
/* This file should be included last. */
#include "target-def.h"
@@ -895,6 +896,46 @@ yes:
return 1;
}
+#undef TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO ft32_elf_encode_section_info
+
+void
+ft32_elf_encode_section_info (tree decl, rtx rtl, int first)
+{
+ enum tree_code code;
+ rtx symbol;
+
+ /* Careful not to prod global register variables. */
+ if (!MEM_P (rtl))
+return;
+ symbol = XEXP (rtl, 0);
+ if (GET_CODE (symbol) != SYMBOL_REF)
+return;
+
+ default_encode_section_info (decl, rtl, first);
+
+ code = TREE_CODE (decl);
+ switch (TREE_CODE_CLASS (code))
+{
+case tcc_declaration:
+ {
+ tree type = TREE_TYPE (decl);
+ int is_flash = (type && TYPE_P (type) && !ADDR_SPACE_GENERIC_P
(TYPE_ADDR_SPACE (type)));
+ if ((code == VAR_DECL) && !is_flash)
+ SYMBOL_REF_FLAGS (symbol) |= 0x1000;
+ }
+ break;
+case tcc_constant:
+case tcc_exceptional:
+ if (code == STRING_CST)
+ SYMBOL_REF_FLAGS (symbol) |= 0x1000;
+}
+
+ // debug_tree (decl);
+ // debug_rtx (rtl);
+ // printf("\n");
+}
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-ft32.h"
Index: gcc/config/ft32/ft32.h
===
--- gcc/config/ft32/ft32.h (revision 237998)
+++ gcc/config/ft32/ft32.h (working copy)
@@ -506,4 +506,14 @@ do { \
extern int ft32_is_mem_pm(rtx o);
+#define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
+ do { \
+assemble_name (stream, XSTR (sym, 0)); \
+int section_debug = in_section && \
+ (SECTION_STYLE (in_section) == SECTION_NAMED) && \
+ (in_section->named.common.flags & SECTION_DEBUG); \
+if (!section_debug && SYMBOL_REF_FLAGS (sym) & 0x1000) \
+ asm_fprintf (stream, "-0x80"); \
+ } while (0)
+
#endif /* GCC_FT32_H */
[patch] Fix DWARF type output for non-default address spaces
FT32 makes use of multiple address spaces. When trying to inspect objects in GDB, GDB was treating them as a straight "const". The cause seems to be in GCC DWARF2 output. This output is handled in gcc/gcc/dwarf2out.c, where modified_type_die() checks that TYPE has qualifiers CV_QUALS. However while TYPE has ADDR_SPACE qualifiers, the modified_type_die() explicitly discards the ADDR_SPACE qualifiers. This patch retains the ADDR_SPACE qualifiers as modified_type_die() outputs the DWARF type tree. This allows the types to match, and correct type information for the object is emitted. OK to commit? [gcc] 2016-07-07 James Bowman <james.bow...@ftdichip.com> * gcc/dwarf2out.c (modified_type_die): Retain ADDR_SPACE qualifiers. (add_type_attribute) likewise. Index: gcc/dwarf2out.c === --- gcc/dwarf2out.c (revision 237998) +++ gcc/dwarf2out.c (working copy) @@ -11222,7 +11222,8 @@ modified_type_die (tree type, int cv_qua dw_die_ref mod_scope; /* Only these cv-qualifiers are currently handled. */ const int cv_qual_mask = (TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE - | TYPE_QUAL_RESTRICT | TYPE_QUAL_ATOMIC); + | TYPE_QUAL_RESTRICT | TYPE_QUAL_ATOMIC | + ENCODE_QUAL_ADDR_SPACE(~0U)); if (code == ERROR_MARK) return NULL; @@ -19027,7 +19028,7 @@ add_type_attribute (dw_die_ref object_di return; type_die = modified_type_die (type, - cv_quals | TYPE_QUALS_NO_ADDR_SPACE (type), + cv_quals | TYPE_QUALS (type), reverse, context_die);
[patch committed FT32] use setup_incoming_varargs
The FT32 target now uses SETUP_INCOMING_VARARGS to handle varargs.
This saves 24 byte per stack frame, because the caller no longer needs to
allocate space on the stack for r0-r5 in the event of a varargs caller.
* config/ft32/ft32.c (ft32_setup_incoming_varargs,
ft32_expand_prolog, ft32_expand_epilogue):
Handle pretend_args.
* config/ft32/ft32.h: Remove OUTGOING_REG_PARM_STACK_SPACE.
* config/ft32/ft32.md: Add pretend_returner.
Index: gcc/config/ft32/ft32.h
===
--- gcc/config/ft32/ft32.h (revision 237115)
+++ gcc/config/ft32/ft32.h (working copy)
@@ -256,15 +256,6 @@ enum reg_class
be allocated. */
#define STARTING_FRAME_OFFSET 0
-/* Define this if the above stack space is to be considered part of the
- space allocated by the caller. */
-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
-/* #define STACK_PARMS_IN_REG_PARM_AREA */
-
-/* Define this if it is the responsibility of the caller to allocate
- the area reserved for arguments passed in registers. */
-#define REG_PARM_STACK_SPACE(FNDECL) (6 * UNITS_PER_WORD)
-
/* Offset from the argument pointer register to the first argument's
address. On some machines it may depend on the data type of the
function. */
Index: gcc/config/ft32/ft32.md
===
--- gcc/config/ft32/ft32.md (revision 237115)
+++ gcc/config/ft32/ft32.md (working copy)
@@ -929,6 +929,14 @@
"reload_completed"
"return")
+(define_insn "pretend_returner"
+ [(set (reg:SI SP_REG)
+(plus:SI (reg:SI SP_REG)
+ (match_operand:SI 0)))
+ (return)]
+ "reload_completed"
+ "pop.l $cc\;add.l $sp,$sp,%0\;jmpi $cc")
+
(define_insn "returner24"
[
(set (reg:SI SP_REG)
Index: gcc/config/ft32/ft32.c
===
--- gcc/config/ft32/ft32.c (revision 237115)
+++ gcc/config/ft32/ft32.c (working copy)
@@ -409,7 +409,7 @@ ft32_compute_frame (void)
cfun->machine->callee_saved_reg_size += 4;
cfun->machine->size_for_adjusting_sp =
-crtl->args.pretend_args_size
+0 // crtl->args.pretend_args_size
+ cfun->machine->local_vars_size
+ (ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
}
@@ -434,15 +434,32 @@ ft32_expand_prologue (void)
ft32_compute_frame ();
+ int args_to_push = crtl->args.pretend_args_size;
+ if (args_to_push)
+{
+ int i;
+
+ insn = emit_insn (gen_movsi_pop ((gen_rtx_REG (Pmode, FT32_R29;
+
+ for (i = 0; i < (args_to_push / 4); i++)
+ {
+ insn =
+ emit_insn (gen_movsi_push ((gen_rtx_REG (Pmode, FT32_R5 - i;
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+
+ insn = emit_insn (gen_movsi_push ((gen_rtx_REG (Pmode, FT32_R29;
+}
+
if (flag_stack_usage_info)
current_function_static_stack_size = cfun->machine->size_for_adjusting_sp;
if (!must_link () && (cfun->machine->callee_saved_reg_size == 4))
{
insn =
-emit_insn (gen_link
- (gen_rtx_REG (Pmode, FT32_R13),
-GEN_INT (-cfun->machine->size_for_adjusting_sp)));
+ emit_insn (gen_link
+ (gen_rtx_REG (Pmode, FT32_R13),
+ GEN_INT (-cfun->machine->size_for_adjusting_sp)));
RTX_FRAME_RELATED_P (insn) = 1;
return;
}
@@ -450,27 +467,27 @@ ft32_expand_prologue (void)
if (optimize_size)
{
for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0;)
-{
- if (!fixed_regs[regno] && !call_used_regs[regno]
- && df_regs_ever_live_p (regno))
-{
- rtx preg = gen_rtx_REG (Pmode, regno);
- emit_insn (gen_call_prolog (preg));
- break;
-}
-}
+ {
+ if (!fixed_regs[regno] && !call_used_regs[regno]
+ && df_regs_ever_live_p (regno))
+ {
+ rtx preg = gen_rtx_REG (Pmode, regno);
+ emit_insn (gen_call_prolog (preg));
+ break;
+ }
+ }
}
else
{
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-{
- if (!fixed_regs[regno] && df_regs_ever_live_p (regno)
- && !call_used_regs[regno])
-{
- insn = emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, regno)));
- RTX_FRAME_RELATED_P (insn) = 1;
-}
-}
+ {
+ if (!fixed_regs[regno] && df_regs_ever_live_p (regno)
+ && !call_used_regs[regno])
+ {
+ insn = emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, regno)));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ }
}
if (65536 <= cfun->machine->size_for_adjusting_sp)
@@ -481,17 +498,17 @@ ft32_expand_prologue (void)
if (must_link ())
{
insn =
-emit_insn
[patch commited FT32] Add -nodiv option
The attached patches add an "-mnodiv" option to FT32, preventing use of the divide and modulo instructions. This required additional software div/mod implemtations in FT32's libgcc. 2016-03-28 James Bowman <james.bow...@ftdichip.com> * config/ft32/ft32.opt (mnodiv): New. * config/ft32/ft32.md (*divsi3, *modsi3): Qualify with TARGET_NODIV. * doc/invoke.texi (FT32 Options -mnodiv): New. 2016-03-28 James Bowman <james.bow...@ftdichip.com> * libgcc/config/ft32/lib1funcs.S (*divsi3, *modsi3): New. Index: gcc/config/ft32/ft32.md === --- gcc/config/ft32/ft32.md (revision 234405) +++ gcc/config/ft32/ft32.md (working copy) @@ -101,7 +101,7 @@ (div:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))] - "" + "!TARGET_NODIV" "div.l %0,%1,%2") (define_insn "modsi3" @@ -109,7 +109,7 @@ (mod:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))] - "" + "!TARGET_NODIV" "mod.l %0,%1,%2") (define_insn "udivsi3" @@ -117,7 +117,7 @@ (udiv:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))] - "" + "!TARGET_NODIV" "udiv.l %0,%1,%2") (define_insn "umodsi3" @@ -125,7 +125,7 @@ (umod:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "register_operand" "r,KA")))] - "" + "!TARGET_NODIV" "umod.l %0,%1,%2") (define_insn "extvsi" Index: gcc/config/ft32/ft32.opt === --- gcc/config/ft32/ft32.opt(revision 234405) +++ gcc/config/ft32/ft32.opt(working copy) @@ -25,3 +25,7 @@ target the software simulator. mlra Target Report Var(ft32_lra_flag) Init(0) Save Use LRA instead of reload. + +mnodiv +Target Report Mask(NODIV) +Avoid use of the DIV and MOD instructions Index: libgcc/config/ft32/lib1funcs.S === --- libgcc/config/ft32/lib1funcs.S (revision 234405) +++ libgcc/config/ft32/lib1funcs.S (working copy) @@ -25,8 +25,8 @@ see the files COPYING3 and COPYING.RUNTI # for implementation details of all except division which is detailed below # +#ifdef L_fp_tools // .global __cmpsf2_ - nan:.long 0x7FFF# also abs mask inf:.long 0x7F80 sign_mask: .long 0x8000 @@ -37,6 +37,14 @@ smallest_norm: .long 0x0080# im high_FF:.long 0xFF00 high_uint: .long 0x +ntz_table: +.byte 32,0,1,12,2,6,0,13,3,0,7,0,0,0,0,14 +.byte 10,4,0,0,8,0,0,25,0,0,0,0,0,21,27,15 +.byte 31,11,5,0,0,0,0,0,9,0,0,24,0,0,20,26 +.byte 30,0,0,0,0,23,0,19,29,0,22,18,28,17,16,0 + +#endif + # Supply a few 'missing' instructions # not @@ -87,12 +95,6 @@ high_uint: .long 0x lpmi.b \x, \x, 0 .endm -ntz_table: -.byte 32,0,1,12,2,6,0,13,3,0,7,0,0,0,0,14 -.byte 10,4,0,0,8,0,0,25,0,0,0,0,0,21,27,15 -.byte 31,11,5,0,0,0,0,0,9,0,0,24,0,0,20,26 -.byte 30,0,0,0,0,23,0,19,29,0,22,18,28,17,16,0 - # calculate leading zero count .macro nlz x, scr flip\x, \x, 31 @@ -503,6 +505,9 @@ mul_z0: ## for implementation details + + +#ifdef L_divsf3 dc_1: .long 0xe7d7 dc_2: .long 0xffe8 dc_3: .long 0xffbad86f @@ -517,9 +522,6 @@ dc_11: .long0x0452b1bf dc_12: .long0xFFC0 spec_val_test: .long 0x7F7F - - -#ifdef L_divsf3 .global __divsf3 __divsf3: push$r13 @@ -869,6 +871,7 @@ float_not_zero2: return #endif +#if 0 ## ## ## float compare @@ -913,7 +916,74 @@ cmp_is_gt: cmp_is_eq: ldk $r0, 0 return +#endif +#ifdef L_udivsi3 +.global __udivsi3 +__udivsi3: + # $r0 is dividend + # $r1 is divisor + ldk $r2,0 + push$r28 + ldk $r28,-32 +0: + lshr$r3,$r0,31 # Shift $r2:$r0 left one + ashl$r0,$r0,1 + ashl$r2,$r2,1 + or $r2,$r2,$r3 + cmp $r2,$r1 + jmpcb,1f +2: + sub $r2,$r2,$r1 + add $r0,$r0,1 +1: + add $r28,$r28,1 + jmpx31,$r28,1,0b + pop $r28 + # $r0: quotient + # $r2: remainder
[patch committed FT32] Pattern for CC to register move
The attached patch adds a pattern for CC to register move. [gcc] 2015-11-11 James Bowman <james.bow...@ftdichip.com> * config/ft32/ft32.md: New pattern *sne Index: gcc/config/ft32/ft32.md === --- gcc/config/ft32/ft32.md (revision 230144) +++ gcc/config/ft32/ft32.md (working copy) @@ -255,6 +255,13 @@ ;; SImode +(define_insn "*sne" + [(set (match_operand:SI 0 "register_operand" "=r") + (reg:SI CC_REG))] + "" + "bextu.l %0,$cc,32|0\;xor.l %0,%0,-1" +) + ;; Push a register onto the stack (define_insn "movsi_push" [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) @@ -884,6 +891,7 @@ DONE; }) + (define_expand "epilogue" [(return)] ""
[patch committed FT32] Limit MEMSET, MEMCPY to <512 bytes
The attached patch limits the MEMSET (setmemsi pattern) and MEMCPY (movmemsi pattern) instructions to 0-511 bytes. There is a hardware limitation on large MEMSET, MEMCPY operations that the library versions of memset() and memcpy() deal with. [gcc] 2015-09-29 James Bowman <james.bow...@ftdichip.com> * config/ft32/predicates.md (ft32_imm_operand): New predicate. * config/ft32/ft32.md (movmemsi, setmemsi): Use ft32_imm_operand predicate, disallow register for operand 2. Index: gcc/config/ft32/ft32.md === --- gcc/config/ft32/ft32.md (revision 228109) +++ gcc/config/ft32/ft32.md (working copy) @@ -841,19 +841,19 @@ ) (define_insn "movmemsi" - [(set (match_operand:BLK 0 "memory_operand" "=W,W,BW") -(match_operand:BLK 1 "memory_operand" "W,W,BW")) -(use (match_operand:SI 2 "ft32_rimm_operand" "r,KA,rKA")) + [(set (match_operand:BLK 0 "memory_operand" "=W,BW") +(match_operand:BLK 1 "memory_operand" "W,BW")) +(use (match_operand:SI 2 "ft32_imm_operand" "KA,KA")) (use (match_operand:SI 3)) ] "" - "memcpy.%d3 %b0,%b1,%2 # %3!" + "memcpy.%d3 %b0,%b1,%2 " ) (define_insn "setmemsi" - [(set (match_operand:BLK 0 "memory_operand" "=BW,BW") (unspec:BLK [ - (use (match_operand:QI 2 "register_operand" "r,r")) - (use (match_operand:SI 1 "ft32_rimm_operand" "r,KA")) + [(set (match_operand:BLK 0 "memory_operand" "=BW") (unspec:BLK [ + (use (match_operand:QI 2 "register_operand" "r")) + (use (match_operand:SI 1 "ft32_imm_operand" "KA")) ] UNSPEC_SETMEM)) (use (match_operand:SI 3)) ] Index: gcc/config/ft32/predicates.md === --- gcc/config/ft32/predicates.md (revision 228109) +++ gcc/config/ft32/predicates.md (working copy) @@ -80,6 +80,10 @@ (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), -512, 511)" +(define_predicate "ft32_imm_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -512, 511)"))) + (define_predicate "ft32_bwidth_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
[patch committed FT32] Fixes for hardware startup
The attached patch contains several fixes for the default hardware startup. [libgcc] 2015-09-21 James Bowman <james.bow...@ftdichip.com> * config/ft32/crti-hw.S: Use __PMSIZE to allow configurable memory layout. Deal correctly with BSS region larger than 32K. Handle a watchdog reset like a power-on reset. Clean up unused code. Index: libgcc/config/ft32/crti-hw.S === --- libgcc/config/ft32/crti-hw.S(revision 227841) +++ libgcc/config/ft32/crti-hw.S(working copy) @@ -1,11 +1,8 @@ -.equ SYS_REGMSC0CFG_B3 , 0x1001b -.equ SYS_REGIRQCTL_B3 , 0x100e3 - .global _start _start: # START Interrupt Vector Table [[ -jmp 0x3fffc # RESET Vector -jmp _watchdog_isr # WATCHDOG Vector # TODO: Change me to reset the chip proper +jmp __PMSIZE-4 +jmp watchdog_init jmp interrupt_0 jmp interrupt_1 jmp interrupt_2 @@ -38,64 +35,66 @@ _start: jmp interrupt_29 jmp interrupt_30 jmp interrupt_31 -jmp 0x3fff8 +jmp __PMSIZE-8 # ]] END Interrupt Vector Table codestart: jmpinit - .global _exithook _exithook: # Debugger uses '_exithook' at 0x90 to catch program exit return +watchdog_init: +ldk$r0,1 init: +ldk $sp,__RAMSIZE # Disable all interrupts -ldk $r0,0x80 -sta.b 0x100e3,$r0 - -# Reset all peripherals -# lda.l $r0, 0x10018 -# bins.l $r0, $r0, 0x23F # Set bit 31 -# sta.l 0x10018, $r0 +ldk $r4,0x80 +sta.b 0x100e3,$r4 # Initialize DATA by copying from program memory -ldk.l $r0,__data_load_start +ldk.l $r4,__data_load_start ldk.l $r1,__data_load_end ldk.l $r2,0 # Will use __data after binutils patch jmp .dscopy .dsloop: -# Copy PM[$r0] to RAM $r2 -lpmi.l $r3,$r0,0 +# Copy PM[$r4] to RAM $r2 +lpmi.l $r3,$r4,0 sti.l $r2,0,$r3 -add.l $r0,$r0,4 +add.l $r4,$r4,4 add.l $r2,$r2,4 .dscopy: -cmp.l $r0,$r1 +cmp.l $r4,$r1 jmpclt,.dsloop # Zero BSS -ldk.l $r0,_bss_start +ldk.l $r4,_bss_start ldk.l $r2,_end -sub.l $r2,$r2,$r0 +sub.l $r2,$r2,$r4 ldk.l $r1,0 -memset.l $r0,$r1,$r2 +ldk$r3,32764 +1: +cmp$r2,$r3 +jmpc lt,2f +memset $r4,$r1,$r3 +add$r4,$r4,$r3 +sub$r2,$r2,$r3 +jmp1b +2: +memset $r4,$r1,$r2 sub.l $sp,$sp,24 # Space for the caller argument frame callmain -.equ EXITEXIT, 0x1fffc +.equ EXITEXIT,0x1fffc .global _exit _exit: sta.l EXITEXIT,$r0# simulator end of test jmp _exithook -_watchdog_isr: -ldk.l $sp, 0x80 # Reset the stack pointer so it doesn't grow to a huge size -jmp 0 - # Macro to construct the interrupt stub code. # it just saves r0, loads r0 with the int vector # and branches to interrupt_common.
[patch committed FT32] Fix address space predicate
The attached patch fixes the FT32's memory address space predicate.
[gcc]
2015-09-16 James Bowman <james.bow...@ftdichip.com>
* config/ft32/ft32.c Fix the memory address space predicate.
Index: gcc/config/ft32/ft32.c
===
--- gcc/config/ft32/ft32.c (revision 227840)
+++ gcc/config/ft32/ft32.c (working copy)
@@ -745,12 +745,8 @@ ft32_arg_partial_bytes (cumulative_args_
int
ft32_is_mem_pm (rtx o)
{
- if (GET_CODE (o) != MEM)
-return false;
- if (MEM_EXPR (o))
-return TYPE_ADDR_SPACE (TREE_TYPE (MEM_EXPR (o))) == ADDR_SPACE_PM;
- else
-return MEM_ADDR_SPACE (o) == ADDR_SPACE_PM;
+ return (MEM_P (o)
+ && !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (o)));
}
/* The Global `targetm' Variable. */
RE: [PATCH, FT32] initial support
On Thu, May 14, 2015 at 07:54:02AM -0500, Segher Boessenkool wrote: I cannot reproduce this with your testcase. Please post the *exact* testcase (nothing snipped) and the command line you used? Making the array volatile and using optimisation helped. Kaboom. It wants to reload pretty much everything. Looking at your code, it seems you use the ancient interfaces instead of TARGET_LEGITIMATE_ADDRESS_P, I don't think LRA works with that? The FT32 target uses TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P (ft32.c line 856). The FT32 itself is a Harvard architecture, and the ft32 port uses address spaces to distinguish between program and data memory. Of the ports that currently support LRA (arc, mips, rs6000, s380, sh) none use address spaces. Perhaps this port's use of address spaces is causing the problem? -- James Bowman FTDI Open Source Liaison
RE: [PATCH, FT32] initial support
On 05/14/2015 01:24 PM, Segher Boessenkool wrote: On Thu, May 14, 2015 at 12:31:40PM -0600, Jeff Law wrote: On 05/14/2015 11:36 AM, Segher Boessenkool wrote: The alternative that allows move to mem is alt 1, but it thinks the operand doesn't match (it is B or W), it picks alt 0, loop, everyone unhappy. B should match it seems? (Why does IRA think r56 should be in memory? Yeah, good question.) Independent of that, if a reg-reg move generated by LRA (which is really a mem-reg or reg-mem) blows up on this target for some reason, then that needs to be addressed independently of whether or not IRA might have made a bad choice for which pseudo to spill. Yes. It probably is because of the volatile I inserted for it to fail at all, anyway. Changing constraints ABWef to be define_memory_constraint (instead of define_constraint) makes this testcase pass. It also makes the build pass (it failed before; 90 reloads in libgcc). Pretty miserable code for those memory accesses, but hey, better than an ICE ;-) Makes sense if it wasn't defined as a memory constraint that LRA would be having trouble -- odds are reload would have barf'd at some point too. The only difference is I'm actually still better at understanding what reload's doing from its dumps than LRA. It's hard to throw away decades of retained knowledge earned the hard way. James, can you go ahead and make that change to ABWef and enable LRA and commit your changes to the trunk? OK, ABWef changes made, and fixed a couple of pattern holes that they exposed. Added a new target option -mlra to enable LRA. Updated invoking.texi. Please can someone commit this, if appropriate, as I do not have write access to the tree. Thanks very much. ChangeLog entry: 2015-05-14 James Bowman james.bow...@ftdichip.com * configure.ac: FT32 target added * libgcc/config.host: FT32 target added * gcc/config/ft32/: FT32 target added * libgcc/config/ft32/: FT32 target added * gcc/doc/install.texi, invoke.texi, md.texi: FT32 details added * gcc/doc/contrib.texi: self added * contrib/config-list.mk: FT32 target added * configure: Regenerated -- James Bowman FTDI Open Source Liaison gcc-ft32.txt.gz Description: gcc-ft32.txt.gz
RE: [PATCH, FT32] initial support
On Tue, May 12, 2015 at 10:17:01PM +, James Bowman wrote:
It seems that with whenever a function's frame is bigger than 512 bytes,
LRA loops. Likely this causes a problem because there is no actual
instruction for subtracting constants more than 512. However, there is a
link pattern that allows this. It is puzzling.
That link pattern does
(minus (reg) (imm))
but that is not canonical RTL; it should be written
(plus (reg) (-imm))
OK, thanks. I have corrected this. Seeing the same failure with LRA.
Compile with -da to get dump files, look at the .reload one (which is
for LRA if that is enabled), stare long and hard. I recommend coffee.
OK! Looking more at this, the LRA is not actually looping on the link, but on
an address calculation
So this code:
int runtest_bigframe()
{
unsigned int i;
unsigned char buf[900];
for (i = 0; i 900; i++)
buf[i] = (i % 237);
Causes this address calculation, attempting to compute the address of buf[]:
(insn 36 30 37 2 (set (reg:SI 96)
(const_int -900 [0xfc7c])) /home/james/tmp/x.c:11 25
{*movsi}
(expr_list:REG_EQUIV (const_int -900 [0xfc7c])
(nil)))
(insn 37 36 39 2 (set (reg:SI 97)
(plus:SI (reg/f:SI 0 $fp)
(reg:SI 96))) /home/james/tmp/x.c:11 2 {addsi3}
(expr_list:REG_DEAD (reg:SI 96)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 0 $fp)
(const_int -900 [0xfc7c]))
(nil
And LRA loops on insn 37, repeatedly allocating a register for (reg:SI 97).
However, something like this:
void foo (void)
{
unsigned char buf[900];
bar(buf);
}
Happily compiles, even though the address calculation is identical!
foo:
link $fp,924
ldk.l $r0,-900
add.l $r0,$fp,$r0
call bar
unlink $r29
return
Here is the relevant part of the dump, just before reload as above:
(insn 11 6 7 2 (set (reg:SI 43)
(const_int -900 [0xfc7c])) /home/james/tmp/x.c:31 25
{*movsi}
(expr_list:REG_EQUIV (const_int -900 [0xfc7c])
(nil)))
(insn 7 11 8 2 (set (reg:SI 2 $r0)
(plus:SI (reg/f:SI 0 $fp)
(reg:SI 43))) /home/james/tmp/x.c:31 2 {addsi3}
(expr_list:REG_DEAD (reg:SI 43)
(nil)))
They look very similar. I am currently baffled.
Do you think it would be easier to make the submission as is, then debug
the LRA issues from that point? If so, I have attached the current patch
set.
You should add a -mlra option so other people can easily enable it, too;
also handy later (when it defaults to on) when LRA blows up (you can
workaround with -mno-lra then).
Sounds good to me. Would that be an acceptable way to get the FT32 port
into the tree? I am very happy to go with the general flow towards LRA,
but at this point perhaps it may be a little early?
--
James Bowman
FTDI Open Source Liaison
RE: [PATCH, FT32] initial support
On 05/08/2015 06:04 PM, James Bowman wrote: Are you using LRA or reload? The former is definitely preferred and for a simple target like this, I'd expect the transition to be very easy. I'm using reload. Attempting to naively switch on LRA resulted in internal compiler error: Max. number of generated reload insns per insn is achieved (90) so I would be very interested in a pointer an LRA clues.D Thanks. Vladimir Makarov would be the best contact point. I'm a bit surprised you ran into this issue given the simplicity of the port. I'd minimize the testcase, then enable debugging dumps, then look at the insn that's causing LRA to loop. If Vlad helps, he's probably going to want that minimized testcase as well, so it's time well spent. It seems that with whenever a function's frame is bigger than 512 bytes, LRA loops. Likely this causes a problem because there is no actual instruction for subtracting constants more than 512. However, there is a link pattern that allows this. It is puzzling. Do you think it would be easier to make the submission as is, then debug the LRA issues from that point? If so, I have attached the current patch set. Thanks. -- James Bowman FTDI Open Source Liaison gcc-ft32.txt.gz Description: gcc-ft32.txt.gz
RE: [PATCH, FT32] initial support
Second ping. Also, have attached updated patchset for the current gcc. Thanks. -- James Bowman FTDI Open Source Liaison From: Joseph Myers [jos...@codesourcery.com] Sent: Tuesday, February 17, 2015 2:06 AM To: James Bowman Cc: gcc-patches@gcc.gnu.org Subject: RE: [PATCH, FT32] initial support On Mon, 16 Feb 2015, James Bowman wrote: I have updated the target options. Space-saving is now enabled by -Os. There is also a new option -msim to enable building for the simulator (the simulator is pending submission to gdb-binutils). The documentation in this patch doesn't seem to have been updated for those changes. -- Joseph S. Myers jos...@codesourcery.com gcc-ft32.txt.gz Description: gcc-ft32.txt.gz
RE: [PATCH, FT32] initial support
On Mon, 16 Feb 2015, James Bowman wrote: I have updated the target options. Space-saving is now enabled by -Os. There is also a new option -msim to enable building for the simulator (the simulator is pending submission to gdb-binutils). The documentation in this patch doesn't seem to have been updated for those changes. Ping. Also, have attached updated patchset for the current gcc. Thanks. -- James Bowman FTDI Open Source Liaison gcc-ft32.txt.gz Description: gcc-ft32.txt.gz
RE: [PATCH, FT32] initial support
Aha yes. Revised attached. invoke.texi now has: These options are defined specifically for the FT32 port. @table @gcctabopt @item -msim @opindex msim Specifies that the program will be run on the simulator. This causes an alternate runtime startup and library to be linked. You must not use this option when generating programs that will run on real hardware; you must provide your own runtime library for whatever I/O functions are needed. @end table -- James Bowman FTDI Open Source Liaison From: Joseph Myers [jos...@codesourcery.com] Sent: Tuesday, February 17, 2015 2:06 AM To: James Bowman Cc: gcc-patches@gcc.gnu.org Subject: RE: [PATCH, FT32] initial support On Mon, 16 Feb 2015, James Bowman wrote: I have updated the target options. Space-saving is now enabled by -Os. There is also a new option -msim to enable building for the simulator (the simulator is pending submission to gdb-binutils). The documentation in this patch doesn't seem to have been updated for those changes. -- Joseph S. Myers jos...@codesourcery.com gcc-ft32.txt.gz Description: gcc-ft32.txt.gz
RE: [PATCH, FT32] initial support
From: Joseph Myers
...
+@table @gcctabopt
+
+@item -mspace
+@opindex mspace
+Enable code-size optimizations.
+Some of these optimizations incur a minor performance penalty.
We already have -Os, so why is an architecture-specific option for this
needed?
+A 16-bit signed constant (-32768..32767)
Use @minus{} for a minus sign in Texinfo documentation, and @dots{}
instead of literal .. or
I have updated the target options. Space-saving is now enabled by
-Os. There is also a new option -msim to enable building for the
simulator (the simulator is pending submission to gdb-binutils).
I have fixed the Texinfo formatting.
FT32 is a new high performance 32-bit RISC core developed by FTDI for embedded
applications.
Support for FT32 has already been added to binutils. This patch adds FT32
support to gcc.
Please can someone review it, and if appropriate commit it, as I do not have
write access to the tree.
The FSF have acknowledged receipt of FTDI's copyright assignment papers.
Thanks very much. ChangeLog entry:
2014-02-16 James Bowman james.bow...@ftdichip.com
* configure.ac: FT32 target added
* libgcc/config.host: FT32 target added
* gcc/config/ft32/: FT32 target added
* libgcc/config/ft32/: FT32 target added
* gcc/doc/install.texi, invoke.texi, md.texi: FT32 details added
* gcc/doc/contrib.texi, MAINTAINERS: self added
* contrib/config-list.mk: FT32 target added
* configure: Regenerated
--
James Bowman
FTDI Open Source Liaison
gcc-ft32.txt.gz
Description: gcc-ft32.txt.gz
RE: [PATCH, FT32] initial support
+@table @gcctabopt + +@item -mspace +@opindex mspace +Enable code-size optimizations. +Some of these optimizations incur a minor performance penalty. We already have -Os, so why is an architecture-specific option for this needed? Code compiled with -mspace is somewhat slower than code without. So we typically build *all* code with -Os, with everything non-critical also compiled -mspace. Is this a legitimate option or should I just use -Os? -- James Bowman FTDI Open Source Liaison
RE: [PATCH, FT32] initial support
(Thanks to everyone for the review. I have reworked the submission as suggested. This does build cleanly with --enable-werror-always) FT32 is a new high performance 32-bit RISC core developed by FTDI for embedded applications. Support for FT32 has already been added to binutils. This patch adds FT32 support to gcc. Please can someone review it, and if appropriate commit it, as I do not have write access to the tree. The FSF have acknowledged receipt of FTDI's copyright assignment papers. Thanks very much. ChangeLog entry: 2014-02-11 James Bowman james.bow...@ftdichip.com * configure.ac: FT32 target added * libgcc/config.host: FT32 target added * gcc/config/ft32/: FT32 target added * libgcc/config/ft32/: FT32 target added * gcc/doc/install.texi, invoke.texi, md.texi: FT32 details added * gcc/doc/contrib.texi, MAINTAINERS: self added * contrib/config-list.mk: FT32 target added * configure: Regenerated -- James Bowman FTDI Open Source Liaison gcc-ft32.txt.gz Description: gcc-ft32.txt.gz
RE: [PATCH, FT32] initial support
optabs.c's expand_abs_nojump already knows this trick:
/* If this machine has expensive jumps, we can do integer absolute
value of X as (((signed) x (W-1)) ^ x) - ((signed) x (W-1)),
where W is the width of MODE. */
So if you define BRANCH_COST to be 2 or more there should be no need for
this pattern at all.
Yes, I just confirmed this. With no abssi2 pattern, this:
int side;
int foo(int x)
{
side = x 31;
return abs(x);
}
does indeed produce:
foo:
ashr.l $r1,$r0,31
sta.l side,$r1
xor.l $r0,$r1,$r0
sub.l $r0,$r0,$r1
return
Thanks.
--
James Bowman
FTDI Open Source Liaison
RE: [PATCH] Update config.sub from upstream config repo
Sorry, should have been clearer. Please can someone review and apply this patch, as I don't have write access to the tree. Thanks.
[PATCH] pass pr20621 testcase on a small stack target
Test pr20621 requires a target with more than 64K of available stack.
This patch adds a path to pass the test when the target has declared
a STACK_SIZE of 64K or less
2014-12-30 James Bowman james.bow...@ftdichip.com
* gcc/testsuite/gcc.c-torture/execute/pr20621-1.c:
pass if stack 64K
Index: gcc/testsuite/gcc.c-torture/execute/pr20621-1.c
===
--- gcc/testsuite/gcc.c-torture/execute/pr20621-1.c (revision 215531)
+++ gcc/testsuite/gcc.c-torture/execute/pr20621-1.c (working copy)
@@ -1,6 +1,10 @@
/* When generating o32 MIPS PIC, main's $gp save slot was out of range
of a single load instruction. */
+#if defined(STACK_SIZE) STACK_SIZE = 0x1
+int main (void) { return 0; }
+#else
struct big { int i[sizeof (int) = 4 sizeof (void *) = 4 ? 0x4000 : 4]; };
struct big gb;
int foo (struct big b, int x) { return b.i[x]; }
int main (void) { return foo (gb, 0) + foo (gb, 1); }
+#endif
--
James Bowman
FTDI Open Source Liaison
[PATCH] Update config.sub from upstream config repo
ChangeLog 2014-12-23 James Bowman james.bow...@ftdichip.com * config.sub: Update from upstream config repo. -- James Bowman FTDI Open Source Liaison Index: config.sub === --- config.sub (revision 219020) +++ config.sub (working copy) @@ -2,7 +2,7 @@ # Configuration validation subroutine script. # Copyright 1992-2014 Free Software Foundation, Inc. -timestamp='2014-09-26' +timestamp='2014-12-21' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -260,7 +260,7 @@ | c4x | c8051 | clipper \ | d10v | d30v | dlx | dsp16xx \ | epiphany \ - | fido | fr30 | frv \ + | fido | fr30 | frv | ft32 \ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | hexagon \ | i370 | i860 | i960 | ia64 \ @@ -313,6 +313,7 @@ | tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ | ubicom32 \ | v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \ + | visium \ | we32k \ | x86 | xc16x | xstormy16 | xtensa \ | z8k | z80) @@ -440,6 +441,7 @@ | ubicom32-* \ | v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \ | vax-* \ + | visium-* \ | we32k-* \ | x86-* | x86_64-* | xc16x-* | xps100-* \ | xstormy16-* | xtensa*-* \
