Re: [PATCH, ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macro

2017-06-16 Thread Prakhar Bahuguna 
On 16/06/2017 15:37:18, Richard Earnshaw (lists) wrote:
> On 16/06/17 08:48, Prakhar Bahuguna wrote:
> > On 15/06/2017 17:23:43, Richard Earnshaw (lists) wrote:
> >> On 14/06/17 10:35, Prakhar Bahuguna wrote:
> >>> The ARM ACLE defines the __ARM_FEATURE_COPROC macro which indicates which
> >>> coprocessor intrinsics are available for the target. If 
> >>> __ARM_FEATURE_COPROC is
> >>> undefined, the target does not support coprocessor intrinsics. The feature
> >>> levels are defined as follows:
> >>>
> >>> +-+---+--+
> >>> | **Bit** | **Value** | **Intrinsics Available** |
> >>> +-+---+--+
> >>> | 0   | 0x1   | __arm_cdp __arm_ldc, __arm_ldcl, __arm_stc,  |
> >>> | |   | __arm_stcl, __arm_mcr and __arm_mrc  |
> >>> +-+---+--+
> >>> | 1   | 0x2   | __arm_cdp2, __arm_ldc2, __arm_stc2, __arm_ldc2l, |
> >>> | |   | __arm_stc2l, __arm_mcr2 and __arm_mrc2   |
> >>> +-+---+--+
> >>> | 2   | 0x4   | __arm_mcrr and __arm_mrrc|
> >>> +-+---+--+
> >>> | 3   | 0x8   | __arm_mcrr2 and __arm_mrrc2  |
> >>> +-+---+--+
> >>>
> >>> This patch implements full support for this feature macro as defined in 
> >>> section
> >>> 5.9 of the ACLE
> >>> (https://developer.arm.com/products/software-development-tools/compilers/arm-compiler-5/docs/101028/latest/5-feature-test-macros).
> >>>
> >>> gcc/ChangeLog:
> >>>
> >>> 2017-06-14  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> >>>
> >>>   * config/arm/arm-c.c (arm_cpu_builtins): New block to define
> >>>__ARM_FEATURE_COPROC according to support.
> >>>
> >>> 2017-06-14  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> >>>   * gcc/testsuite/gcc.target/arm/acle/cdp.c: Add feature macro bitmap
> >>>   test.
> >>>   * gcc/testsuite/gcc.target/arm/acle/cdp2.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/ldc.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/ldc2.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/ldc2l.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/ldcl.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mcr.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mcr2.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mcrr.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mcrr2.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mrc.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mrc2.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mrrc.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/mrrc2.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/stc.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/stc2.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/stc2l.c: Likewise.
> >>>   * gcc/testsuite/gcc.target/arm/acle/stcl.c: Likewise.
> >>>
> >>> Testing done: ACLE regression tests updated with tests for feature macro 
> >>> bits.
> >>> All regression tests pass.
> >>>
> >>> Okay for trunk?
> >>>
> >>>
> >>> 0001-Implement-__ARM_FEATURE_COPROC-coprocessor-intrinsic.patch
> >>>
> >>>
> >>> From 79d71aec9d2bdee936b240ae49368ff5f8d8fc48 Mon Sep 17 00:00:00 2001
> >>> From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
> >>> Date: Tue, 2 May 2017 13:43:40 +0100
> >>> Subject: [PATCH] Implement __ARM_FEATURE_COPROC coprocessor intrinsic 
> >>> feature
> >>>  macro
> >>>
> >>> ---
> >>>  gcc/config/arm/arm-c.c| 19 +++
> >>>  gcc/testsuite/gcc.target/arm/acle/cdp.c   |  3 +++
> >>>  gcc/testsuite/gcc.target/arm/acle/cdp2.c  |  3 +++
> >>>  gcc/testsuite/gcc.target/arm/acle/ldc.c   |  3 +++
> >&g

Re: [PATCH, ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macro

2017-06-16 Thread Prakhar Bahuguna 
Patch updated with code style fixes.

-- 

Prakhar Bahuguna
>From f1d76a6309a1fe16711b800507938eaa4f78852e Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Tue, 2 May 2017 13:43:40 +0100
Subject: [PATCH] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature
 macro

---
 gcc/config/arm/arm-c.c| 17 +
 gcc/testsuite/gcc.target/arm/acle/cdp.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/cdp2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldc.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldc2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldc2l.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldcl.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcr.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcr2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcrr.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcrr2.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrc.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrc2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrrc.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrrc2.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stc.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stc2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stc2l.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stcl.c  |  3 +++
 19 files changed, 71 insertions(+)

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 3abe7d1f1f5..d8b17ffdccc 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -200,6 +200,23 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV);
 
   def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified);
+
+  if ((!TARGET_THUMB || TARGET_THUMB2) && arm_arch4
+  && !(arm_arch8 && arm_arch_notm))
+{
+  int coproc_level = 0x1;
+
+  if (arm_arch5)
+   coproc_level |= 0x2;
+  if (arm_arch5e)
+   coproc_level |= 0x4;
+  if (arm_arch6)
+   coproc_level |= 0x8;
+
+  builtin_define_with_int_value ("__ARM_FEATURE_COPROC", coproc_level);
+}
+  else
+  cpp_undef (pfile, "__ARM_FEATURE_COPROC");
 }
 
 void
diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp.c 
b/gcc/testsuite/gcc.target/arm/acle/cdp.c
index 28b218e7cfc..cebd8c4024e 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cdp.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cdp.c
@@ -5,6 +5,9 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif
 
 void test_cdp (void)
 {
diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp2.c 
b/gcc/testsuite/gcc.target/arm/acle/cdp2.c
index 00bcd502b56..945d435d2fb 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cdp2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cdp2.c
@@ -5,6 +5,9 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif
 
 void test_cdp2 (void)
 {
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc.c 
b/gcc/testsuite/gcc.target/arm/acle/ldc.c
index f45f25d8c97..cd57343208f 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc.c
@@ -5,6 +5,9 @@
 /* { dg-require-effective-target arm_coproc1_ok } */
 
 #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif
 
 extern void * p;
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2.c 
b/gcc/testsuite/gcc.target/arm/acle/ldc2.c
index 433bf8a1204..d7691e30d76 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc2.c
@@ -5,6 +5,9 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif
 
 extern void * p;
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c 
b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
index 88c8aa44765..9ee63afa055 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
@@ -5,6 +5,9 @@
 /* { dg-require-effective-target arm_coproc2_ok } */
 
 #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif
 
 extern void * p;
 
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldcl.c 
b/gcc/testsuite/gcc.target/arm/acle/ldcl.c
index 72a97f1d7b7..a6bfd9011dc 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldcl.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldcl.c
@@ -5,6 +5,9 @@
 /* { dg-require-effective-target arm_coproc1_ok } */

Re: [PATCH, ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macro

2017-06-16 Thread Prakhar Bahuguna 
On 15/06/2017 17:23:43, Richard Earnshaw (lists) wrote:
> On 14/06/17 10:35, Prakhar Bahuguna wrote:
> > The ARM ACLE defines the __ARM_FEATURE_COPROC macro which indicates which
> > coprocessor intrinsics are available for the target. If 
> > __ARM_FEATURE_COPROC is
> > undefined, the target does not support coprocessor intrinsics. The feature
> > levels are defined as follows:
> > 
> > +-+---+--+
> > | **Bit** | **Value** | **Intrinsics Available** |
> > +-+---+--+
> > | 0   | 0x1   | __arm_cdp __arm_ldc, __arm_ldcl, __arm_stc,  |
> > | |   | __arm_stcl, __arm_mcr and __arm_mrc  |
> > +-+---+--+
> > | 1   | 0x2   | __arm_cdp2, __arm_ldc2, __arm_stc2, __arm_ldc2l, |
> > | |   | __arm_stc2l, __arm_mcr2 and __arm_mrc2   |
> > +-+---+--+
> > | 2   | 0x4   | __arm_mcrr and __arm_mrrc|
> > +-+---+--+
> > | 3   | 0x8   | __arm_mcrr2 and __arm_mrrc2  |
> > +-+---+--+
> > 
> > This patch implements full support for this feature macro as defined in 
> > section
> > 5.9 of the ACLE
> > (https://developer.arm.com/products/software-development-tools/compilers/arm-compiler-5/docs/101028/latest/5-feature-test-macros).
> > 
> > gcc/ChangeLog:
> > 
> > 2017-06-14  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > 
> > * config/arm/arm-c.c (arm_cpu_builtins): New block to define
> >  __ARM_FEATURE_COPROC according to support.
> > 
> > 2017-06-14  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > * gcc/testsuite/gcc.target/arm/acle/cdp.c: Add feature macro bitmap
> > test.
> > * gcc/testsuite/gcc.target/arm/acle/cdp2.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/ldc.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/ldc2.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/ldc2l.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/ldcl.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mcr.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mcr2.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mcrr.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mcrr2.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mrc.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mrc2.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mrrc.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/mrrc2.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/stc.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/stc2.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/stc2l.c: Likewise.
> > * gcc/testsuite/gcc.target/arm/acle/stcl.c: Likewise.
> > 
> > Testing done: ACLE regression tests updated with tests for feature macro 
> > bits.
> > All regression tests pass.
> > 
> > Okay for trunk?
> > 
> > 
> > 0001-Implement-__ARM_FEATURE_COPROC-coprocessor-intrinsic.patch
> > 
> > 
> > From 79d71aec9d2bdee936b240ae49368ff5f8d8fc48 Mon Sep 17 00:00:00 2001
> > From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
> > Date: Tue, 2 May 2017 13:43:40 +0100
> > Subject: [PATCH] Implement __ARM_FEATURE_COPROC coprocessor intrinsic 
> > feature
> >  macro
> > 
> > ---
> >  gcc/config/arm/arm-c.c| 19 +++
> >  gcc/testsuite/gcc.target/arm/acle/cdp.c   |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/cdp2.c  |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/ldc.c   |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/ldc2.c  |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/ldc2l.c |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/ldcl.c  |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/mcr.c   |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/mcr2.c  |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/mcrr.c  |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/mcrr2.c |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/mrc.c   |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/mrc2.c  |  3 +++
> >  gcc/testsuite/gcc.target/arm/acle/mrrc.c  |  3 +++
> >  gcc/testsuite/gcc.targe

[PATCH, ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macro

2017-06-14 Thread Prakhar Bahuguna 
The ARM ACLE defines the __ARM_FEATURE_COPROC macro which indicates which
coprocessor intrinsics are available for the target. If __ARM_FEATURE_COPROC is
undefined, the target does not support coprocessor intrinsics. The feature
levels are defined as follows:

+-+---+--+
| **Bit** | **Value** | **Intrinsics Available** |
+-+---+--+
| 0   | 0x1   | __arm_cdp __arm_ldc, __arm_ldcl, __arm_stc,  |
| |   | __arm_stcl, __arm_mcr and __arm_mrc  |
+-+---+--+
| 1   | 0x2   | __arm_cdp2, __arm_ldc2, __arm_stc2, __arm_ldc2l, |
| |   | __arm_stc2l, __arm_mcr2 and __arm_mrc2   |
+-+---+--+
| 2   | 0x4   | __arm_mcrr and __arm_mrrc|
+-+---+--+
| 3   | 0x8   | __arm_mcrr2 and __arm_mrrc2  |
+-+---+--+

This patch implements full support for this feature macro as defined in section
5.9 of the ACLE
(https://developer.arm.com/products/software-development-tools/compilers/arm-compiler-5/docs/101028/latest/5-feature-test-macros).

gcc/ChangeLog:

2017-06-14  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

* config/arm/arm-c.c (arm_cpu_builtins): New block to define
 __ARM_FEATURE_COPROC according to support.

2017-06-14  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
* gcc/testsuite/gcc.target/arm/acle/cdp.c: Add feature macro bitmap
test.
* gcc/testsuite/gcc.target/arm/acle/cdp2.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/ldc.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/ldc2.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/ldc2l.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/ldcl.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mcr.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mcr2.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mcrr.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mcrr2.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mrc.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mrc2.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mrrc.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/mrrc2.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/stc.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/stc2.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/stc2l.c: Likewise.
* gcc/testsuite/gcc.target/arm/acle/stcl.c: Likewise.

Testing done: ACLE regression tests updated with tests for feature macro bits.
All regression tests pass.

Okay for trunk?

-- 

Prakhar Bahuguna
>From 79d71aec9d2bdee936b240ae49368ff5f8d8fc48 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Tue, 2 May 2017 13:43:40 +0100
Subject: [PATCH] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature
 macro

---
 gcc/config/arm/arm-c.c| 19 +++
 gcc/testsuite/gcc.target/arm/acle/cdp.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/cdp2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldc.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldc2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldc2l.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/ldcl.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcr.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcr2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcrr.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mcrr2.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrc.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrc2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrrc.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/mrrc2.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stc.c   |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stc2.c  |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stc2l.c |  3 +++
 gcc/testsuite/gcc.target/arm/acle/stcl.c  |  3 +++
 19 files changed, 73 insertions(+)

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 3abe7d1f1f5..3daf4e5e1f3 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -200,6 +200,25 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV);
 
   def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified);
+
+  if ((!TARGET_THUMB || TARGET_THUMB2) && arm_arch4 &&
+  !(arm_arch8 && arm_arch_notm))
+{
+  int coproc_level = 0x1;
+
+  if (arm_arch5)
+   coproc_level |= 0x2;
+  if (arm_arch5e)
+   coproc_level |= 0x4;
+  if (arm_arch6)
+

[PATCH, GCC/THUMB1] New define_insn_and_split pattern to optimize out unnecessary uxtb instructions

2017-06-05 Thread Prakhar Bahuguna 
GCC currently generates unnecessary uxtb instructions when compiling
gcc.target/arm/unsigned-extend-1.c for Thumb1 targets such as the Cortex-M0.
This test case is as follows:

unsigned char foo (unsigned char c)
{
  return (c >= '0') && (c <= '9');
}

The assembly output generated with "-mcpu=cortex-m0 -O2":

foo:
mov r3, r0
mov r2, #9
mov r0, #0
sub r3, r3, #48
uxtbr3, r3
cmp r2, r3
adc r0, r0, r0
@ sp needed
uxtbr0, r0
bx  lr

The uxtb instructions are supposed to be optimized out at the rtl combine pass,
but the current thumb1_addsi3_addgeu insn pattern is not friendly to the
combine pass. Upon entering the combine pass, we have this rtl:

(insn 6 3 7 2 (set (reg:SI 116)
(plus:SI (reg/v:SI 114 [ c ])
(const_int -48 [0xffd0])))

(insn 7 6 8 2 (set (reg:SI 117)
(zero_extend:SI (subreg:QI (reg:SI 116) 0)))

(insn 8 7 9 2 (set (reg:SI 119)
(const_int 9 [0x9]))

(insn 9 8 10 2 (set (reg:SI 120)
(const_int 0 [0]))

(insn 10 9 12 2 (set (reg:SI 118)
(plus:SI (plus:SI (reg:SI 120)
(reg:SI 120))
(geu:SI (reg:SI 119)
(reg:SI 117

During the rtl combine pass, operand 0 of the first plus operator is
(plus:SI (reg:SI 120) (reg:SI 120)) and this will be optimized to (const_int 0)
as reg 120 is zero after insn 9. The first plus operator will be subsequently
optimized out as it performs addition with zero. Finally, insn 10 is turned
into:

(insn 10 9 12 2 (set (reg:SI 118)
 (leu:SI (reg:SI 116) (const_int 9

The optimization to the leu comparator matches our expectation that reg 116
will be used directly instead of reg 117 to eliminate uxtb insn 7.
Unfortunately, this new insn 10 is an illegal rtl for Thumb1. Hence, the
optimization done in the combine pass is undone and the unnecessary uxtb
instruction is kept.

This patch implements a veneer for the insn pattern thumb1_addsi3_addgeu. This
veneer insn pattern looks like the new insn 10 in the above example and can
facilitate the combine pass to optimize out the unnecessary uxtb instructions.
During the rtl expand stage, GIMPLE trees are expanded to this veneer insn
pattern rather than the normal thumb1_addsi3_addgeu. Later on in the split1
stage, this veneer insn pattern will be turned into normal thumb1_addsi3_addgeu
pattern for future code generation.

gcc/ChangeLog:

2017-06-05  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

* config/arm/arm.md (cstoresi_leu_thumb1): New define_insn_and_split
pattern.
(cstoresi4): Use above new pattern.

testsuite/ChangeLog:

2017-06-05  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

* gcc.target/arm/thumb1-unsigned-extend-1.c: New file.

Testing done: Ran regression tests, added new test to confirm uxtb instructions
are optimized out for Thumb1 targets.

Okay for stage1?

-- 

Prakhar Bahuguna
>From c0c5d410536238bf57967cbc50bdc8e7f7f0ab59 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Fri, 24 Mar 2017 10:48:03 +
Subject: [PATCH] New define_insn_and_split pattern to optimize out unnecessary
 uxtb instructions

---
 gcc/config/arm/arm.md  | 36 ++
 .../gcc.target/arm/thumb1-unsigned-extend-1.c  | 10 ++
 2 files changed, 40 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb1-unsigned-extend-1.c

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index e6e1ac54a85..656ede7c2f5 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -7691,18 +7691,14 @@
 
 case LEU:
   op3 = force_reg (SImode, operands[3]);
-  scratch = force_reg (SImode, const0_rtx);
-  emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch,
- op3, operands[2]));
+  emit_insn (gen_cstoresi_leu_thumb1 (operands[0], operands[2], op3));
   break;
 
 case GEU:
   op3 = operands[3];
   if (!thumb1_cmp_operand (op3, SImode))
 op3 = force_reg (SImode, op3);
-  scratch = force_reg (SImode, const0_rtx);
-  emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch,
- operands[2], op3));
+  emit_insn (gen_cstoresi_leu_thumb1 (operands[0], op3, operands[2]));
   break;
 
 case LTU:
@@ -7781,6 +,34 @@
}"
 )
 
+(define_insn_and_split "cstoresi_leu_thumb1"
+  [(set (match_operand:SI 0 "s_register_operand" "=l")
+   (leu:SI (match_operand:SI 1 "s_register_operand" "l")
+   (match_operand:SI 2 "thumb1_cmp_operand" "lI")))]
+  "TARGET_THUMB1"
+  "#"
+  "TARGET_THUMB1 && !reload_completed"
+  [(set (match_dup 3

[PATCH, GCC/ARM/gcc-6-branch] Backport PR71607

2017-06-02 Thread Prakhar Bahuguna 
This patch tackles the issue reported in PR71607. This patch takes a different
approach for disabling the creation of literal pools. Instead of disabling the
patterns that would normally transform the rtl into actual literal pools, it
disables the creation of this literal pool rtl by making the target hook
TARGET_CANNOT_FORCE_CONST_MEM return true if arm_disable_literal_pool is true.
I added patterns to split floating point constants for both SF and DFmode. A
pattern to handle the addressing of label_refs had to be included as well since
all "memory_operand" patterns are disabled when TARGET_CANNOT_FORCE_CONST_MEM
returns true. Also the pattern for splitting 32-bit immediates had to be
changed, it was not accepting unsigned 32-bit unsigned integers with the MSB
set. I believe const_int_operand expects the mode of the operand to be set to
VOIDmode and not SImode. I have only changed it in the patterns that were
affecting this code, though I suggest looking into changing it in the rest of
the ARM backend.

Additionally, the use of thread-local storage is disabled if literal pools are
disabled, as there are no relocations for TLS variables and incorrect code is
generated as a result. The patch now emits a diagnostic in TLS-enabled
toolchains if a TLS symbol is found when -mpure-code or -mslow-flash-data are
enabled.

2017-06-02  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

Backport from mainline
2017-05-05  Andre Vieira  <andre.simoesdiasvie...@arm.com>
    Prakhar Bahuguna  <prakhar.bahug...@arm.com>

gcc/
PR target/71607
* config/arm/arm.md (use_literal_pool): Remove.
(64-bit immediate split): No longer takes cost into consideration
if arm_disable_literal_pool is enabled.
* config/arm/arm.c (arm_tls_referenced_p): Add diagnostic if TLS is
used when arm_disable_literal_pool is enabled.
(arm_max_const_double_inline_cost): Remove use of
arm_disable_literal_pool.
(push_minipool_fix): Add assert.
(arm_reorg): Add return if arm_disable_literal_pool is enabled.
* config/arm/vfp.md (no_literal_pool_df_immediate): New.
(no_literal_pool_sf_immediate): New.

2017-05-05  Andre Vieira  <andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>
Prakhar Bahuguna  <prakhar.bahug...@arm.com>

gcc/testsuite/
PR target/71607
* gcc.target/arm/thumb2-slow-flash-data.c: Renamed to ...
* gcc.target/arm/thumb2-slow-flash-data-1.c: ... this.
* gcc.target/arm/thumb2-slow-flash-data-2.c: New.
* gcc.target/arm/thumb2-slow-flash-data-3.c: New.
* gcc.target/arm/thumb2-slow-flash-data-4.c: New.
* gcc.target/arm/thumb2-slow-flash-data-5.c: New.
* gcc.target/arm/tls-disable-literal-pool.c: New.

Testing done: Ran regression tests for arm-eabi-none for ARMv7-M and ARMv8-M
targets. A bootstrap for arm-none-linux-gnueabihf was also successful.

Okay for 6 branch?

-- 

Prakhar Bahuguna
>From 4d411741ac86a5d86b7c1e656d341bf72d1c772a Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Tue, 18 Apr 2017 14:16:46 +0100
Subject: [PATCH] PR71607: Fix ICE when loading constant

---
 gcc/config/arm/arm.c   | 21 +---
 gcc/config/arm/arm.md  |  9 ++
 gcc/config/arm/vfp.md  | 37 ++
 ...low-flash-data.c => thumb2-slow-flash-data-1.c} |  0
 .../gcc.target/arm/thumb2-slow-flash-data-2.c  | 28 
 .../gcc.target/arm/thumb2-slow-flash-data-3.c  | 25 +++
 .../gcc.target/arm/thumb2-slow-flash-data-4.c  | 26 +++
 .../gcc.target/arm/thumb2-slow-flash-data-5.c  | 14 
 .../gcc.target/arm/tls-disable-literal-pool.c  | 14 
 9 files changed, 163 insertions(+), 11 deletions(-)
 rename gcc/testsuite/gcc.target/arm/{thumb2-slow-flash-data.c => 
thumb2-slow-flash-data-1.c} (100%)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 9c0813d598d..7fa8275550a 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8240,7 +8240,16 @@ arm_tls_referenced_p (rtx x)
 {
   const_rtx x = *iter;
   if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
-   return true;
+   {
+ /* ARM currently does not provide relocations to encode TLS variables
+into AArch32 instructio

Re: [PATCH, GCC/ARM/gcc-7-branch] Backport PR71607

2017-06-01 Thread Prakhar Bahuguna 
On 01/06/2017 07:15:47, Richard Sandiford wrote:
> Prakhar Bahuguna <prakhar.bahug...@arm.com> writes:
> > On 31/05/2017 14:11:43, Richard Sandiford wrote:
> >> Prakhar Bahuguna <prakhar.bahug...@arm.com> writes:
> >> > On 31/05/2017 09:19:40, Richard Sandiford wrote:
> >> >> const_ints are supposed to be stored in sign-extended form, so a 32-bit
> >> >> integer with the MSB set should be 0x8000|x instead of
> >> >> 0x8000|x.  It's a bug if you have one where that isn't true.
> >> >> 
> >> >> In the patch it looks like this could come from:
> >> >> ...these two splits, where the GEN_INTs should probably be:
> >> >> 
> >> >>   gen_int_mode (..., SImode);
> >> >> 
> >> >> instead.
> >> >
> >> > Hi Richard, thanks for the tip. Is there a test case that could produce 
> >> > an
> >> > incorrect result? I've attempted to create one using negative doubles and
> >> > floats but haven't succeeded.
> >> 
> >> Just to check, are you testing with --enable-checking=yes,rtl?
> >> 
> >> When the values you tried were split, did you get the sign-extended form
> >> or the zero-extended form?
> >> 
> >> Thanks,
> >> Richard
> >
> > I've now rebuilt with --enable-checking=yes,rtl and it appears that the 
> > split
> > values are being correctly sign-extended in the rtl and appear correctly in 
> > the
> > assembly.
> >
> > However, if you believe it is safer to use gen_int_mode(), I'll respin the
> > patch accordingly.
> 
> Yeah, I think it would be safer.  But if they were already correctly
> sign-extended, then what did you mean by:
> 
>   Also the pattern for splitting 32-bit immediates had to be changed, it
>   was not accepting unsigned 32-bit unsigned integers with the MSB
>   set. I believe const_int_operand expects the mode of the operand to be
>   set to VOIDmode and not SImode. I have only changed it in the patterns
>   that were affecting this code, though I suggest looking into changing
>   it in the rest of the ARM backend.
> 
> Thanks,
> Richard

This part of the patch was written by Andre. After checking with him, it seems
that some of the confusion arises from the comment on real_to_target() which
states "There are always 32 bits in each long, no matter the size of the host
long". While this may imply the value is zero-extended on hosts with wider
longs, it seems like the value is always correctly sign-extended and thus
gen_int_mode() should be unnecessary.

As for why VOIDmode is used with the values casted to int, there is a reason
for why it is done this way to get it working but this has been long-forgotten.
I only have the code and this message to rely on.

-- 

Prakhar Bahuguna

Re: [PATCH, GCC/ARM/gcc-7-branch] Backport PR71607

2017-05-31 Thread Prakhar Bahuguna 
On 31/05/2017 14:11:43, Richard Sandiford wrote:
> Prakhar Bahuguna <prakhar.bahug...@arm.com> writes:
> > On 31/05/2017 09:19:40, Richard Sandiford wrote:
> >> const_ints are supposed to be stored in sign-extended form, so a 32-bit
> >> integer with the MSB set should be 0x8000|x instead of
> >> 0x8000|x.  It's a bug if you have one where that isn't true.
> >> 
> >> In the patch it looks like this could come from:
> >> ...these two splits, where the GEN_INTs should probably be:
> >> 
> >>   gen_int_mode (..., SImode);
> >> 
> >> instead.
> >
> > Hi Richard, thanks for the tip. Is there a test case that could produce an
> > incorrect result? I've attempted to create one using negative doubles and
> > floats but haven't succeeded.
> 
> Just to check, are you testing with --enable-checking=yes,rtl?
> 
> When the values you tried were split, did you get the sign-extended form
> or the zero-extended form?
> 
> Thanks,
> Richard

I've now rebuilt with --enable-checking=yes,rtl and it appears that the split
values are being correctly sign-extended in the rtl and appear correctly in the
assembly.

However, if you believe it is safer to use gen_int_mode(), I'll respin the
patch accordingly.

-- 

Prakhar Bahuguna

Re: [PATCH, GCC/ARM/gcc-7-branch] Backport PR71607

2017-05-31 Thread Prakhar Bahuguna 
On 31/05/2017 09:19:40, Richard Sandiford wrote:
> const_ints are supposed to be stored in sign-extended form, so a 32-bit
> integer with the MSB set should be 0x8000|x instead of
> 0x8000|x.  It's a bug if you have one where that isn't true.
> 
> In the patch it looks like this could come from:
> ...these two splits, where the GEN_INTs should probably be:
> 
>   gen_int_mode (..., SImode);
> 
> instead.

Hi Richard, thanks for the tip. Is there a test case that could produce an
incorrect result? I've attempted to create one using negative doubles and
floats but haven't succeeded.

Thanks,

-- 

Prakhar Bahuguna

[arm-embedded] Enable Purecode for ARMv8-M Baseline

2017-05-31 Thread Prakhar Bahuguna 
We have decided to apply the following patch to ARM/embedded-7-branch and
ARM/embedded-6-branch to enable Purecode support for ARMv8-M Baseline targets.

ChangeLog:

2017-05-31  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

Backport from mainline
2017-05-04  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
Andre Simoes Dias Vieira  <andre.simoesdiasvie...@arm.com>

gcc/
* config/arm/arm.md (movsi): Add TARGET_32BIT in addition to the
TARGET_HAVE_MOVT conditional.
(movt splitter): Likewise.
* config/arm/arm.c (arm_option_check_internal): Change arm_arch_thumb2
to TARGET_HAVE_MOVT, and merge with -mslow-flash-data check.
(const_ok_for_arm): Change else to else if (TARGET_THUMB2) and add else
block for Thumb-1 with MOVT.
(thumb2_legitimate_address_p): Move code block ...
(can_avoid_literal_pool_for_label_p): ... into this new function.
(thumb1_legitimate_address_p): Add check for TARGET_HAVE_MOVT and
literal pool.
(thumb_legitimate_constant_p): Add conditional on TARGET_HAVE_MOVT
* doc/invoke.texi (-mpure-code): Change "ARMv7-M targets" for
"M-profile targets with the MOVT instruction".

gcc/testsuite/
* gcc.target/arm/pure-code/pure-code.exp: Add conditional for
check_effective_target_arm_thumb1_movt_ok.

-- 

Prakhar Bahuguna
>From a9a11e668170e9f832ba76fb9dd35284069756cf Mon Sep 17 00:00:00 2001
From: thopre01 <thopre01@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 4 May 2017 10:26:25 +
Subject: [PATCH] [ARM] Enable Purecode for ARMv8-M Baseline

This patch adds support for purecode to ARMv8-M Baseline, in addition to
the existing support for ARMv7-M and ARMv8-M Mainline.
---
 gcc/config/arm/arm.c   | 78 ++
 gcc/config/arm/arm.md  |  6 +-
 gcc/doc/invoke.texi|  3 +-
 .../gcc.target/arm/pure-code/pure-code.exp |  5 +-
 4 files changed, 58 insertions(+), 34 deletions(-)

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f3a6b64b168..acee644fa98 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2832,16 +2832,16 @@ arm_option_check_internal (struct gcc_options *opts)
   flag_pic = 0;
 }
 
-  /* We only support -mslow-flash-data on armv7-m targets.  */
-  if (target_slow_flash_data
-  && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
- || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
-error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
-
-  /* We only support pure-code on Thumb-2 M-profile targets.  */
-  if (target_pure_code
-  && (!arm_arch_thumb2 || arm_arch_notm || flag_pic || TARGET_NEON))
-error ("-mpure-code only supports non-pic code on armv7-m targets");
+  /* We only support -mpure-code and -mslow-flash-data on M-profile targets
+ with MOVT.  */
+  if ((target_pure_code || target_slow_flash_data)
+  && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
+{
+  const char *flag = (target_pure_code ? "-mpure-code" :
+"-mslow-flash-data");
+  error ("%s only supports non-pic code on M-profile targets with the "
+"MOVT instruction", flag);
+}
 
 }
 
@@ -4076,7 +4076,7 @@ const_ok_for_arm (HOST_WIDE_INT i)
   || (i & ~0xfc03) == 0))
return TRUE;
 }
-  else
+  else if (TARGET_THUMB2)
 {
   HOST_WIDE_INT v;
 
@@ -4092,6 +4092,14 @@ const_ok_for_arm (HOST_WIDE_INT i)
   if (i == v)
return TRUE;
 }
+  else if (TARGET_HAVE_MOVT)
+{
+  /* Thumb-1 Targets with MOVT.  */
+  if (i > 0x)
+   return FALSE;
+  else
+   return TRUE;
+}
 
   return FALSE;
 }
@@ -7699,6 +7707,32 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx 
x, RTX_CODE outer,
   return 0;
 }
 
+/* Return true if we can avoid creating a constant pool entry for x.  */
+static bool
+can_avoid_literal_pool_for_label_p (rtx x)
+{
+  /* Normally we can assign constant values to target registers without
+ the help of constant pool.  But there are cases we have to use constant
+ pool like:
+ 1) assign a label to register.
+ 2) sign-extend a 8bit value to 32bit and then assign to register.
+
+ Constant pool access in format:
+ (set (reg r0) (mem (symbol_ref (".LC0"
+ will cause the use of literal pool (later in function arm_reorg).
+ So here we mark such format as an invalid format, then the compiler
+ will adjust it into:
+ (set (reg r0) (symbol_ref (".LC0")))
+ (set (reg r0) (mem (reg r0))).
+ No extra register is required, and (mem (reg r0)) won't cause the use

[PATCH, Committed] Add self to MAINTAINERS

2017-05-31 Thread Prakhar Bahuguna 
I have added myself to the Write After Approval section of the MAINTAINERS
list.

ChangeLog:

2017-05-31  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

* MAINTAINERS: Add self to Write After Approval

-- 

Prakhar Bahuguna

Re: [PING][PATCH, GCC/ARM] Only test tls-disable-literal-pool.c if target supports native TLS

2017-05-30 Thread Prakhar Bahuguna 
On 30/05/2017 14:11:22, Christophe Lyon wrote:
> On 30 May 2017 at 09:44, Prakhar Bahuguna <prakhar.bahug...@arm.com> wrote:
> > On 29/05/2017 14:23:05, Christophe Lyon wrote:
> >> On 19 May 2017 at 14:29, Prakhar Bahuguna <prakhar.bahug...@arm.com> wrote:
> >> > On 11/05/2017 14:54:37, Prakhar Bahuguna wrote:
> >> >> tls-disable-literal-pool.c should only be run if the toolchain and 
> >> >> target
> >> >> support native thread-local storage rather than emulated TLS. This 
> >> >> patch also
> >> >> improves the matching of the error message.
> >> >>
> >> >> testsuite/ChangeLog:
> >> >>
> >> >> 2017-05-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> >> >>
> >> >>   * gcc.target/arm/tls-disable-literal-pool.c: Change
> >> >>   require-effective-target to tls_native.
> >> >>   Move dg-error to return statement line and change to dg-message.
> >> >>
> >> >> Testing done: Regression testing for ARMv7-M with a TLS-enabled 
> >> >> toolchain and a
> >> >> TLS-disabled toolchain.
> >> >>
> >>
> >> Hi,
> >> Can you share more details on the configuration you used?
> >> In my testing, the only cortex-M config I have is arm-none-eabi
> >> --with-cpu=cortex-m3.
> >> Since arm-none-eabi means native-tls is disabled, this test is skipped.
> >> A constraint for me is that m3 was the only cortex-m cpu supported by qemu 
> >> the
> >> last time I checked.
> >>
> >> Thanks,
> >>
> >> Christophe
> >>
> >
> > Hi Christophe,
> >
> > For a regular arm-none-eabi build, TLS is indeed disabled and the test 
> > should
> > be skipped. The diagnostic and test is meant to catch instances where the
> > toolchain has been built with native TLS enabled. This can be done either by
> > explicitly passing the --enable-tls configure flag for arm-none-eabi, or by
> 
> This didn't occur to me: what does --target arm-none-eabi --enable-tls 
> actually
> means in terms of functionality? Do you use newlib +  a suitable kernel to
> provide thread support? Or are all the tls-related GCC tests compile-only,
> and we do not need a setup with proper thread support to actually test this?
> 

Hi Christophe, the test is compile-only. Threading isn't really a thing in the
context of bare-metal code on a microcontroller, but this diagnostic is there
to prevent the compiler from generating garbage assembly even if the user is
going out of their way to do something nonsensical. The test exists to validate
that the diagnostic triggers under such conditions.

> > using an arm-none-linux-gnueabi[hf] toolchain and testing against an 
> > M-profile
> > target.
> I guess you use a board for that? As I'm using qemu (user mode) for GCC 
> testing,
> I'm not sure how I could test such a configuration given that qemu
> does not support
> any v7m processor to my knowledge.

As above, the execution target does not matter as there is no code to execute.
The compiler should simply error out if told to compile code with thread-local
variables and literal pools disabled.

-- 

Prakhar Bahuguna

Re: [PING][PATCH, GCC/ARM] Only test tls-disable-literal-pool.c if target supports native TLS

2017-05-30 Thread Prakhar Bahuguna 
On 29/05/2017 14:23:05, Christophe Lyon wrote:
> On 19 May 2017 at 14:29, Prakhar Bahuguna <prakhar.bahug...@arm.com> wrote:
> > On 11/05/2017 14:54:37, Prakhar Bahuguna wrote:
> >> tls-disable-literal-pool.c should only be run if the toolchain and target
> >> support native thread-local storage rather than emulated TLS. This patch 
> >> also
> >> improves the matching of the error message.
> >>
> >> testsuite/ChangeLog:
> >>
> >> 2017-05-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> >>
> >>   * gcc.target/arm/tls-disable-literal-pool.c: Change
> >>   require-effective-target to tls_native.
> >>   Move dg-error to return statement line and change to dg-message.
> >>
> >> Testing done: Regression testing for ARMv7-M with a TLS-enabled toolchain 
> >> and a
> >> TLS-disabled toolchain.
> >>
> 
> Hi,
> Can you share more details on the configuration you used?
> In my testing, the only cortex-M config I have is arm-none-eabi
> --with-cpu=cortex-m3.
> Since arm-none-eabi means native-tls is disabled, this test is skipped.
> A constraint for me is that m3 was the only cortex-m cpu supported by qemu the
> last time I checked.
> 
> Thanks,
> 
> Christophe
> 

Hi Christophe,

For a regular arm-none-eabi build, TLS is indeed disabled and the test should
be skipped. The diagnostic and test is meant to catch instances where the
toolchain has been built with native TLS enabled. This can be done either by
explicitly passing the --enable-tls configure flag for arm-none-eabi, or by
using an arm-none-linux-gnueabi[hf] toolchain and testing against an M-profile
target.

Hope this helps,

-- 

Prakhar Bahuguna

[PATCH, GCC/ARM/gcc-7-branch] Backport PR71607

2017-05-25 Thread Prakhar Bahuguna 
This patch tackles the issue reported in PR71607. This patch takes a different
approach for disabling the creation of literal pools. Instead of disabling the
patterns that would normally transform the rtl into actual literal pools, it
disables the creation of this literal pool rtl by making the target hook
TARGET_CANNOT_FORCE_CONST_MEM return true if arm_disable_literal_pool is true.
I added patterns to split floating point constants for both SF and DFmode. A
pattern to handle the addressing of label_refs had to be included as well since
all "memory_operand" patterns are disabled when TARGET_CANNOT_FORCE_CONST_MEM
returns true. Also the pattern for splitting 32-bit immediates had to be
changed, it was not accepting unsigned 32-bit unsigned integers with the MSB
set. I believe const_int_operand expects the mode of the operand to be set to
VOIDmode and not SImode. I have only changed it in the patterns that were
affecting this code, though I suggest looking into changing it in the rest of
the ARM backend.

Additionally, the use of thread-local storage is disabled if literal pools are
disabled, as there are no relocations for TLS variables and incorrect code is
generated as a result. The patch now emits a diagnostic in TLS-enabled
toolchains if a TLS symbol is found when -mpure-code or -mslow-flash-data are
enabled.

2017-05-25  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

Backport from mainline
2017-05-05  Andre Vieira  <andre.simoesdiasvie...@arm.com>
    Prakhar Bahuguna  <prakhar.bahug...@arm.com>

gcc/
PR target/71607
* config/arm/arm.md (use_literal_pool): Remove.
(64-bit immediate split): No longer takes cost into consideration
if arm_disable_literal_pool is enabled.
* config/arm/arm.c (arm_tls_referenced_p): Add diagnostic if TLS is
used when arm_disable_literal_pool is enabled.
(arm_max_const_double_inline_cost): Remove use of
arm_disable_literal_pool.
(push_minipool_fix): Add assert.
(arm_reorg): Add return if arm_disable_literal_pool is enabled.
* config/arm/vfp.md (no_literal_pool_df_immediate): New.
(no_literal_pool_sf_immediate): New.

2017-05-05  Andre Vieira  <andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>
Prakhar Bahuguna  <prakhar.bahug...@arm.com>

gcc/testsuite/
PR target/71607
* gcc.target/arm/thumb2-slow-flash-data.c: Renamed to ...
* gcc.target/arm/thumb2-slow-flash-data-1.c: ... this.
* gcc.target/arm/thumb2-slow-flash-data-2.c: New.
* gcc.target/arm/thumb2-slow-flash-data-3.c: New.
* gcc.target/arm/thumb2-slow-flash-data-4.c: New.
* gcc.target/arm/thumb2-slow-flash-data-5.c: New.
* gcc.target/arm/tls-disable-literal-pool.c: New.

Testing done: Ran regression tests for arm-eabi-none for ARMv7-M and ARMv8-M
targets. A bootstrap for arm-none-linux-gnueabihf was also successful.

-- 

Prakhar Bahuguna
>From 93ee5640b11cb7efbbe9aec53ce0d12d377c2be3 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Tue, 18 Apr 2017 14:16:46 +0100
Subject: [PATCH] PR71607: Fix ICE when loading constant

---
 gcc/config/arm/arm.c   | 21 +---
 gcc/config/arm/arm.md  |  9 ++
 gcc/config/arm/vfp.md  | 37 ++
 ...low-flash-data.c => thumb2-slow-flash-data-1.c} |  0
 .../gcc.target/arm/thumb2-slow-flash-data-2.c  | 28 
 .../gcc.target/arm/thumb2-slow-flash-data-3.c  | 25 +++
 .../gcc.target/arm/thumb2-slow-flash-data-4.c  | 26 +++
 .../gcc.target/arm/thumb2-slow-flash-data-5.c  | 14 
 .../gcc.target/arm/tls-disable-literal-pool.c  | 14 
 9 files changed, 163 insertions(+), 11 deletions(-)
 rename gcc/testsuite/gcc.target/arm/{thumb2-slow-flash-data.c => 
thumb2-slow-flash-data-1.c} (100%)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f3a6b64b168..ea371e27797 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8633,7 +8633,16 @@ arm_tls_referenced_p (rtx x)
 {
   const_rtx x = *iter;
   if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
-   return true;
+   {
+ /* ARM currently does not provide relocations to encode TLS variables
+into AArch32 instructions, only data, so there

[PING][PATCH, GCC/ARM] Only test tls-disable-literal-pool.c if target supports native TLS

2017-05-19 Thread Prakhar Bahuguna 
On 11/05/2017 14:54:37, Prakhar Bahuguna wrote:
> tls-disable-literal-pool.c should only be run if the toolchain and target
> support native thread-local storage rather than emulated TLS. This patch also
> improves the matching of the error message.
> 
> testsuite/ChangeLog:
> 
> 2017-05-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> 
>   * gcc.target/arm/tls-disable-literal-pool.c: Change
>   require-effective-target to tls_native.
>   Move dg-error to return statement line and change to dg-message.
> 
> Testing done: Regression testing for ARMv7-M with a TLS-enabled toolchain and 
> a
> TLS-disabled toolchain.
> 
> Okay for stage1?
> 
> -- 
> 
> Prakhar Bahuguna

> From 84837978d480a1abcebe7b4d2ac21af0eb6645b4 Mon Sep 17 00:00:00 2001
> From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
> Date: Thu, 11 May 2017 13:24:39 +0100
> Subject: [PATCH] Only test tls-disable-literal-pool.c if target supports
>  native TLS
> 
> This test should only be run if the toolchain and target support native
> thread-local storage rather than emulated TLS.
> ---
>  gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c 
> b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
> index fe14a6b132c..283201fdd97 100644
> --- a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
> +++ b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
> @@ -1,5 +1,5 @@
>  /* { dg-do compile } */
> -/* { dg-require-effective-target tls } */
> +/* { dg-require-effective-target tls_native } */
>  /* { dg-require-effective-target arm_cortex_m } */
>  /* { dg-require-effective-target arm_thumb2_ok } */
>  /* { dg-options "-mslow-flash-data" } */
> @@ -9,7 +9,6 @@ __thread int x = 0;
>  int
>  bar ()
>  {
> -  return x;
> +  return x; /* { dg-message "sorry, unimplemented: accessing thread-local 
> storage is not currently supported with -mpure-code or -mslow-flash-data" } */
>  }
>  
> -/* { dg-error "accessing thread-local storage is not currently supported 
> with -mpure-code or -mslow-flash-data" "" { target *-*-* } 12 } */
> -- 
> 2.11.0
> 

Ping.

-- 

Prakhar Bahuguna

Re: [PATCH, GCC/ARM, Stage 1] Add missing TARGET_32BIT conditional to movsi

2017-05-12 Thread Prakhar Bahuguna 
On 11/05/2017 10:58:52, Kyrill Tkachov wrote:
> 
> On 11/05/17 10:56, Prakhar Bahuguna wrote:
> > Resolve the regressions introduced on non-Thumb targets by the Purecode for
> > ARMv8-M Baseline patch. The TARGET_32BIT conditional has been re-added to 
> > the
> > movsi expander and splitter in addition to TARGET_HAVE_MOVT.
> > 
> > gcc/ChangeLog:
> > 
> > 2017-05-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > 
> > * config/arm/arm.md (movsi): Add TARGET_32BIT in addition to the
> > TARGET_HAVE_MOVT conditional.
> > (movt splitter): Likewise.
> > 
> > Testing done: Full regression testing for ARMv5 (including XScale), ARMv7-A,
> > ARMv7-M and ARMv8-M. The failing tests in particular 
> > (gcc.target/arm/scd42-2.c
> > and g++.dg/torture/vshuf-v4si.c) now pass and no further regressions were
> > found.
> 
> Ok if a bootstrap on arm-none-linux-gnueabihf target passes as well.
> 
> Thanks,
> Kyrill

Patch was committed in r247971 with one trivial change (brackets around the
conditionals), and an arm-none-linux-gnueabihf bootstrap was successful with
this modified patch.

-- 

Prakhar Bahuguna

[PATCH, GCC/ARM] Only test tls-disable-literal-pool.c if target supports native TLS

2017-05-11 Thread Prakhar Bahuguna 
tls-disable-literal-pool.c should only be run if the toolchain and target
support native thread-local storage rather than emulated TLS. This patch also
improves the matching of the error message.

testsuite/ChangeLog:

2017-05-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

* gcc.target/arm/tls-disable-literal-pool.c: Change
require-effective-target to tls_native.
Move dg-error to return statement line and change to dg-message.

Testing done: Regression testing for ARMv7-M with a TLS-enabled toolchain and a
TLS-disabled toolchain.

Okay for stage1?

-- 

Prakhar Bahuguna
>From 84837978d480a1abcebe7b4d2ac21af0eb6645b4 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Thu, 11 May 2017 13:24:39 +0100
Subject: [PATCH] Only test tls-disable-literal-pool.c if target supports
 native TLS

This test should only be run if the toolchain and target support native
thread-local storage rather than emulated TLS.
---
 gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c 
b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
index fe14a6b132c..283201fdd97 100644
--- a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
+++ b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target tls } */
+/* { dg-require-effective-target tls_native } */
 /* { dg-require-effective-target arm_cortex_m } */
 /* { dg-require-effective-target arm_thumb2_ok } */
 /* { dg-options "-mslow-flash-data" } */
@@ -9,7 +9,6 @@ __thread int x = 0;
 int
 bar ()
 {
-  return x;
+  return x; /* { dg-message "sorry, unimplemented: accessing thread-local 
storage is not currently supported with -mpure-code or -mslow-flash-data" } */
 }
 
-/* { dg-error "accessing thread-local storage is not currently supported with 
-mpure-code or -mslow-flash-data" "" { target *-*-* } 12 } */
-- 
2.11.0

[PATCH, GCC/ARM, Stage 1] Add missing TARGET_32BIT conditional to movsi

2017-05-11 Thread Prakhar Bahuguna 
Resolve the regressions introduced on non-Thumb targets by the Purecode for
ARMv8-M Baseline patch. The TARGET_32BIT conditional has been re-added to the
movsi expander and splitter in addition to TARGET_HAVE_MOVT.

gcc/ChangeLog:

2017-05-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

* config/arm/arm.md (movsi): Add TARGET_32BIT in addition to the
TARGET_HAVE_MOVT conditional.
(movt splitter): Likewise.

Testing done: Full regression testing for ARMv5 (including XScale), ARMv7-A,
ARMv7-M and ARMv8-M. The failing tests in particular (gcc.target/arm/scd42-2.c
and g++.dg/torture/vshuf-v4si.c) now pass and no further regressions were
found.

-- 

Prakhar Bahuguna
>From 6e19667cbe8f66b4a054c1243443a29845fb7397 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Thu, 11 May 2017 10:12:02 +0100
Subject: [PATCH] Add missing TARGET_32BIT conditional to movsi

Resolves the regressions introduced on non-Thumb targets by the Purecode
for ARMv8-M Baseline patch.
---
 gcc/config/arm/arm.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4a2b623e528..6c391347b68 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5969,7 +5969,7 @@
   {
   rtx base, offset, tmp;
 
-  if (TARGET_HAVE_MOVT)
+  if (TARGET_32BIT || TARGET_HAVE_MOVT)
 {
   /* Everything except mem = const or mem = mem can be done easily.  */
   if (MEM_P (operands[0]))
@@ -6093,7 +6093,7 @@
 (define_split
   [(set (match_operand:SI 0 "arm_general_register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
-  "TARGET_HAVE_MOVT
+  "TARGET_32BIT || TARGET_HAVE_MOVT
   && (!(const_ok_for_arm (INTVAL (operands[1]))
 || const_ok_for_arm (~INTVAL (operands[1]"
   [(clobber (const_int 0))]
-- 
2.11.0

Re: [PATCH, GCC/ARM, Stage 1] PR71607: Fix ICE when loading constant

2017-05-04 Thread Prakhar Bahuguna 
On 03/05/2017 11:30:13, Richard Earnshaw (lists) wrote:
> On 20/04/17 10:54, Prakhar Bahuguna wrote:
> > [ARM] PR71607: Fix ICE when loading constant
> > 
> > gcc/ChangeLog:
> > 
> > 2017-04-18  Andre Vieira  <andre.simoesdiasvie...@arm.com>
> > Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > 
> > PR target/71607
> > * config/arm/arm.md (use_literal_pool): Removes.
> > (64-bit immediate split): No longer takes cost into consideration
> > if 'arm_disable_literal_pool' is enabled.
> > * config/arm/arm.c (arm_tls_referenced_p): Add diagnostic if TLS is
> > used when arm_disable_literal_pool is enabled.
> > (arm_max_const_double_inline_cost): Remove use of
> > arm_disable_literal_pool.
> > (arm_reorg): Add return if arm_disable_literal_pool is enabled.
> > * config/arm/vfp.md (no_literal_pool_df_immediate): New.
> > (no_literal_pool_sf_immediate): New.
> > 
> > testsuite/ChangeLog:
> > 
> > 2017-04-18  Andre Vieira  <andre.simoesdiasvie...@arm.com>
> > Thomas Preud'homme  <thomas.preudho...@arm.com>
> > Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > 
> > PR target/71607
> > * gcc.target/arm/thumb2-slow-flash-data.c: Renamed to ...
> > * gcc.target/arm/thumb2-slow-flash-data-1.c: ... this.
> > * gcc.target/arm/thumb2-slow-flash-data-2.c: New.
> > * gcc.target/arm/thumb2-slow-flash-data-3.c: New.
> > * gcc.target/arm/thumb2-slow-flash-data-4.c: New.
> > * gcc.target/arm/thumb2-slow-flash-data-5.c: New.
> > * gcc.target/arm/tls-disable-literal-pool.c: New.
> > 
> > Okay for stage1?
> > 
> 
> This patch lacks a description of what's going on and why the change is
> necessary (it should stand alone from the PR data).  It's clearly a
> non-trivial change, so why have you adopted this approach?
> 
> R.
> 

Hi,

This patch is based off an earlier patch that was applied to the
embedded-6-branch, and I had neglected to include the full description, which
is presented below:

This patch tackles the issue reported in PR71607. This patch takes a different
approach for disabling the creation of literal pools. Instead of disabling the
patterns that would normally transform the rtl into actual literal pools, it
disables the creation of this literal pool rtl by making the target hook
TARGET_CANNOT_FORCE_CONST_MEM return true if arm_disable_literal_pool is true.
I added patterns to split floating point constants for both SF and DFmode. A
pattern to handle the addressing of label_refs had to be included as well since
all "memory_operand" patterns are disabled when TARGET_CANNOT_FORCE_CONST_MEM
returns true. Also the pattern for splitting 32-bit immediates had to be
changed, it was not accepting unsigned 32-bit unsigned integers with the MSB
set. I believe const_int_operand expects the mode of the operand to be set to
VOIDmode and not SImode. I have only changed it in the patterns that were
affecting this code, though I suggest looking into changing it in the rest of
the ARM backend.

Additionally, the use of thread-local storage is disabled if literal pools are
disabled, as there are no relocations for TLS variables and incorrect code is
generated as a result. The patch now emits a diagnostic in TLS-enabled
toolchains if a TLS symbol is found when -mpure-code or -mslow-flash-data are
enabled.

-- 

Prakhar Bahuguna

Re: [PATCH, GCC/ARM, Stage 1] Enable Purecode for ARMv8-M Baseline

2017-05-04 Thread Prakhar Bahuguna 
On 02/05/2017 16:20:50, Ramana Radhakrishnan wrote:
> On Tue, May 02, 2017 at 11:45:48AM +0100, Prakhar Bahuguna wrote:
> > This patch adds support for purecode to ARMv8-M Baseline, in addition to the
> > existing support for ARMv7-M and ARMv8-M Mainline.
> > 
> > gcc/ChangeLog:
> > 
> > 2017-01-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > Andre Simoes Dias Vieira  <andre.simoesdiasvie...@arm.com>
> > 
> > * config/arm/arm.md (movsi): Change TARGET_32BIT to TARGET_HAVE_MOVT.
> > (movt splitter): Likewise.
> > * config/arm/arm.c (arm_option_check_internal): Change arm_arch_thumb2
> > to TARGET_HAVE_MOVT, and merge with -mslow-flash-data check.
> > (const_ok_for_arm): Change else to else if (TARGET_THUMB2) and add else
> > block for Thumb-1 with MOVT.
> > (thumb2_legitimate_address_p): Move code block ...
> > (can_avoid_literal_pool_for_label_p): ... into this new function.
> > (thumb1_legitimate_address_p): Add check for TARGET_HAVE_MOVT and
> > literal pool.
> > (thumb_legitimate_constant_p): Add conditional on TARGET_HAVE_MOVT
> > 
> > doc/ChangeLog:
> > 
> > 2017-01-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > Andre Simoes Dias Vieira  <andre.simoesdiasvie...@arm.com>
> > 
> > * invoke.texi (-mpure-code): Change "ARMv7-M targets" for
> > "Thumb-only targets with the MOVT instruction".
> > 
> > testsuite/ChangeLog:
> > 
> > 2017-01-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> > Andre Simoes Dias Vieira  <andre.simoesdiasvie...@arm.com>
> > 
> > * gcc.target/arm/pure-code/pure-code.exp: Add conditional for
> > check_effective_target_arm_thumb1_movt_ok.
> > 
> > Testing done: Ran regression tests for arm-eabi-none targeting Cortex-M23, 
> > both
> > with and without -mpure-code.
> > 
> > Okay for stage 1?
> > 
> > -- 
> > 
> > Prakhar Bahuguna
> 
> > From a77336404fdbdc9ed9b836e4e164803915aa3b22 Mon Sep 17 00:00:00 2001
> > From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
> > Date: Wed, 15 Mar 2017 10:25:03 +
> > Subject: [PATCH] Enable Purecode for ARMv8-M Baseline.
> > 
> > ---
> >  gcc/config/arm/arm.c   | 77 
> > ++
> >  gcc/config/arm/arm.md  |  6 +-
> >  gcc/doc/invoke.texi|  3 +-
> >  .../gcc.target/arm/pure-code/pure-code.exp |  5 +-
> >  4 files changed, 57 insertions(+), 34 deletions(-)
> > 
> > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> > index d719020dcde..1088895e7e5 100644
> > --- a/gcc/config/arm/arm.c
> > +++ b/gcc/config/arm/arm.c
> > @@ -2833,16 +2833,15 @@ arm_option_check_internal (struct gcc_options *opts)
> >flag_pic = 0;
> >  }
> >  
> > -  /* We only support -mslow-flash-data on armv7-m targets.  */
> > -  if (target_slow_flash_data
> > -  && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
> > - || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
> > -error ("-mslow-flash-data only supports non-pic code on armv7-m 
> > targets");
> > -
> > -  /* We only support pure-code on Thumb-2 M-profile targets.  */
> > -  if (target_pure_code
> > -  && (!arm_arch_thumb2 || arm_arch_notm || flag_pic || TARGET_NEON))
> > -error ("-mpure-code only supports non-pic code on armv7-m targets");
> > +  /* We only support -mpure-code and -mslow-flash-data on Thumb-only 
> > targets
> > + with MOVT.  */
> 
> 
> It would be good to support this with movw / movt but without
> new relocations it's not possible.
> 
> 
> 
> > +  if ((target_pure_code || target_slow_flash_data)
> > +  && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
> > +{
> > +  const char *flag = (target_pure_code ? "-mpure-code" : 
> > "-mslow-flash-data");
> 
> Check line length here.
> 
>   const char *flag = (target_pure_code ? "-mpure-code"
>  : "-mslow-flash-data");
> 
> > +  error ("%s only supports non-pic code on Thumb-only targets with the 
> > "
> > +"MOVT instruction", flag);
> 
> I'd prefer the error message to be direct and say
> "M profile targets" instead of "Thumb-only targ

[PATCH, GCC/ARM, Stage 1] Enable Purecode for ARMv8-M Baseline

2017-05-02 Thread Prakhar Bahuguna 
This patch adds support for purecode to ARMv8-M Baseline, in addition to the
existing support for ARMv7-M and ARMv8-M Mainline.

gcc/ChangeLog:

2017-01-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
Andre Simoes Dias Vieira  <andre.simoesdiasvie...@arm.com>

* config/arm/arm.md (movsi): Change TARGET_32BIT to TARGET_HAVE_MOVT.
(movt splitter): Likewise.
* config/arm/arm.c (arm_option_check_internal): Change arm_arch_thumb2
to TARGET_HAVE_MOVT, and merge with -mslow-flash-data check.
(const_ok_for_arm): Change else to else if (TARGET_THUMB2) and add else
block for Thumb-1 with MOVT.
(thumb2_legitimate_address_p): Move code block ...
(can_avoid_literal_pool_for_label_p): ... into this new function.
(thumb1_legitimate_address_p): Add check for TARGET_HAVE_MOVT and
literal pool.
(thumb_legitimate_constant_p): Add conditional on TARGET_HAVE_MOVT

doc/ChangeLog:

2017-01-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
Andre Simoes Dias Vieira  <andre.simoesdiasvie...@arm.com>

* invoke.texi (-mpure-code): Change "ARMv7-M targets" for
"Thumb-only targets with the MOVT instruction".
    
testsuite/ChangeLog:

2017-01-11  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
Andre Simoes Dias Vieira  <andre.simoesdiasvie...@arm.com>

* gcc.target/arm/pure-code/pure-code.exp: Add conditional for
check_effective_target_arm_thumb1_movt_ok.

Testing done: Ran regression tests for arm-eabi-none targeting Cortex-M23, both
with and without -mpure-code.

Okay for stage 1?

-- 

Prakhar Bahuguna
>From a77336404fdbdc9ed9b836e4e164803915aa3b22 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Wed, 15 Mar 2017 10:25:03 +
Subject: [PATCH] Enable Purecode for ARMv8-M Baseline.

---
 gcc/config/arm/arm.c   | 77 ++
 gcc/config/arm/arm.md  |  6 +-
 gcc/doc/invoke.texi|  3 +-
 .../gcc.target/arm/pure-code/pure-code.exp |  5 +-
 4 files changed, 57 insertions(+), 34 deletions(-)

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d719020dcde..1088895e7e5 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2833,16 +2833,15 @@ arm_option_check_internal (struct gcc_options *opts)
   flag_pic = 0;
 }
 
-  /* We only support -mslow-flash-data on armv7-m targets.  */
-  if (target_slow_flash_data
-  && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
- || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
-error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
-
-  /* We only support pure-code on Thumb-2 M-profile targets.  */
-  if (target_pure_code
-  && (!arm_arch_thumb2 || arm_arch_notm || flag_pic || TARGET_NEON))
-error ("-mpure-code only supports non-pic code on armv7-m targets");
+  /* We only support -mpure-code and -mslow-flash-data on Thumb-only targets
+ with MOVT.  */
+  if ((target_pure_code || target_slow_flash_data)
+  && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
+{
+  const char *flag = (target_pure_code ? "-mpure-code" : 
"-mslow-flash-data");
+  error ("%s only supports non-pic code on Thumb-only targets with the "
+"MOVT instruction", flag);
+}
 
 }
 
@@ -4077,7 +4076,7 @@ const_ok_for_arm (HOST_WIDE_INT i)
   || (i & ~0xfc03) == 0))
return TRUE;
 }
-  else
+  else if (TARGET_THUMB2)
 {
   HOST_WIDE_INT v;
 
@@ -4093,6 +4092,14 @@ const_ok_for_arm (HOST_WIDE_INT i)
   if (i == v)
return TRUE;
 }
+  else if (TARGET_HAVE_MOVT)
+{
+  /* Thumb-1 Targets with MOVT.  */
+  if (i > 0x)
+   return FALSE;
+  else
+   return TRUE;
+}
 
   return FALSE;
 }
@@ -7736,6 +7743,32 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx 
x, RTX_CODE outer,
   return 0;
 }
 
+/* Return true if we can avoid creating a constant pool entry for x.  */
+bool
+can_avoid_literal_pool_for_label_p (rtx x)
+{
+  /* Normally we can assign constant values to target registers without
+ the help of constant pool.  But there are cases we have to use constant
+ pool like:
+ 1) assign a label to register.
+ 2) sign-extend a 8bit value to 32bit and then assign to register.
+
+ Constant pool access in format:
+ (set (reg r0) (mem (symbol_ref (".LC0"
+ will cause the use of literal pool (later in function arm_reorg).
+ So here we mark such format as an invalid format, then the compiler
+ will adjust it into:
+ (set (reg r0) (symbol_ref (".LC0")))
+ (set (reg r0) (mem (reg r0))).
+ No e

[PATCH, GCC/ARM, Stage 1] PR71607: Fix ICE when loading constant

2017-04-20 Thread Prakhar Bahuguna 
[ARM] PR71607: Fix ICE when loading constant

gcc/ChangeLog:

2017-04-18  Andre Vieira  <andre.simoesdiasvie...@arm.com>
    Prakhar Bahuguna  <prakhar.bahug...@arm.com>

PR target/71607
* config/arm/arm.md (use_literal_pool): Removes.
(64-bit immediate split): No longer takes cost into consideration
if 'arm_disable_literal_pool' is enabled.
* config/arm/arm.c (arm_tls_referenced_p): Add diagnostic if TLS is
used when arm_disable_literal_pool is enabled.
(arm_max_const_double_inline_cost): Remove use of
arm_disable_literal_pool.
(arm_reorg): Add return if arm_disable_literal_pool is enabled.
* config/arm/vfp.md (no_literal_pool_df_immediate): New.
(no_literal_pool_sf_immediate): New.

testsuite/ChangeLog:

2017-04-18  Andre Vieira  <andre.simoesdiasvie...@arm.com>
Thomas Preud'homme  <thomas.preudho...@arm.com>
Prakhar Bahuguna  <prakhar.bahug...@arm.com>

PR target/71607
* gcc.target/arm/thumb2-slow-flash-data.c: Renamed to ...
* gcc.target/arm/thumb2-slow-flash-data-1.c: ... this.
* gcc.target/arm/thumb2-slow-flash-data-2.c: New.
* gcc.target/arm/thumb2-slow-flash-data-3.c: New.
* gcc.target/arm/thumb2-slow-flash-data-4.c: New.
* gcc.target/arm/thumb2-slow-flash-data-5.c: New.
* gcc.target/arm/tls-disable-literal-pool.c: New.

Okay for stage1?

--

Prakhar Bahuguna
>From 985100bbf8f168ab9a88ca29869453844eb6b58e Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Tue, 18 Apr 2017 14:16:46 +0100
Subject: [PATCH] [ARM] PR71607: Fix ICE when loading constant

---
 gcc/config/arm/arm.c   | 20 +---
 gcc/config/arm/arm.md  |  9 ++
 gcc/config/arm/vfp.md  | 37 ++
 ...low-flash-data.c => thumb2-slow-flash-data-1.c} |  0
 .../gcc.target/arm/thumb2-slow-flash-data-2.c  | 28 
 .../gcc.target/arm/thumb2-slow-flash-data-3.c  | 25 +++
 .../gcc.target/arm/thumb2-slow-flash-data-4.c  | 26 +++
 .../gcc.target/arm/thumb2-slow-flash-data-5.c  | 14 
 .../gcc.target/arm/tls-disable-literal-pool.c  | 15 +
 9 files changed, 163 insertions(+), 11 deletions(-)
 rename gcc/testsuite/gcc.target/arm/{thumb2-slow-flash-data.c => 
thumb2-slow-flash-data-1.c} (100%)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
 create mode 100644 gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a2d80cfd645..01d8c52d8c5 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8633,7 +8633,16 @@ arm_tls_referenced_p (rtx x)
 {
   const_rtx x = *iter;
   if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
-   return true;
+   {
+ /* ARM currently does not provide relocations to encode TLS variables
+into AArch32 instructions, only data, so there is no way to
+currently implement these if a literal pool is disabled.  */
+ if (arm_disable_literal_pool)
+   sorry ("accessing thread-local storage is not currently supported "
+  "with -mpure-code or -mslow-flash-data");
+
+ return true;
+   }
 
   /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
 TLS offsets, not real symbol references.  */
@@ -16391,10 +16400,6 @@ push_minipool_fix (rtx_insn *insn, HOST_WIDE_INT 
address, rtx *loc,
 int
 arm_max_const_double_inline_cost ()
 {
-  /* Let the value get synthesized to avoid the use of literal pools.  */
-  if (arm_disable_literal_pool)
-return 99;
-
   return ((optimize_size || arm_ld_sched) ? 3 : 4);
 }
 
@@ -17341,6 +17346,11 @@ arm_reorg (void)
   if (!optimize)
 split_all_insns_noflow ();
 
+  /* Make sure we do not attempt to create a literal pool even though it should
+ no longer be necessary to create any.  */
+  if (arm_disable_literal_pool)
+return ;
+
   minipool_fix_head = minipool_fix_tail = NULL;
 
   /* The first insn must always be a note, or the code below won't
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 21cfe3a4c31..f9365cde504 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -233,10 +233,6 @@
   (match_test "arm_restrict_it"))
  (const_string "no")
 
- (and (eq_attr "use_literal_pool" "yes")
-  (match_test "arm_disable_literal_pool"))
- (const_string "

Re: [PATCH, GCC/ARM, Stage 1] Rename FPSCR builtins to correct names

2017-04-10 Thread Prakhar Bahuguna 
On 22/03/2017 10:46:30, Prakhar Bahuguna wrote:
> The GCC documentation in section 6.60.8 ARM Floating Point Status and Control
> Intrinsics states that the FPSCR register can be read and written to using the
> intrinsics __builtin_arm_get_fpscr and __builtin_arm_set_fpscr. However, these
> are misnamed within GCC itself and these intrinsic names are not recognised.
> This patch corrects the intrinsic names to match the documentation, and adds
> tests to verify these intrinsics generate the correct instructions.
> 
> Testing done: Ran regression tests on arm-none-eabi for Cortex-M4.
> 
> 2017-03-09  Prakhar Bahuguna  <prakhar.bahug...@arm.com>
> 
> gcc/ChangeLog:
> 
>   * gcc/config/arm/arm-builtins.c (arm_init_builtins): Rename
> __builtin_arm_ldfscr to __builtin_arm_get_fpscr, and rename
> __builtin_arm_stfscr to __builtin_arm_set_fpscr.
>   * gcc/testsuite/gcc.target/arm/fpscr.c: New file.
> 
> Okay for stage 1?
> 
> --
> 
> Prakhar Bahuguna

Bumping, could I get a review for this please?

Thanks,

--

Prakhar Bahuguna

[PATCH, GCC/ARM, Stage 1] Rename FPSCR builtins to correct names

2017-03-22 Thread Prakhar Bahuguna 
The GCC documentation in section 6.60.8 ARM Floating Point Status and Control
Intrinsics states that the FPSCR register can be read and written to using the
intrinsics __builtin_arm_get_fpscr and __builtin_arm_set_fpscr. However, these
are misnamed within GCC itself and these intrinsic names are not recognised.
This patch corrects the intrinsic names to match the documentation, and adds
tests to verify these intrinsics generate the correct instructions.

Testing done: Ran regression tests on arm-none-eabi for Cortex-M4.

2017-03-09  Prakhar Bahuguna  <prakhar.bahug...@arm.com>

gcc/ChangeLog:

* gcc/config/arm/arm-builtins.c (arm_init_builtins): Rename
  __builtin_arm_ldfscr to __builtin_arm_get_fpscr, and rename
  __builtin_arm_stfscr to __builtin_arm_set_fpscr.
* gcc/testsuite/gcc.target/arm/fpscr.c: New file.

Okay for stage 1?

--

Prakhar Bahuguna
>From 8359732084b5b5585d14b7fbdf70d3cfa4c6dda2 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahug...@arm.com>
Date: Wed, 8 Mar 2017 16:29:09 +
Subject: [PATCH] Rename FPSCR builtins to correct names

---
 gcc/config/arm/arm-builtins.c|  4 ++--
 gcc/testsuite/gcc.target/arm/fpscr.c | 16 
 2 files changed, 18 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/fpscr.c

diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index ca622519b7d..aef05d0127f 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -1860,10 +1860,10 @@ arm_init_builtins (void)
= build_function_type_list (unsigned_type_node, NULL);
 
   arm_builtin_decls[ARM_BUILTIN_GET_FPSCR]
-   = add_builtin_function ("__builtin_arm_ldfscr", ftype_get_fpscr,
+   = add_builtin_function ("__builtin_arm_get_fpscr", ftype_get_fpscr,
ARM_BUILTIN_GET_FPSCR, BUILT_IN_MD, NULL, 
NULL_TREE);
   arm_builtin_decls[ARM_BUILTIN_SET_FPSCR]
-   = add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
+   = add_builtin_function ("__builtin_arm_set_fpscr", ftype_set_fpscr,
ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, 
NULL_TREE);
 }
 
diff --git a/gcc/testsuite/gcc.target/arm/fpscr.c 
b/gcc/testsuite/gcc.target/arm/fpscr.c
new file mode 100644
index 000..7b4d71d72d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fpscr.c
@@ -0,0 +1,16 @@
+/* Test the fpscr builtins.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_fp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } 
} */
+/* { dg-add-options arm_fp } */
+
+void
+test_fpscr ()
+{
+  volatile unsigned int status = __builtin_arm_get_fpscr ();
+  __builtin_arm_set_fpscr (status);
+}
+
+/* { dg-final { scan-assembler "mrc\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */
+/* { dg-final { scan-assembler "mcr\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */
-- 
2.11.0