Re: [PING][RFC][PATCH] RL78 - Add predicates to reduce code bloat when accessing volatile memory.
On 09/05/14 21:20, DJ Delorie wrote: The key to the msp430 change is that I reviewed every pattern that used the predicates, and only changed the ones where the pattern was known to be volatile-safe. For the RL78, the devirtualizer may make a pattern non-volatile-safe, and many patterns are macros which are not always volatile-safe. So, just changing the predicates is probably not enough. Did you review every pattern that used the changed predicates, to ensure that they're each volatile safe? Hi, Well, I've done my best to confirm that it doesn't break anything. I've looked over the patterns as best I could and looked at the code being generated (obviously not every pattern is being used), which didn't show anything that seemed wrong, and I've had no issues with running the generated code. My understanding of 'volatile' is that even the resulting code I gave as an example is not actually volatile-safe: mova, !240 ora, #32 mov!240, a as the value stored in address 240 could change just before and/or just after the 'or', and get overwritten by the second move. Given that the 'bsf' and 'bcf' instructions (bit set/bit clear) have not been included in any patterns, that is as volatile-safe as it can get, isn't it? As I understand it, one of the reasons for having the virtual pass was to make the instruction set appear completely orthogonal. Why then, when every instruction can use every virtual register in any addressing mode, does it think that: movwr10, #240 movwax, r10 movwhl, ax mova, [hl] ora, #32 mov[hl], a is more volatile-safe? Unless I'm missing something (which I'm quite prepared to accept) it's not less volatile-safe but it's certainly more bloated, and makes further optimizations harder. Richard.
[PING][RFC][PATCH] RL78 - Add predicates to reduce code bloat when accessing volatile memory.
http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01108.html Original Message Subject: [RFC][PATCH] RL78 - Add predicates to reduce code bloat when accessing volatile memory. Date: Fri, 18 Apr 2014 21:15:01 +0200 From: Richard Hulme pepe...@yahoo.com To: GCC Patches gcc-patches@gcc.gnu.org Hi, This patch adds predicates (taken and renamed from the MSP430 backend) to allow more efficient code generation when accessing volatile memory turning this (for example): movwr10, #240 movwax, r10 movwhl, ax mov a, [hl] or a, #32 mov [hl], a into this: mov a, !240 or a, #32 mov !240, a Regards, Richard. 2014-04-18 Richard Hulme pepe...@yahoo.com * config/rl78/predicates.md (rl78_volatile_memory_operand): New (rl78_general_operand): New (rl78_nonimmediate_operand): New (rl78_any_operand): Now includes volatile memory (rl78_nonfar_operand): Likewise (rl78_nonfar_nonimm_operand): Likewise --- gcc/config/rl78/predicates.md | 26 +++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/gcc/config/rl78/predicates.md b/gcc/config/rl78/predicates.md index e564f43..29e3922 100644 --- a/gcc/config/rl78/predicates.md +++ b/gcc/config/rl78/predicates.md @@ -18,18 +18,38 @@ ;; along with GCC; see the file COPYING3. If not see ;; http://www.gnu.org/licenses/. -(define_predicate rl78_any_operand +(define_predicate rl78_volatile_memory_operand + (and (match_code mem) + (match_test (memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0), MEM_ADDR_SPACE (op) +) + +; TRUE for any valid general operand. We do this because +; general_operand refuses to match volatile memory refs. + +(define_predicate rl78_general_operand (ior (match_operand 0 general_operand) + (match_operand 0 rl78_volatile_memory_operand)) +) + +; Likewise for nonimmediate_operand. + +(define_predicate rl78_nonimmediate_operand + (ior (match_operand 0 nonimmediate_operand) + (match_operand 0 rl78_volatile_memory_operand)) +) + +(define_predicate rl78_any_operand + (ior (match_operand 0 rl78_general_operand) (match_code mem,const_int,const_double,reg)) ) (define_predicate rl78_nonfar_operand - (and (match_operand 0 general_operand) + (and (match_operand 0 rl78_general_operand) (not (match_test rl78_far_p (op ) (define_predicate rl78_nonfar_nonimm_operand - (and (match_operand 0 nonimmediate_operand) + (and (match_operand 0 rl78_nonimmediate_operand) (not (match_test rl78_far_p (op ) -- 1.7.9.5
[RFC][PATCH] RL78 - Add predicates to reduce code bloat when accessing volatile memory.
Hi, This patch adds predicates (taken and renamed from the MSP430 backend) to allow more efficient code generation when accessing volatile memory turning this (for example): movwr10, #240 movwax, r10 movwhl, ax mov a, [hl] or a, #32 mov [hl], a into this: mov a, !240 or a, #32 mov !240, a Regards, Richard. 2014-04-18 Richard Hulme pepe...@yahoo.com * config/rl78/predicates.md (rl78_volatile_memory_operand): New (rl78_general_operand): New (rl78_nonimmediate_operand): New (rl78_any_operand): Now includes volatile memory (rl78_nonfar_operand): Likewise (rl78_nonfar_nonimm_operand): Likewise --- gcc/config/rl78/predicates.md | 26 +++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/gcc/config/rl78/predicates.md b/gcc/config/rl78/predicates.md index e564f43..29e3922 100644 --- a/gcc/config/rl78/predicates.md +++ b/gcc/config/rl78/predicates.md @@ -18,18 +18,38 @@ ;; along with GCC; see the file COPYING3. If not see ;; http://www.gnu.org/licenses/. -(define_predicate rl78_any_operand +(define_predicate rl78_volatile_memory_operand + (and (match_code mem) + (match_test (memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0), MEM_ADDR_SPACE (op) +) + +; TRUE for any valid general operand. We do this because +; general_operand refuses to match volatile memory refs. + +(define_predicate rl78_general_operand (ior (match_operand 0 general_operand) + (match_operand 0 rl78_volatile_memory_operand)) +) + +; Likewise for nonimmediate_operand. + +(define_predicate rl78_nonimmediate_operand + (ior (match_operand 0 nonimmediate_operand) + (match_operand 0 rl78_volatile_memory_operand)) +) + +(define_predicate rl78_any_operand + (ior (match_operand 0 rl78_general_operand) (match_code mem,const_int,const_double,reg)) ) (define_predicate rl78_nonfar_operand - (and (match_operand 0 general_operand) + (and (match_operand 0 rl78_general_operand) (not (match_test rl78_far_p (op ) (define_predicate rl78_nonfar_nonimm_operand - (and (match_operand 0 nonimmediate_operand) + (and (match_operand 0 rl78_nonimmediate_operand) (not (match_test rl78_far_p (op ) -- 1.7.9.5
Re: [RFC][PATCH] RL78 - clean-up of missing operand mode warnings.
On 15/04/14 22:58, DJ Delorie wrote: I typically leave the mode off when the operand accepts a CONST_INT as I've had problems with patterns matching CONST_INTs otherwise, as CONST_INT rtx's do not have a mode (or have VOIDmode). (yes, I know gcc is supposed to accomodate that, but like I said, I've had problems...) Ok, that's fine. I was just trying to mop up one little bit of the sea of warnings. It seems a little inconsistent, however, that *movqi_real and *xorqi3_real don't specify modes but *movhi_real and *andqi_real/*iorqi_real do (and they also accept CONST_INTs). Not that I'm advocating generating more warnings, but my inner OCD likes consistency :) Richard.
[RFC][PATCH] RL78 - clean-up of missing operand mode warnings.
Hi, This patch cleans up some warnings when building due to missing operand modes. trampoline_init in rl78.md still produces warnings but I'm not entirely sure about how best to fix that insn and I didn't want to break anything. Regards, Richard 2014-04-15 Richard Hulme pepe...@yahoo.com * config/rl78/rl78.md (addsi3, addsi3_internal_virt, addsi3_internal_real, subsi3, subsi3_internal_virt, subsi3_internal_real): Add missing modes to operands. * config/rl78/rl78-real.md (*movqi_real, *xorqi3_real): Likewise. * config/rl78/rl78-virt.md (*movqi_virt, *xorqi3_vidr): Likewise. --- gcc/config/rl78/rl78-real.md |4 ++-- gcc/config/rl78/rl78-virt.md |4 ++-- gcc/config/rl78/rl78.md | 12 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/gcc/config/rl78/rl78-real.md b/gcc/config/rl78/rl78-real.md index 5d5c598..847a82d 100644 --- a/gcc/config/rl78/rl78-real.md +++ b/gcc/config/rl78/rl78-real.md @@ -45,7 +45,7 @@ (define_insn *movqi_real [(set (match_operand:QI 0 nonimmediate_operand =g,RaxbcWab,RaxbcWab,a, bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx) - (match_operand1 general_operand 0,K,M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R))] + (match_operand:QI 1 general_operand 0,K,M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R))] rl78_real_insns_ok () @ ; mov\t%0, %1 @@ -194,7 +194,7 @@ (define_insn *xorqi3_real [(set (match_operand:QI 0 nonimmediate_operand =A,R,v) (xor:QI (match_operand:QI 1 general_operand %0,0,0) - (match_operand2 general_operand iRvWabWhbWh1Whl,A,i))) + (match_operand:QI 2 general_operand iRvWabWhbWh1Whl,A,i))) ] rl78_real_insns_ok () xor\t%0, %2 diff --git a/gcc/config/rl78/rl78-virt.md b/gcc/config/rl78/rl78-virt.md index 1db3751..189cf79 100644 --- a/gcc/config/rl78/rl78-virt.md +++ b/gcc/config/rl78/rl78-virt.md @@ -35,7 +35,7 @@ (define_insn *movqi_virt [(set (match_operand:QI 0 nonimmediate_operand =vY,v,Wfr) - (match_operand1 general_operand vInt8JY,Wfr,vInt8J))] + (match_operand:QI 1 general_operand vInt8JY,Wfr,vInt8J))] rl78_virt_insns_ok () v.mov %0, %1 [(set_attr valloc op1)] @@ -126,7 +126,7 @@ (define_insn *xor3_virt [(set (match_operand:QI 0 rl78_nonfar_nonimm_operand =v,vm,m) (xor:QI (match_operand:QI 1 rl78_nonfar_operand %0,vm,vm) - (match_operand2 general_operand i,vm,vim))) + (match_operand:QI 2 general_operand i,vm,vim))) ] rl78_virt_insns_ok () v.xor\t%0, %1, %2 diff --git a/gcc/config/rl78/rl78.md b/gcc/config/rl78/rl78.md index eb4c468..ede4eac 100644 --- a/gcc/config/rl78/rl78.md +++ b/gcc/config/rl78/rl78.md @@ -208,7 +208,7 @@ (define_expand addsi3 [(set (match_operand:SI 0 nonimmediate_operand =vm) (plus:SI (match_operand:SI 1 general_operand vim) -(match_operand2 general_operand vim))) +(match_operand:SI 2 general_operand vim))) ] emit_insn (gen_addsi3_internal_virt (operands[0], operands[1], operands[2])); @@ -218,7 +218,7 @@ (define_insn addsi3_internal_virt [(set (match_operand:SI 0 nonimmediate_operand =v,vm, vm) (plus:SI (match_operand:SI 1 general_operand 0, vim, vim) -(match_operand2 general_operand vim,vim,vim))) +(match_operand:SI 2 general_operand vim,vim,vim))) (clobber (reg:HI AX_REG)) (clobber (reg:HI BC_REG)) ] @@ -230,7 +230,7 @@ (define_insn addsi3_internal_real [(set (match_operand:SI 0 nonimmediate_operand =v,vU, vU) (plus:SI (match_operand:SI 1 general_operand +0, viU, viU) - (match_operand2 general_operand viWabWhlWh1,viWabWhlWh1,viWabWhlWh1))) + (match_operand:SI 2 general_operand viWabWhlWh1,viWabWhlWh1,viWabWhlWh1))) (clobber (reg:HI AX_REG)) (clobber (reg:HI BC_REG)) ] @@ -245,7 +245,7 @@ (define_expand subsi3 [(set (match_operand:SI 0 nonimmediate_operand =vm) (minus:SI (match_operand:SI 1 general_operand vim) - (match_operand2 general_operandvim))) + (match_operand:SI 2 general_operandvim))) ] emit_insn (gen_subsi3_internal_virt (operands[0], operands[1], operands[2])); @@ -255,7 +255,7 @@ (define_insn subsi3_internal_virt [(set (match_operand:SI 0 nonimmediate_operand =v,vm, vm) (minus:SI (match_operand:SI 1 general_operand 0, vim, vim) - (match_operand2 general_operand vim,vim,vim))) + (match_operand:SI 2 general_operand vim,vim,vim))) (clobber (reg:HI AX_REG)) (clobber (reg:HI BC_REG)) ] @@ -267,7 +267,7 @@ (define_insn subsi3_internal_real [(set (match_operand:SI
Re: [PATCH] RL78 - minor size optimization
On 28/03/14 00:20, DJ Delorie wrote:
This is OK after 4.9 branches (i.e. stage1). I suspect we could add
AX to the first alternative, although I don't know if it will get
used. We could add HL to the second alternative to complete the
replacement of the 'r' constraint.
Yes, the missing AX in the first alternative came to me later too. HL
is already in the second alternative ('T').
Looking at it again, it probably makes sense to change the third
alternative to 'shrw %0,8'. It's the same length as mov x,a/clrb a but
it's a cycle shorter. It also makes it more like the extendqihi2_real
insn, which isn't especially important, but does mean there's a certain
symmetry about it.
2014-03-28 Richard Hulme pepe...@yahoo.com
* config/rl78/rl78-real.md (zero_extendqihi2_real):
Minor optimizations to use clrb instruction where possible,
which is 1 byte shorter than 'mov'ing #0, and shrw, which
is 1 cycle less than a mov/clrb sequence.
---
gcc/config/rl78/rl78-real.md |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rl78/rl78-real.md b/gcc/config/rl78/rl78-real.md
index 27ff60f..5d5c598 100644
--- a/gcc/config/rl78/rl78-real.md
+++ b/gcc/config/rl78/rl78-real.md
@@ -77,12 +77,14 @@
;;-- Conversions
(define_insn *zero_extendqihi2_real
- [(set (match_operand:HI 0 nonimmediate_operand =rv,A)
- (zero_extend:HI (match_operand:QI 1 general_operand 0,a)))]
+ [(set (match_operand:HI 0 nonimmediate_operand
=ABv,DT,A,B)
+ (zero_extend:HI (match_operand:QI 1 general_operand 0,0,a,b)))]
rl78_real_insns_ok ()
@
+ clrb\t%Q0
mov\t%Q0, #0
- mov\tx, a \;mov\ta, #0
+ shrw\t%0, 8
+ shrw\t%0, 8
)
(define_insn *extendqihi2_real
--
1.7.9.5
[PATCH] RL78 - minor size optimization
Hi, This patch is a small optimization for the RL78 target that uses the 'clrb' instruction where possible when performing a zero-extend instead of 'mov'ing a literal #0. This saves a byte on each operation. Regards, Richard 2014-03-27 Richard Hulme pepe...@yahoo.com * config/rl78/rl78-real.md (zero_extendqihi2_real): Minor optimization to use clrb instruction where possible, which is 1 byte shorter than 'mov'ing #0. --- gcc/config/rl78/rl78-real.md |7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/config/rl78/rl78-real.md b/gcc/config/rl78/rl78-real.md index 27ff60f..3503a02 100644 --- a/gcc/config/rl78/rl78-real.md +++ b/gcc/config/rl78/rl78-real.md @@ -77,12 +77,13 @@ ;;-- Conversions (define_insn *zero_extendqihi2_real - [(set (match_operand:HI 0 nonimmediate_operand =rv,A) - (zero_extend:HI (match_operand:QI 1 general_operand 0,a)))] + [(set (match_operand:HI 0 nonimmediate_operand =Bv,DT,A) + (zero_extend:HI (match_operand:QI 1 general_operand 0,0,a)))] rl78_real_insns_ok () @ + clrb\t%Q0 mov\t%Q0, #0 - mov\tx, a \;mov\ta, #0 + mov\tx, a \;clrb\ta ) (define_insn *extendqihi2_real -- 1.7.9.5
