Re: [committed] Get avr building again
Jeff Law via Gcc-patches writes: > Removes references to CC_STATUS_INIT from the avr port, which should get > it to the point of building again. > > > Committed to the trunk. Thanks, I was about to send a patch for that. Regards Senthil > > > Jeff
Re: [Ping, PATCH 2/n] AVR CC0 conversion - adjust peepholes
Could someone please approve this patch too? The base conversion patch (https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568658.html) was approved and committed, and fixing peepholes addresses a bunch of code size regressions introduced by the base patch. No regressions on all 4 devices, as mentioned in the base patch submission. Regards Senthil Senthil Kumar Selvaraj writes: > Applies cleanly on rebased version of previous patch > (https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568658.html). > > Senthil Kumar Selvaraj writes: > >> Hi, >> >> This patch, to be applied on top of >> https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html, >> adjusts peepholes to match and generate parallels with a clobber of >> REG_CC. >> >> It also sets mov_insn as the name of the pattern for the split >> insn (rather than the define_insn_and_split), so that >> avr_2word_insn_p, which looks for CODE_FOR_mov_insn, works >> correctly. This is required for the *cpse.eq peephole to fire, and >> also helps generate better code for avr_out_sbxx_branch. >> >> There are no regressions, and the number of test cases reporting >> UNSUPPORTED or FAIL because of code size changes (when compared to >> mainline) for attiny40 and atmega8 are now down to 3 and 3, >> respectively, from 10 and 25 previously. >> >> The embench-iot numbers also show a good improvement. >> >> Benchmark Baseline Current Increase % >> - --- -- >> aha-mont64 6,944 6,944 0 >> crc32 704 706 0.28 >> cubic 9,428 9,428 0 >> edn 3,854 3,854 0 >> huffbench 2,890 2,890 0 >> matmult-int 1,164 1,164 0 >> minver 3,960 3,956 -0.1 >> nbody 3,106 3,110 0.13 >> nettle-aes 5,292 5,304 0.23 >> nettle-sha256 25,748 25,748 0 >> nsichneu 39,622 39,622 0 >> picojpeg9,898 9,980 0.83 >> qrduino 9,234 9,356 1.32 >> sglib-combined 4,658 4,658 0 >> slre4,000 4,000 0 >> st 3,356 3,356 0 >> statemate 5,490 5,502 0.22 >> ud 2,940 2,940 0 >> wikisort 20,776 20,772 -0.02 >> >> Regards >> Senthil >> >> >> gcc/ChangeLog: >> >> * config/avr/avr.md: Adjust peepholes to match and >> generate parallels with clobber of REG_CC. >> (mov_insn): Rename to mov_insn_split. >> (*mov_insn): Rename to mov_insn. >> >> >> diff --git gcc/config/avr/avr.md gcc/config/avr/avr.md >> index 2206fa19671..a1a325b7a8c 100644 >> --- gcc/config/avr/avr.md >> +++ gcc/config/avr/avr.md >> @@ -724,9 +724,7 @@ (define_expand "mov" >> ;; are call-saved registers, and most of LD_REGS are call-used registers, >> ;; so this may still be a win for registers live across function calls. >> >> -;; "movqi_insn" >> -;; "movqq_insn" "movuqq_insn" >> -(define_insn_and_split "mov_insn" >> +(define_insn_and_split "mov_insn_split" >>[(set (match_operand:ALL1 0 "nonimmediate_operand" "=r,d,Qm ,r >> ,q,r,*r") >> (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r >> Y00,Qm,r,q,i"))] >>"register_operand (operands[0], mode) >> @@ -737,7 +735,9 @@ (define_insn_and_split "mov_insn" >> (match_dup 1)) >>(clobber (reg:CC REG_CC))])]) >> >> -(define_insn "*mov_insn" >> +;; "movqi_insn" >> +;; "movqq_insn" "movuqq_insn" >> +(define_insn "mov_insn" >>[(set (match_operand:ALL1 0 "nonimmediate_operand" "=r,d,Qm ,r >> ,q,r,*r") >> (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r >> Y00,Qm,r,q,i")) >> (clobber (reg:CC REG_CC))] >> @@ -758,7 +758,8 @@ (define_insn "*mov_insn" >> (define_insn "*reload_in" >>[(set (match_operand:ALL1 0 "register_operand""=l") >> (match_operand:ALL1 1 "const_operand""i")) >> - (clobber (match_operand:QI 2 "register_operand" "="))] >> + (clobber (match_operand:QI 2 "register_operand" "=")) >> + (clobber (reg:CC REG_CC))] >>"reload_completed" >>"ldi %2,lo8(%1) >> mov %0,%2" >> @@ -766,15 +767,17 @@ (define_insn "*reload_in" >> >> (define_peephole2 >>[(match_scratch:QI 2 "d") >> - (set (match_operand:ALL1 0 "l_register_operand" "") >> -(match_operand:ALL1 1 "const_operand" ""))] >> + (parallel [(set (match_operand:ALL1 0 "l_register_operand" "") >> + (match_operand:ALL1 1 "const_operand" "")) >> + (clobber (reg:CC REG_CC))])] >>; No need for a clobber reg for 0x0, 0x01 or 0xff >>"!satisfies_constraint_Y00 (operands[1]) >> && !satisfies_constraint_Y01 (operands[1]) >> && !satisfies_constraint_Ym1 (operands[1])" >>[(parallel [(set (match_dup 0) >> (match_dup 1)) >> - (clobber (match_dup 2))])]) >> +
Re: [Ping] AVR CC0 conversion
John Paul Adrian Glaubitz writes: > On 4/28/21 7:59 PM, Senthil Kumar Selvaraj wrote: OK for trunk. >>> >>> Anything else that keeps us from merging the changes? Would be great to >>> have the last backend besides CR-16 finally converted to MODE_CC on trunk. >> >> Nope. Committed and pushed just now - >> https://gcc.gnu.org/git?p=gcc.git;a=commit;h=3ba781d3b5c8efadb60866c9743b657e8f0eb222 > > Awesome \o/. Should we wait for the second patch [1] to be merged as well > before closing the PR? [2] I guess it depends on the scope of the PR? If it was about removing cc0, then this patch would do. If it was about getting the generated code also to be as close to what it was with cc0, then no, it cannot be closed. OTOH, while the second patch (adjusting peepholes) does help, there are other things in the pipeline - addition of new CC modes and enabling compare elimination, adjusting rtx costs etc. I will continue to work on them in my spare time and submit patches when ready. Regards Senthil > > Adrian > >> [1] https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568659.html >> [2] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92729
Re: [Ping] AVR CC0 conversion
John Paul Adrian Glaubitz writes: > Hi Senthil! > >> On Mon, Apr 26, 2021 at 9:20 AM Senthil Kumar Selvaraj via Gcc-patches >> wrote: >>> >>> Hi, >>> >>> This is >>> https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html, >>> rebased against latest gcc master. The only change is modification of >>> avr_md_asm_adjust's signature to match the extra input_modes parameter >>> that TARGET_MD_ASM_ADJUST gained. >>> >>> I re-ran regression tests for atmega128, atxmega128a3, attiny40 and >>> atmega8 (after applying >>> https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563779.html >>> also) and verified that the results matched the original patchset. >> >> OK for trunk. > > Anything else that keeps us from merging the changes? Would be great to > have the last backend besides CR-16 finally converted to MODE_CC on trunk. Nope. Committed and pushed just now - https://gcc.gnu.org/git?p=gcc.git;a=commit;h=3ba781d3b5c8efadb60866c9743b657e8f0eb222 Regards Senthil > > Adrian
[Ping, PATCH 2/n] AVR CC0 conversion - adjust peepholes
Applies cleanly on rebased version of previous patch (https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568658.html). Senthil Kumar Selvaraj writes: > Hi, > > This patch, to be applied on top of > https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html, > adjusts peepholes to match and generate parallels with a clobber of > REG_CC. > > It also sets mov_insn as the name of the pattern for the split > insn (rather than the define_insn_and_split), so that > avr_2word_insn_p, which looks for CODE_FOR_mov_insn, works > correctly. This is required for the *cpse.eq peephole to fire, and > also helps generate better code for avr_out_sbxx_branch. > > There are no regressions, and the number of test cases reporting > UNSUPPORTED or FAIL because of code size changes (when compared to > mainline) for attiny40 and atmega8 are now down to 3 and 3, > respectively, from 10 and 25 previously. > > The embench-iot numbers also show a good improvement. > > Benchmark Baseline Current Increase % > - --- -- > aha-mont64 6,944 6,944 0 > crc32 704 706 0.28 > cubic 9,428 9,428 0 > edn 3,854 3,854 0 > huffbench 2,890 2,890 0 > matmult-int 1,164 1,164 0 > minver 3,960 3,956 -0.1 > nbody 3,106 3,110 0.13 > nettle-aes 5,292 5,304 0.23 > nettle-sha256 25,748 25,748 0 > nsichneu 39,622 39,622 0 > picojpeg9,898 9,980 0.83 > qrduino 9,234 9,356 1.32 > sglib-combined 4,658 4,658 0 > slre4,000 4,000 0 > st 3,356 3,356 0 > statemate 5,490 5,502 0.22 > ud 2,940 2,940 0 > wikisort 20,776 20,772 -0.02 > > Regards > Senthil > > > gcc/ChangeLog: > > * config/avr/avr.md: Adjust peepholes to match and > generate parallels with clobber of REG_CC. > (mov_insn): Rename to mov_insn_split. > (*mov_insn): Rename to mov_insn. > > > diff --git gcc/config/avr/avr.md gcc/config/avr/avr.md > index 2206fa19671..a1a325b7a8c 100644 > --- gcc/config/avr/avr.md > +++ gcc/config/avr/avr.md > @@ -724,9 +724,7 @@ (define_expand "mov" > ;; are call-saved registers, and most of LD_REGS are call-used registers, > ;; so this may still be a win for registers live across function calls. > > -;; "movqi_insn" > -;; "movqq_insn" "movuqq_insn" > -(define_insn_and_split "mov_insn" > +(define_insn_and_split "mov_insn_split" >[(set (match_operand:ALL1 0 "nonimmediate_operand" "=r,d,Qm ,r > ,q,r,*r") > (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r > Y00,Qm,r,q,i"))] >"register_operand (operands[0], mode) > @@ -737,7 +735,9 @@ (define_insn_and_split "mov_insn" > (match_dup 1)) >(clobber (reg:CC REG_CC))])]) > > -(define_insn "*mov_insn" > +;; "movqi_insn" > +;; "movqq_insn" "movuqq_insn" > +(define_insn "mov_insn" >[(set (match_operand:ALL1 0 "nonimmediate_operand" "=r,d,Qm ,r > ,q,r,*r") > (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r > Y00,Qm,r,q,i")) > (clobber (reg:CC REG_CC))] > @@ -758,7 +758,8 @@ (define_insn "*mov_insn" > (define_insn "*reload_in" >[(set (match_operand:ALL1 0 "register_operand""=l") > (match_operand:ALL1 1 "const_operand""i")) > - (clobber (match_operand:QI 2 "register_operand" "="))] > + (clobber (match_operand:QI 2 "register_operand" "=")) > + (clobber (reg:CC REG_CC))] >"reload_completed" >"ldi %2,lo8(%1) > mov %0,%2" > @@ -766,15 +767,17 @@ (define_insn "*reload_in" > > (define_peephole2 >[(match_scratch:QI 2 "d") > - (set (match_operand:ALL1 0 "l_register_operand" "") > -(match_operand:ALL1 1 "const_operand" ""))] > + (parallel [(set (match_operand:ALL1 0 "l_register_operand" "") > + (match_operand:ALL1 1 "const_operand" "")) > + (clobber (reg:CC REG_CC))])] >; No need for a clobber reg for 0x0, 0x01 or 0xff >"!satisfies_constraint_Y00 (operands[1]) > && !satisfies_constraint_Y01 (operands[1]) > && !satisfies_constraint_Ym1 (operands[1])" >[(parallel [(set (match_dup 0) > (match_dup 1)) > - (clobber (match_dup 2))])]) > + (clobber (match_dup 2)) > + (clobber (reg:CC REG_CC))])]) > > > ;; > ;; move word (16 bit) > @@ -804,12 +807,14 @@ (define_insn "movhi_sp_r" > > (define_peephole2 >[(match_scratch:QI 2 "d") > - (set (match_operand:ALL2 0 "l_register_operand" "") > -(match_operand:ALL2 1 "const_or_immediate_operand" ""))] > + (parallel [(set (match_operand:ALL2 0 "l_register_operand" "") > +
[PATCH 2/n] AVR CC0 conversion - adjust peepholes
Hi, This patch, to be applied on top of https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html, adjusts peepholes to match and generate parallels with a clobber of REG_CC. It also sets mov_insn as the name of the pattern for the split insn (rather than the define_insn_and_split), so that avr_2word_insn_p, which looks for CODE_FOR_mov_insn, works correctly. This is required for the *cpse.eq peephole to fire, and also helps generate better code for avr_out_sbxx_branch. There are no regressions, and the number of test cases reporting UNSUPPORTED or FAIL because of code size changes (when compared to mainline) for attiny40 and atmega8 are now down to 3 and 3, respectively, from 10 and 25 previously. The embench-iot numbers also show a good improvement. Benchmark Baseline Current Increase % - --- -- aha-mont64 6,944 6,944 0 crc32 704 706 0.28 cubic 9,428 9,428 0 edn 3,854 3,854 0 huffbench 2,890 2,890 0 matmult-int 1,164 1,164 0 minver 3,960 3,956 -0.1 nbody 3,106 3,110 0.13 nettle-aes 5,292 5,304 0.23 nettle-sha256 25,748 25,748 0 nsichneu 39,622 39,622 0 picojpeg9,898 9,980 0.83 qrduino 9,234 9,356 1.32 sglib-combined 4,658 4,658 0 slre4,000 4,000 0 st 3,356 3,356 0 statemate 5,490 5,502 0.22 ud 2,940 2,940 0 wikisort 20,776 20,772 -0.02 Regards Senthil gcc/ChangeLog: * config/avr/avr.md: Adjust peepholes to match and generate parallels with clobber of REG_CC. (mov_insn): Rename to mov_insn_split. (*mov_insn): Rename to mov_insn. diff --git gcc/config/avr/avr.md gcc/config/avr/avr.md index 2206fa19671..a1a325b7a8c 100644 --- gcc/config/avr/avr.md +++ gcc/config/avr/avr.md @@ -724,9 +724,7 @@ (define_expand "mov" ;; are call-saved registers, and most of LD_REGS are call-used registers, ;; so this may still be a win for registers live across function calls. -;; "movqi_insn" -;; "movqq_insn" "movuqq_insn" -(define_insn_and_split "mov_insn" +(define_insn_and_split "mov_insn_split" [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r,d,Qm ,r ,q,r,*r") (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i"))] "register_operand (operands[0], mode) @@ -737,7 +735,9 @@ (define_insn_and_split "mov_insn" (match_dup 1)) (clobber (reg:CC REG_CC))])]) -(define_insn "*mov_insn" +;; "movqi_insn" +;; "movqq_insn" "movuqq_insn" +(define_insn "mov_insn" [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r,d,Qm ,r ,q,r,*r") (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i")) (clobber (reg:CC REG_CC))] @@ -758,7 +758,8 @@ (define_insn "*mov_insn" (define_insn "*reload_in" [(set (match_operand:ALL1 0 "register_operand""=l") (match_operand:ALL1 1 "const_operand""i")) - (clobber (match_operand:QI 2 "register_operand" "="))] + (clobber (match_operand:QI 2 "register_operand" "=")) + (clobber (reg:CC REG_CC))] "reload_completed" "ldi %2,lo8(%1) mov %0,%2" @@ -766,15 +767,17 @@ (define_insn "*reload_in" (define_peephole2 [(match_scratch:QI 2 "d") - (set (match_operand:ALL1 0 "l_register_operand" "") -(match_operand:ALL1 1 "const_operand" ""))] + (parallel [(set (match_operand:ALL1 0 "l_register_operand" "") + (match_operand:ALL1 1 "const_operand" "")) + (clobber (reg:CC REG_CC))])] ; No need for a clobber reg for 0x0, 0x01 or 0xff "!satisfies_constraint_Y00 (operands[1]) && !satisfies_constraint_Y01 (operands[1]) && !satisfies_constraint_Ym1 (operands[1])" [(parallel [(set (match_dup 0) (match_dup 1)) - (clobber (match_dup 2))])]) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])]) ;; ;; move word (16 bit) @@ -804,12 +807,14 @@ (define_insn "movhi_sp_r" (define_peephole2 [(match_scratch:QI 2 "d") - (set (match_operand:ALL2 0 "l_register_operand" "") -(match_operand:ALL2 1 "const_or_immediate_operand" ""))] + (parallel [(set (match_operand:ALL2 0 "l_register_operand" "") + (match_operand:ALL2 1 "const_or_immediate_operand" "")) + (clobber (reg:CC REG_CC))])] "operands[1] != CONST0_RTX (mode)" [(parallel [(set (match_dup 0) (match_dup 1)) - (clobber (match_dup 2))])]) + (clobber (match_dup 2)) + (clobber (reg:CC REG_CC))])]) ;; '*' because it is not used in
Re: [PATCH] avr: cc0 to mode_cc conversion
Senthil Kumar Selvaraj writes: > Georg-Johann Lay writes: > >> >> Finally, some general remarks: > > The work on my github branch was not complete - I'd blindly followed > whatever the CC0 Transition wiki mentioned (the first three steps of > case #2), and fixed any regression fallout (for ATmega128). > > I intend to try out a define_subst/early clobber of reg_cc based > approach (inspired by the cris port) and see if that can help avoid the > proliferation of define_insn_and_splits. Will update how that works out. I had some time this past week to try implementing some of the changes you suggested. > >> >> 2) We just saw 100reds of insns being dublicated, basically the whole >> machine description except for the few insns that leave cc alone. >> Isn't is possible to use define subst for the bulk of the insns and >> get a neat code that's better to grasp and to maintain? >> After all it's just appending a clobber of reg_cc, and in the current >> proposal almost 50% of the backend is just redundent repetitions of >> previous insns. I could not find a way to get define_subst to do define_insn_and_split - other targets using the same approach (pdp11, h8300) have the duplication as well. >> >> 4) Many insns don't have reloads and don't need to be turned into a >> splitter + yet another insns, it should be all right to clobber >> reg_cc from the very start. Or am I missing something? I think >> I marked all places, but it should be easy enough to spot them. If I remove the define_insn_and_split and add a (clobber (reg:CC REG_CC)) to the define_insn itself for xcall patterns, then the producer of the pattern (define_expand, output template of define-insn-and-split/define-split etc.. or C code) needs to modified to include the clobber of REG_CC in a PARALLEL, so that's a whole bunch of changes. If that is done at define_expand, for example, then similar patterns that do not use the hard regs (non-call variants) will also need to be modified to add the clobber, and therefore there's no point in define_insn without clobber and split after reload with clobber for those patterns. Did I get that right? FWIW, I'm also working on a parallel implementation that clobbers REG_CC in all patterns from the start (with matching clobbers in define_expand etc..) - still not in good enough shape though. It will avoid duplication, but at the expense of modification of nearly every pattern to emit or accept a clobber of REG_CC. Regards Senthil
Re: [PATCH] emit-rtl.c: Allow splitting of RTX_FRAME_RELATED_P insns?
Richard Sandiford writes:
> Senthil Kumar via Gcc-patches writes:
>> Hi,
>>
>> I'm working on converting the AVR backend to MODE_CC, following
>> the steps described for case #2 in the CC0 transition wiki page,
>> and I've implemented the first three bullet
>> points (https://github.com/saaadhu/gcc-avr-cc0/tree/avr-cc0-squashed). With
>> the below patch, there are zero regressions (for mega and xmega
>> subarchs) compared to the current mainline, as of yesterday.
>>
>> The wiki suggests using post-reload splitters, so that's the
>> direction I took, but I ran into an issue where split_insn
>> bails out early if RTX_FRAME_RELATED_P is true - this means
>> that splits for REG_CC clobbering insns with
>> RTX_FRAME_RELATED_P will never execute, resulting in a
>> could-not-split insn ICE in the final stage.
>>
>> I see that the recog.c:peep2_attempt allows splitting of a
>> RTX_FRAME_RELATED_P insn, provided the result of the split is a
>> single insn. Would it be ok to modify try_split also to
>> allow those kinds of insns (tentative patch attached, code
>> copied over from peep2_attempt, only setting old and new_insn)? Or is there
>> a different approach to fix this?
>
> I agree there's no obvious reason why splitting to a single insn
> should be rejected but a peephole2 to a single instruction should be OK.
> And reusing the existing, tried-and-tested code is the way to go.
>
> But could you split the code out of peep2_attempt into a subroutine
> (probably still in recog.c) and reuse it in try_split?
How does the below patch look? Bootstrapped and reg tested on
x86_64-linux.
>
> BTW, just to check: is your email address in MAINTAINERS still correct?
It was out-of-date, yes - updated now.
Regards
Senthil
2020-08-13 Senthil Kumar Selvaraj
gcc/ChangeLog:
* emit-rtl.c (try_split): Call copy_frame_info_to_split_insn
to split certain RTX_FRAME_RELATED_P insns.
* recog.c (copy_frame_info_to_split_insn): New function.
(peep2_attempt): Split copying of frame related info of
RTX_FRAME_RELATED_P insns into above function and call it.
* recog.h (copy_frame_info_to_split_insn): Declare it.
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index f9b0e9714d9..3706f0a03fd 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -3822,10 +3822,6 @@ try_split (rtx pat, rtx_insn *trial, int last)
int njumps = 0;
rtx_insn *call_insn = NULL;
- /* We're not good at redistributing frame information. */
- if (RTX_FRAME_RELATED_P (trial))
-return trial;
-
if (any_condjump_p (trial)
&& (note = find_reg_note (trial, REG_BR_PROB, 0)))
split_branch_probability
@@ -3842,6 +3838,7 @@ try_split (rtx pat, rtx_insn *trial, int last)
if (!seq)
return trial;
+ int split_insn_count = 0;
/* Avoid infinite loop if any insn of the result matches
the original pattern. */
insn_last = seq;
@@ -3850,11 +3847,25 @@ try_split (rtx pat, rtx_insn *trial, int last)
if (INSN_P (insn_last)
&& rtx_equal_p (PATTERN (insn_last), pat))
return trial;
+ split_insn_count++;
if (!NEXT_INSN (insn_last))
break;
insn_last = NEXT_INSN (insn_last);
}
+ /* We're not good at redistributing frame information if
+ the split occurs before reload or if it results in more
+ than one insn. */
+ if (RTX_FRAME_RELATED_P (trial))
+{
+ if (!reload_completed || split_insn_count != 1)
+return trial;
+
+ rtx_insn *new_insn = seq;
+ rtx_insn *old_insn = trial;
+ copy_frame_info_to_split_insn (old_insn, new_insn);
+}
+
/* We will be adding the new sequence to the function. The splitters
may have introduced invalid RTL sharing, so unshare the sequence now. */
unshare_all_rtl_in_chain (seq);
diff --git a/gcc/recog.c b/gcc/recog.c
index 25f19b1b1cf..e024597f9d7 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -3277,6 +3277,78 @@ peep2_reinit_state (regset live)
COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
}
+/* Copies frame related info of an insn (old_insn) to the single
+ insn (new_insn) that was obtained by splitting old_insn. */
+
+void
+copy_frame_info_to_split_insn (rtx_insn *old_insn, rtx_insn *new_insn)
+{
+ bool any_note = false;
+ rtx note;
+
+ if (!RTX_FRAME_RELATED_P (old_insn))
+return;
+
+ RTX_FRAME_RELATED_P (new_insn) = 1;
+
+ /* Allow the backend to fill in a note during the split. */
+ for (note = REG_NOTES (new_insn); note ; note = XEXP (note, 1))
+switch (REG_NOTE_KIND (note))
+ {
+ case REG_FRAME_RELATED_EXPR:
+ case REG_CFA_DEF_CFA:
+ case REG_CFA_ADJUST_CFA:
+ case REG_CFA_OFFSET:
+ case REG_CFA_REGISTER:
+ case REG_CFA_EXPRESSION:
+ case REG_CFA_RESTORE:
+ case REG_CFA_SET_VDRAP:
+any_note = true;
+break;
+ default:
+break;
+ }
+
+ /* If the backend didn't supply a note, copy
[Committed] Update email address
This patch updates my email address in the MAINTAINERS file 2020-08-12 Senthil Kumar Selvaraj * MAINTAINERS: Update my email address. diff --git MAINTAINERS MAINTAINERS index 0b825c7ea6d..217ec9c9eca 100644 --- MAINTAINERS +++ MAINTAINERS @@ -588,7 +588,7 @@ Stefan Schulze Frielinghaus Tilo Schwarz Martin Sebor Svein Seldal -Senthil Kumar Selvaraj +Senthil Kumar Selvaraj Thiemo Seufer Bill Seurer Tim Shen
