Re: [PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).
Ping!!
From: Gcc-patches
on behalf of
Srinath Parvathaneni via Gcc-patches
Sent: 27 January 2023 17:44
To: gcc-patches@gcc.gnu.org
Cc: nd ; Richard Earnshaw ; Kyrylo
Tkachov
Subject: [PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).
Hello,
I have committed a fix [1] into gcc trunk for a build issue mentioned in
pr108505 and
latter received few upstream comments proposing more robust fix for this issue.
In this patch I'm addressing those comments and sending this as a followup
patch.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610513.html
Regards,
Srinath.
gcc/ChangeLog:
2023-01-27 Srinath Parvathaneni
PR target/108505
* config.gcc (tm_mlib_file): Define new variable.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
89f56047cfe3126bc6c8e90c8b4840dea13538f9..2aab92bbfd8b4088259ebf9b565af8e8bbef1122
100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4355,6 +4355,7 @@ case "${target}" in
case ${arm_multilib} in
aprofile|rmprofile)
tmake_profile_file="arm/t-multilib"
+ tm_mlib_file="arm/arm-mlib.h"
;;
@*)
ml=`echo "X$arm_multilib" |
sed '1s,^X@,,'`
@@ -4393,7 +4394,7 @@ case "${target}" in
# through to the multilib selector
with_float="soft"
tmake_file="${tmake_file}
${tmake_profile_file}"
- tm_file="$tm_file arm/arm-mlib.h"
+ tm_file="$tm_file $tm_mlib_file"
TM_MULTILIB_CONFIG="$with_multilib_list"
fi
fi
[PATCH][GCC] arm: Optimize arm-mlib.h header inclusion (pr108505).
Hello,
I have committed a fix [1] into gcc trunk for a build issue mentioned in
pr108505 and
latter received few upstream comments proposing more robust fix for this issue.
In this patch I'm addressing those comments and sending this as a followup
patch.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610513.html
Regards,
Srinath.
gcc/ChangeLog:
2023-01-27 Srinath Parvathaneni
PR target/108505
* config.gcc (tm_mlib_file): Define new variable.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
89f56047cfe3126bc6c8e90c8b4840dea13538f9..2aab92bbfd8b4088259ebf9b565af8e8bbef1122
100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4355,6 +4355,7 @@ case "${target}" in
case ${arm_multilib} in
aprofile|rmprofile)
tmake_profile_file="arm/t-multilib"
+ tm_mlib_file="arm/arm-mlib.h"
;;
@*)
ml=`echo "X$arm_multilib" | sed
'1s,^X@,,'`
@@ -4393,7 +4394,7 @@ case "${target}" in
# through to the multilib selector
with_float="soft"
tmake_file="${tmake_file} ${tmake_profile_file}"
- tm_file="$tm_file arm/arm-mlib.h"
+ tm_file="$tm_file $tm_mlib_file"
TM_MULTILIB_CONFIG="$with_multilib_list"
fi
fi
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
89f56047cfe3126bc6c8e90c8b4840dea13538f9..2aab92bbfd8b4088259ebf9b565af8e8bbef1122
100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4355,6 +4355,7 @@ case "${target}" in
case ${arm_multilib} in
aprofile|rmprofile)
tmake_profile_file="arm/t-multilib"
+ tm_mlib_file="arm/arm-mlib.h"
;;
@*)
ml=`echo "X$arm_multilib" | sed
'1s,^X@,,'`
@@ -4393,7 +4394,7 @@ case "${target}" in
# through to the multilib selector
with_float="soft"
tmake_file="${tmake_file} ${tmake_profile_file}"
- tm_file="$tm_file arm/arm-mlib.h"
+ tm_file="$tm_file $tm_mlib_file"
TM_MULTILIB_CONFIG="$with_multilib_list"
fi
fi
[PATCH][GCC] arm: Fix inclusion of arm-mlib.h header more than once (pr108505).
Hello,
The patch fixes the build issue for arm-none-eabi target configured with
--with-multilib-list=aprofile,rmprofile, in which case the header file
arm/arm-mlib.h is being included more than once and the toolchain build
is failing (PR108505).
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2023-01-24 Srinath Parvathaneni
PR target/108505
* config.gcc (tm_file): Move the variable out of loop.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
771bd35e803b47e79c0a62eab8f4845e9bbf96ef..d828223c16d3076da0ab6582dfaf59ad657ea438
100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4350,7 +4350,6 @@ case "${target}" in
case ${arm_multilib} in
aprofile|rmprofile)
tmake_profile_file="arm/t-multilib"
- tm_file="$tm_file
arm/arm-mlib.h"
;;
@*)
ml=`echo "X$arm_multilib" | sed
'1s,^X@,,'`
@@ -4389,6 +4388,7 @@ case "${target}" in
# through to the multilib selector
with_float="soft"
tmake_file="${tmake_file} ${tmake_profile_file}"
+ tm_file="$tm_file arm/arm-mlib.h"
TM_MULTILIB_CONFIG="$with_multilib_list"
fi
fi
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
771bd35e803b47e79c0a62eab8f4845e9bbf96ef..d828223c16d3076da0ab6582dfaf59ad657ea438
100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4350,7 +4350,6 @@ case "${target}" in
case ${arm_multilib} in
aprofile|rmprofile)
tmake_profile_file="arm/t-multilib"
- tm_file="$tm_file
arm/arm-mlib.h"
;;
@*)
ml=`echo "X$arm_multilib" | sed
'1s,^X@,,'`
@@ -4389,6 +4388,7 @@ case "${target}" in
# through to the multilib selector
with_float="soft"
tmake_file="${tmake_file} ${tmake_profile_file}"
+ tm_file="$tm_file arm/arm-mlib.h"
TM_MULTILIB_CONFIG="$with_multilib_list"
fi
fi
[Committed][GCC] arm: Documentation fix for -mbranch-protection option.
Hello,
This patch fixes the documentation for -mbranch-protection command line option.
Committed this patch to trunk as obvious fix.
Regards,
Srinath.
gcc/ChangeLog:
2023-01-23 Srinath Parvathaneni
* doc/invoke.texi (-mbranch-protection): Update documentation.
### Attachment also inlined for ease of reply###
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
f1c0b52012b8979070c265b7978810afe4601047..06d77983e30fff39886f360920fdfc521d2f69e4
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22564,8 +22564,7 @@ The opposite @option{-mno-fdpic} option is useful (and
required) to
build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi})
toolchain as the one used to build the userland programs.
-@item
--mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
+@item
-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
@opindex mbranch-protection
Enable branch protection features (armv8.1-m.main only).
@samp{none} generate code without branch protection or return address
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
f1c0b52012b8979070c265b7978810afe4601047..06d77983e30fff39886f360920fdfc521d2f69e4
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22564,8 +22564,7 @@ The opposite @option{-mno-fdpic} option is useful (and
required) to
build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi})
toolchain as the one used to build the userland programs.
-@item
--mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
+@item
-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]
@opindex mbranch-protection
Enable branch protection features (armv8.1-m.main only).
@samp{none} generate code without branch protection or return address
[PATCH v2][GCC] arm: Add support for new frame unwinding instruction "0xb5".
Hi,
This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When
an exception is taken and "0xb5" instruction is encounter during runtime
stack-unwinding, we use effective vsp as modifier in pointer authentication.
On completion of stack unwinding if "0xb5" instruction is not encountered
then CFA will be used as modifier in pointer authentication.
[1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode opcode
"0xb5".
### Attachment also inlined for ease of reply###
diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c
index
e48854587c667a959aa66ccc4982231f6ecc..1fbc41e17c227c21af1937344ded2a7fd80e61df
100644
--- a/libgcc/config/arm/pr-support.c
+++ b/libgcc/config/arm/pr-support.c
@@ -107,7 +107,9 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
_uw op;
int set_pc;
int set_pac = 0;
+ int set_pac_sp = 0;
_uw reg;
+ _uw sp;
set_pc = 0;
for (;;)
@@ -124,10 +126,11 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
#if defined(TARGET_HAVE_PACBTI)
if (set_pac)
{
- _uw sp;
_uw lr;
_uw pac;
- _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, );
+ if (!set_pac_sp)
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32,
+);
_Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, );
_Unwind_VRS_Get (context, _UVRSC_PAC, R_IP,
_UVRSD_UINT32, );
@@ -259,6 +262,14 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
continue;
}
+ /* Use current VSP as modifier in PAC validation. */
+ if (op == 0xb5)
+ {
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, );
+ set_pac_sp = 1;
+ continue;
+ }
+
if ((op & 0xfc) == 0xb4) /* Obsolete FPA. */
return _URC_FAILURE;
diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c
index
e48854587c667a959aa66ccc4982231f6ecc..1fbc41e17c227c21af1937344ded2a7fd80e61df
100644
--- a/libgcc/config/arm/pr-support.c
+++ b/libgcc/config/arm/pr-support.c
@@ -107,7 +107,9 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
_uw op;
int set_pc;
int set_pac = 0;
+ int set_pac_sp = 0;
_uw reg;
+ _uw sp;
set_pc = 0;
for (;;)
@@ -124,10 +126,11 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
#if defined(TARGET_HAVE_PACBTI)
if (set_pac)
{
- _uw sp;
_uw lr;
_uw pac;
- _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, );
+ if (!set_pac_sp)
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32,
+);
_Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, );
_Unwind_VRS_Get (context, _UVRSC_PAC, R_IP,
_UVRSD_UINT32, );
@@ -259,6 +262,14 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
continue;
}
+ /* Use current VSP as modifier in PAC validation. */
+ if (op == 0xb5)
+ {
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, );
+ set_pac_sp = 1;
+ continue;
+ }
+
if ((op & 0xfc) == 0xb4) /* Obsolete FPA. */
return _URC_FAILURE;
RE: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".
Hi Ramana, > -Original Message- > From: Ramana Radhakrishnan > Sent: Sunday, November 20, 2022 10:48 PM > To: Srinath Parvathaneni > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > ; Kyrylo Tkachov > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwinding > instruction "0xb5". > > On Fri, Nov 18, 2022 at 9:33 AM Srinath Parvathaneni > wrote: > > > > Hi, > > > > > -Original Message- > > > From: Ramana Radhakrishnan > > > Sent: Thursday, November 17, 2022 8:27 PM > > > To: Srinath Parvathaneni > > > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > > > ; Kyrylo Tkachov > > > > Subject: Re: [PATCH][GCC] arm: Add support for new frame unwinding > > > instruction "0xb5". > > > > > > On Thu, Nov 10, 2022 at 10:38 AM Srinath Parvathaneni via > > > Gcc-patches wrote: > > > > > > > > Hi, > > > > > > > > This patch adds support for Arm frame unwinding instruction "0xb5" > > > > [1]. When an exception is taken and "0xb5" instruction is > > > > encounter during runtime stack-unwinding, we use effective vsp as > > > > modifier in pointer > > > authentication. > > > > On completion of stack unwinding if "0xb5" instruction is not > > > > encountered then CFA will be used as modifier in pointer > authentication. > > > > > > > > [1] > > > > https://github.com/ARM-software/abi- > > > aa/releases/download/2022Q3/ehabi3 > > > > 2.pdf > > > > > > > > Regression tested on arm-none-eabi target and found no regressions. > > > > > > > > Ok for master? > > > > > > > > > > No, not yet. > > > > > > Presumably the logic to produce 0xb5 is in the source base and this > > > was tested with suitable options that produce said opcode ? I see no > > > logic in place to produce the said opcode in the backend in a quick > > > read as the pacbti patches still seem to be in review. ? > > > > > > So what was the test suite run actually testing ? > > > > Sorry for the late response, the patch supporting the said opcode (directive > ".pacspval)" is here: > > https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605524.html > > (still under upstream review) > > > > and the patch to encode ".pacspval" with the mentioned opcode "0xb5" in > binutils is here: > > https://sourceware.org/pipermail/binutils/2022-November/124328.html > (approved and committed to binutils). > > Thanks for the answer but perhaps I should make my question more explicit > - are you saying that this patch was tested in combination with those and > other dependent patches on a suitable simulator with suitable multilibs and > C++ to test for this presumably for frame unwinding ? > Sorry for the late response, I'm re-spinning other pacbti patches on top of which this patch needs to be applied, so I could not respond to you. I have applied this patch on top of all the pacbti and related multilib patches, the patch applies cleanly, and the toolchain build is successful. I have tested this patch with C testcase with nested function (which emits .pacspval directive in case of clobber IP) on a simulator which supports PACBTI and executed the binary successfully. But I'm unable to test this patch for C++ frame unwinding for this opcode because C++ doesn't support nested functions and with current pacbti code IP register is clobbered and we emit .pacspval directive only for nested function. > For the future , it would certainly be worth being explicit about this in your > patch submission :) Thank you, I will keep this is in mind for my later patch submissions. Regards, Srinath. > regards > Ramana > > > > > Regards, > > Srinath. > > > > > regards > > > Ramana > > > > > > > > > > Regards, > > > > Srinath. > > > > > > > > gcc/ChangeLog: > > > > > > > > 2022-11-09 Srinath Parvathaneni > > > > > > > > * libgcc/config/arm/pr-support.c (__gnu_unwind_execute): > > > > Decode > > > opcode > > > > "0xb5". > > > > > > > > > > > > ### Attachment also inlined for ease of reply > > > ### > > > > > > > > > > > > diff --git a/libgcc/config/arm/pr-support.c > > > > b/libg
[GCC][PATCH 13/15, v6] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to emit ".pacspval" directive when "pac ip, lr,
sp" instruction
in generated in the assembly.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Applying this patch on top of PACBTI series posted here
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599658.html and when
compiling the following
test.c with "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard
fasynchronous-unwind-tables -g -O0 -S" command line options, the assembly
output after this patch
looks like below:
$cat test.c
void fun1(int a);
void fun(int a,...)
{
fun1(a);
}
int main()
{
fun (10);
return 0;
}
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve+pacbti
-mbranch-protection=pac-ret -mthumb -mfloat-abi=hard
-fasynchronous-unwind-tables -g -O0 -S test.s
Assembly output:
...
fun:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -24
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
main:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -8
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
2023-01-18 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add entry in enum.
(emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression.
(arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
(arm_expand_prologue): Update frame related information and reg notes
for pac/pacbit insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_init_machine_status): Set pacspval_needed to zero.
(arm_debugger_regno): Check for PAC register.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_unwind_emit_set): Add entry for IP_REGNUM in switch case.
(arm_unwind_emit): Update REG_CFA_REGISTER case._
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(DWARF_PAC_REGNUM): Define.
(IS_PAC_REGNUM): Likewise.
(enum reg_class): Add PAC_REG entry.
(machine_function): Add pacbti_needed state to structure.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2023-01-18 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-15.c: Likewise.
pacbti_dwarf.patch
Description: pacbti_dwarf.patch
[GCC][PATCH v4] arm: Add pacbti related multilib support for armv8.1-m.main.
Hi, This patch adds the support for pacbti multlilib linking by making "-mbranch-protection=none" as default multilib option for arm-none-eabi target. Eg 1. If the passed command line flags are (without mbranch-protection): a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto "-mbranch-protection=none" will be used in the multilib matching. Eg 2. If the passed command line flags are (with mbranch-protection): a) -march=armv8.1-m.main+mve+pacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret "-mbranch-protection=standard" will be used in the multilib matching. Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2023-01-11 Srinath Parvathaneni * config.gcc ($tm_file): Update variable. * config/arm/arm-mlib.h: Create new header file. * config/arm/t-rmprofile (MULTI_ARCH_DIRS_RM): Rename mbranch-protection multilib arch directory. (MULTILIB_REUSE): Add multilib reuse rules. (MULTILIB_MATCHES): Add multilib match rules. gcc/testsuite/ChangeLog: 2023-01-11 Srinath Parvathaneni * gcc.target/arm/multilib.exp (multilib_config "rmprofile"): Update tests. * gcc.target/arm/pac-12.c: New test. * gcc.target/arm/pac-13.c: Likewise. * gcc.target/arm/pac-14.c: Likewise. multilib_pacbti Description: multilib_pacbti
[GCC][PATCH 13/15, v5] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to emit ".pacspval" directive when "pac ip, lr,
sp" instruction
in generated in the assembly.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Applying this patch on top of PACBTI series posted here
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599658.html and when
compiling the following
test.c with "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard
fasynchronous-unwind-tables -g -O0 -S" command line options, the assembly
output after this patch
looks like below:
$cat test.c
void fun1(int a);
void fun(int a,...)
{
fun1(a);
}
int main()
{
fun (10);
return 0;
}
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve+pacbti
-mbranch-protection=pac-ret -mthumb -mfloat-abi=hard
-fasynchronous-unwind-tables -g -O0 -S test.s
Assembly output:
...
fun:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -24
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
main:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -8
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
2023-01-11 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add entry in enum.
(emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression.
(arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
(arm_expand_prologue): Update frame related information and reg notes
for pac/pacbit insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_init_machine_status): Set pacspval_needed to zero.
(arm_debugger_regno): Check for PAC register.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_unwind_emit_set): Add entry for IP_REGNUM in switch case.
(arm_unwind_emit): Update REG_CFA_REGISTER case._
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(DWARF_PAC_REGNUM): Define.
(IS_PAC_REGNUM): Likewise.
(enum reg_class): Add PAC_REG entry.
(machine_function): Add pacbti_needed state to structure.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2023-01-11 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-15.c: Likewise.
dwarf_pacbti
Description: dwarf_pacbti
[Committed] arm: Add cde feature support for Cortex-M55 CPU.
Hi,
This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer
[1] for more details. To use this feature we need to specify +cdecpN
(e.g. -mcpu=cortex-m55+cdecp), where N is the coprocessor number 0 to 7.
Bootstrapped for arm-none-linux-gnueabihf target, regression tested
on arm-none-eabi target and found no regressions.
[1] https://developer.arm.com/documentation/101051/0101/?lang=en (version:
r1p1).
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2023-01-13 Srinath Parvathaneni
* common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde
options for -mlibarch.
* config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
* doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.
gcc/testsuite/ChangeLog:
2023-01-13 Srinath Parvathaneni
* gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55 CPU.
### Attachment also inlined for ease of reply###
diff --git a/gcc/common/config/arm/arm-common.cc
b/gcc/common/config/arm/arm-common.cc
index
c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..9ed6830417bbcc984f67237fe30beb5ebec76c00
100644
--- a/gcc/common/config/arm/arm-common.cc
+++ b/gcc/common/config/arm/arm-common.cc
@@ -685,8 +685,10 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool
arch_for_multilib)
auto_sbitmap target_isa (isa_num_bits);
auto_sbitmap base_isa (isa_num_bits);
auto_sbitmap fpu_isa (isa_num_bits);
+ auto_sbitmap ignore_multilib_isa (isa_num_bits);
bitmap_clear (fpu_isa);
+ bitmap_clear (ignore_multilib_isa);
const arch_option *selected_arch = NULL;
@@ -719,15 +721,6 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool
arch_for_multilib)
arm_initialize_isa (target_isa, selected_arch->common.isa_bits);
arm_parse_option_features (target_isa, _arch->common,
strchr (arch, '+'));
- if (arch_for_multilib)
- {
- const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
-isa_nobit};
- sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
- arm_initialize_isa (isa_bits, removable_bits);
- bitmap_and_compl (target_isa, target_isa, isa_bits);
- }
-
if (fpu && strcmp (fpu, "auto") != 0)
{
/* We assume that architectures do not have any FPU bits
@@ -806,6 +799,16 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool
arch_for_multilib)
bitmap_clear_bit (target_isa, isa_bit_vfpv2);
}
+ /* Here we remove feature isa bits from -mlibarch string which are not
+ necessary for multilib string comparsion. */
+ if ((arch || cpu) && arch_for_multilib)
+{
+ const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
+isa_nobit};
+ arm_initialize_isa (ignore_multilib_isa, removable_bits);
+ bitmap_and_compl (target_isa, target_isa, ignore_multilib_isa);
+}
+
/* If we don't have a selected architecture by now, something's
badly wrong. */
gcc_assert (selected_arch);
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index
e89106c51b41d709b2159073da3273423af537f8..579cf35636632869947f37753bbf0ba79277808c
100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1644,6 +1644,14 @@ begin cpu cortex-m55
option nomve remove mve mve_float
option nofp remove ALL_FP mve_float
option nodsp remove MVE mve_float
+ option cdecp0 add cdecp0
+ option cdecp1 add cdecp1
+ option cdecp2 add cdecp2
+ option cdecp3 add cdecp3
+ option cdecp4 add cdecp4
+ option cdecp5 add cdecp5
+ option cdecp6 add cdecp6
+ option cdecp7 add cdecp7
isa quirk_no_asmcpu quirk_vlldm
costs v7m
vendor 41
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
701c228bd0a824dee52c7d4e23c9f687000cd3d6..0b0bdb63436e5a63b12a06c3c6cd5544cc54c808
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22168,6 +22168,10 @@ floating-point instructions on @samp{cortex-m55}.
Disable the M-Profile Vector Extension (MVE) single precision floating-point
instructions on @samp{cortex-m55}.
+@item +cdecp0, +cdecp1, ... , +cdecp7
+Enable the Custom Datapath Extension (CDE) on selected coprocessors according
+to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}.
+
@item +nofp
Disables the floating-point instructions on @samp{arm9e},
@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp
b/gcc/testsuite/gcc.target/arm/multilib.exp
index
f903f028a83f884bdc1521f810f7e70e4130a715..e9c9b9cf885155d9a7e4106161c570df1b57ffab
100644
--- a/gcc/testsuite/gcc.target/arm/multilib.exp
+++ b/gcc/testsuite/gcc.target/arm/multilib.exp
@@ -854,6 +854,18 @@ if {[multilib_config "rmprofile"] } {
{-mcpu=cortex-m55+nomve+nofp -mfpu=auto
RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.
Ping!!
-
From: Srinath Parvathaneni
Sent: Tuesday, December 6, 2022 11:32 AM
To: gcc-patches@gcc.gnu.org; Richard Earnshaw
Cc: Christophe Lyon
Subject: Re: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.
Ping!!
From: Srinath Parvathaneni
Sent: 31 October 2022 12:38
To: mailto:gcc-patches@gcc.gnu.org <mailto:gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <mailto:richard.earns...@arm.com>; Christophe Lyon
<mailto:christophe.l...@arm.com>
Subject: RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.
Hi,
> -Original Message-
> From: Christophe Lyon <mailto:christophe.l...@arm.com>
> Sent: Monday, October 17, 2022 2:30 PM
> To: Srinath Parvathaneni <mailto:srinath.parvathan...@arm.com>; gcc-
> mailto:patc...@gcc.gnu.org
> Cc: Richard Earnshaw <mailto:richard.earns...@arm.com>
> Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55
> CPU.
>
> Hi Srinath,
>
>
> On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi,
> >
> > This patch adds cde feature (optional) support for Cortex-M55 CPU,
> > please refer [1] for more details. To use this feature we need to
> > specify +cdecpN (e.g. -mcpu=cortex-m55+cdecp), where N is the
> coprocessor number 0 to 7.
> >
> > Bootstrapped for arm-none-linux-gnueabihf target, regression tested on
> > arm-none-eabi target and found no regressions.
> >
> > [1] https://developer.arm.com/documentation/101051/0101/?lang=en
> (version: r1p1).
> >
> > Ok for master?
> >
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2022-10-07 Srinath Parvathaneni <mailto:srinath.parvathan...@arm.com>
> >
> > * common/config/arm/arm-common.cc (arm_canon_arch_option_1):
> Ignore cde
> > options for mlibarch.
> > * config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
> > * doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2022-10-07 Srinath Parvathaneni <mailto:srinath.parvathan...@arm.com>
> >
> > * gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55
> >CPU.
> >
> >
> > ### Attachment also inlined for ease of reply
> ###
> >
> >
> > diff --git a/gcc/common/config/arm/arm-common.cc
> > b/gcc/common/config/arm/arm-common.cc
> > index
> >
> c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..b6f955b3c012475f398382e72
> c9a
> > 3966412991ec 100644
> > --- a/gcc/common/config/arm/arm-common.cc
> > +++ b/gcc/common/config/arm/arm-common.cc
> > @@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char
> **argv, bool arch_for_multilib)
> > arm_initialize_isa (target_isa, selected_cpu->common.isa_bits);
> > arm_parse_option_features (target_isa, _cpu->common,
> > strchr (cpu, '+'));
> > + if (arch_for_multilib)
> > + {
> > + const enum isa_feature removable_bits[] =
> {ISA_IGNORE_FOR_MULTILIB,
> > + isa_nobit};
> > + sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
> > + arm_initialize_isa (isa_bits, removable_bits);
> > + bitmap_and_compl (target_isa, target_isa, isa_bits);
> > + }
> > +
>
> I can see the piece of code you add here is exactly the same as the one a few
> lines above when handling "if (arch)". Can this be moved below and thus be
> common to the two cases, or does it have to be performed before
> bitmap_ior of fpu_isa?
Thanks for pointing out this, I have moved the common code below the arch and
cpu
if blocks in the attached patch.
> Also, IIUC, CDE was already optional for other CPUs (M33, M35P, star-mc1),
> so the hunk above fixes a latent bug when handling multilibs for these CPUs
> too? If so, maybe worth splitting the patch into two parts since the above is
> not strictly related to M55?
>
Even though CDE is optional for the mentioned CPUs as per the specs, the code to
enable CDE as optional feature is missing in current compiler.
Current GCC compiler supports CDE as optional feature only with -march options
and
this pass adds CDE as optional for M55 and so this is not a fix bug.
> But I'm not a maintainer ;-)
>
> Thanks,
>
> Christophe
>
> > if (fpu && strcmp (fpu, "auto") != 0)
> > {
> > /* The easiest and safest way to remove the default fpu diff
> > --git a/gcc/config/arm/arm-cpus.in b/gcc/c
Re: [GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Ping!!
From: Gcc-patches
on behalf of
Srinath Parvathaneni via Gcc-patches
Sent: 09 November 2022 14:32
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw ; Kyrylo Tkachov
Subject: [GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and
pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to emit ".pacspval" directive when "pac ip, lr,
sp" instruction
in generated in the assembly.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Applying this patch on top of PACBTI series posted here
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599658.html and when
compiling the following
test.c with "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard
fasynchronous-unwind-tables -g -O0 -S" command line options, the assembly
output after this patch
looks like below:
$cat test.c
void fun1(int a);
void fun(int a,...)
{
fun1(a);
}
int main()
{
fun (10);
return 0;
}
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve+pacbti
-mbranch-protection=pac-ret -mthumb -mfloat-abi=hard
-fasynchronous-unwind-tables -g -O0 -S test.s
Assembly output:
...
fun:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -24
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
main:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -8
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2022-11-04 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-9.c: New test.
2022-11-04 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add entry in enum.
* config/arm/arm.cc (pac_emit): Declare new global boolean variable.
(emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression.
(arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
(arm_expand_prologue): Update frame related infomration and reg notes
for pac/pacbit insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_unwind_emit_set): Add entry for IP_REGNUM in switch case.
(arm_unwind_emit): Update REG_CFA_REGISTER case._
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_PSEUDO_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2022-11-04 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-9.c: Likewise.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
b918ad3782fbee82320febb8b6e72ad615780261..ffeed45a678f17c63d5b42c21f020ca416cbf23f
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
a2dc3fc145c52d8381c54634687376089a47e704..91c400f12568156ed29bf5d5e59460bf887fbefb
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -820,7 +820,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication.
Re: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.
Ping!!
From: Srinath Parvathaneni
Sent: 31 October 2022 12:38
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw ; Christophe Lyon
Subject: RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.
Hi,
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, October 17, 2022 2:30 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55
> CPU.
>
> Hi Srinath,
>
>
> On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi,
> >
> > This patch adds cde feature (optional) support for Cortex-M55 CPU,
> > please refer [1] for more details. To use this feature we need to
> > specify +cdecpN (e.g. -mcpu=cortex-m55+cdecp), where N is the
> coprocessor number 0 to 7.
> >
> > Bootstrapped for arm-none-linux-gnueabihf target, regression tested on
> > arm-none-eabi target and found no regressions.
> >
> > [1] https://developer.arm.com/documentation/101051/0101/?lang=en
> (version: r1p1).
> >
> > Ok for master?
> >
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2022-10-07 Srinath Parvathaneni
> >
> > * common/config/arm/arm-common.cc (arm_canon_arch_option_1):
> Ignore cde
> > options for mlibarch.
> > * config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
> > * doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2022-10-07 Srinath Parvathaneni
> >
> > * gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55
> > CPU.
> >
> >
> > ### Attachment also inlined for ease of reply
> ###
> >
> >
> > diff --git a/gcc/common/config/arm/arm-common.cc
> > b/gcc/common/config/arm/arm-common.cc
> > index
> >
> c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..b6f955b3c012475f398382e72
> c9a
> > 3966412991ec 100644
> > --- a/gcc/common/config/arm/arm-common.cc
> > +++ b/gcc/common/config/arm/arm-common.cc
> > @@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char
> **argv, bool arch_for_multilib)
> > arm_initialize_isa (target_isa, selected_cpu->common.isa_bits);
> > arm_parse_option_features (target_isa, _cpu->common,
> > strchr (cpu, '+'));
> > + if (arch_for_multilib)
> > + {
> > + const enum isa_feature removable_bits[] =
> {ISA_IGNORE_FOR_MULTILIB,
> > +isa_nobit};
> > + sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
> > + arm_initialize_isa (isa_bits, removable_bits);
> > + bitmap_and_compl (target_isa, target_isa, isa_bits);
> > + }
> > +
>
> I can see the piece of code you add here is exactly the same as the one a few
> lines above when handling "if (arch)". Can this be moved below and thus be
> common to the two cases, or does it have to be performed before
> bitmap_ior of fpu_isa?
Thanks for pointing out this, I have moved the common code below the arch and
cpu
if blocks in the attached patch.
> Also, IIUC, CDE was already optional for other CPUs (M33, M35P, star-mc1),
> so the hunk above fixes a latent bug when handling multilibs for these CPUs
> too? If so, maybe worth splitting the patch into two parts since the above is
> not strictly related to M55?
>
Even though CDE is optional for the mentioned CPUs as per the specs, the code to
enable CDE as optional feature is missing in current compiler.
Current GCC compiler supports CDE as optional feature only with -march options
and
this pass adds CDE as optional for M55 and so this is not a fix bug.
> But I'm not a maintainer ;-)
>
> Thanks,
>
> Christophe
>
> > if (fpu && strcmp (fpu, "auto") != 0)
> > {
> >/* The easiest and safest way to remove the default fpu diff
> > --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index
> >
> 5a63bc548e54dbfdce5d1df425bd615d81895d80..aa02c04c4924662f3ddd58e
> 69673
> > 92ba3f4b4a87 100644
> > --- a/gcc/config/arm/arm-cpus.in
> > +++ b/gcc/config/arm/arm-cpus.in
> > @@ -1633,6 +1633,14 @@ begin cpu cortex-m55
> >option nomve remove mve mve_float
> >option nofp remove ALL_FP mve_float
> >option nodsp remove MVE mve_float
> > + option cdecp0 add cdecp0
> > + option cdecp1 add cdecp1
> > + option cdecp2 add cdecp2
> > + option cdecp3 add cdecp3
> > + option cdecp4 add
Re: [GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main.
Ping!! From: Gcc-patches on behalf of Srinath Parvathaneni via Gcc-patches Sent: 31 October 2022 15:36 To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main. Hi, This patch adds the support for pacbti multlilib linking by making "-mbranch-protection=none" as default in the command line for all M-profile targets and uses "-mbranch-protection=none" for multilib matching. If any valid value is passed to "-mbranch-protection" in the command line, this new value overwrites the default value in the command line and uses "-mbranch-protection=standard" for multilib matching. Eg 1. If the passed command line flags are: a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto b) -mcpu=cortex-m85+nopacbti -mfloat-abi=hard -mfpu=auto After this patch the command line flags the compiler receives will be: a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto -mbranch-protection=none b) -mcpu=cortex-m85+nopacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=none "-mbranch-protection=none" will be used in the multilib matching. Eg 2. If the passed command line flags are: a) -march=armv8.1-m.main+mve+pacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret b) -mcpu=cortex-m85 -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret+bti After this patch the command line flags the compiler receives will be: a) -march=armv8.1-m.main+mve+pacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret b) -mcpu=cortex-m85 -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret+bti "-mbranch-protection=standard" will be used in the multilib matching. Eg 3. For A-profile target, if the passed command line flags are: -march=armv8-a+simd -mfloat-abi=hard -mfpu=auto Even after this patch the command line flags compiler receives will remain the same: -march=armv8-a+simd -mfloat-abi=hard -mfpu=auto Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-10-28 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_branch_protection_option): Define new function. * config/arm/arm-cpus.in (armv8.1-m.main): Move dsp option below pacbti option. * config/arm/arm.h (arm_canon_branch_protection_option): Define function prototype. (CANON_BRANCH_PROTECTION_SPEC_FUNCTION): Define macro. (MBRANCH_PROTECTION_SPECS): Likewise. * config/arm/t-rmprofile (MULTI_ARCH_OPTS_RM): Add new options. (MULTI_ARCH_DIRS_RM): Add new directories. (MULTILIB_REQUIRED): Add new option. (MULTILIB_REUSE): Reuse existing multlibs. (MULTILIB_MATCHES): Match multilib strings. gcc/testsuite/ChangeLog: 2022-10-28 Srinath Parvathaneni * gcc.target/arm/multilib.exp (multilib_config "rmprofile"): Update tests. * gcc.target/arm/pac-10.c: New test. * gcc.target/arm/pac-11.c: Likewise. * gcc.target/arm/pac-12.c: Likewise.
RE: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".
Hi,
> -Original Message-
> From: Ramana Radhakrishnan
> Sent: Thursday, November 17, 2022 8:27 PM
> To: Srinath Parvathaneni
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; Kyrylo Tkachov
> Subject: Re: [PATCH][GCC] arm: Add support for new frame unwinding
> instruction "0xb5".
>
> On Thu, Nov 10, 2022 at 10:38 AM Srinath Parvathaneni via Gcc-patches patc...@gcc.gnu.org> wrote:
> >
> > Hi,
> >
> > This patch adds support for Arm frame unwinding instruction "0xb5"
> > [1]. When an exception is taken and "0xb5" instruction is encounter
> > during runtime stack-unwinding, we use effective vsp as modifier in pointer
> authentication.
> > On completion of stack unwinding if "0xb5" instruction is not
> > encountered then CFA will be used as modifier in pointer authentication.
> >
> > [1]
> > https://github.com/ARM-software/abi-
> aa/releases/download/2022Q3/ehabi3
> > 2.pdf
> >
> > Regression tested on arm-none-eabi target and found no regressions.
> >
> > Ok for master?
> >
>
> No, not yet.
>
> Presumably the logic to produce 0xb5 is in the source base and this was
> tested with suitable options that produce said opcode ? I see no logic in
> place
> to produce the said opcode in the backend in a quick read as the pacbti
> patches still seem to be in review. ?
>
> So what was the test suite run actually testing ?
Sorry for the late response, the patch supporting the said opcode (directive
".pacspval)" is here:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605524.html (still
under upstream review)
and the patch to encode ".pacspval" with the mentioned opcode "0xb5" in
binutils is here:
https://sourceware.org/pipermail/binutils/2022-November/124328.html (approved
and committed to binutils).
Regards,
Srinath.
> regards
> Ramana
>
>
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2022-11-09 Srinath Parvathaneni
> >
> > * libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode
> opcode
> > "0xb5".
> >
> >
> > ### Attachment also inlined for ease of reply
> ###
> >
> >
> > diff --git a/libgcc/config/arm/pr-support.c
> > b/libgcc/config/arm/pr-support.c index
> >
> e48854587c667a959aa66ccc4982231f6ecc..73e4942a39b34a83c2da85de
> f6b1
> > 3e82ec501552 100644
> > --- a/libgcc/config/arm/pr-support.c
> > +++ b/libgcc/config/arm/pr-support.c
> > @@ -107,7 +107,9 @@ __gnu_unwind_execute (_Unwind_Context *
> context, __gnu_unwind_state * uws)
> >_uw op;
> >int set_pc;
> >int set_pac = 0;
> > + int set_pac_sp = 0;
> >_uw reg;
> > + _uw sp;
> >
> >set_pc = 0;
> >for (;;)
> > @@ -124,10 +126,11 @@ __gnu_unwind_execute (_Unwind_Context *
> context,
> > __gnu_unwind_state * uws) #if defined(TARGET_HAVE_PACBTI)
> > if (set_pac)
> > {
> > - _uw sp;
> > _uw lr;
> > _uw pac;
> > - _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP,
> _UVRSD_UINT32, );
> > + if (!set_pac_sp)
> > + _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP,
> _UVRSD_UINT32,
> > +);
> > _Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32,
> );
> > _Unwind_VRS_Get (context, _UVRSC_PAC, R_IP,
> >_UVRSD_UINT32, ); @@ -259,7 +262,19
> > @@ __gnu_unwind_execute (_Unwind_Context * context,
> __gnu_unwind_state * uws)
> > continue;
> > }
> >
> > - if ((op & 0xfc) == 0xb4) /* Obsolete FPA. */
> > + /* Use current VSP as modifier in PAC validation. */
> > + if (op == 0xb5)
> > + {
> > + if (set_pac)
> > + _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP,
> _UVRSD_UINT32,
> > +);
> > + else
> > + return _URC_FAILURE;
> > + set_pac_sp = 1;
> > + continue;
> > + }
> > +
> > + if ((op & 0xfd) == 0xb6) /* Obsolete FPA. */
> > return _URC_FAILURE;
> >
> > /* op & 0xf8 == 0xb8. */
> >
> >
> >
RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.
Hi,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Monday, November 14, 2022 2:47 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.
>
>
>
> > -Original Message-
> > From: Srinath Parvathaneni
> > Sent: Friday, November 11, 2022 3:08 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Richard Sandiford ; Kyrylo Tkachov
> >
> > Subject: [PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.
> >
> > Hi,
> >
> > This patch adds support for Cortex-X3 CPU.
> >
> > Bootstrapped on aarch64-none-linux-gnu and found no regressions.
> >
> > Ok for GCC master?
>
> Ok, but the documentation needs to be rebased as we've moved back to
> .texi.
Thank you Kyrill, I have rebased and committed the patch, updated invoke.texi.
Regards,
Srinath.
> Thanks,
> Kyrill
>
> >
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2022-11-09 Srinath Parvathaneni
> >
> > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add
> > Cortex-X3 CPU.
> > * config/aarch64/aarch64-tune.md: Regenerate.
> > *
> > doc/gcc/gcc-command-options/machine-dependent-options/aarch64-
> > options.rst:
> > Document Cortex-X3 CPU.
> >
> >
> > ### Attachment also inlined for ease of reply
> > ###
> >
> >
> > diff --git a/gcc/config/aarch64/aarch64-cores.def
> > b/gcc/config/aarch64/aarch64-cores.def
> > index
> >
> 3055da9b268b6b71bc3bd6db721812b387e8dd44..a2062468136bf1c38b941c
> > 53868d26dafedda276 100644
> > --- a/gcc/config/aarch64/aarch64-cores.def
> > +++ b/gcc/config/aarch64/aarch64-cores.def
> > @@ -172,6 +172,8 @@ AARCH64_CORE("cortex-a715", cortexa715,
> > cortexa57, V9A, (SVE2_BITPERM, MEMTAG,
> >
> > AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM,
> > MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
> >
> > +AARCH64_CORE("cortex-x3", cortexx3, cortexa57, V9A, (SVE2_BITPERM,
> > MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd4e, -1)
> > +
> > AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM,
> BF16,
> > SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
> >
> > AARCH64_CORE("demeter", demeter, cortexa57, V9A, (I8MM, BF16,
> > SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1) diff
> > --git a/gcc/config/aarch64/aarch64-tune.md
> > b/gcc/config/aarch64/aarch64-tune.md
> > index
> >
> 22ec1be5a4c71b930221d2c4f1e62df57df0cadf..74c4384712b202058a58f1da0
> > ca28adec97a6b9b 100644
> > --- a/gcc/config/aarch64/aarch64-tune.md
> > +++ b/gcc/config/aarch64/aarch64-tune.md
> > @@ -1,5 +1,5 @@
> > ;; -*- buffer-read-only: t -*-
> > ;; Generated automatically by gentune.sh from aarch64-cores.def
> > (define_attr "tune"
> > -
> > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> >
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunde
> > r
> >
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> > hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> > a
> > 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,
> > co
> > rtexx1,cortexx1c,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,oct
> > eo
> >
> ntx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,t
> > s
> >
> v110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cor
> > t
> > exa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa
> > 7
> > 5cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa7
> > 15 ,cortexx2,neoversen2,demeter,neoversev2"
> > +
> > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> >
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunde
> > r
> >
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> > hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> > a
> > 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,
> > co
> > rtexx1,cortexx1c,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,oct
> > eo
> >
> ntx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,t
> > s
> >
> v110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cor
> > t
> > exa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa
> > 7
> > 5cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa7
> > 15 ,cortexx2,cortexx3,neoversen2,demeter,neoversev2"
> > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git
> > a/gcc/doc/gcc/gcc-command-options/machine-dependent-
> > options/aarch64-options.rst b/gcc/doc/gcc/gcc-command-
> options/machine-
> > dependent-options/aarch64-options.rst
> > index
> >
> d97515d9e54feaa85a2ead4e9b73f0eb966cb39f..7cc369ef95e510e30873159b
> > 8e2130c4f77a57d3 100644
> > --- a/gcc/doc/gcc/gcc-command-options/machine-dependent-
> > options/aarch64-options.rst
> > +++
[PATCH][GCC] aarch64: Add support for Cortex-X3 CPU.
Hi,
This patch adds support for Cortex-X3 CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X3 CPU.
* config/aarch64/aarch64-tune.md: Regenerate.
*
doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst:
Document Cortex-X3 CPU.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index
3055da9b268b6b71bc3bd6db721812b387e8dd44..a2062468136bf1c38b941c53868d26dafedda276
100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -172,6 +172,8 @@ AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A,
(SVE2_BITPERM, MEMTAG,
AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM, MEMTAG,
I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
+AARCH64_CORE("cortex-x3", cortexx3, cortexa57, V9A, (SVE2_BITPERM, MEMTAG,
I8MM, BF16), neoversen2, 0x41, 0xd4e, -1)
+
AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16,
SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
AARCH64_CORE("demeter", demeter, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM,
RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md
b/gcc/config/aarch64/aarch64-tune.md
index
22ec1be5a4c71b930221d2c4f1e62df57df0cadf..74c4384712b202058a58f1da0ca28adec97a6b9b
100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
-
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,neoversen2,demeter,neoversev2"
+
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,cortexx3,neoversen2,demeter,neoversev2"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
index
d97515d9e54feaa85a2ead4e9b73f0eb966cb39f..7cc369ef95e510e30873159b8e2130c4f77a57d3
100644
---
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
+++
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
@@ -258,8 +258,8 @@ These options are defined for AArch64 implementations:
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
:samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
:samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x1c`, :samp:`cortex-x2`,
- :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`cortex-a715`,
:samp:`ampere1`,
- :samp:`native`.
+ :samp:`cortex-x3`, :samp:`cortex-a510`, :samp:`cortex-a710`,
+ :samp:`cortex-a715`, :samp:`ampere1`, :samp:`native`.
The values :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index
3055da9b268b6b71bc3bd6db721812b387e8dd44..a2062468136bf1c38b941c53868d26dafedda276
100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -172,6 +172,8 @@ AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A,
(SVE2_BITPERM, MEMTAG,
AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM, MEMTAG,
I8MM, BF16),
RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
Hi,
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Friday, November 11, 2022 2:24 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: RE: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
>
> Hi Srinath,
>
> > -Original Message-
> > From: Srinath Parvathaneni
> > Sent: Friday, November 11, 2022 11:58 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Richard Sandiford ; Kyrylo Tkachov
> >
> > Subject: [PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
> >
> > Hi,
> >
> > This patch adds support for Cortex-A715 CPU.
> >
> > Bootstrapped on aarch64-none-linux-gnu and found no regressions.
> >
> > Ok for GCC master?
> >
>
> Ok. Please make sure aarch64-tune.md is appropriately regenerated in
> combination with the other -mcpu options you're adding.
Thank you Kyrill for approving the patches, I have re-checked the regenerated
aarch64-tune.md for the added CPU's support and committed the code on to GCC
master.
Regards,
Srinath.
> Thanks,
> Kyrill
>
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2022-11-09 Srinath Parvathaneni
> >
> > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add
> > Cortex-A715 CPU.
> > * config/aarch64/aarch64-tune.md: Regenerate.
> > *
> > doc/gcc/gcc-command-options/machine-dependent-options/aarch64-
> > options.rst:
> > Document Cortex-A715 CPU.
> >
> >
> > ### Attachment also inlined for ease of reply
> > ###
> >
> >
> > diff --git a/gcc/config/aarch64/aarch64-cores.def
> > b/gcc/config/aarch64/aarch64-cores.def
> > index
> >
> e9a4b622be018d92a790db10f4d5cf926bba512c..380bd8d90fdc7bddea2c846
> > 5522a30f938c2ffc5 100644
> > --- a/gcc/config/aarch64/aarch64-cores.def
> > +++ b/gcc/config/aarch64/aarch64-cores.def
> > @@ -167,6 +167,8 @@ AARCH64_CORE("cortex-a510", cortexa510,
> > cortexa55, V9A, (SVE2_BITPERM, MEMTAG,
> >
> > AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A,
> > (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd47, -1)
> >
> > +AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A,
> > (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd4d, -1)
> > +
> > AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM,
> > MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
> >
> > AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM,
> BF16,
> > SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1) diff
> > --git a/gcc/config/aarch64/aarch64-tune.md
> > b/gcc/config/aarch64/aarch64-tune.md
> > index
> >
> 84e9bbf44f6222b3e5bcf4cbf8fab7ebf17015e1..f5b1482ba357d14f36e13ca3c
> > 4358865d4238e9a 100644
> > --- a/gcc/config/aarch64/aarch64-tune.md
> > +++ b/gcc/config/aarch64/aarch64-tune.md
> > @@ -1,5 +1,5 @@
> > ;; -*- buffer-read-only: t -*-
> > ;; Generated automatically by gentune.sh from aarch64-cores.def
> > (define_attr "tune"
> > -
> > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> >
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunde
> > r
> >
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> > hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> > a
> > 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,
> > co
> > rtexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,
> > oc
> >
> teontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thun
> > derx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,co
> > rt
> >
> exa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa5
> > 5
> > ,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen
> > 2,
> > demeter,neoversev2"
> > +
> > "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> >
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunde
> > r
> >
> xt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,t
> > hunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortex
> > a
> > 76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,
> > co
> > rtexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,
> > oc
> >
> teontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thun
> > derx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,co
> > rt
> >
> exa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa5
> > 5
> > ,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx
> > 2,n
> > eoversen2,demeter,neoversev2"
> > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git
> > a/gcc/doc/gcc/gcc-command-options/machine-dependent-
> > options/aarch64-options.rst b/gcc/doc/gcc/gcc-command-
> options/machine-
> > dependent-options/aarch64-options.rst
> > index
> >
> c2b23a6ee97ef2b7c74119f22c1d3e3d85385f4d..2e1bd6dbfb1fcff53dd562ec5
> > e8923d0a21cf715 100644
> > ---
[PATCH][GCC] aarch64: Add support for Cortex-X1C CPU.
Hi,
This patch adds support for Cortex-X1C CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X1C CPU.
* config/aarch64/aarch64-tune.md: Regenerate.
*
doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst:
Document Cortex-X1C CPU.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index
380bd8d90fdc7bddea2c8465522a30f938c2ffc5..d2671778928678f1ab8f7e6c79c9721f3abe1f5c
100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -110,6 +110,7 @@ AARCH64_CORE("cortex-a78c", cortexa78c, cortexa57, V8_2A,
(F16, RCPC, DOTPROD,
AARCH64_CORE("cortex-a65", cortexa65, cortexa53, V8_2A, (F16, RCPC, DOTPROD,
SSBS), cortexa73, 0x41, 0xd06, -1)
AARCH64_CORE("cortex-a65ae", cortexa65ae, cortexa53, V8_2A, (F16, RCPC,
DOTPROD, SSBS), cortexa73, 0x41, 0xd43, -1)
AARCH64_CORE("cortex-x1", cortexx1, cortexa57, V8_2A, (F16, RCPC, DOTPROD,
SSBS, PROFILE), neoversen1, 0x41, 0xd44, -1)
+AARCH64_CORE("cortex-x1c", cortexx1c, cortexa57, V8_2A, (F16, RCPC, DOTPROD,
SSBS, PROFILE, PAUTH), neoversen1, 0x41, 0xd4c, -1)
AARCH64_CORE("ares", ares, cortexa57, V8_2A, (F16, RCPC, DOTPROD, PROFILE),
neoversen1, 0x41, 0xd0c, -1)
AARCH64_CORE("neoverse-n1", neoversen1, cortexa57, V8_2A, (F16, RCPC,
DOTPROD, PROFILE), neoversen1, 0x41, 0xd0c, -1)
AARCH64_CORE("neoverse-e1", neoversee1, cortexa53, V8_2A, (F16, RCPC,
DOTPROD, SSBS), cortexa73, 0x41, 0xd4a, -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md
b/gcc/config/aarch64/aarch64-tune.md
index
f5b1482ba357d14f36e13ca3c4358865d4238e9a..22ec1be5a4c71b930221d2c4f1e62df57df0cadf
100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
-
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,neoversen2,demeter,neoversev2"
+
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,neoversen2,demeter,neoversev2"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
index
2e1bd6dbfb1fcff53dd562ec5e8923d0a21cf715..d97515d9e54feaa85a2ead4e9b73f0eb966cb39f
100644
---
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
+++
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
@@ -257,7 +257,7 @@ These options are defined for AArch64 implementations:
:samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
:samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
- :samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x2`,
+ :samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x1c`, :samp:`cortex-x2`,
:samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`cortex-a715`,
:samp:`ampere1`,
:samp:`native`.
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index
380bd8d90fdc7bddea2c8465522a30f938c2ffc5..d2671778928678f1ab8f7e6c79c9721f3abe1f5c
100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -110,6 +110,7 @@
[PATCH][GCC] aarch64: Add support for Cortex-A715 CPU.
Hi,
This patch adds support for Cortex-A715 CPU.
Bootstrapped on aarch64-none-linux-gnu and found no regressions.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715 CPU.
* config/aarch64/aarch64-tune.md: Regenerate.
*
doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst:
Document Cortex-A715 CPU.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index
e9a4b622be018d92a790db10f4d5cf926bba512c..380bd8d90fdc7bddea2c8465522a30f938c2ffc5
100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -167,6 +167,8 @@ AARCH64_CORE("cortex-a510", cortexa510, cortexa55, V9A,
(SVE2_BITPERM, MEMTAG,
AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A, (SVE2_BITPERM,
MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd47, -1)
+AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A, (SVE2_BITPERM,
MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd4d, -1)
+
AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM, MEMTAG,
I8MM, BF16), neoversen2, 0x41, 0xd48, -1)
AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16,
SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1)
diff --git a/gcc/config/aarch64/aarch64-tune.md
b/gcc/config/aarch64/aarch64-tune.md
index
84e9bbf44f6222b3e5bcf4cbf8fab7ebf17015e1..f5b1482ba357d14f36e13ca3c4358865d4238e9a
100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
-
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen2,demeter,neoversev2"
+
"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexa715,cortexx2,neoversen2,demeter,neoversev2"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
index
c2b23a6ee97ef2b7c74119f22c1d3e3d85385f4d..2e1bd6dbfb1fcff53dd562ec5e8923d0a21cf715
100644
---
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
+++
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst
@@ -258,7 +258,8 @@ These options are defined for AArch64 implementations:
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
:samp:`cortex-a75.cortex-a55`, :samp:`cortex-a76.cortex-a55`,
:samp:`cortex-r82`, :samp:`cortex-x1`, :samp:`cortex-x2`,
- :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`ampere1`, :samp:`native`.
+ :samp:`cortex-a510`, :samp:`cortex-a710`, :samp:`cortex-a715`,
:samp:`ampere1`,
+ :samp:`native`.
The values :samp:`cortex-a57.cortex-a53`, :samp:`cortex-a72.cortex-a53`,
:samp:`cortex-a73.cortex-a35`, :samp:`cortex-a73.cortex-a53`,
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index
e9a4b622be018d92a790db10f4d5cf926bba512c..380bd8d90fdc7bddea2c8465522a30f938c2ffc5
100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -167,6 +167,8 @@ AARCH64_CORE("cortex-a510", cortexa510, cortexa55, V9A,
(SVE2_BITPERM, MEMTAG,
AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A, (SVE2_BITPERM,
MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd47, -1)
+AARCH64_CORE("cortex-a715", cortexa715, cortexa57, V9A, (SVE2_BITPERM,
[PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".
Hi,
This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When
an exception is taken and "0xb5" instruction is encounter during runtime
stack-unwinding, we use effective vsp as modifier in pointer authentication.
On completion of stack unwinding if "0xb5" instruction is not encountered
then CFA will be used as modifier in pointer authentication.
[1] https://github.com/ARM-software/abi-aa/releases/download/2022Q3/ehabi32.pdf
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode opcode
"0xb5".
### Attachment also inlined for ease of reply###
diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c
index
e48854587c667a959aa66ccc4982231f6ecc..73e4942a39b34a83c2da85def6b13e82ec501552
100644
--- a/libgcc/config/arm/pr-support.c
+++ b/libgcc/config/arm/pr-support.c
@@ -107,7 +107,9 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
_uw op;
int set_pc;
int set_pac = 0;
+ int set_pac_sp = 0;
_uw reg;
+ _uw sp;
set_pc = 0;
for (;;)
@@ -124,10 +126,11 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
#if defined(TARGET_HAVE_PACBTI)
if (set_pac)
{
- _uw sp;
_uw lr;
_uw pac;
- _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, );
+ if (!set_pac_sp)
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32,
+);
_Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, );
_Unwind_VRS_Get (context, _UVRSC_PAC, R_IP,
_UVRSD_UINT32, );
@@ -259,7 +262,19 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
continue;
}
- if ((op & 0xfc) == 0xb4) /* Obsolete FPA. */
+ /* Use current VSP as modifier in PAC validation. */
+ if (op == 0xb5)
+ {
+ if (set_pac)
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32,
+);
+ else
+ return _URC_FAILURE;
+ set_pac_sp = 1;
+ continue;
+ }
+
+ if ((op & 0xfd) == 0xb6) /* Obsolete FPA. */
return _URC_FAILURE;
/* op & 0xf8 == 0xb8. */
diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c
index
e48854587c667a959aa66ccc4982231f6ecc..73e4942a39b34a83c2da85def6b13e82ec501552
100644
--- a/libgcc/config/arm/pr-support.c
+++ b/libgcc/config/arm/pr-support.c
@@ -107,7 +107,9 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
_uw op;
int set_pc;
int set_pac = 0;
+ int set_pac_sp = 0;
_uw reg;
+ _uw sp;
set_pc = 0;
for (;;)
@@ -124,10 +126,11 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
#if defined(TARGET_HAVE_PACBTI)
if (set_pac)
{
- _uw sp;
_uw lr;
_uw pac;
- _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, );
+ if (!set_pac_sp)
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32,
+);
_Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, );
_Unwind_VRS_Get (context, _UVRSC_PAC, R_IP,
_UVRSD_UINT32, );
@@ -259,7 +262,19 @@ __gnu_unwind_execute (_Unwind_Context * context,
__gnu_unwind_state * uws)
continue;
}
- if ((op & 0xfc) == 0xb4) /* Obsolete FPA. */
+ /* Use current VSP as modifier in PAC validation. */
+ if (op == 0xb5)
+ {
+ if (set_pac)
+ _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32,
+);
+ else
+ return _URC_FAILURE;
+ set_pac_sp = 1;
+ continue;
+ }
+
+ if ((op & 0xfd) == 0xb6) /* Obsolete FPA. */
return _URC_FAILURE;
/* op & 0xf8 == 0xb8. */
[PATCH][GCC] arm: Add support for Cortex-X1C CPU.
Hi,
This patch adds the -mcpu support for the Arm Cortex-X1C CPU.
Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf.
Ok for GCC master?
Regards,
Srinath.
gcc/ChangeLog:
2022-11-09 Srinath Parvathaneni
* config/arm/arm-cpus.in (cortex-x1c): Define new CPU.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* doc/gcc/gcc-command-options/machine-dependent-options/arm-options.rst:
Document Cortex-X1C CPU.
gcc/testsuite/ChangeLog:
2022-11-09 Srinath Parvathaneni
* gcc.target/arm/multilib.exp: Add tests for Cortex-X1C.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index
5a63bc548e54dbfdce5d1df425bd615d81895d80..5ed4db340bc5d7c9a41e6d1a3f660bf2a97b058b
100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1542,6 +1542,17 @@ begin cpu cortex-x1
part d44
end cpu cortex-x1
+begin cpu cortex-x1c
+ cname cortexx1c
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16+dotprod
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a57
+ vendor 41
+ part d4c
+end cpu cortex-x1c
+
begin cpu neoverse-n1
cname neoversen1
alias !ares
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index
e6461abcc57cd485025f3e18535267c454662cbe..a10a09e36cd004165b6f1efddeb3bfc29d8337ac
100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -255,6 +255,9 @@ Enum(processor_type) String(cortex-a710) Value(
TARGET_CPU_cortexa710)
EnumValue
Enum(processor_type) String(cortex-x1) Value( TARGET_CPU_cortexx1)
+EnumValue
+Enum(processor_type) String(cortex-x1c) Value( TARGET_CPU_cortexx1c)
+
EnumValue
Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index
abc290edd094179379f3856a3f8f64781e0c33f2..8af8c936abe31fb60e3de2fd713f4c6946c2a752
100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -46,7 +46,7 @@
cortexa73cortexa53,cortexa55,cortexa75,
cortexa76,cortexa76ae,cortexa77,
cortexa78,cortexa78ae,cortexa78c,
- cortexa710,cortexx1,neoversen1,
+ cortexa710,cortexx1,cortexx1c,neoversen1,
cortexa75cortexa55,cortexa76cortexa55,neoversev1,
neoversen2,cortexm23,cortexm33,
cortexm35p,cortexm55,starmc1,
diff --git
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/arm-options.rst
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/arm-options.rst
index
3315114969381995d47162b53abeb9bfc442fd28..d531eced20cbb583ecaba2ab3927937faf69b9de
100644
--- a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/arm-options.rst
+++ b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/arm-options.rst
@@ -594,7 +594,7 @@ These :samp:`-m` options are defined for the ARM port:
:samp:`cortex-r7`, :samp:`cortex-r8`, :samp:`cortex-r52`,
:samp:`cortex-r52plus`,
:samp:`cortex-m0`, :samp:`cortex-m0plus`, :samp:`cortex-m1`,
:samp:`cortex-m3`,
:samp:`cortex-m4`, :samp:`cortex-m7`, :samp:`cortex-m23`, :samp:`cortex-m33`,
- :samp:`cortex-m35p`, :samp:`cortex-m55`, :samp:`cortex-x1`,
+ :samp:`cortex-m35p`, :samp:`cortex-m55`, :samp:`cortex-x1`,
:samp:`cortex-x1c`,
:samp:`cortex-m1.small-multiply`, :samp:`cortex-m0.small-multiply`,
:samp:`cortex-m0plus.small-multiply`, :samp:`exynos-m1`, :samp:`marvell-pj4`,
:samp:`neoverse-n1`, :samp:`neoverse-n2`, :samp:`neoverse-v1`,
:samp:`xscale`,
diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp
b/gcc/testsuite/gcc.target/arm/multilib.exp
index
2fa648c61dafebb663969198bf7849400a7547f6..f903f028a83f884bdc1521f810f7e70e4130a715
100644
--- a/gcc/testsuite/gcc.target/arm/multilib.exp
+++ b/gcc/testsuite/gcc.target/arm/multilib.exp
@@ -450,6 +450,9 @@ if {[multilib_config "aprofile"] } {
{-march=armv8-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=hard -mthumb}
"thumb/v8-a+simd/hard"
{-march=armv7-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -mthumb}
"thumb/v7-a+simd/softfp"
{-march=armv8-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -mthumb}
"thumb/v8-a+simd/softfp"
+ {-mcpu=cortex-x1c -mfpu=auto -mfloat-abi=softfp -mthumb}
"thumb/v8-a+simd/softfp"
+ {-mcpu=cortex-x1c -mfpu=auto -mfloat-abi=hard -mthumb}
"thumb/v8-a+simd/hard"
+ {-mcpu=cortex-x1c -mfpu=auto -mfloat-abi=soft -mthumb} "thumb/v8-a/nofp"
} {
check_multi_dir $opts $dir
}
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index
5a63bc548e54dbfdce5d1df425bd615d81895d80..5ed4db340bc5d7c9a41e6d1a3f660bf2a97b058b
100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1542,6 +1542,17 @@ begin cpu cortex-x1
part d44
end cpu cortex-x1
+begin cpu cortex-x1c
+ cname cortexx1c
+
[GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives
accordingly.
This patch also adds support to emit ".pacspval" directive when "pac ip, lr,
sp" instruction
in generated in the assembly.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
Applying this patch on top of PACBTI series posted here
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599658.html and when
compiling the following
test.c with "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard
fasynchronous-unwind-tables -g -O0 -S" command line options, the assembly
output after this patch
looks like below:
$cat test.c
void fun1(int a);
void fun(int a,...)
{
fun1(a);
}
int main()
{
fun (10);
return 0;
}
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve+pacbti
-mbranch-protection=pac-ret -mthumb -mfloat-abi=hard
-fasynchronous-unwind-tables -g -O0 -S test.s
Assembly output:
...
fun:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -24
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
main:
...
.pacspval
pac ip, lr, sp
.cfi_register 143, 12
push{r3, r7, ip, lr}
.save {r3, r7, ra_auth_code, lr}
...
.cfi_offset 143, -8
...
.cfi_restore 143
...
aut ip, lr, sp
bx lr
...
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2022-11-04 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-9.c: New test.
2022-11-04 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add entry in enum.
* config/arm/arm.cc (pac_emit): Declare new global boolean variable.
(emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression.
(arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
(arm_expand_prologue): Update frame related infomration and reg notes
for pac/pacbit insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_unwind_emit_set): Add entry for IP_REGNUM in switch case.
(arm_unwind_emit): Update REG_CFA_REGISTER case._
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_PSEUDO_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2022-11-04 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-9.c: Likewise.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
b918ad3782fbee82320febb8b6e72ad615780261..ffeed45a678f17c63d5b42c21f020ca416cbf23f
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
a2dc3fc145c52d8381c54634687376089a47e704..91c400f12568156ed29bf5d5e59460bf887fbefb
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -820,7 +820,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_codePseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -861,7 +862,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -891,7 +892,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/*
[GCC][PATCH v2] arm: Add pacbti related multilib support for armv8.1-m.main.
Hi, This patch adds the support for pacbti multlilib linking by making "-mbranch-protection=none" as default in the command line for all M-profile targets and uses "-mbranch-protection=none" for multilib matching. If any valid value is passed to "-mbranch-protection" in the command line, this new value overwrites the default value in the command line and uses "-mbranch-protection=standard" for multilib matching. Eg 1. If the passed command line flags are: a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto b) -mcpu=cortex-m85+nopacbti -mfloat-abi=hard -mfpu=auto After this patch the command line flags the compiler receives will be: a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto -mbranch-protection=none b) -mcpu=cortex-m85+nopacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=none "-mbranch-protection=none" will be used in the multilib matching. Eg 2. If the passed command line flags are: a) -march=armv8.1-m.main+mve+pacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret b) -mcpu=cortex-m85 -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret+bti After this patch the command line flags the compiler receives will be: a) -march=armv8.1-m.main+mve+pacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret b) -mcpu=cortex-m85 -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret+bti "-mbranch-protection=standard" will be used in the multilib matching. Eg 3. For A-profile target, if the passed command line flags are: -march=armv8-a+simd -mfloat-abi=hard -mfpu=auto Even after this patch the command line flags compiler receives will remain the same: -march=armv8-a+simd -mfloat-abi=hard -mfpu=auto Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-10-28 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_branch_protection_option): Define new function. * config/arm/arm-cpus.in (armv8.1-m.main): Move dsp option below pacbti option. * config/arm/arm.h (arm_canon_branch_protection_option): Define function prototype. (CANON_BRANCH_PROTECTION_SPEC_FUNCTION): Define macro. (MBRANCH_PROTECTION_SPECS): Likewise. * config/arm/t-rmprofile (MULTI_ARCH_OPTS_RM): Add new options. (MULTI_ARCH_DIRS_RM): Add new directories. (MULTILIB_REQUIRED): Add new option. (MULTILIB_REUSE): Reuse existing multlibs. (MULTILIB_MATCHES): Match multilib strings. gcc/testsuite/ChangeLog: 2022-10-28 Srinath Parvathaneni * gcc.target/arm/multilib.exp (multilib_config "rmprofile"): Update tests. * gcc.target/arm/pac-10.c: New test. * gcc.target/arm/pac-11.c: Likewise. * gcc.target/arm/pac-12.c: Likewise. rb16143.patch.gz Description: application/gzip
RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU.
Hi,
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, October 17, 2022 2:30 PM
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55
> CPU.
>
> Hi Srinath,
>
>
> On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi,
> >
> > This patch adds cde feature (optional) support for Cortex-M55 CPU,
> > please refer [1] for more details. To use this feature we need to
> > specify +cdecpN (e.g. -mcpu=cortex-m55+cdecp), where N is the
> coprocessor number 0 to 7.
> >
> > Bootstrapped for arm-none-linux-gnueabihf target, regression tested on
> > arm-none-eabi target and found no regressions.
> >
> > [1] https://developer.arm.com/documentation/101051/0101/?lang=en
> (version: r1p1).
> >
> > Ok for master?
> >
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2022-10-07 Srinath Parvathaneni
> >
> > * common/config/arm/arm-common.cc (arm_canon_arch_option_1):
> Ignore cde
> > options for mlibarch.
> > * config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
> > * doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2022-10-07 Srinath Parvathaneni
> >
> > * gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55
> > CPU.
> >
> >
> > ### Attachment also inlined for ease of reply
> ###
> >
> >
> > diff --git a/gcc/common/config/arm/arm-common.cc
> > b/gcc/common/config/arm/arm-common.cc
> > index
> >
> c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..b6f955b3c012475f398382e72
> c9a
> > 3966412991ec 100644
> > --- a/gcc/common/config/arm/arm-common.cc
> > +++ b/gcc/common/config/arm/arm-common.cc
> > @@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char
> **argv, bool arch_for_multilib)
> > arm_initialize_isa (target_isa, selected_cpu->common.isa_bits);
> > arm_parse_option_features (target_isa, _cpu->common,
> > strchr (cpu, '+'));
> > + if (arch_for_multilib)
> > + {
> > + const enum isa_feature removable_bits[] =
> {ISA_IGNORE_FOR_MULTILIB,
> > +isa_nobit};
> > + sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
> > + arm_initialize_isa (isa_bits, removable_bits);
> > + bitmap_and_compl (target_isa, target_isa, isa_bits);
> > + }
> > +
>
> I can see the piece of code you add here is exactly the same as the one a few
> lines above when handling "if (arch)". Can this be moved below and thus be
> common to the two cases, or does it have to be performed before
> bitmap_ior of fpu_isa?
Thanks for pointing out this, I have moved the common code below the arch and
cpu
if blocks in the attached patch.
> Also, IIUC, CDE was already optional for other CPUs (M33, M35P, star-mc1),
> so the hunk above fixes a latent bug when handling multilibs for these CPUs
> too? If so, maybe worth splitting the patch into two parts since the above is
> not strictly related to M55?
>
Even though CDE is optional for the mentioned CPUs as per the specs, the code to
enable CDE as optional feature is missing in current compiler.
Current GCC compiler supports CDE as optional feature only with -march options
and
this pass adds CDE as optional for M55 and so this is not a fix bug.
> But I'm not a maintainer ;-)
>
> Thanks,
>
> Christophe
>
> > if (fpu && strcmp (fpu, "auto") != 0)
> > {
> > /* The easiest and safest way to remove the default fpu diff
> > --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index
> >
> 5a63bc548e54dbfdce5d1df425bd615d81895d80..aa02c04c4924662f3ddd58e
> 69673
> > 92ba3f4b4a87 100644
> > --- a/gcc/config/arm/arm-cpus.in
> > +++ b/gcc/config/arm/arm-cpus.in
> > @@ -1633,6 +1633,14 @@ begin cpu cortex-m55
> >option nomve remove mve mve_float
> >option nofp remove ALL_FP mve_float
> >option nodsp remove MVE mve_float
> > + option cdecp0 add cdecp0
> > + option cdecp1 add cdecp1
> > + option cdecp2 add cdecp2
> > + option cdecp3 add cdecp3
> > + option cdecp4 add cdecp4
> > + option cdecp5 add cdecp5
> > + option cdecp6 add cdecp6
> > + option cdecp7 add cdecp7
> >isa quirk_no_asmcpu quirk_vlldm
> >costs v7m
> >vendor 41
> > diff --git a/
[GCC][PATCH] arm: Add cde feature support for Cortex-M55 CPU.
Hi,
This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer
[1] for more details. To use this feature we need to specify +cdecpN
(e.g. -mcpu=cortex-m55+cdecp), where N is the coprocessor number 0 to 7.
Bootstrapped for arm-none-linux-gnueabihf target, regression tested
on arm-none-eabi target and found no regressions.
[1] https://developer.arm.com/documentation/101051/0101/?lang=en (version:
r1p1).
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2022-10-07 Srinath Parvathaneni
* common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde
options for mlibarch.
* config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
* doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.
gcc/testsuite/ChangeLog:
2022-10-07 Srinath Parvathaneni
* gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55 CPU.
### Attachment also inlined for ease of reply###
diff --git a/gcc/common/config/arm/arm-common.cc
b/gcc/common/config/arm/arm-common.cc
index
c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..b6f955b3c012475f398382e72c9a3966412991ec
100644
--- a/gcc/common/config/arm/arm-common.cc
+++ b/gcc/common/config/arm/arm-common.cc
@@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool
arch_for_multilib)
arm_initialize_isa (target_isa, selected_cpu->common.isa_bits);
arm_parse_option_features (target_isa, _cpu->common,
strchr (cpu, '+'));
+ if (arch_for_multilib)
+ {
+ const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
+isa_nobit};
+ sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_bits, removable_bits);
+ bitmap_and_compl (target_isa, target_isa, isa_bits);
+ }
+
if (fpu && strcmp (fpu, "auto") != 0)
{
/* The easiest and safest way to remove the default fpu
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index
5a63bc548e54dbfdce5d1df425bd615d81895d80..aa02c04c4924662f3ddd58e6967392ba3f4b4a87
100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1633,6 +1633,14 @@ begin cpu cortex-m55
option nomve remove mve mve_float
option nofp remove ALL_FP mve_float
option nodsp remove MVE mve_float
+ option cdecp0 add cdecp0
+ option cdecp1 add cdecp1
+ option cdecp2 add cdecp2
+ option cdecp3 add cdecp3
+ option cdecp4 add cdecp4
+ option cdecp5 add cdecp5
+ option cdecp6 add cdecp6
+ option cdecp7 add cdecp7
isa quirk_no_asmcpu quirk_vlldm
costs v7m
vendor 41
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
aa5655764a0360959f9c1061749d2cc9ebd23489..26857f7a90e42d925bc6908686ac78138a53c4ad
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21698,6 +21698,10 @@ floating-point instructions on @samp{cortex-m55}.
Disable the M-Profile Vector Extension (MVE) single precision floating-point
instructions on @samp{cortex-m55}.
+@item +cdecp0, +cdecp1, ... , +cdecp7
+Enable the Custom Datapath Extension (CDE) on selected coprocessors according
+to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}.
+
@item +nofp
Disables the floating-point instructions on @samp{arm9e},
@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp
b/gcc/testsuite/gcc.target/arm/multilib.exp
index
2fa648c61dafebb663969198bf7849400a7547f6..7a977bff58b7b68bfe9e49d7602989a39caa6534
100644
--- a/gcc/testsuite/gcc.target/arm/multilib.exp
+++ b/gcc/testsuite/gcc.target/arm/multilib.exp
@@ -851,6 +851,18 @@ if {[multilib_config "rmprofile"] } {
{-mcpu=cortex-m55+nomve+nofp -mfpu=auto -mfloat-abi=softfp}
"thumb/v8-m.main/nofp"
{-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=soft}
"thumb/v8-m.main/nofp"
{-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=softfp}
"thumb/v8-m.main/nofp"
+ {-mcpu=cortex-m55 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard"
+ {-mcpu=cortex-m55+cdecp0 -mfloat-abi=hard -mfpu=auto}
"thumb/v8-m.main+dp/hard"
+ {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=hard -mfpu=auto}
"thumb/v8-m.main+dp/hard"
+
{-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
-mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard"
+ {-mcpu=cortex-m55 -mfloat-abi=softfp -mfpu=auto}
"thumb/v8-m.main+dp/softfp"
+ {-mcpu=cortex-m55+cdecp0 -mfloat-abi=softfp -mfpu=auto}
"thumb/v8-m.main+dp/softfp"
+ {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=softfp -mfpu=auto}
"thumb/v8-m.main+dp/softfp"
+
{-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
-mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp"
+ {-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp"
+
[GCC 13/15][PATCH v3] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
When compiled with " -march=armv8.1-m.main -mbranch-protection=pac-ret+leaf+bti
-mthumb
-mfloat-abi=soft -fasynchronous-unwind-tables -g -O2 -S" command line options,
the assembly
output after this patch looks like below:
...
.cfi_startproc
pacbti ip, lr, sp
movsr1, #40
push{ip, lr}
.save {ra_auth_code, lr}
.cfi_def_cfa_offset 8
.cfi_offset 143, -8
.cfi_offset 14, -4
...
pop {ip, lr}
.cfi_restore 14
.cfi_restore 143
.cfi_def_cfa_offset 0
movsr0, #0
aut ip, lr, sp
bx lr
.cfi_endproc
...
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2022-08-17 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add to enum.
* config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression.
(arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
(arm_expand_prologue): Mark as frame related insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_Pseudo_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2022-08-17 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-9.c: Likewise.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
b918ad3782fbee82320febb8b6e72ad615780261..ffeed45a678f17c63d5b42c21f020ca416cbf23f
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
3495ab857eac38ecdf37e55f1d201b1c35cbde0b..c7067819f6785e44d30d8e5365505ab98682
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -816,7 +816,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_codePseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -857,7 +858,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -887,7 +888,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1063,10 +1064,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1253,12 +1254,15 @@ extern int arm_regs_in_sequence[];
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM,\
SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
- APSRGE_REGNUM, VPR_REGNUM\
+ APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE
RE: [GCC][PATCH v2] arm: Add support for Arm Cortex-M85 CPU.
Hi, This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default. -mpcu=cortex-m85 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp. Also following options are provided to disable default features. +nomve.fp (disables MVE Floating point) +nomve (disables MVE Integer and MVE Floating point) +nodsp (disables dsp, MVE Integer and MVE Floating point) +nopacbti (disables pacbti) +nofp (disables floating point and MVE floating point) Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni * config/arm/arm-cpus.in (cortex-m85): Define new CPU. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m85. * (-mfix-cmse-cve-2021-35465): Likewise. gcc/testsuite/ChangeLog: 2022-08-12 Srinath Parvathaneni * gcc.target/arm/multilib.exp: Add tests for cortex-m85. patch_15922 Description: patch_15922
[PATCH 13/15] arm: Add pacbti related multilib support for armv8.1-m.main.
Hi, This patch supports following -march/-mbranch-protection combination by linking them to existing pacbti multilibs. $ -march=armv8.1-m.main+pacbti+fp.dp+mve.fp -mbranch-protection=standard -mfloat-abi=hard -mthumb $ -march=armv8.1-m.main+pacbti+fp.dp+mve -mbranch-protection=standard -mfloat-abi=hard -mthumb $ -march=armv8.1-m.main+dsp+pacbti+fp.dp -mbranch-protection=standard -mfloat-abi=hard -mthumb Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni * config/arm/t-rmprofile: Add pacbti multililb variants. gcc/testsuite/ChangeLog: 2022-08-12 Srinath Parvathaneni * gcc.target/arm/pac-10.c: New test. * gcc.target/arm/pac-11.c: Likewise. * gcc.target/arm/pac-12.c: Likewise. patch_16143 Description: patch_16143
[Committed] arm: Document +no options for Cortex-M55 CPU.
Hi,
This patch documents the following options for Arm Cortex-M55 CPU under -mcpu=
list.
+nomve.fp (disables MVE single precision floating point instructions)
+nomve (disables MVE integer and single precision floating point instructions)
+nodsp (disables dsp, MVE integer and single precision floating point
instructions)
+nofp (disables floating point instructions)
Committed as obvious to master.
Regards,
Srinath.
gcc/ChangeLog:
2022-08-12 Srinath Parvathaneni
* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55 options.
### Attachment also inlined for ease of reply###
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
3b529c420c94f70519abfd79acd90d216203c8a7..b264ae28fe6dbe5c298f3b91e4ce3fd8e6a0fb7f
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21638,14 +21638,25 @@ The following extension options are common to the
listed CPUs:
@table @samp
@item +nodsp
-Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}.
+Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}
+and @samp{cortex-m55}. Also disable the M-Profile Vector Extension (MVE)
+integer and single precision floating-point instructions on @samp{cortex-m55}.
+
+@item +nomve
+Disable the M-Profile Vector Extension (MVE) integer and single precision
+floating-point instructions on @samp{cortex-m55}.
+
+@item +nomve.fp
+Disable the M-Profile Vector Extension (MVE) single precision floating-point
+instructions on @samp{cortex-m55}.
@item +nofp
Disables the floating-point instructions on @samp{arm9e},
@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
@samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
@samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
-@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}.
+@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}
+and @samp{cortex-m55}.
Disables the floating-point and SIMD instructions on
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
3b529c420c94f70519abfd79acd90d216203c8a7..b264ae28fe6dbe5c298f3b91e4ce3fd8e6a0fb7f
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21638,14 +21638,25 @@ The following extension options are common to the
listed CPUs:
@table @samp
@item +nodsp
-Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}.
+Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}
+and @samp{cortex-m55}. Also disable the M-Profile Vector Extension (MVE)
+integer and single precision floating-point instructions on @samp{cortex-m55}.
+
+@item +nomve
+Disable the M-Profile Vector Extension (MVE) integer and single precision
+floating-point instructions on @samp{cortex-m55}.
+
+@item +nomve.fp
+Disable the M-Profile Vector Extension (MVE) single precision floating-point
+instructions on @samp{cortex-m55}.
@item +nofp
Disables the floating-point instructions on @samp{arm9e},
@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
@samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
@samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
-@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}.
+@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}
+and @samp{cortex-m55}.
Disables the floating-point and SIMD instructions on
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
[GCC][PATCH] arm: Add support for Arm Cortex-M85 CPU.
Hi,
This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an
Armv8.1-M Mainline CPU supporting MVE and PACBTI by default.
-mpcu=cortex-m85 switch by default matches to
-march=armv8.1-m.main+pacbti+mve.fp+fp.dp.
Also following options are provided to disable default features.
+nomve.fp (disables MVE Floating point)
+nomve (disables MVE Integer and MVE Floating point)
+nodsp (disables dsp, MVE Integer and MVE Floating point)
+nopacbti (disables pacbti)
+nofp (disables floating point and MVE floating point)
Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2022-08-05 Srinath Parvathaneni
* config/arm/arm-cpus.in (cortex-m85): Define new cpu.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* config/arm/t-rmprofile: Re-use multilibs.
* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m85.
* (-mfix-cmse-cve-2021-35465): Likewise.
gcc/testsuite/ChangeLog:
2022-08-05 Srinath Parvathaneni
* gcc.target/arm/multilib.exp: Add tests for cortex-m85.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index
9502a34fa974744f02ded4f32c03de6169950120..a6f364309f8728d6d2264b4e60feb75d51b87b64
100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1643,6 +1643,21 @@ begin cpu cortex-m55
vendor 41
end cpu cortex-m55
+begin cpu cortex-m85
+ cname cortexm85
+ tune flags LDSCHED
+ architecture armv8.1-m.main+pacbti+mve.fp+fp.dp
+ option nopacbti remove pacbti
+ option nomve.fp remove mve_float
+ option nomve remove mve mve_float
+ option nofp remove ALL_FP mve_float
+ option nodsp remove MVE mve_float
+ isa quirk_no_asmcpu quirk_vlldm
+ costs v7m
+ part 0xd23
+ vendor 41
+end cpu cortex-m85
+
# V8 R-profile implementations.
begin cpu cortex-r52
cname cortexr52
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index
ef0cc5ef0c87ce37958fc0ac9b1623078b890187..54f87da7852b3e495da9fd08106d9f6bd7c99716
100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m35p) Value(
TARGET_CPU_cortexm35p)
EnumValue
Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55)
+EnumValue
+Enum(processor_type) String(cortex-m85) Value( TARGET_CPU_cortexm85)
+
EnumValue
Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index
3422553604245035089e4f52b3feb9db4c51b2b5..27cafe9b4caf9270cb5f537c988d57715495a207
100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -49,6 +49,6 @@
cortexa710,cortexx1,neoversen1,
cortexa75cortexa55,cortexa76cortexa55,neoversev1,
neoversen2,cortexm23,cortexm33,
- cortexm35p,cortexm55,cortexr52,
+ cortexm35p,cortexm55,cortexm85,cortexr52,
cortexr52plus"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile
index
fe46a1efa1a8b212e6f4051283573debfc386ff8..77e248e47feeddb2328a82aec6b485ff0f6fd62e
100644
--- a/gcc/config/arm/t-rmprofile
+++ b/gcc/config/arm/t-rmprofile
@@ -97,6 +97,13 @@ MULTILIB_MATCHES += $(foreach FP, $(v8_1m_sp_variants), \
MULTILIB_MATCHES += $(foreach FP, $(v8_1m_dp_variants), \
march?armv8-m.main+fp.dp=mlibarch?armv8.1-m.main$(FP))
+MULTILIB_MATCHES +=
march?armv8.1-m.main+pacbti+fp.dp=march?armv8.1-m.main+pacbti+fp.dp+mve.fp
+MULTILIB_MATCHES +=
march?armv8.1-m.main+pacbti+fp.dp=mlibarch?armv8.1-m.main+pacbti+fp.dp+mve.fp
+MULTILIB_MATCHES +=
march?armv8.1-m.main+pacbti+fp.dp=march?armv8.1-m.main+pacbti+fp.dp+mve
+MULTILIB_MATCHES +=
march?armv8.1-m.main+pacbti+fp.dp=mlibarch?armv8.1-m.main+pacbti+fp.dp+mve
+MULTILIB_MATCHES +=
march?armv8.1-m.main+pacbti+fp.dp=march?armv8.1-m.main+dsp+pacbti+fp.dp
+MULTILIB_MATCHES +=
march?armv8.1-m.main+pacbti+fp.dp=mlibarch?armv8.1-m.main+dsp+pacbti+fp.dp
+
# Map all mbranch-protection values other than 'none' to 'standard'.
MULTILIB_MATCHES += mbranch-protection?standard=mbranch-protection?bti
MULTILIB_MATCHES +=
mbranch-protection?standard=mbranch-protection?pac-ret
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
a2be3446594822f0b13dc7ba92ada4213a3a965c..47988ca6bedccc8efd1801a784d4f313959e8bb4
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21079,7 +21079,7 @@ Permissible names are: @samp{arm7tdmi},
@samp{arm7tdmi-s}, @samp{arm710t},
@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus},
@samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
RE: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Ping!!
> -Original Message-
> From: Gcc-patches bounces+srinath.parvathaneni=arm@gcc.gnu.org> On Behalf Of Srinath
> Parvathaneni via Gcc-patches
> Sent: 05 May 2022 12:02
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: [PATCH v2][GCC] arm: Add support for dwarf debug directives and
> pseudo hard-register for PAC feature.
>
> Hello,
>
> This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
> hard-register and also .save {ra_auth_code} and .cfi_offset ra_auth_code
> dwarf directives for the PAC feature in Armv8.1-M architecture.
>
> RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
>
> When compiled with " -march=armv8.1-m.main -mbranch-protection=pac-
> ret+leaf+bti -mthumb -mfloat-abi=soft -fasynchronous-unwind-tables -g -O2
> -S" command line options, the assembly output after this patch looks like
> below:
>
> ...
> .cfi_startproc
> pacbti ip, lr, sp
> movsr1, #40
> push{ip, lr}
> .save {ra_auth_code, lr}
> .cfi_def_cfa_offset 8
> .cfi_offset 143, -8
> .cfi_offset 14, -4
> ...
> pop {ip, lr}
> .cfi_restore 14
> .cfi_restore 143
> .cfi_def_cfa_offset 0
> movsr0, #0
> aut ip, lr, sp
> bx lr
> .cfi_endproc
> ...
>
> This patch can be committed after the patch at
> https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583407.html
> is committed.
>
> Regression tested on arm-none-eabi target and found no regressions.
>
> Ok for master?
>
> Regards,
> Srinath.
>
> gcc/ChangeLog:
>
> 2022-04-06 Srinath Parvathaneni
>
> * config/arm/aout.h (ra_auth_code): Add to enum.
> * config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE
> register to
> dwarf frame expression.
> (arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
> (arm_expand_prologue): Mark as frame related insn.
> (arm_regno_class): Check for pac pseudo reigster.
> (arm_dbx_register_number): Assign ra_auth_code register number in
> dwarf.
> (arm_unwind_emit_sequence): Print .save directive with ra_auth_code
> register.
> (arm_conditional_register_usage): Mark ra_auth_code in fixed
> reigsters.
> * config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
> (IS_PAC_Pseudo_REGNUM): Define.
> (enum reg_class): Add PAC_REG entry.
> * config/arm/arm.md (RA_AUTH_CODE): Define.
>
> gcc/testsuite/ChangeLog:
>
> 2022-04-06 Srinath Parvathaneni
>
> * g++.target/arm/pac-1.C: New test.
> * gcc.target/arm/pac-9.c: Likewise.
>
>
> ### Attachment also inlined for ease of reply
> ###
>
>
> diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index
> b918ad3782fbee82320febb8b6e72ad615780261..ffeed45a678f17c63d5b42c2
> 1f020ca416cbf23f 100644
> --- a/gcc/config/arm/aout.h
> +++ b/gcc/config/arm/aout.h
> @@ -74,7 +74,8 @@
>"wr8", "wr9", "wr10", "wr11", \
>"wr12", "wr13", "wr14", "wr15", \
>"wcgr0", "wcgr1", "wcgr2", "wcgr3",\
> - "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
> + "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0", \
> + "ra_auth_code" \
> }
> #endif
>
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index
> 3495ab857eac38ecdf37e55f1d201b1c35cbde0b..c7067819f6785e44d30d
> 8e5365505ab98682 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -816,7 +816,8 @@ extern const int arm_arch_cde_coproc_bits[];
> s16-s31 S VFP variable (aka d8-d15).
> vfpcc Not a real register. Represents the VFP condition
> code flags.
> - vpr Used to represent MVE VPR predication. */
> + vpr Used to represent MVE VPR predication.
> + ra_auth_codePseudo register to save PAC. */
>
> /* The stack backtrace structure is as follows:
>fp points to here: | save code pointer | [fp]
> @@ -857,7 +858,7 @@ extern const int arm_arch_cde_coproc_bits[];
>1,1,1,1,1,1,1,1, \
>1,1,1,1,
[PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
When compiled with " -march=armv8.1-m.main -mbranch-protection=pac-ret+leaf+bti
-mthumb
-mfloat-abi=soft -fasynchronous-unwind-tables -g -O2 -S" command line options,
the assembly
output after this patch looks like below:
...
.cfi_startproc
pacbti ip, lr, sp
movsr1, #40
push{ip, lr}
.save {ra_auth_code, lr}
.cfi_def_cfa_offset 8
.cfi_offset 143, -8
.cfi_offset 14, -4
...
pop {ip, lr}
.cfi_restore 14
.cfi_restore 143
.cfi_def_cfa_offset 0
movsr0, #0
aut ip, lr, sp
bx lr
.cfi_endproc
...
This patch can be committed after the patch at
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583407.html
is committed.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2022-04-06 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add to enum.
* config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression.
(arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
(arm_expand_prologue): Mark as frame related insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_Pseudo_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2022-04-06 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
* gcc.target/arm/pac-9.c: Likewise.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
b918ad3782fbee82320febb8b6e72ad615780261..ffeed45a678f17c63d5b42c21f020ca416cbf23f
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
3495ab857eac38ecdf37e55f1d201b1c35cbde0b..c7067819f6785e44d30d8e5365505ab98682
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -816,7 +816,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_codePseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -857,7 +858,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -887,7 +888,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1063,10 +1064,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1253,12 +1254,15 @@ extern int arm_regs_in_sequence[];
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM,\
SP_REGNUM,
Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Ping!!
From: Srinath Parvathaneni
Sent: 13 December 2021 10:44
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Tejas Belagod
Subject: Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and
pseudo hard-register for PAC feature.
Ping!!
From: Srinath Parvathaneni
Sent: 12 November 2021 18:03
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Tejas Belagod
Subject: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo
hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
When compiled with "arm-none-eabi-gcc -O2 -mthumb -march=armv8.1-m.main+pacbti
-S -fasynchronous-unwind-tables -g"
command line options, the directives supported in this patch looks like below:
...
push{ip}
.save {ra_auth_code}
.cfi_def_cfa_offset 8
.cfi_offset 143, -8
...
This patch can be committed after the patch at
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583407.html
is committed.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2021-11-12 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add to enum.
* config/arm/arm.c (emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression instead of IP_REGNUM.
(arm_expand_prologue): Mark as frame related insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_Pseudo_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2021-11-12 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
25a2812a663742893b928398b0d3948e97f1905b..c69e299e012f46c8d0711830125dbf2f6b2e93d7
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
8e6ef41f6b065217d1af3f4f1cb85b2d8fbd0dc0..f31944e85c9ab83501f156d138e2aea1bcb5b79d
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -815,7 +815,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_codePseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -856,7 +857,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -886,7 +887,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1062,10 +1063,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1248,12
Re: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Ping!!
From: Srinath Parvathaneni
Sent: 12 November 2021 18:03
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Tejas Belagod
Subject: [PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo
hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
When compiled with "arm-none-eabi-gcc -O2 -mthumb -march=armv8.1-m.main+pacbti
-S -fasynchronous-unwind-tables -g"
command line options, the directives supported in this patch looks like below:
...
push{ip}
.save {ra_auth_code}
.cfi_def_cfa_offset 8
.cfi_offset 143, -8
...
This patch can be committed after the patch at
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583407.html
is committed.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2021-11-12 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add to enum.
* config/arm/arm.c (emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression instead of IP_REGNUM.
(arm_expand_prologue): Mark as frame related insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_Pseudo_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2021-11-12 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
25a2812a663742893b928398b0d3948e97f1905b..c69e299e012f46c8d0711830125dbf2f6b2e93d7
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
8e6ef41f6b065217d1af3f4f1cb85b2d8fbd0dc0..f31944e85c9ab83501f156d138e2aea1bcb5b79d
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -815,7 +815,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_codePseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -856,7 +857,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -886,7 +887,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1062,10 +1063,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1248,12 +1249,15 @@ extern int arm_regs_in_sequence[];
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM,\
SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
- APSRGE_REGNUM, VPR_REGNUM\
+ APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \
}
[PATCH v2][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
When compiled with "arm-none-eabi-gcc -O2 -mthumb -march=armv8.1-m.main+pacbti
-S -fasynchronous-unwind-tables -g"
command line options, the directives supported in this patch looks like below:
...
push{ip}
.save {ra_auth_code}
.cfi_def_cfa_offset 8
.cfi_offset 143, -8
...
This patch can be committed after the patch at
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583407.html
is committed.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2021-11-12 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add to enum.
* config/arm/arm.c (emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression instead of IP_REGNUM.
(arm_expand_prologue): Mark as frame related insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_Pseudo_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2021-11-12 Srinath Parvathaneni
* g++.target/arm/pac-1.C: New test.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
25a2812a663742893b928398b0d3948e97f1905b..c69e299e012f46c8d0711830125dbf2f6b2e93d7
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
8e6ef41f6b065217d1af3f4f1cb85b2d8fbd0dc0..f31944e85c9ab83501f156d138e2aea1bcb5b79d
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -815,7 +815,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_codePseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -856,7 +857,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -886,7 +887,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1062,10 +1063,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1248,12 +1249,15 @@ extern int arm_regs_in_sequence[];
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM,\
SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
- APSRGE_REGNUM, VPR_REGNUM\
+ APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \
}
#define IS_VPR_REGNUM(REGNUM) \
((REGNUM) == VPR_REGNUM)
+#define IS_PAC_Pseudo_REGNUM(REGNUM) \
+ ((REGNUM) == RA_AUTH_CODE)
+
/* Use different register alloc ordering for Thumb. */
#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
@@ -1292,6 +1296,7 @@ enum
[PATCH][GCC] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature.
Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
When compiled with "arm-none-eabi-gcc -O2 -mthumb -march=armv8.1-m.main+pacbti
-S -fasynchronous-unwind-tables -g"
command line options, the directives supported in this patch looks like below:
...
push{ip}
.save {ra_auth_code}
.cfi_def_cfa_offset 8
.cfi_offset 143, -8
...
This patch can be committed after the patch at
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583407.html
is committed.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2021-11-12 Srinath Parvathaneni
* config/arm/aout.h (ra_auth_code): Add to enum.
* config/arm/arm.c (emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression instead of IP_REGNUM.
(arm_expand_prologue): Mark as frame related insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_Pseudo_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2021-11-12 Srinath Parvathaneni
* gcc.target/arm/pac-6.c: New test.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
25a2812a663742893b928398b0d3948e97f1905b..c69e299e012f46c8d0711830125dbf2f6b2e93d7
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
8e6ef41f6b065217d1af3f4f1cb85b2d8fbd0dc0..f31944e85c9ab83501f156d138e2aea1bcb5b79d
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -815,7 +815,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_codePseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -856,7 +857,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -886,7 +887,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1\
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1062,10 +1063,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1248,12 +1249,15 @@ extern int arm_regs_in_sequence[];
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM,\
SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
- APSRGE_REGNUM, VPR_REGNUM\
+ APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \
}
#define IS_VPR_REGNUM(REGNUM) \
((REGNUM) == VPR_REGNUM)
+#define IS_PAC_Pseudo_REGNUM(REGNUM) \
+ ((REGNUM) == RA_AUTH_CODE)
+
/* Use different register alloc ordering for Thumb. */
#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
@@ -1292,6 +1296,7 @@ enum
[PATCH][GCC-11] arm: Fix multilib mapping for CDE extensions [PR100856].
Hi,
This is a backport to gcc-11 and the patch applied cleanly on the branch.
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by
generating a separate canonical string by removing compiler options which are
not
required for multilib linking from march string and assign the new string to
mlibarch
option. This mlibarch string is used for multilib comparison.
Ok for gcc-11 branch?
Regards,
Srinath.
gcc/ChangeLog:
2021-06-10 Srinath Parvathaneni
PR target/100856
* common/config/arm/arm-common.c (arm_canon_arch_option_1): New function
derived from arm_canon_arch.
(arm_canon_arch_option): Call it.
(arm_canon_arch_multilib_option): New function.
* config/arm/arm-cpus.in (IGNORE_FOR_MULTILIB): New fgroup.
* config/arm/arm.h (arm_canon_arch_multilib_option): New prototype.
(CANON_ARCH_MULTILIB_SPEC_FUNCTION): New macro.
(MULTILIB_ARCH_CANONICAL_SPECS): New macro.
(DRIVER_SELF_SPECS): Add MULTILIB_ARCH_CANONICAL_SPECS.
* config/arm/arm.opt (mlibarch): New option.
* config/arm/t-rmprofile (MULTILIB_MATCHES): For armv8*-m, replace use
of march on RHS with mlibarch.
gcc/testsuite/ChangeLog:
2021-06-10 Srinath Parvathaneni
PR target/100856
* gcc.target/arm/acle/pr100856.c: New test.
* gcc.target/arm/multilib.exp: Add tests for cde options.
(cherry picked from commit f58d03b5df25f9eab06b7eacea8da780fc2e0219)
### Attachment also inlined for ease of reply###
diff --git a/gcc/common/config/arm/arm-common.c
b/gcc/common/config/arm/arm-common.c
index
9980af6885c3dfe68f61fa0f39b23022b4e59c19..481aa9e43d9c73e464e1e992ad7d94c30d2db001
100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -627,9 +627,15 @@ public:
The options array consists of couplets of information where the
first item in each couplet is the string describing which option
name was selected (arch, cpu, fpu) and the second is the value
- passed for that option. */
-const char *
-arm_canon_arch_option (int argc, const char **argv)
+ passed for that option.
+
+ arch_for_multilib is boolean variable taking value true or false.
+ arch_for_multilib is false when the canonical representation is for -march
+ option and it is true when canonical representation is for -mlibarch option.
+ On passing arch_for_multilib true the canonical string generated will be
+ without the compiler options which are not required for multilib linking.
*/
+static const char *
+arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib)
{
const char *arch = NULL;
const char *cpu = NULL;
@@ -694,8 +700,8 @@ arm_canon_arch_option (int argc, const char **argv)
/* First build up a bitmap describing the target architecture. */
if (arch)
{
- selected_arch = arm_parse_arch_option_name (all_architectures,
- "-march", arch);
+ selected_arch = arm_parse_arch_option_name (all_architectures, "-march",
+ arch, !arch_for_multilib);
if (selected_arch == NULL)
return "";
@@ -703,6 +709,15 @@ arm_canon_arch_option (int argc, const char **argv)
arm_initialize_isa (target_isa, selected_arch->common.isa_bits);
arm_parse_option_features (target_isa, _arch->common,
strchr (arch, '+'));
+ if (arch_for_multilib)
+ {
+ const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
+isa_nobit};
+ sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_bits, removable_bits);
+ bitmap_and_compl (target_isa, target_isa, isa_bits);
+ }
+
if (fpu && strcmp (fpu, "auto") != 0)
{
/* We assume that architectures do not have any FPU bits
@@ -719,7 +734,8 @@ arm_canon_arch_option (int argc, const char **argv)
else if (cpu)
{
const cpu_option *selected_cpu
- = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu);
+ = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu,
+!arch_for_multilib);
if (selected_cpu == NULL)
return "";
@@ -1069,3 +1085,22 @@ arm_asm_auto_mfpu (int argc, const char **argv)
#define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+
+/* Returns a canonical representation of the -march option from the current
+ -march string (if given) and other options on the command line that might
+ affect the architecture. */
+const char *
+arm_canon_arch_option (int argc, const char **argv)
+{
+ return arm_canon_arch_option_1 (argc, argv, false);
+}
+
[PATCH][GCC-10] arm: Fix multilib mapping for CDE extensions [PR100856].
Hi,
This is a backport to gcc-10 and the patch applied cleanly on the branch.
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by
generating a separate canonical string by removing compiler options which are
not
required for multilib linking from march string and assign the new string to
mlibarch
option. This mlibarch string is used for multilib comparison.
Ok for gcc-10 branch?
Regards,
Srinath.
gcc/ChangeLog:
2021-06-10 Srinath Parvathaneni
PR target/100856
* common/config/arm/arm-common.c (arm_canon_arch_option_1): New function
derived from arm_canon_arch.
(arm_canon_arch_option): Call it.
(arm_canon_arch_multilib_option): New function.
* config/arm/arm-cpus.in (IGNORE_FOR_MULTILIB): New fgroup.
* config/arm/arm.h (arm_canon_arch_multilib_option): New prototype.
(CANON_ARCH_MULTILIB_SPEC_FUNCTION): New macro.
(MULTILIB_ARCH_CANONICAL_SPECS): New macro.
(DRIVER_SELF_SPECS): Add MULTILIB_ARCH_CANONICAL_SPECS.
* config/arm/arm.opt (mlibarch): New option.
* config/arm/t-rmprofile (MULTILIB_MATCHES): For armv8*-m, replace use
of march on RHS with mlibarch.
gcc/testsuite/ChangeLog:
2021-06-10 Srinath Parvathaneni
PR target/100856
* gcc.target/arm/acle/pr100856.c: New test.
* gcc.target/arm/multilib.exp: Add tests for cde options.
(cherry picked from commit f58d03b5df25f9eab06b7eacea8da780fc2e0219)
### Attachment also inlined for ease of reply###
diff --git a/gcc/common/config/arm/arm-common.c
b/gcc/common/config/arm/arm-common.c
index
78a779c935071c534a780821d399cb7d2e170808..a4b3e86ad5251be18f7131cd05fdab40f11d3742
100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -590,9 +590,15 @@ public:
The options array consists of couplets of information where the
first item in each couplet is the string describing which option
name was selected (arch, cpu, fpu) and the second is the value
- passed for that option. */
-const char *
-arm_canon_arch_option (int argc, const char **argv)
+ passed for that option.
+
+ arch_for_multilib is boolean variable taking value true or false.
+ arch_for_multilib is false when the canonical representation is for -march
+ option and it is true when canonical representation is for -mlibarch option.
+ On passing arch_for_multilib true the canonical string generated will be
+ without the compiler options which are not required for multilib linking.
*/
+static const char *
+arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib)
{
const char *arch = NULL;
const char *cpu = NULL;
@@ -657,8 +663,8 @@ arm_canon_arch_option (int argc, const char **argv)
/* First build up a bitmap describing the target architecture. */
if (arch)
{
- selected_arch = arm_parse_arch_option_name (all_architectures,
- "-march", arch);
+ selected_arch = arm_parse_arch_option_name (all_architectures, "-march",
+ arch, !arch_for_multilib);
if (selected_arch == NULL)
return "";
@@ -666,6 +672,15 @@ arm_canon_arch_option (int argc, const char **argv)
arm_initialize_isa (target_isa, selected_arch->common.isa_bits);
arm_parse_option_features (target_isa, _arch->common,
strchr (arch, '+'));
+ if (arch_for_multilib)
+ {
+ const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
+isa_nobit};
+ sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_bits, removable_bits);
+ bitmap_and_compl (target_isa, target_isa, isa_bits);
+ }
+
if (fpu && strcmp (fpu, "auto") != 0)
{
/* We assume that architectures do not have any FPU bits
@@ -682,7 +697,8 @@ arm_canon_arch_option (int argc, const char **argv)
else if (cpu)
{
const cpu_option *selected_cpu
- = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu);
+ = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu,
+!arch_for_multilib);
if (selected_cpu == NULL)
return "";
@@ -1032,3 +1048,22 @@ arm_asm_auto_mfpu (int argc, const char **argv)
#define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+
+/* Returns a canonical representation of the -march option from the current
+ -march string (if given) and other options on the command line that might
+ affect the architecture. */
+const char *
+arm_canon_arch_option (int argc, const char **argv)
+{
+ return arm_canon_arch_option_1 (argc, argv, false);
+}
+
[GCC][PATCH] arm: Fix multilib mapping for CDE extensions [PR100856].
Hi Richard,
I have all addressed all your review comments (in [1]) in the below patch.
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by
generating a separate canonical string by removing compiler options which are
not
required for multilib linking from march string and assign the new string to
mlibarch
option. This mlibarch string is used for multilib comparison.
Regression tested on arm-none-eabi and found no regressions.
Ok for master?
[1] https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571731.html
Regards,
Srinath.
gcc/ChangeLog:
2021-06-14 Srinath Parvathaneni
PR target/100856
* common/config/arm/arm-common.c (arm_canon_arch_option_1): New function
derived from arm_canon_arch.
(arm_canon_arch_option): Call it.
(arm_canon_arch_multilib_option): New function.
* config/arm/arm-cpus.in (IGNORE_FOR_MULTILIB): New fgroup.
* config/arm/arm.h (arm_canon_arch_multilib_option): New prototype.
(CANON_ARCH_MULTILIB_SPEC_FUNCTION): New macro.
(MULTILIB_ARCH_CANONICAL_SPECS): New macro.
(DRIVER_SELF_SPECS): Add MULTILIB_ARCH_CANONICAL_SPECS.
* config/arm/arm.opt (mlibarch): New option.
* config/arm/t-rmprofile (MULTILIB_MATCHES): For armv8*-m, replace use
of march on RHS with mlibarch.
gcc/testsuite/ChangeLog:
2021-06-14 Srinath Parvathaneni
PR target/100856
* gcc.target/arm/acle/pr100856.c: New test.
* gcc.target/arm/multilib.exp: Add tests for cde options.
### Attachment also inlined for ease of reply###
diff --git a/gcc/common/config/arm/arm-common.c
b/gcc/common/config/arm/arm-common.c
index
9980af6885c3dfe68f61fa0f39b23022b4e59c19..481aa9e43d9c73e464e1e992ad7d94c30d2db001
100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -627,9 +627,15 @@ public:
The options array consists of couplets of information where the
first item in each couplet is the string describing which option
name was selected (arch, cpu, fpu) and the second is the value
- passed for that option. */
-const char *
-arm_canon_arch_option (int argc, const char **argv)
+ passed for that option.
+
+ arch_for_multilib is boolean variable taking value true or false.
+ arch_for_multilib is false when the canonical representation is for -march
+ option and it is true when canonical representation is for -mlibarch option.
+ On passing arch_for_multilib true the canonical string generated will be
+ without the compiler options which are not required for multilib linking.
*/
+static const char *
+arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib)
{
const char *arch = NULL;
const char *cpu = NULL;
@@ -694,8 +700,8 @@ arm_canon_arch_option (int argc, const char **argv)
/* First build up a bitmap describing the target architecture. */
if (arch)
{
- selected_arch = arm_parse_arch_option_name (all_architectures,
- "-march", arch);
+ selected_arch = arm_parse_arch_option_name (all_architectures, "-march",
+ arch, !arch_for_multilib);
if (selected_arch == NULL)
return "";
@@ -703,6 +709,15 @@ arm_canon_arch_option (int argc, const char **argv)
arm_initialize_isa (target_isa, selected_arch->common.isa_bits);
arm_parse_option_features (target_isa, _arch->common,
strchr (arch, '+'));
+ if (arch_for_multilib)
+ {
+ const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
+isa_nobit};
+ sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_bits, removable_bits);
+ bitmap_and_compl (target_isa, target_isa, isa_bits);
+ }
+
if (fpu && strcmp (fpu, "auto") != 0)
{
/* We assume that architectures do not have any FPU bits
@@ -719,7 +734,8 @@ arm_canon_arch_option (int argc, const char **argv)
else if (cpu)
{
const cpu_option *selected_cpu
- = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu);
+ = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu,
+!arch_for_multilib);
if (selected_cpu == NULL)
return "";
@@ -1069,3 +1085,22 @@ arm_asm_auto_mfpu (int argc, const char **argv)
#define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+
+/* Returns a canonical representation of the -march option from the current
+ -march string (if given) and other options on the command line that might
+ affect the architecture. */
+const char *
+arm_canon_arch_option (int argc, const char
[GCC-10 backport][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.
Hi, This patch fixes the issue mentioned in PR101016, which is mve polymorphic variants failing at linking with undefined reference to "__ARM_undef" error. Regression tested on arm-none-eabi and found no regressions. This patch have cleanly applied, ok for the GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants matching code. (__arm_vld1q_z): Likewise. (__arm_vld2q): Likewise. (__arm_vld4q): Likewise. (__arm_vldrbq_gather_offset): Likewise. (__arm_vldrbq_gather_offset_z): Likewise. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * gcc.target/arm/mve/intrinsics/pr101016.c: New test. (cherry picked from commit b13f297f01c943aa167f7c6eb94bed40dce0d553) ### Attachment also inlined for ease of reply### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 1132c7cf87d217a380cf26dd6f110130ea7bf175..4aa3787ca536215450fcb1a5bb602b7d5bdbbb16 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -37559,47 +37559,47 @@ extern void *__ARM_undef; #define __arm_vld1q(p0) (\ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(p0, int8_t const *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(p0, int16_t const *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(p0, int32_t const *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(p0, uint8_t const *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(p0, uint16_t const *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(p0, uint32_t const *)), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(p0, float16_t const *)), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(p0, float32_t const * + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t * #define __arm_vld1q_z(p0,p1) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce(p0, int8_t const *), p1), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce(p0, int16_t const *), p1), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce(p0, int32_t const *), p1), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce(p0, uint8_t const *), p1), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce(p0, uint16_t const *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce(p0, uint32_t const *), p1), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce(p0, float16_t const *), p1), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce(p0, float32_t const *), p1))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) #define __arm_vld2q(p0) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce(p0, int8_t const *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]:
[GCC-11 backport][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.
Hi, This patch fixes the issue mentioned in PR101016, which is mve polymorphic variants failing at linking with undefined reference to "__ARM_undef" error. Regression tested on arm-none-eabi and found no regressions. This patch have cleanly applied, ok for the GCC-11 branch? gcc/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants matching code. (__arm_vld1q_z): Likewise. (__arm_vld2q): Likewise. (__arm_vld4q): Likewise. (__arm_vldrbq_gather_offset): Likewise. (__arm_vldrbq_gather_offset_z): Likewise. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/101016 * gcc.target/arm/mve/intrinsics/pr101016.c: New test. (cherry picked from commit b13f297f01c943aa167f7c6eb94bed40dce0d553) ### Attachment also inlined for ease of reply### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index dc1d874a6366eb5fe755a70c72ed371c915bd04b..182b2aac6da5d4f0046aa628b0d813ff8e43839a 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -37565,47 +37565,47 @@ extern void *__ARM_undef; #define __arm_vld1q(p0) (\ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(p0, int8_t const *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(p0, int16_t const *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(p0, int32_t const *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(p0, uint8_t const *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(p0, uint16_t const *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(p0, uint32_t const *)), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(p0, float16_t const *)), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(p0, float32_t const * + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t * #define __arm_vld1q_z(p0,p1) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce(p0, int8_t const *), p1), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce(p0, int16_t const *), p1), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce(p0, int32_t const *), p1), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce(p0, uint8_t const *), p1), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce(p0, uint16_t const *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce(p0, uint32_t const *), p1), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce(p0, float16_t const *), p1), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce(p0, float32_t const *), p1))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) #define __arm_vld2q(p0) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce(p0, int8_t const *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16
[GCC-10 backport][PATCH] arm: Fix the mve multilib for the broken cmse support (pr99939).
Hi,
The current CMSE support in the multilib build for
"-march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto" is broken
as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
This patch have cleanly applied, ok for the GCC-10 branch?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2021-06-11 Srinath Parvathaneni
PR target/99939
* gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler
directives check for target is v8.1-m.main+mve or not before
comparing the assembly output.
* gcc.target/arm/cmse/cmse-20.c: New test.
libgcc/ChangeLog:
2021-06-11 Srinath Parvathaneni
PR target/99939
* config/arm/cmse_nonsecure_call.S: Add __ARM_FEATURE_MVE
macro.
* config/arm/t-arm: To link cmse.o and cmse_nonsecure_call.o
on passing -mcmse option.
(cherry picked from commit c5ed0148347beea1bd34795de146a2454c36)
### Attachment also inlined for ease of reply###
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
..08e89bff6378f1f96950fc40f3ab3946bd433773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
@@ -0,0 +1,28 @@
+/* This test is executed only if the execution engine supports CMSE
instructions. */
+/* { dg-options "--save-temps -mcmse
-Wl,--section-start,.gnu.sgstubs=0x0040" } */
+
+#include
+#include
+#include
+
+void __attribute__((cmse_nonsecure_entry))
+secure_fun (int a, int *p)
+{
+ void *b = cmse_check_address_range ((void *)p, a, 1);
+
+ if (b == NULL)
+ __builtin_abort ();
+ printf("%d", *((int *)b));
+}
+
+int
+main (void)
+{
+ int *ptr;
+ int size = 1;
+ ptr = (int *) calloc (1, sizeof(int *));
+ *ptr = 1315852292;
+ secure_fun (size, ptr);
+ free (ptr);
+ return 0;
+}
diff --git a/libgcc/config/arm/cmse_nonsecure_call.S
b/libgcc/config/arm/cmse_nonsecure_call.S
index
5ba28692d6b8a919939404d0f0d97d490df472e9..b1954b8714d6badc7311992847492c8c123799e0
100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -25,7 +25,7 @@
.syntax unified
#ifdef __ARM_PCS_VFP
-# if __ARM_FP & 0x8
+# if (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
.fpu fpv5-d16
# else
.fpu fpv4-sp-d16
@@ -59,7 +59,7 @@ vmov s24, s25, r5, r5
vmov s26, s27, r5, r5
vmov s28, s29, r5, r5
vmov s30, s31, r5, r5
-#elif __ARM_FP & 0x08
+#elif (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
vmov.f64d9, d8
vmov.f64d10, d8
vmov.f64d11, d8
diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm
index
3625a2590beec4e4e0e0881be9ad284c595c7190..c1553d4e5d80751b13dc2e9c9e36d5ebe82e5f8c
100644
--- a/libgcc/config/arm/t-arm
+++ b/libgcc/config/arm/t-arm
@@ -3,18 +3,17 @@ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi
_thumb1_case_shi \
_thumb1_case_uhi _thumb1_case_si _speculation_barrier
HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E
- /dev/null
2>/dev/null; echo $$?),0)
CMSE_OPTS:=-mcmse
endif
ifdef HAVE_CMSE
-ifndef HAVE_V81M
+
libgcc-objects += cmse.o cmse_nonsecure_call.o
cmse.o: $(srcdir)/config/arm/cmse.c
$(gcc_compile) -c $(CMSE_OPTS) $<
+
cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
$(gcc_compile) -c $<
endif
-endif
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
[GCC-11 backport][PATCH] arm: Fix the mve multilib for the broken cmse support (pr99939).
Hi,
The current CMSE support in the multilib build for
"-march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto" is broken
as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
This patch have cleanly applied, ok for the GCC-11 branch?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2021-06-11 Srinath Parvathaneni
PR target/99939
* gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler
directives check for target is v8.1-m.main+mve or not before
comparing the assembly output.
* gcc.target/arm/cmse/cmse-20.c: New test.
libgcc/ChangeLog:
2021-06-11 Srinath Parvathaneni
PR target/99939
* config/arm/cmse_nonsecure_call.S: Add __ARM_FEATURE_MVE
macro.
* config/arm/t-arm: To link cmse.o and cmse_nonsecure_call.o
on passing -mcmse option.
(cherry picked from commit c5ed0148347beea1bd34795de146a2454c36)
### Attachment also inlined for ease of reply###
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
..08e89bff6378f1f96950fc40f3ab3946bd433773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
@@ -0,0 +1,28 @@
+/* This test is executed only if the execution engine supports CMSE
instructions. */
+/* { dg-options "--save-temps -mcmse
-Wl,--section-start,.gnu.sgstubs=0x0040" } */
+
+#include
+#include
+#include
+
+void __attribute__((cmse_nonsecure_entry))
+secure_fun (int a, int *p)
+{
+ void *b = cmse_check_address_range ((void *)p, a, 1);
+
+ if (b == NULL)
+ __builtin_abort ();
+ printf("%d", *((int *)b));
+}
+
+int
+main (void)
+{
+ int *ptr;
+ int size = 1;
+ ptr = (int *) calloc (1, sizeof(int *));
+ *ptr = 1315852292;
+ secure_fun (size, ptr);
+ free (ptr);
+ return 0;
+}
diff --git a/libgcc/config/arm/cmse_nonsecure_call.S
b/libgcc/config/arm/cmse_nonsecure_call.S
index
146f3ed52e9c7e915e5dbd9b70624ec3bd7cd5b5..00830ade98ea650c328c709d5d308fbc96f7f21c
100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -25,7 +25,7 @@
.syntax unified
#ifdef __ARM_PCS_VFP
-# if __ARM_FP & 0x8
+# if (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
.fpu fpv5-d16
# else
.fpu fpv4-sp-d16
@@ -59,7 +59,7 @@ vmov s24, s25, r5, r5
vmov s26, s27, r5, r5
vmov s28, s29, r5, r5
vmov s30, s31, r5, r5
-#elif __ARM_FP & 0x08
+#elif (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
vmov.f64d9, d8
vmov.f64d10, d8
vmov.f64d11, d8
diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm
index
3625a2590beec4e4e0e0881be9ad284c595c7190..c1553d4e5d80751b13dc2e9c9e36d5ebe82e5f8c
100644
--- a/libgcc/config/arm/t-arm
+++ b/libgcc/config/arm/t-arm
@@ -3,18 +3,17 @@ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi
_thumb1_case_shi \
_thumb1_case_uhi _thumb1_case_si _speculation_barrier
HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E
- /dev/null
2>/dev/null; echo $$?),0)
CMSE_OPTS:=-mcmse
endif
ifdef HAVE_CMSE
-ifndef HAVE_V81M
+
libgcc-objects += cmse.o cmse_nonsecure_call.o
cmse.o: $(srcdir)/config/arm/cmse.c
$(gcc_compile) -c $(CMSE_OPTS) $<
+
cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
$(gcc_compile) -c $<
endif
-endif
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).
Hi Richard,
I have addressed all your review comments in
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571739.html
in the following patch.
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve
-mfloat-abi=hard -mfpu=auto"
is broken as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
Ok for master? and Ok for GCC-10 branch?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2021-06-11 Srinath Parvathaneni
PR target/99939
* gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler
directives check for target is v8.1-m.main+mve or not before
comparing the assembly output.
* gcc.target/arm/cmse/cmse-20.c: New test.
libgcc/ChangeLog:
2021-06-11 Srinath Parvathaneni
PR target/99939
* config/arm/cmse_nonsecure_call.S: Add __ARM_FEATURE_MVE
macro.
* config/arm/t-arm: To link cmse.o and cmse_nonsecure_call.o
on passing -mcmse option.
### Attachment also inlined for ease of reply###
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
..08e89bff6378f1f96950fc40f3ab3946bd433773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
@@ -0,0 +1,28 @@
+/* This test is executed only if the execution engine supports CMSE
instructions. */
+/* { dg-options "--save-temps -mcmse
-Wl,--section-start,.gnu.sgstubs=0x0040" } */
+
+#include
+#include
+#include
+
+void __attribute__((cmse_nonsecure_entry))
+secure_fun (int a, int *p)
+{
+ void *b = cmse_check_address_range ((void *)p, a, 1);
+
+ if (b == NULL)
+ __builtin_abort ();
+ printf("%d", *((int *)b));
+}
+
+int
+main (void)
+{
+ int *ptr;
+ int size = 1;
+ ptr = (int *) calloc (1, sizeof(int *));
+ *ptr = 1315852292;
+ secure_fun (size, ptr);
+ free (ptr);
+ return 0;
+}
diff --git a/libgcc/config/arm/cmse_nonsecure_call.S
b/libgcc/config/arm/cmse_nonsecure_call.S
index
146f3ed52e9c7e915e5dbd9b70624ec3bd7cd5b5..00830ade98ea650c328c709d5d308fbc96f7f21c
100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -25,7 +25,7 @@
.syntax unified
#ifdef __ARM_PCS_VFP
-# if __ARM_FP & 0x8
+# if (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
.fpu fpv5-d16
# else
.fpu fpv4-sp-d16
@@ -59,7 +59,7 @@ vmov s24, s25, r5, r5
vmov s26, s27, r5, r5
vmov s28, s29, r5, r5
vmov s30, s31, r5, r5
-#elif __ARM_FP & 0x08
+#elif (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
vmov.f64d9, d8
vmov.f64d10, d8
vmov.f64d11, d8
diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm
index
3625a2590beec4e4e0e0881be9ad284c595c7190..c1553d4e5d80751b13dc2e9c9e36d5ebe82e5f8c
100644
--- a/libgcc/config/arm/t-arm
+++ b/libgcc/config/arm/t-arm
@@ -3,18 +3,17 @@ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi
_thumb1_case_shi \
_thumb1_case_uhi _thumb1_case_si _speculation_barrier
HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E
- /dev/null
2>/dev/null; echo $$?),0)
CMSE_OPTS:=-mcmse
endif
ifdef HAVE_CMSE
-ifndef HAVE_V81M
+
libgcc-objects += cmse.o cmse_nonsecure_call.o
cmse.o: $(srcdir)/config/arm/cmse.c
$(gcc_compile) -c $(CMSE_OPTS) $<
+
cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
$(gcc_compile) -c $<
endif
-endif
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).
Hi Richard,
I have addressed all your review comments in
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571739.html
in the following patch.
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve
-mfloat-abi=hard -mfpu=auto"
is broken as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
Ok for master? and Ok for GCC-10 branch?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2021-06-11 Srinath Parvathaneni
* gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler
directives check for target is v8.1-m.main+mve or not before
comparing the assembly output.
* gcc.target/arm/cmse/cmse-20.c: New test.
libgcc/ChangeLog:
2021-06-11 Srinath Parvathaneni
* config/arm/cmse_nonsecure_call.S: Add __ARM_FEATURE_MVE
macro.
* config/arm/t-arm: To link cmse.o and cmse_nonsecure_call.o
on passing -mcmse option.
### Attachment also inlined for ease of reply###
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
..08e89bff6378f1f96950fc40f3ab3946bd433773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
@@ -0,0 +1,28 @@
+/* This test is executed only if the execution engine supports CMSE
instructions. */
+/* { dg-options "--save-temps -mcmse
-Wl,--section-start,.gnu.sgstubs=0x0040" } */
+
+#include
+#include
+#include
+
+void __attribute__((cmse_nonsecure_entry))
+secure_fun (int a, int *p)
+{
+ void *b = cmse_check_address_range ((void *)p, a, 1);
+
+ if (b == NULL)
+ __builtin_abort ();
+ printf("%d", *((int *)b));
+}
+
+int
+main (void)
+{
+ int *ptr;
+ int size = 1;
+ ptr = (int *) calloc (1, sizeof(int *));
+ *ptr = 1315852292;
+ secure_fun (size, ptr);
+ free (ptr);
+ return 0;
+}
diff --git a/libgcc/config/arm/cmse_nonsecure_call.S
b/libgcc/config/arm/cmse_nonsecure_call.S
index
146f3ed52e9c7e915e5dbd9b70624ec3bd7cd5b5..00830ade98ea650c328c709d5d308fbc96f7f21c
100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -25,7 +25,7 @@
.syntax unified
#ifdef __ARM_PCS_VFP
-# if __ARM_FP & 0x8
+# if (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
.fpu fpv5-d16
# else
.fpu fpv4-sp-d16
@@ -59,7 +59,7 @@ vmov s24, s25, r5, r5
vmov s26, s27, r5, r5
vmov s28, s29, r5, r5
vmov s30, s31, r5, r5
-#elif __ARM_FP & 0x08
+#elif (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1)
vmov.f64d9, d8
vmov.f64d10, d8
vmov.f64d11, d8
diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm
index
3625a2590beec4e4e0e0881be9ad284c595c7190..c1553d4e5d80751b13dc2e9c9e36d5ebe82e5f8c
100644
--- a/libgcc/config/arm/t-arm
+++ b/libgcc/config/arm/t-arm
@@ -3,18 +3,17 @@ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi
_thumb1_case_shi \
_thumb1_case_uhi _thumb1_case_si _speculation_barrier
HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E
- /dev/null
2>/dev/null; echo $$?),0)
CMSE_OPTS:=-mcmse
endif
ifdef HAVE_CMSE
-ifndef HAVE_V81M
+
libgcc-objects += cmse.o cmse_nonsecure_call.o
cmse.o: $(srcdir)/config/arm/cmse.c
$(gcc_compile) -c $(CMSE_OPTS) $<
+
cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
$(gcc_compile) -c $<
endif
-endif
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
index
e1ff09257b7900982f49117d4cfc16f3bd79d76c..db7d975a90ea4bd1810aea03949ec1e8837e
100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-18.c
@@ -8,4 +8,5 @@ void bar(f func, int a)
func(a);
}
-/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r4:SI\\\]\\\]" "final" {
target { ! arm_v8_1m_mve_ok } } } } */
+/* { dg-final { scan-rtl-dump "call unspec\\\[\\\[r\[0-7\]:SI\\\]\\\]" "final"
{ target { arm_v8_1m_mve_ok } } } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
RE: [GCC][PATCH] arm: Fix multilib mapping for CDE extensions.
Hi Richard,
I have all addressed all your review comments in the trailing in the patch
attached.
Please review and let me know if it ok for master?
Regards,
Srinath.
> -Original Message-
> From: Richard Earnshaw
> Sent: 02 June 2021 15:20
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [GCC][PATCH] arm: Fix multilib mapping for CDE extensions.
>
>
>
> On 01/06/2021 18:08, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi All,
> >
> > On passing +cdecp[0-7] extension to the -march string in command line
> > options, multilib linking is failing as mentioned in PR100856. This
> > patch fixes this issue by generating a separate -march string only for
> multilib comparison.
> >
> > Regression tested on arm-none-eabi and found no regressions.
> >
> > Ok for master?
> >
> Not as it stands. More comments below.
>
> > Regards,
> > Srinath.
> >
> > gcc/ChangeLog:
> >
> > 2021-06-01 Srinath Parvathaneni
> >
> > PR target/100856
> > * common/config/arm/arm-common.c (arm_canon_arch_option):
> Modify
> > function to generate canonical march string after removing cde
> related
> > compiler extensions.
> > (arm_canon_arch_multilib_option): Define function.
> > * config/arm/arm-cpus.in (CDE_LIST): Define fgroup.
> > * config/arm/arm.h (arm_canon_arch_multilib_option): Define
> macro.
> > (CANON_ARCH_MULTILIB_SPEC_FUNCTION): Define macro.
> > (ARCH_CANONICAL_MULTILIB_SPECS): Define macro.
> > (TARGET_MULTLILIB_ARCH): Define macro.
> > * gcc.c (used_arg_t::operator ()): Add condition to generate separate
> > march string for multilib matching.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2021-06-01 Srinath Parvathaneni
> >
> > PR target/100856
> > * gcc.target/arm/acle/pr100856.c: New test.
> > * gcc.target/arm/multilib.exp: Modify.
> >
> >
> >
> > ### Attachment also inlined for ease of reply
> ###
> >
> >
> > diff --git a/gcc/common/config/arm/arm-common.c
> > b/gcc/common/config/arm/arm-common.c
> > index
> >
> 9980af6885c3dfe68f61fa0f39b23022b4e59c19..7d8c6e5253f3f1683eed99f479
> a0
> > 9186a46c2d22 100644
> > --- a/gcc/common/config/arm/arm-common.c
> > +++ b/gcc/common/config/arm/arm-common.c
> > @@ -616,6 +616,8 @@ public:
> > }
> > };
> >
> > +static int multilib_arch = 0;
>
> Please, no! Instead...
>
> > +
> > /* Generate a canonical representation of the -march option from the
> > current -march string (if given) and other options on the command
> > line that might affect the architecture. This aids multilib
> > selection @@ -703,6 +705,14 @@ arm_canon_arch_option (int argc, const
> > char **argv)
>
> This function should be renamed arm_canon_arch_option_1 and given an
> extra (bool) parameter to control the behaviour. Then
> arm_canon_arch_option can call it with the parameter false to maintain the
> existing behaviour and arm_canon_arch_multilib_option can pass true.
>
> > arm_initialize_isa (target_isa, selected_arch->common.isa_bits);
> > arm_parse_option_features (target_isa, _arch->common,
> > strchr (arch, '+'));
> > + if (multilib_arch == 1)
> > + {
> > + const enum isa_feature cde_bitlist[] = {ISA_ALL_CDE, isa_nobit};
>
> This is too specific, but that's mostly a naming problem. Instead we need a
> new feature group IGNORE_FOR_MULTILIB (which at present just contains
> ALL_CDE).
>
> > + sbitmap isa_cdebits = sbitmap_alloc (isa_num_bits);
> > + arm_initialize_isa (isa_cdebits, cde_bitlist);
> > + bitmap_and_compl (target_isa, target_isa, isa_cdebits);
> > + }
> > +
> > if (fpu && strcmp (fpu, "auto") != 0)
> > {
> > /* We assume that architectures do not have any FPU bits @@
> > -786,18 +796,27 @@ arm_canon_arch_option (int argc, const char **argv)
> >
> > arm_initialize_isa (base_isa, selected_arch->common.isa_bits);
> >
> > - /* Architecture has no extension options, so just return the canonical
> > - architecture name. */
> > - if (selected_arch->common.extensions == NULL)
> > -return selected_arch->common.name;
> > -
> > /* We're only interested in extension bits. */
> > bitmap_and_compl (target_isa, target_isa, base_isa);
> >
> > + /* Architecture has
[GCC][PATCH] arm: Fix polymorphic variants failing with undefined reference to `__ARM_undef` error.
Hi, This patch fixes the issue mentioned in PR101016, which is mve polymorphic variants failing at linking with undefined reference to "__ARM_undef" error. Regression tested on arm-none-eabi and found no regressions. Ok for master? Regards, Srinath. gcc/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants matching code. (__arm_vld1q_z): Likewise. (__arm_vld2q): Likewise. (__arm_vld4q): Likewise. (__arm_vldrbq_gather_offset): Likewise. (__arm_vldrbq_gather_offset_z): Likewise. gcc/testsuite/ChangeLog: 2021-06-10 Srinath Parvathaneni PR target/101016 * gcc.target/arm/mve/intrinsics/pr101016.c: New test. ### Attachment also inlined for ease of reply### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 1380f3acbfe64026bc882c308bb1c243e27ac4b3..83f10036990fc3df956fb2fa4818d1304138b485 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -37565,47 +37565,47 @@ extern void *__ARM_undef; #define __arm_vld1q(p0) (\ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce(p0, int8_t const *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce(p0, int16_t const *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce(p0, int32_t const *)), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce(p0, uint8_t const *)), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce(p0, uint16_t const *)), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce(p0, uint32_t const *)), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce(p0, float16_t const *)), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce(p0, float32_t const * + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_s8 (__ARM_mve_coerce1(p0, int8_t *)), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_s16 (__ARM_mve_coerce1(p0, int16_t *)), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_s32 (__ARM_mve_coerce1(p0, int32_t *)), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_u8 (__ARM_mve_coerce1(p0, uint8_t *)), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_u16 (__ARM_mve_coerce1(p0, uint16_t *)), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_u32 (__ARM_mve_coerce1(p0, uint32_t *)), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_f16 (__ARM_mve_coerce1(p0, float16_t *)), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_f32 (__ARM_mve_coerce1(p0, float32_t * #define __arm_vld1q_z(p0,p1) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce(p0, int8_t const *), p1), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce(p0, int16_t const *), p1), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce(p0, int32_t const *), p1), \ - int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce(p0, uint8_t const *), p1), \ - int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce(p0, uint16_t const *), p1), \ - int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce(p0, uint32_t const *), p1), \ - int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce(p0, float16_t const *), p1), \ - int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce(p0, float32_t const *), p1))) + int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld1q_z_s8 (__ARM_mve_coerce1(p0, int8_t *), p1), \ + int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld1q_z_s16 (__ARM_mve_coerce1(p0, int16_t *), p1), \ + int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld1q_z_s32 (__ARM_mve_coerce1(p0, int32_t *), p1), \ + int (*)[__ARM_mve_type_uint8_t_ptr]: __arm_vld1q_z_u8 (__ARM_mve_coerce1(p0, uint8_t *), p1), \ + int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld1q_z_u16 (__ARM_mve_coerce1(p0, uint16_t *), p1), \ + int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld1q_z_u32 (__ARM_mve_coerce1(p0, uint32_t *), p1), \ + int (*)[__ARM_mve_type_float16_t_ptr]: __arm_vld1q_z_f16 (__ARM_mve_coerce1(p0, float16_t *), p1), \ + int (*)[__ARM_mve_type_float32_t_ptr]: __arm_vld1q_z_f32 (__ARM_mve_coerce1(p0, float32_t *), p1))) #define __arm_vld2q(p0) ( \ _Generic( (int (*)[__ARM_mve_typeid(p0)])0, \ - int (*)[__ARM_mve_type_int8_t_ptr]: __arm_vld2q_s8 (__ARM_mve_coerce(p0, int8_t const *)), \ - int (*)[__ARM_mve_type_int16_t_ptr]: __arm_vld2q_s16 (__ARM_mve_coerce(p0, int16_t const *)), \ - int (*)[__ARM_mve_type_int32_t_ptr]: __arm_vld2q_s32
RE: [GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).
Hi Richard,
> -Original Message-
> From: Richard Earnshaw
> Sent: 13 April 2021 14:55
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [GCC][Patch] arm: Fix the mve multilib for the broken cmse
> support (pr99939).
>
>
>
> On 12/04/2021 14:04, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi,
> >
> > The current CMSE support in the multilib build for "-march=armv8.1-
> m.main+mve -mfloat-abi=hard -mfpu=auto"
> > is broken as specified in PR99939 and this patch fixes the issue.
> >
> > Regression tested on arm-none-eabi and found no regressions.
> >
> > Ok for master? and Ok for GCC-10 branch?
> >
> > Regards,
> > Srinath.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2021-04-12 Srinath Parvathaneni
> >
> > PR target/99939
> > * gcc.target/arm/cmse/cmse-20.c: New test.
> >
> > libgcc/ChangeLog:
> >
> > 2021-04-12 Srinath Parvathaneni
> >
> > PR target/99939
> > * config/arm/t-arm: Make changes to use cmse.c for all the
> > armv8.1-m.main mulitlibs.
> >
> >
> >
> > ### Attachment also inlined for ease of reply
> ###
> >
> >
> > diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
> > b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
> > new file mode 100644
> > index
> >
> ..7e2739e14792624adf5b428
> 0ca58
> > a5d8320acbf0
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
> > @@ -0,0 +1,28 @@
> > +/* { dg-do run } */
> > +/* { dg-additional-options "-mcmse
> > +-Wl,--section-start,.gnu.sgstubs=0x0019" } */
> > +
> > +#include
> > +#include
> > +#include
> > +
> > +void __attribute__((cmse_nonsecure_entry))
> > +secure_fun (int a, int *p)
> > +{
> > + void *b = cmse_check_address_range ((void *)p, a, 1);
> > +
> > + if (b == NULL)
> > + __builtin_abort ();
> > + printf("%d", *((int *)b));
> > +}
> > +
> > +int
> > +main (void)
> > +{
> > + int *ptr;
> > + int size = 1;
> > + ptr = (int *) calloc (1, sizeof(int *));
> > + *ptr = 1315852292;
> > + secure_fun (size, ptr);
> > + free (ptr);
> > + return 0;
> > +}
> > diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm index
> >
> 3625a2590beec4e4e0e0881be9ad284c595c7190..949e2ee06653680211ff2dcf
> 0b55
> > a41a6aedc31c 100644
> > --- a/libgcc/config/arm/t-arm
> > +++ b/libgcc/config/arm/t-arm
> > @@ -9,11 +9,12 @@ CMSE_OPTS:=-mcmse
> > endif
> >
> > ifdef HAVE_CMSE
> > -ifndef HAVE_V81M
> > -libgcc-objects += cmse.o cmse_nonsecure_call.o
> > +libgcc-objects += cmse.o
> >
> > cmse.o: $(srcdir)/config/arm/cmse.c
> > $(gcc_compile) -c $(CMSE_OPTS) $<
> > +ifndef HAVE_V81M
> > +libgcc-objects += cmse_nonsecure_call.o
> > cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
> >$(gcc_compile) -c $<
> > endif
> >
>
> So if I have two object files using CMSE and one is built with v8m, but the
> other with v8.1m, when I link them, the needed additional support for the
> v8m object file will be missing the library support.
>
> Wouldn't it be better to just build the cmse_nonsecure_call code
> unconditionally? It won't be called if it's not needed, but will be there if
> something does require it.
I have modified the patch to build the cmse_nonsecure_call code unconditionally,
I have attached the diff and cover letter in this email.
Please let me know if it is ok for master?
Regards,
Srinath.
>
> R.
Hi,
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve
-mfloat-abi=hard -mfpu=auto"
is broken as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
Ok for master? and Ok for GCC-10 branch?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2021-06-01 Srinath Parvathaneni
* gcc.target/arm/cmse/cmse-18.c: Modify
* gcc.target/arm/cmse/cmse-20.c: New test.
libgcc/ChangeLog:
2021-06-01 Srinath Parvathaneni
* config/arm/cmse_nonsecure_call.S: Modify to add
__ARM_FEATURE_MVE macro check.
* config/arm/t-arm: Make changes to link cmse.o and
cmse_nonsecure_call.o on finding -mcmse gcc options.
diff (2).patch
Description: diff (2).patch
[GCC][PATCH] arm: Fix multilib mapping for CDE extensions.
Hi All,
On passing +cdecp[0-7] extension to the -march string in command line options,
multilib linking is failing as mentioned in PR100856. This patch fixes this
issue by generating a separate -march string only for multilib comparison.
Regression tested on arm-none-eabi and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2021-06-01 Srinath Parvathaneni
PR target/100856
* common/config/arm/arm-common.c (arm_canon_arch_option): Modify
function to generate canonical march string after removing cde related
compiler extensions.
(arm_canon_arch_multilib_option): Define function.
* config/arm/arm-cpus.in (CDE_LIST): Define fgroup.
* config/arm/arm.h (arm_canon_arch_multilib_option): Define macro.
(CANON_ARCH_MULTILIB_SPEC_FUNCTION): Define macro.
(ARCH_CANONICAL_MULTILIB_SPECS): Define macro.
(TARGET_MULTLILIB_ARCH): Define macro.
* gcc.c (used_arg_t::operator ()): Add condition to generate separate
march string for multilib matching.
gcc/testsuite/ChangeLog:
2021-06-01 Srinath Parvathaneni
PR target/100856
* gcc.target/arm/acle/pr100856.c: New test.
* gcc.target/arm/multilib.exp: Modify.
### Attachment also inlined for ease of reply###
diff --git a/gcc/common/config/arm/arm-common.c
b/gcc/common/config/arm/arm-common.c
index
9980af6885c3dfe68f61fa0f39b23022b4e59c19..7d8c6e5253f3f1683eed99f479a09186a46c2d22
100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -616,6 +616,8 @@ public:
}
};
+static int multilib_arch = 0;
+
/* Generate a canonical representation of the -march option from the
current -march string (if given) and other options on the command
line that might affect the architecture. This aids multilib selection
@@ -703,6 +705,14 @@ arm_canon_arch_option (int argc, const char **argv)
arm_initialize_isa (target_isa, selected_arch->common.isa_bits);
arm_parse_option_features (target_isa, _arch->common,
strchr (arch, '+'));
+ if (multilib_arch == 1)
+ {
+ const enum isa_feature cde_bitlist[] = {ISA_ALL_CDE, isa_nobit};
+ sbitmap isa_cdebits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_cdebits, cde_bitlist);
+ bitmap_and_compl (target_isa, target_isa, isa_cdebits);
+ }
+
if (fpu && strcmp (fpu, "auto") != 0)
{
/* We assume that architectures do not have any FPU bits
@@ -786,18 +796,27 @@ arm_canon_arch_option (int argc, const char **argv)
arm_initialize_isa (base_isa, selected_arch->common.isa_bits);
- /* Architecture has no extension options, so just return the canonical
- architecture name. */
- if (selected_arch->common.extensions == NULL)
-return selected_arch->common.name;
-
/* We're only interested in extension bits. */
bitmap_and_compl (target_isa, target_isa, base_isa);
+ /* Architecture has no extension options, so just return the canonical
+ architecture name. */
+ if (multilib_arch == 0 && selected_arch->common.extensions == NULL)
+return selected_arch->common.name;
/* There are no extensions needed. Just return the canonical architecture
name. */
- if (bitmap_empty_p (target_isa))
+ else if (multilib_arch == 0 && bitmap_empty_p (target_isa))
return selected_arch->common.name;
+ else if (multilib_arch == 1
+ && (selected_arch->common.extensions == NULL
+ || bitmap_empty_p (target_isa)))
+{
+ canonical_arch = (char *) xmalloc (strlen (selected_arch->common.name)
++ strlen ("march="));
+ strcpy (canonical_arch, "march=");
+ strcat (canonical_arch, selected_arch->common.name);
+ return canonical_arch;
+}
/* What is left is the architecture that the compiler will target. We
now need to map that back into a suitable option+features list.
@@ -899,10 +918,20 @@ arm_canon_arch_option (int argc, const char **argv)
}
}
- canonical_arch
-= (char *) xmalloc (len + strlen (selected_arch->common.name));
-
- strcpy (canonical_arch, selected_arch->common.name);
+ if (multilib_arch == 1)
+{
+ canonical_arch
+ = (char *) xmalloc (len + strlen (selected_arch->common.name)
+ + strlen ("march="));
+ strcpy (canonical_arch, "march=");
+ strcat (canonical_arch, selected_arch->common.name);
+}
+ else
+{
+ canonical_arch
+ = (char *) xmalloc (len + strlen (selected_arch->common.name));
+ strcpy (canonical_arch, selected_arch->common.name);
+}
for (std::list::iterator iter = extensions.begin ();
iter != extensions.end (); ++iter)
@@ -1069,3 +1098,15 @@ arm_asm_auto_mfpu (int argc, const char **argv)
#define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info
struct
RE: [GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for -O0 (pr97205).
Ping!!
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 30 April 2021 16:24
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
>
> Subject: [GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for
> -O0 (pr97205).
>
> Hi,
>
> This is a backport to GCC-10 to fix PR97205, patch applies cleanly on the
> branch.
>
> Regression tested and found no issues.
>
> Ok for GCC-10 backport?
>
> Regards,
> Srinath.
>
> This makes sure that stack allocated SSA_NAMEs are
> at least MODE_ALIGNED. Also increase the MEM_ALIGN
> for the corresponding rtl objects.
>
> gcc:
> 2020-11-03 Bernd Edlinger
>
> PR target/97205
> * cfgexpand.c (align_local_variable): Make SSA_NAMEs
> at least MODE_ALIGNED.
> (expand_one_stack_var_at): Increase MEM_ALIGN for SSA_NAMEs.
>
> gcc/testsuite:
> 2020-11-03 Bernd Edlinger
>
> PR target/97205
> * gcc.c-torture/compile/pr97205.c: New test.
>
> (cherry picked from commit
> 23ac7a009ecfeec3eab79136abed8aac9768b458)
>
>
> ### Attachment also inlined for ease of reply
> ###
>
>
> diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index
> bf4f194ed993134109cc21be9cb0ed8a5c170824..4fef5d6ebf420ce4d6f59606e
> cd064f45ae59065 100644
> --- a/gcc/cfgexpand.c
> +++ b/gcc/cfgexpand.c
> @@ -366,7 +366,15 @@ align_local_variable (tree decl, bool really_expand)
>unsigned int align;
>
>if (TREE_CODE (decl) == SSA_NAME)
> -align = TYPE_ALIGN (TREE_TYPE (decl));
> +{
> + tree type = TREE_TYPE (decl);
> + machine_mode mode = TYPE_MODE (type);
> +
> + align = TYPE_ALIGN (type);
> + if (mode != BLKmode
> + && align < GET_MODE_ALIGNMENT (mode))
> + align = GET_MODE_ALIGNMENT (mode);
> +}
>else
> {
>align = LOCAL_DECL_ALIGNMENT (decl); @@ -999,20 +1007,21 @@
> expand_one_stack_var_at (tree decl, rtx base, unsigned base_align,
>x = plus_constant (Pmode, base, offset);
>x = gen_rtx_MEM (TREE_CODE (decl) == SSA_NAME
> ? TYPE_MODE (TREE_TYPE (decl))
> -: DECL_MODE (SSAVAR (decl)), x);
> +: DECL_MODE (decl), x);
> +
> + /* Set alignment we actually gave this decl if it isn't an SSA name.
> + If it is we generate stack slots only accidentally so it isn't as
> + important, we'll simply set the alignment directly on the MEM. */
> +
> + if (base == virtual_stack_vars_rtx)
> +offset -= frame_phase;
> + align = known_alignment (offset);
> + align *= BITS_PER_UNIT;
> + if (align == 0 || align > base_align)
> +align = base_align;
>
>if (TREE_CODE (decl) != SSA_NAME)
> {
> - /* Set alignment we actually gave this decl if it isn't an SSA name.
> - If it is we generate stack slots only accidentally so it isn't as
> - important, we'll simply use the alignment that is already set. */
> - if (base == virtual_stack_vars_rtx)
> - offset -= frame_phase;
> - align = known_alignment (offset);
> - align *= BITS_PER_UNIT;
> - if (align == 0 || align > base_align)
> - align = base_align;
> -
>/* One would think that we could assert that we're not decreasing
>alignment here, but (at least) the i386 port does exactly this
>via the MINIMUM_ALIGNMENT hook. */
> @@ -1022,6 +1031,8 @@ expand_one_stack_var_at (tree decl, rtx base,
> unsigned base_align,
> }
>
>set_rtl (decl, x);
> +
> + set_mem_align (x, align);
> }
>
> class stack_vars_data
> @@ -1327,13 +1338,11 @@ expand_one_stack_var_1 (tree var)
> {
>tree type = TREE_TYPE (var);
>size = tree_to_poly_uint64 (TYPE_SIZE_UNIT (type));
> - byte_align = TYPE_ALIGN_UNIT (type);
> }
>else
> -{
> - size = tree_to_poly_uint64 (DECL_SIZE_UNIT (var));
> - byte_align = align_local_variable (var, true);
> -}
> +size = tree_to_poly_uint64 (DECL_SIZE_UNIT (var));
> +
> + byte_align = align_local_variable (var, true);
>
>/* We handle highly aligned variables in expand_stack_vars. */
>gcc_assert (byte_align * BITS_PER_UNIT <=
> MAX_SUPPORTED_STACK_ALIGNMENT); diff --git a/gcc/testsuite/gcc.c-
> torture/compile/pr97205.c b/gcc/testsuite/gcc.c-torture/compile/pr97205.c
> new file mode 100644
> index
> ..6600011fcf84660edcba8d9
> 68c78ee6aaa0aa923
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/compile/pr97205.c
> @@ -0,0 +1,7 @@
> +int a;
> +typedef __attribute__((aligned(2))) int x; int f () {
> + x b = a;
> + return b;
> +}
[GCC-10 backport][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).
Hi,
This is a backport to GCC-10 branch, this patch got applied cleanly on the
branch.
This patch removes several duplicated intrinsic definitions from
arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
in few of intrinsics polymorphic variants.
Ok for GCC-10 branch?
gcc/ChangeLog:
2021-05-04 Srinath Parvathaneni
PR target/100419
* config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong
arguments.
(__arm_vcmpneq): Remove duplicate definition.
(__arm_vstrwq_scatter_offset_p): Likewise.
(__arm_vmaxq_x): Likewise.
(__arm_vmlsdavaq): Likewise.
(__arm_vmlsdavaxq): Likewise.
(__arm_vmlsdavq_p): Likewise.
(__arm_vmlsdavxq_p): Likewise.
(__arm_vrmlaldavhaq): Likewise.
(__arm_vstrbq_p): Likewise.
(__arm_vstrbq_scatter_offset): Likewise.
(__arm_vstrbq_scatter_offset_p): Likewise.
(__arm_vstrdq_scatter_offset): Likewise.
(__arm_vstrdq_scatter_offset_p): Likewise.
(__arm_vstrdq_scatter_shifted_offset): Likewise.
(__arm_vstrdq_scatter_shifted_offset_p): Likewise.
Co-authored-by: Joe Ramsay
(cherry picked from commit 9b905ba9ebba8d2cc805c26351225e7f74c02333)
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
449219e90fccd6344c725404366147f5932e8660..1132c7cf87d217a380cf26dd6f110130ea7bf175
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -37802,33 +37802,19 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32(p0, p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_p_f32(p0, p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
+#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t)));})
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1,
__ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1,
__ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1,
__ARM_mve_coerce(__p2, float32x4_t)));})
-#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
(p1); \
+#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =
(p0); \
__typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
(p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int
[GCC-11 backport][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).
Hi,
This is a backport to GCC-11 branch, this patch got applied cleanly on the
branch.
This patch removes several duplicated intrinsic definitions from
arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
in few of intrinsics polymorphic variants.
Ok for GCC-11 branch?
gcc/ChangeLog:
2021-05-04 Srinath Parvathaneni
PR target/100419
* config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong
arguments.
(__arm_vcmpneq): Remove duplicate definition.
(__arm_vstrwq_scatter_offset_p): Likewise.
(__arm_vmaxq_x): Likewise.
(__arm_vmlsdavaq): Likewise.
(__arm_vmlsdavaxq): Likewise.
(__arm_vmlsdavq_p): Likewise.
(__arm_vmlsdavxq_p): Likewise.
(__arm_vrmlaldavhaq): Likewise.
(__arm_vstrbq_p): Likewise.
(__arm_vstrbq_scatter_offset): Likewise.
(__arm_vstrbq_scatter_offset_p): Likewise.
(__arm_vstrdq_scatter_offset): Likewise.
(__arm_vstrdq_scatter_offset_p): Likewise.
(__arm_vstrdq_scatter_shifted_offset): Likewise.
(__arm_vstrdq_scatter_shifted_offset_p): Likewise.
Co-authored-by: Joe Ramsay
(cherry picked from commit 9b905ba9ebba8d2cc805c26351225e7f74c02333)
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
3a40c6e68161b64319b071f57a5b0d8393303cfd..dc1d874a6366eb5fe755a70c72ed371c915bd04b
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -37808,33 +37808,19 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32(p0, p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_p_f32(p0, p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
+#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t)));})
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1,
__ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1,
__ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1,
__ARM_mve_coerce(__p2, float32x4_t)));})
-#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
(p1); \
+#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =
(p0); \
__typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
(p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int
[GCC-10 backport][PATCH] arm: PR target/95646: Do not clobber callee saved registers with CMSE.
Hi,
This is a backport to gcc-10, cleanly applied on the branch.
As reported in bugzilla when the -mcmse option is used while compiling for size
(-Os) with a thumb-1 target the generated code will clear the registers r7-r10.
These however are callee saved and should be preserved accross ABI boundaries.
The reason this happens is because these registers are made "fixed" when
optimising for size with Thumb-1 in a way to make sure they are not used, as
pushing and popping hi-registers requires extra moves to and from LO_REGS.
To fix this, this patch uses 'callee_saved_reg_p', which accounts for this
optimisation, instead of 'call_used_or_fixed_reg_p'. Be aware of
'callee_saved_reg_p''s definition, as it does still take call used registers
into account, which aren't callee_saved in my opinion, so it is a rather
misnoemer, works in our advantage here though as it does exactly what we need.
Regression tested on arm-none-eabi.
Is this Ok for GCC-10 branch?
Regards,
Srinath.
gcc/ChangeLog:
2020-06-19 Andre Vieira
PR target/95646
* config/arm/arm.c: (cmse_nonsecure_entry_clear_before_return): Use
'callee_saved_reg_p' instead of 'calL_used_or_fixed_reg_p'.
gcc/testsuite/ChangeLog:
2020-06-19 Andre Vieira
PR target/95646
* gcc.target/arm/pr95646.c: New test.
(cherry picked from commit 5f426554fd804d65509875d706d8b8bc3a48393b)
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
781bcc8ca42e10524595cb6c90b61450a41f739e..6f4381fd6e959321d8d319fafdce4079c7b54e5f
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -27011,7 +27011,7 @@ cmse_nonsecure_entry_clear_before_return (void)
continue;
if (IN_RANGE (regno, IP_REGNUM, PC_REGNUM))
continue;
- if (call_used_or_fixed_reg_p (regno)
+ if (!callee_saved_reg_p (regno)
&& (!IN_RANGE (regno, FIRST_VFP_REGNUM, LAST_VFP_REGNUM)
|| TARGET_HARD_FLOAT))
bitmap_set_bit (to_clear_bitmap, regno);
diff --git a/gcc/testsuite/gcc.target/arm/pr95646.c
b/gcc/testsuite/gcc.target/arm/pr95646.c
new file mode 100644
index
..12d06a0c8c1ed7de1f8d4d15130432259e613a32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr95646.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" }
{ "-march=armv8-m.base" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mcpu=*" } {
"-mcpu=cortex-m23" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfpu=*" } {
} } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } {
"-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
+/* { dg-options "-mcpu=cortex-m23 -mcmse" } */
+/* { dg-additional-options "-Os" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+int __attribute__ ((cmse_nonsecure_entry))
+foo (void)
+{
+ return 1;
+}
+/* { { dg-final { scan-assembler-not "mov\tr9, r0" } } */
+
+/*
+** __acle_se_bar:
+** mov (r[0-3]), r9
+** push{\1}
+** ...
+** pop {(r[0-3])}
+** mov r9, \2
+** ...
+** bxnslr
+*/
+int __attribute__ ((cmse_nonsecure_entry))
+bar (void)
+{
+ asm ("": : : "r9");
+ return 1;
+}
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
781bcc8ca42e10524595cb6c90b61450a41f739e..6f4381fd6e959321d8d319fafdce4079c7b54e5f
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -27011,7 +27011,7 @@ cmse_nonsecure_entry_clear_before_return (void)
continue;
if (IN_RANGE (regno, IP_REGNUM, PC_REGNUM))
continue;
- if (call_used_or_fixed_reg_p (regno)
+ if (!callee_saved_reg_p (regno)
&& (!IN_RANGE (regno, FIRST_VFP_REGNUM, LAST_VFP_REGNUM)
|| TARGET_HARD_FLOAT))
bitmap_set_bit (to_clear_bitmap, regno);
diff --git a/gcc/testsuite/gcc.target/arm/pr95646.c
b/gcc/testsuite/gcc.target/arm/pr95646.c
new file mode 100644
index
..12d06a0c8c1ed7de1f8d4d15130432259e613a32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr95646.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" }
{ "-march=armv8-m.base" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mcpu=*" } {
"-mcpu=cortex-m23" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfpu=*" } {
} } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } {
"-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
+/* { dg-options "-mcpu=cortex-m23 -mcmse" } */
+/* { dg-additional-options "-Os" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+int __attribute__ ((cmse_nonsecure_entry))
+foo (void)
+{
+ return 1;
+}
+/* { { dg-final { scan-assembler-not "mov\tr9, r0" } } */
+
+/*
+** __acle_se_bar:
+** mov
[GCC-10 backport][PATCH] arm: Fix testisms introduced with fix for pr target/95646.
Hi,
This is a backport to gcc-10, cleanly applied on the branch.
This patch changes the test to use the effective-target machinery disables the
error message "ARMv8-M Security Extensions incompatible with selected FPU" when
-mfloat-abi=soft.
Further changes 'asm' to '__asm__' to avoid failures with '-std=' options.
Regression tested on arm-none-eabi.
Is this Ok for GCC-10 branch?
Regards,
Srinath.
gcc/ChangeLog:
2020-07-06 Andre Vieira
* config/arm/arm.c (arm_options_perform_arch_sanity_checks): Do not
check +D32 for CMSE if -mfloat-abi=soft
gcc/testsuite/ChangeLog:
2020-07-06 Andre Vieira
* gcc.target/arm/pr95646.c: Fix testism.
(cherry picked from commit 80297f897758f59071968ddff2a04a8d11481117)
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
6f4381fd6e959321d8d319fafdce4079c7b54e5f..c3bbd9fd5e177f07b37610df57d4f02bd0402761
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3850,7 +3850,7 @@ arm_options_perform_arch_sanity_checks (void)
/* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions
and ARMv8-M Baseline and Mainline do not allow such configuration. */
- if (use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM)
+ if (use_cmse && TARGET_HARD_FLOAT && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM)
error ("ARMv8-M Security Extensions incompatible with selected FPU");
diff --git a/gcc/testsuite/gcc.target/arm/pr95646.c
b/gcc/testsuite/gcc.target/arm/pr95646.c
index
12d06a0c8c1ed7de1f8d4d15130432259e613a32..cde1b2d9d36a4e39cd916fdcc9eef424a22bd589
100644
--- a/gcc/testsuite/gcc.target/arm/pr95646.c
+++ b/gcc/testsuite/gcc.target/arm/pr95646.c
@@ -1,10 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" }
{ "-march=armv8-m.base" } } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mcpu=*" } {
"-mcpu=cortex-m23" } } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfpu=*" } {
} } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } {
"-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
-/* { dg-options "-mcpu=cortex-m23 -mcmse" } */
-/* { dg-additional-options "-Os" } */
+/* { dg-require-effective-target arm_arch_v8m_base_ok } */
+/* { dg-add-options arm_arch_v8m_base } */
+/* { dg-additional-options "-mcmse -Os" } */
/* { dg-final { check-function-bodies "**" "" } } */
int __attribute__ ((cmse_nonsecure_entry))
@@ -27,6 +24,6 @@ foo (void)
int __attribute__ ((cmse_nonsecure_entry))
bar (void)
{
- asm ("": : : "r9");
+ __asm__ ("" : : : "r9");
return 1;
}
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
6f4381fd6e959321d8d319fafdce4079c7b54e5f..c3bbd9fd5e177f07b37610df57d4f02bd0402761
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3850,7 +3850,7 @@ arm_options_perform_arch_sanity_checks (void)
/* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions
and ARMv8-M Baseline and Mainline do not allow such configuration. */
- if (use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM)
+ if (use_cmse && TARGET_HARD_FLOAT && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM)
error ("ARMv8-M Security Extensions incompatible with selected FPU");
diff --git a/gcc/testsuite/gcc.target/arm/pr95646.c
b/gcc/testsuite/gcc.target/arm/pr95646.c
index
12d06a0c8c1ed7de1f8d4d15130432259e613a32..cde1b2d9d36a4e39cd916fdcc9eef424a22bd589
100644
--- a/gcc/testsuite/gcc.target/arm/pr95646.c
+++ b/gcc/testsuite/gcc.target/arm/pr95646.c
@@ -1,10 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" }
{ "-march=armv8-m.base" } } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mcpu=*" } {
"-mcpu=cortex-m23" } } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfpu=*" } {
} } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } {
"-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
-/* { dg-options "-mcpu=cortex-m23 -mcmse" } */
-/* { dg-additional-options "-Os" } */
+/* { dg-require-effective-target arm_arch_v8m_base_ok } */
+/* { dg-add-options arm_arch_v8m_base } */
+/* { dg-additional-options "-mcmse -Os" } */
/* { dg-final { check-function-bodies "**" "" } } */
int __attribute__ ((cmse_nonsecure_entry))
@@ -27,6 +24,6 @@ foo (void)
int __attribute__ ((cmse_nonsecure_entry))
bar (void)
{
- asm ("": : : "r9");
+ __asm__ ("" : : : "r9");
return 1;
}
RE: [GCC][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).
Hi Richard,
> -Original Message-
> From: Richard Earnshaw
> Sent: 05 May 2021 11:15
> To: Srinath Parvathaneni ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [GCC][PATCH] arm: Remove duplicate definitions from
> arm_mve.h (pr100419).
>
>
>
> On 05/05/2021 10:56, Srinath Parvathaneni via Gcc-patches wrote:
> > Hi All,
> >
> > This patch removes several duplicated intrinsic definitions from
> > arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
> > in few of intrinsics polymorphic variants.
> >
> > Regression tested and found no issues.
> >
> > Ok for master ? GCC-11 and GCC-10 branch backports?
> > gcc/ChangeLog:
> >
> > 2021-05-04 Srinath Parvathaneni
> >
> > PR target/100419
> > * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong
> arguments.
> > (__arm_vcmpneq): Remove duplicate definition.
> > (__arm_vstrwq_scatter_offset_p): Likewise.
> > (__arm_vmaxq_x): Likewise.
> > (__arm_vmlsdavaq): Likewise.
> > (__arm_vmlsdavaxq): Likewise.
> > (__arm_vmlsdavq_p): Likewise.
> > (__arm_vmlsdavxq_p): Likewise.
> > (__arm_vrmlaldavhaq): Likewise.
> > (__arm_vstrbq_p): Likewise.
> > (__arm_vstrbq_scatter_offset): Likewise.
> > (__arm_vstrbq_scatter_offset_p): Likewise.
> > (__arm_vstrdq_scatter_offset): Likewise.
> > (__arm_vstrdq_scatter_offset_p): Likewise.
> > (__arm_vstrdq_scatter_shifted_offset): Likewise.
> > (__arm_vstrdq_scatter_shifted_offset_p): Likewise.
> >
> > Co-authored-by: Joe Ramsay
>
> Let's take this example:
>
> -#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 =
> (p1); \
> +#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 =
> (p0); \
> __typeof(p2) __p2 = (p2); \
> - _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
> - int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
> __ARM_mve_coerce(__p2, int32x4_t)), \
> - int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint32_t *),
> __p1,
> __ARM_mve_coerce(__p2, uint32x4_t)));})
> + _Generic( (int
> (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
> + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
> __arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1,
> __ARM_mve_coerce(__p2, int32x4_t)), \
> + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
> __arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *),
> p1,
> __ARM_mve_coerce(__p2, uint32x4_t)));})
>
> It removes the safe shadow copy of p1 but adds a safe shadow copy of p0.
> Why? Isn't it better (and safer) to just create shadow copies of all
> the arguments and let the compiler worry about when it's safe to
> eliminate them?
As you already know polymorphic variants are used to select the intrinsics
based on type of their arguments.
Consider the following code from arm_mve.h:
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vstrwq_scatter_offset_s32 (int32_t * __base, uint32x4_t __offset,
int32x4_t __value)
{
__builtin_mve_vstrwq_scatter_offset_sv4si ((__builtin_neon_si *) __base,
__offset, __value);
}
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vstrwq_scatter_offset_u32 (uint32_t * __base, uint32x4_t __offset,
uint32x4_t __value)
{
__builtin_mve_vstrwq_scatter_offset_uv4si ((__builtin_neon_si *) __base,
__offset, __value);
}
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vstrwq_scatter_offset_f32 (float32_t * __base, uint32x4_t __offset,
float32x4_t __value)
{
__builtin_mve_vstrwq_scatter_offset_fv4sf ((__builtin_neon_si *) __base,
__offset, __value);
}
Of above 3 functions, which function is to be called from the following
polymorphic variant is
decided based on type of arguments p0, p1 and p2.
#define __arm_vstrwq_scatter_offset(p0,p1,p2)
For the 3 function definitions mentioned above, only type of arguments 1 (p0)
and 3 (p2) varies
whereas type of second argument (p1) is same (uint32x4_t).
This is the reason we need only shadow copy of p0 and p2 to determine the
actual function to be called
and type of p1 is irrelevant. Previously p1 was wrongly used to determine the
function instead of p0
and that is a bug, which got fixed in this patch.
Since type of p1
[GCC][PATCH] arm: Remove duplicate definitions from arm_mve.h (pr100419).
Hi All,
This patch removes several duplicated intrinsic definitions from
arm_mve.h mentioned in PR100419 and also fixes the wrong arguments
in few of intrinsics polymorphic variants.
Regression tested and found no issues.
Ok for master ? GCC-11 and GCC-10 branch backports?
gcc/ChangeLog:
2021-05-04 Srinath Parvathaneni
PR target/100419
* config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong
arguments.
(__arm_vcmpneq): Remove duplicate definition.
(__arm_vstrwq_scatter_offset_p): Likewise.
(__arm_vmaxq_x): Likewise.
(__arm_vmlsdavaq): Likewise.
(__arm_vmlsdavaxq): Likewise.
(__arm_vmlsdavq_p): Likewise.
(__arm_vmlsdavxq_p): Likewise.
(__arm_vrmlaldavhaq): Likewise.
(__arm_vstrbq_p): Likewise.
(__arm_vstrbq_scatter_offset): Likewise.
(__arm_vstrbq_scatter_offset_p): Likewise.
(__arm_vstrdq_scatter_offset): Likewise.
(__arm_vstrdq_scatter_offset_p): Likewise.
(__arm_vstrdq_scatter_shifted_offset): Likewise.
(__arm_vstrdq_scatter_shifted_offset_p): Likewise.
Co-authored-by: Joe Ramsay
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
3a40c6e68161b64319b071f57a5b0d8393303cfd..dc1d874a6366eb5fe755a70c72ed371c915bd04b
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -37808,33 +37808,19 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_p_u32(p0, p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_p_f32(p0, p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
+#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t)), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t)), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t)));})
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_s32 (__ARM_mve_coerce(__p0, int32_t *), p1,
__ARM_mve_coerce(__p2, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_u32 (__ARM_mve_coerce(__p0, uint32_t *), p1,
__ARM_mve_coerce(__p2, uint32x4_t)), \
+ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_f32 (__ARM_mve_coerce(__p0, float32_t *), p1,
__ARM_mve_coerce(__p2, float32x4_t)));})
-#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
(p1); \
+#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =
(p0); \
__typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vstrwq_scatter_offset_p(p0,p1,p2,p3) ({ __typeof(p1) __p1 =
(p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4_t]:
__arm_vstrwq_scatter_offset_p_s32 (__ARM_mve_coerce(p0, int32_t *), __p1,
__ARM_mve_coerce(__p2, int32x4_t), p3), \
- int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4_t]:
__arm_vstrwq_scatter_offset_p_u32 (__ARM_mve_coerce(p0, uint32_t *), __p1,
__ARM_mve_coerce(__p2, uint32x4_t), p3), \
- int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4_t]:
__arm_vstrwq_scatter_offset_p_f32 (__ARM_mve_coerce(p0, float32_t *), __p1,
__ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vstrwq_scatter_offset(p0,p1,p2) ({ __typeof(p1) __p1 = (p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(p0)][__ARM_mve_typeid(__p2)])0, \
- int
[GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for -O0 (pr97205).
Hi,
This is a backport to GCC-10 to fix PR97205, patch applies
cleanly on the branch.
Regression tested and found no issues.
Ok for GCC-10 backport?
Regards,
Srinath.
This makes sure that stack allocated SSA_NAMEs are
at least MODE_ALIGNED. Also increase the MEM_ALIGN
for the corresponding rtl objects.
gcc:
2020-11-03 Bernd Edlinger
PR target/97205
* cfgexpand.c (align_local_variable): Make SSA_NAMEs
at least MODE_ALIGNED.
(expand_one_stack_var_at): Increase MEM_ALIGN for SSA_NAMEs.
gcc/testsuite:
2020-11-03 Bernd Edlinger
PR target/97205
* gcc.c-torture/compile/pr97205.c: New test.
(cherry picked from commit 23ac7a009ecfeec3eab79136abed8aac9768b458)
### Attachment also inlined for ease of reply###
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index
bf4f194ed993134109cc21be9cb0ed8a5c170824..4fef5d6ebf420ce4d6f59606ecd064f45ae59065
100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -366,7 +366,15 @@ align_local_variable (tree decl, bool really_expand)
unsigned int align;
if (TREE_CODE (decl) == SSA_NAME)
-align = TYPE_ALIGN (TREE_TYPE (decl));
+{
+ tree type = TREE_TYPE (decl);
+ machine_mode mode = TYPE_MODE (type);
+
+ align = TYPE_ALIGN (type);
+ if (mode != BLKmode
+ && align < GET_MODE_ALIGNMENT (mode))
+ align = GET_MODE_ALIGNMENT (mode);
+}
else
{
align = LOCAL_DECL_ALIGNMENT (decl);
@@ -999,20 +1007,21 @@ expand_one_stack_var_at (tree decl, rtx base, unsigned
base_align,
x = plus_constant (Pmode, base, offset);
x = gen_rtx_MEM (TREE_CODE (decl) == SSA_NAME
? TYPE_MODE (TREE_TYPE (decl))
- : DECL_MODE (SSAVAR (decl)), x);
+ : DECL_MODE (decl), x);
+
+ /* Set alignment we actually gave this decl if it isn't an SSA name.
+ If it is we generate stack slots only accidentally so it isn't as
+ important, we'll simply set the alignment directly on the MEM. */
+
+ if (base == virtual_stack_vars_rtx)
+offset -= frame_phase;
+ align = known_alignment (offset);
+ align *= BITS_PER_UNIT;
+ if (align == 0 || align > base_align)
+align = base_align;
if (TREE_CODE (decl) != SSA_NAME)
{
- /* Set alignment we actually gave this decl if it isn't an SSA name.
- If it is we generate stack slots only accidentally so it isn't as
-important, we'll simply use the alignment that is already set. */
- if (base == virtual_stack_vars_rtx)
- offset -= frame_phase;
- align = known_alignment (offset);
- align *= BITS_PER_UNIT;
- if (align == 0 || align > base_align)
- align = base_align;
-
/* One would think that we could assert that we're not decreasing
alignment here, but (at least) the i386 port does exactly this
via the MINIMUM_ALIGNMENT hook. */
@@ -1022,6 +1031,8 @@ expand_one_stack_var_at (tree decl, rtx base, unsigned
base_align,
}
set_rtl (decl, x);
+
+ set_mem_align (x, align);
}
class stack_vars_data
@@ -1327,13 +1338,11 @@ expand_one_stack_var_1 (tree var)
{
tree type = TREE_TYPE (var);
size = tree_to_poly_uint64 (TYPE_SIZE_UNIT (type));
- byte_align = TYPE_ALIGN_UNIT (type);
}
else
-{
- size = tree_to_poly_uint64 (DECL_SIZE_UNIT (var));
- byte_align = align_local_variable (var, true);
-}
+size = tree_to_poly_uint64 (DECL_SIZE_UNIT (var));
+
+ byte_align = align_local_variable (var, true);
/* We handle highly aligned variables in expand_stack_vars. */
gcc_assert (byte_align * BITS_PER_UNIT <= MAX_SUPPORTED_STACK_ALIGNMENT);
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr97205.c
b/gcc/testsuite/gcc.c-torture/compile/pr97205.c
new file mode 100644
index
..6600011fcf84660edcba8d968c78ee6aaa0aa923
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr97205.c
@@ -0,0 +1,7 @@
+int a;
+typedef __attribute__((aligned(2))) int x;
+int f ()
+{
+ x b = a;
+ return b;
+}
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index
bf4f194ed993134109cc21be9cb0ed8a5c170824..4fef5d6ebf420ce4d6f59606ecd064f45ae59065
100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -366,7 +366,15 @@ align_local_variable (tree decl, bool really_expand)
unsigned int align;
if (TREE_CODE (decl) == SSA_NAME)
-align = TYPE_ALIGN (TREE_TYPE (decl));
+{
+ tree type = TREE_TYPE (decl);
+ machine_mode mode = TYPE_MODE (type);
+
+ align = TYPE_ALIGN (type);
+ if (mode != BLKmode
+ && align < GET_MODE_ALIGNMENT (mode))
+ align = GET_MODE_ALIGNMENT (mode);
+}
else
{
align = LOCAL_DECL_ALIGNMENT (decl);
@@ -999,20 +1007,21 @@ expand_one_stack_var_at (tree decl, rtx base, unsigned
base_align,
x = plus_constant (Pmode, base, offset);
x = gen_rtx_MEM (TREE_CODE (decl) == SSA_NAME
[GCC][Patch] arm: Fix the mve multilib for the broken cmse support (pr99939).
Hi,
The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve
-mfloat-abi=hard -mfpu=auto"
is broken as specified in PR99939 and this patch fixes the issue.
Regression tested on arm-none-eabi and found no regressions.
Ok for master? and Ok for GCC-10 branch?
Regards,
Srinath.
gcc/testsuite/ChangeLog:
2021-04-12 Srinath Parvathaneni
PR target/99939
* gcc.target/arm/cmse/cmse-20.c: New test.
libgcc/ChangeLog:
2021-04-12 Srinath Parvathaneni
PR target/99939
* config/arm/t-arm: Make changes to use cmse.c for all the
armv8.1-m.main mulitlibs.
### Attachment also inlined for ease of reply###
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
..7e2739e14792624adf5b4280ca58a5d8320acbf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-additional-options "-mcmse
-Wl,--section-start,.gnu.sgstubs=0x0019" } */
+
+#include
+#include
+#include
+
+void __attribute__((cmse_nonsecure_entry))
+secure_fun (int a, int *p)
+{
+ void *b = cmse_check_address_range ((void *)p, a, 1);
+
+ if (b == NULL)
+ __builtin_abort ();
+ printf("%d", *((int *)b));
+}
+
+int
+main (void)
+{
+ int *ptr;
+ int size = 1;
+ ptr = (int *) calloc (1, sizeof(int *));
+ *ptr = 1315852292;
+ secure_fun (size, ptr);
+ free (ptr);
+ return 0;
+}
diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm
index
3625a2590beec4e4e0e0881be9ad284c595c7190..949e2ee06653680211ff2dcf0b55a41a6aedc31c
100644
--- a/libgcc/config/arm/t-arm
+++ b/libgcc/config/arm/t-arm
@@ -9,11 +9,12 @@ CMSE_OPTS:=-mcmse
endif
ifdef HAVE_CMSE
-ifndef HAVE_V81M
-libgcc-objects += cmse.o cmse_nonsecure_call.o
+libgcc-objects += cmse.o
cmse.o: $(srcdir)/config/arm/cmse.c
$(gcc_compile) -c $(CMSE_OPTS) $<
+ifndef HAVE_V81M
+libgcc-objects += cmse_nonsecure_call.o
cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
$(gcc_compile) -c $<
endif
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
new file mode 100644
index
..7e2739e14792624adf5b4280ca58a5d8320acbf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-20.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-additional-options "-mcmse
-Wl,--section-start,.gnu.sgstubs=0x0019" } */
+
+#include
+#include
+#include
+
+void __attribute__((cmse_nonsecure_entry))
+secure_fun (int a, int *p)
+{
+ void *b = cmse_check_address_range ((void *)p, a, 1);
+
+ if (b == NULL)
+ __builtin_abort ();
+ printf("%d", *((int *)b));
+}
+
+int
+main (void)
+{
+ int *ptr;
+ int size = 1;
+ ptr = (int *) calloc (1, sizeof(int *));
+ *ptr = 1315852292;
+ secure_fun (size, ptr);
+ free (ptr);
+ return 0;
+}
diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm
index
3625a2590beec4e4e0e0881be9ad284c595c7190..949e2ee06653680211ff2dcf0b55a41a6aedc31c
100644
--- a/libgcc/config/arm/t-arm
+++ b/libgcc/config/arm/t-arm
@@ -9,11 +9,12 @@ CMSE_OPTS:=-mcmse
endif
ifdef HAVE_CMSE
-ifndef HAVE_V81M
-libgcc-objects += cmse.o cmse_nonsecure_call.o
+libgcc-objects += cmse.o
cmse.o: $(srcdir)/config/arm/cmse.c
$(gcc_compile) -c $(CMSE_OPTS) $<
+ifndef HAVE_V81M
+libgcc-objects += cmse_nonsecure_call.o
cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S
$(gcc_compile) -c $<
endif
[PATCH][GCC-10 backport][COMMITTED] arm: Fix the warning -mcpu=cortex-m55 conflicting with -march=armv8.1-m.main (pr97327).
As this patch is approved here
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556387.html ,
committed to releases/gcc-10 branch.
This patch fixes (PR97327) the warning -mcpu=cortex-m55 conflicts with
-march=armv8.1-m.main
for -mfloat-abi=soft by adding the isa_bit_mve_float to clearing FP bit list.
The following combination are fixed with this patch:
$ cat bug.c
int main(){
return 0;
}
$ arm-none-eabi-gcc -mcpu=cortex-m55 -mfloat-abi=soft bug.c -c
$ arm-none-eabi-gcc -mcpu=cortex-m55 -mfloat-abi=soft -march=armv8.1-m.main+mve
bug.c -c
Before this patch for above combinations:
cc1: warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main'
switch
After this patch for above combinations no warning/errors.
gcc/ChangeLog:
2020-10-16 Srinath Parvathaneni
PR target/97327
* config/arm/arm.c (fp_bitlist): Add isa_bit_mve_float to FP bits array.
gcc/testsuite/ChangeLog:
PR target/97327
* gcc.target/arm/mve/intrinsics/pr97327.c: New test.
(cherry picked from commit 90042c43a92c452a5f9f3afbfcdad511ea09a54f)
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
11292c2658c866d22962f2534b64ec13246346e6..99b1e926dc3025f8547e4bb5b98cdba02a6abe86
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3445,8 +3445,9 @@ arm_option_override (void)
{
static const enum isa_feature fpu_bitlist_internal[]
= { ISA_ALL_FPU_INTERNAL, isa_nobit };
+ /* isa_bit_mve_float is also part of FP bit list for arch v8.1-m.main. */
static const enum isa_feature fp_bitlist[]
-= { ISA_ALL_FP, isa_nobit };
+= { ISA_ALL_FP, isa_bit_mve_float, isa_nobit };
static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
cl_target_option opts;
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
new file mode 100644
index
..8f6d36063811607623048c0a95920b29e43f4c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
@@ -0,0 +1,8 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=hard" } { ""
} } */
+/* { dg-additional-options "-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto
-Werror" } */
+
+int main ()
+{
+ return 0;
+}
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
11292c2658c866d22962f2534b64ec13246346e6..99b1e926dc3025f8547e4bb5b98cdba02a6abe86
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3445,8 +3445,9 @@ arm_option_override (void)
{
static const enum isa_feature fpu_bitlist_internal[]
= { ISA_ALL_FPU_INTERNAL, isa_nobit };
+ /* isa_bit_mve_float is also part of FP bit list for arch v8.1-m.main. */
static const enum isa_feature fp_bitlist[]
-= { ISA_ALL_FP, isa_nobit };
+= { ISA_ALL_FP, isa_bit_mve_float, isa_nobit };
static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
cl_target_option opts;
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
new file mode 100644
index
..8f6d36063811607623048c0a95920b29e43f4c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
@@ -0,0 +1,8 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=hard" } { ""
} } */
+/* { dg-additional-options "-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto
-Werror" } */
+
+int main ()
+{
+ return 0;
+}
[PATCH][GCC] arm: Fix the warning -mcpu=cortex-m55 conflicting with -march=armv8.1-m.main (pr97327).
Hello,
This patch fixes (PR97327) the warning -mcpu=cortex-m55 conflicts with
-march=armv8.1-m.main
for -mfloat-abi=soft by adding the isa_bit_mve_float to clearing FP bit list.
The following combination are fixed with this patch:
$ cat bug.c
int main(){
return 0;
}
$ arm-none-eabi-gcc -mcpu=cortex-m55 -mfloat-abi=soft bug.c -c
$ arm-none-eabi-gcc -mcpu=cortex-m55 -mfloat-abi=soft -march=armv8.1-m.main+mve
bug.c -c
Before this patch for above combinations:
cc1: warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8.1-m.main'
switch
After this patch for above combinations no warning/errors.
Regression tested on arm-none-eabi and found no regressions.
Ok for master? Ok for GCC-10 branch?
Regards,
Srinath.
gcc/ChangeLog:
2020-10-16 Srinath Parvathaneni
PR target/97327
* config/arm/arm.c (fp_bitlist): Add isa_bit_mve_float to FP bits array.
gcc/testsuite/ChangeLog:
PR target/97327
* gcc.target/arm/mve/intrinsics/pr97327.c: New test.
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
0b8c5fa074d32e9ced107d1917323479c19d4c4e..dfadaca6fdfe16cfd5b6531ae8564d01063bbe77
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3429,8 +3429,9 @@ arm_option_override (void)
{
static const enum isa_feature fpu_bitlist_internal[]
= { ISA_ALL_FPU_INTERNAL, isa_nobit };
+ /* isa_bit_mve_float is also part of FP bit list for arch v8.1-m.main. */
static const enum isa_feature fp_bitlist[]
-= { ISA_ALL_FP, isa_nobit };
+= { ISA_ALL_FP, isa_bit_mve_float, isa_nobit };
static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
cl_target_option opts;
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
new file mode 100644
index
..8f6d36063811607623048c0a95920b29e43f4c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
@@ -0,0 +1,8 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=hard" } { ""
} } */
+/* { dg-additional-options "-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto
-Werror" } */
+
+int main ()
+{
+ return 0;
+}
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
0b8c5fa074d32e9ced107d1917323479c19d4c4e..dfadaca6fdfe16cfd5b6531ae8564d01063bbe77
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3429,8 +3429,9 @@ arm_option_override (void)
{
static const enum isa_feature fpu_bitlist_internal[]
= { ISA_ALL_FPU_INTERNAL, isa_nobit };
+ /* isa_bit_mve_float is also part of FP bit list for arch v8.1-m.main. */
static const enum isa_feature fp_bitlist[]
-= { ISA_ALL_FP, isa_nobit };
+= { ISA_ALL_FP, isa_bit_mve_float, isa_nobit };
static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
cl_target_option opts;
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
new file mode 100644
index
..8f6d36063811607623048c0a95920b29e43f4c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/pr97327.c
@@ -0,0 +1,8 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=hard" } { ""
} } */
+/* { dg-additional-options "-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto
-Werror" } */
+
+int main ()
+{
+ return 0;
+}
[PATCH][GCC-10 backport] arm: [MVE] Remove illegal intrinsics (PR target/96914)
Hello, Applied cleanly, Ok for backporting this patch to GCC-10? A few MVE intrinsics had an unsigned variant implement while they are supported by the hardware. This patch removes them: __arm_vqrdmlashq_n_u8 __arm_vqrdmlahq_n_u8 __arm_vqdmlahq_n_u8 __arm_vqrdmlashq_n_u16 __arm_vqrdmlahq_n_u16 __arm_vqdmlahq_n_u16 __arm_vqrdmlashq_n_u32 __arm_vqrdmlahq_n_u32 __arm_vqdmlahq_n_u32 __arm_vmlaldavaxq_p_u32 __arm_vmlaldavaxq_p_u16 2020-10-08 Christophe Lyon gcc/ PR target/96914 * config/arm/arm_mve.h (vqrdmlashq_n_u8, vqrdmlashq_n_u16) (vqrdmlashq_n_u32, vqrdmlahq_n_u8, vqrdmlahq_n_u16) (vqrdmlahq_n_u32, vqdmlahq_n_u8, vqdmlahq_n_u16, vqdmlahq_n_u32) (vmlaldavaxq_p_u16, vmlaldavaxq_p_u32): Remove. * config/arm/arm_mve_builtins.def (vqrdmlashq_n_u, vqrdmlahq_n_u) (vqdmlahq_n_u, vmlaldavaxq_p_u): Remove. * config/arm/unspecs.md (VQDMLAHQ_N_U, VQRDMLAHQ_N_U) (VQRDMLASHQ_N_U) (VMLALDAVAXQ_P_U): Remove unspecs. * config/arm/iterators.md (VQDMLAHQ_N_U, VQRDMLAHQ_N_U) (VQRDMLASHQ_N_U, VMLALDAVAXQ_P_U): Remove attributes. (VQDMLAHQ_N, VQRDMLAHQ_N, VQRDMLASHQ_N, VMLALDAVAXQ_P): Remove unsigned variants from iterators. * config/arm/mve.md (mve_vqdmlahq_n_) (mve_vqrdmlahq_n_) (mve_vqrdmlashq_n_, mve_vmlaldavaxq_p_): Update comment. gcc/testsuite/ PR target/96914 * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c: Remove. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c: Remove. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c: Remove. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c: Remove. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c: Remove. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c: Remove. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c: Remove. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c: Remove. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c: Remove. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c: Remove. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c: Remove. (cherry picked from commit 237f12da4124b91503646b099a8282aa6b251ef9) ### Attachment also inlined for ease of reply### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 424a5ae84623569c9feafae78107933cb1de5744..f0de29477abd9a1474eaaf028aa9a6ea57b58142 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1236,9 +1236,6 @@ #define vpselq_u8(__a, __b, __p) __arm_vpselq_u8(__a, __b, __p) #define vpselq_s8(__a, __b, __p) __arm_vpselq_s8(__a, __b, __p) #define vrev64q_m_u8(__inactive, __a, __p) __arm_vrev64q_m_u8(__inactive, __a, __p) -#define vqrdmlashq_n_u8(__a, __b, __c) __arm_vqrdmlashq_n_u8(__a, __b, __c) -#define vqrdmlahq_n_u8(__a, __b, __c) __arm_vqrdmlahq_n_u8(__a, __b, __c) -#define vqdmlahq_n_u8(__a, __b, __c) __arm_vqdmlahq_n_u8(__a, __b, __c) #define vmvnq_m_u8(__inactive, __a, __p) __arm_vmvnq_m_u8(__inactive, __a, __p) #define vmlasq_n_u8(__a, __b, __c) __arm_vmlasq_n_u8(__a, __b, __c) #define vmlaq_n_u8(__a, __b, __c) __arm_vmlaq_n_u8(__a, __b, __c) @@ -1322,9 +1319,6 @@ #define vpselq_u16(__a, __b, __p) __arm_vpselq_u16(__a, __b, __p) #define vpselq_s16(__a, __b, __p) __arm_vpselq_s16(__a, __b, __p) #define vrev64q_m_u16(__inactive, __a, __p) __arm_vrev64q_m_u16(__inactive, __a, __p) -#define vqrdmlashq_n_u16(__a, __b, __c) __arm_vqrdmlashq_n_u16(__a, __b, __c) -#define vqrdmlahq_n_u16(__a, __b, __c) __arm_vqrdmlahq_n_u16(__a, __b, __c) -#define vqdmlahq_n_u16(__a, __b, __c) __arm_vqdmlahq_n_u16(__a, __b, __c) #define vmvnq_m_u16(__inactive, __a, __p) __arm_vmvnq_m_u16(__inactive, __a, __p) #define vmlasq_n_u16(__a, __b, __c) __arm_vmlasq_n_u16(__a, __b, __c) #define vmlaq_n_u16(__a, __b, __c) __arm_vmlaq_n_u16(__a, __b, __c) @@ -1408,9 +1402,6 @@ #define vpselq_u32(__a, __b, __p) __arm_vpselq_u32(__a, __b, __p) #define vpselq_s32(__a, __b, __p) __arm_vpselq_s32(__a, __b, __p) #define vrev64q_m_u32(__inactive, __a, __p) __arm_vrev64q_m_u32(__inactive, __a, __p) -#define vqrdmlashq_n_u32(__a, __b, __c) __arm_vqrdmlashq_n_u32(__a, __b, __c) -#define vqrdmlahq_n_u32(__a, __b, __c) __arm_vqrdmlahq_n_u32(__a, __b, __c) -#define vqdmlahq_n_u32(__a, __b, __c) __arm_vqdmlahq_n_u32(__a, __b, __c) #define vmvnq_m_u32(__inactive, __a, __p) __arm_vmvnq_m_u32(__inactive, __a, __p) #define vmlasq_n_u32(__a, __b, __c) __arm_vmlasq_n_u32(__a, __b, __c) #define vmlaq_n_u32(__a, __b, __c) __arm_vmlaq_n_u32(__a, __b, __c) @@ -2032,8 +2023,6 @@ #define vmlaldavaq_p_u16(__a, __b, __c, __p) __arm_vmlaldavaq_p_u16(__a, __b, __c, __p) #define vmlaldavaxq_p_s32(__a, __b, __c, __p) __arm_vmlaldavaxq_p_s32(__a, __b, __c, __p) #define vmlaldavaxq_p_s16(__a, __b, __c, __p) __arm_vmlaldavaxq_p_s16(__a, __b, __c, __p) -#define vmlaldavaxq_p_u32(__a, __b, __c, __p)
[PATCH][GCC-10 backport] arm: [MVE] Add vqdmlashq intrinsics (PR target/96914)
Hello, Applied cleanly, Ok for backporting this patch to GCC-10? This patch adds: vqdmlashq_m_n_s16 vqdmlashq_m_n_s32 vqdmlashq_m_n_s8 vqdmlashq_n_s16 vqdmlashq_n_s32 vqdmlashq_n_s8 2020-10-08 Christophe Lyon gcc/ PR target/96914 * config/arm/arm_mve.h (vqdmlashq, vqdmlashq_m): Define. * config/arm/arm_mve_builtins.def (vqdmlashq_n_s) (vqdmlashq_m_n_s,): New. * config/arm/unspecs.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New unspecs. * config/arm/iterators.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New attributes. (VQDMLASHQ_N): New iterator. * config/arm/mve.md (mve_vqdmlashq_n_, mve_vqdmlashq_m_n_s): New patterns. gcc/testsuite/ PR target/96914 * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s16.c: New test. * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s32.c: New test. * gcc.target/arm/mve/intrinsics/vqdmlashq_m_n_s8.c: New test. * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s16.c: New test. * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s32.c: New test. * gcc.target/arm/mve/intrinsics/vqdmlashq_n_s8.c: New test. (cherry picked from commit afb198ee3729c29c8e681aedc656f55f4afe4053) ### Attachment also inlined for ease of reply### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 02dd216cb6039c20dbeda0c2ee1ca7ee8cb77549..424a5ae84623569c9feafae78107933cb1de5744 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -141,6 +141,7 @@ #define vrev64q_m(__inactive, __a, __p) __arm_vrev64q_m(__inactive, __a, __p) #define vqrdmlashq(__a, __b, __c) __arm_vqrdmlashq(__a, __b, __c) #define vqrdmlahq(__a, __b, __c) __arm_vqrdmlahq(__a, __b, __c) +#define vqdmlashq(__a, __b, __c) __arm_vqdmlashq(__a, __b, __c) #define vqdmlahq(__a, __b, __c) __arm_vqdmlahq(__a, __b, __c) #define vmvnq_m(__inactive, __a, __p) __arm_vmvnq_m(__inactive, __a, __p) #define vmlasq(__a, __b, __c) __arm_vmlasq(__a, __b, __c) @@ -260,6 +261,7 @@ #define vorrq_m(__inactive, __a, __b, __p) __arm_vorrq_m(__inactive, __a, __b, __p) #define vqaddq_m(__inactive, __a, __b, __p) __arm_vqaddq_m(__inactive, __a, __b, __p) #define vqdmladhq_m(__inactive, __a, __b, __p) __arm_vqdmladhq_m(__inactive, __a, __b, __p) +#define vqdmlashq_m(__a, __b, __c, __p) __arm_vqdmlashq_m(__a, __b, __c, __p) #define vqdmladhxq_m(__inactive, __a, __b, __p) __arm_vqdmladhxq_m(__inactive, __a, __b, __p) #define vqdmlahq_m(__a, __b, __c, __p) __arm_vqdmlahq_m(__a, __b, __c, __p) #define vqdmlsdhq_m(__inactive, __a, __b, __p) __arm_vqdmlsdhq_m(__inactive, __a, __b, __p) @@ -1306,6 +1308,7 @@ #define vqdmlsdhxq_s8(__inactive, __a, __b) __arm_vqdmlsdhxq_s8(__inactive, __a, __b) #define vqdmlsdhq_s8(__inactive, __a, __b) __arm_vqdmlsdhq_s8(__inactive, __a, __b) #define vqdmlahq_n_s8(__a, __b, __c) __arm_vqdmlahq_n_s8(__a, __b, __c) +#define vqdmlashq_n_s8(__a, __b, __c) __arm_vqdmlashq_n_s8(__a, __b, __c) #define vqdmladhxq_s8(__inactive, __a, __b) __arm_vqdmladhxq_s8(__inactive, __a, __b) #define vqdmladhq_s8(__inactive, __a, __b) __arm_vqdmladhq_s8(__inactive, __a, __b) #define vmlsdavaxq_s8(__a, __b, __c) __arm_vmlsdavaxq_s8(__a, __b, __c) @@ -1390,6 +1393,7 @@ #define vqrdmladhq_s16(__inactive, __a, __b) __arm_vqrdmladhq_s16(__inactive, __a, __b) #define vqdmlsdhxq_s16(__inactive, __a, __b) __arm_vqdmlsdhxq_s16(__inactive, __a, __b) #define vqdmlsdhq_s16(__inactive, __a, __b) __arm_vqdmlsdhq_s16(__inactive, __a, __b) +#define vqdmlashq_n_s16(__a, __b, __c) __arm_vqdmlashq_n_s16(__a, __b, __c) #define vqdmlahq_n_s16(__a, __b, __c) __arm_vqdmlahq_n_s16(__a, __b, __c) #define vqdmladhxq_s16(__inactive, __a, __b) __arm_vqdmladhxq_s16(__inactive, __a, __b) #define vqdmladhq_s16(__inactive, __a, __b) __arm_vqdmladhq_s16(__inactive, __a, __b) @@ -1475,6 +1479,7 @@ #define vqrdmladhq_s32(__inactive, __a, __b) __arm_vqrdmladhq_s32(__inactive, __a, __b) #define vqdmlsdhxq_s32(__inactive, __a, __b) __arm_vqdmlsdhxq_s32(__inactive, __a, __b) #define vqdmlsdhq_s32(__inactive, __a, __b) __arm_vqdmlsdhq_s32(__inactive, __a, __b) +#define vqdmlashq_n_s32(__a, __b, __c) __arm_vqdmlashq_n_s32(__a, __b, __c) #define vqdmlahq_n_s32(__a, __b, __c) __arm_vqdmlahq_n_s32(__a, __b, __c) #define vqdmladhxq_s32(__inactive, __a, __b) __arm_vqdmladhxq_s32(__inactive, __a, __b) #define vqdmladhq_s32(__inactive, __a, __b) __arm_vqdmladhq_s32(__inactive, __a, __b) @@ -1901,6 +1906,9 @@ #define vqdmladhxq_m_s8(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s8(__inactive, __a, __b, __p) #define vqdmladhxq_m_s32(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s32(__inactive, __a, __b, __p) #define vqdmladhxq_m_s16(__inactive, __a, __b, __p) __arm_vqdmladhxq_m_s16(__inactive, __a, __b, __p) +#define vqdmlashq_m_n_s8(__a, __b, __c, __p) __arm_vqdmlashq_m_n_s8(__a, __b, __c, __p) +#define vqdmlashq_m_n_s32(__a, __b, __c, __p)
[PATCH][GCC-10 backport] arm: [MVE] Add missing __arm_vcvtnq_u32_f32 intrinsic (PR 96914)
Hello,
Applied cleanly, Ok for backporting this patch to GCC-10?
__arm_vcvtnq_u32_f32 was missing from arm_mve.h, although the s32_f32 and
[su]16_f16 versions were present.
This patch adds the missing version and testcase, which are
cut-and-paste from the other versions.
2020-10-08 Christophe Lyon
gcc/
PR target/96914
* config/arm/arm_mve.h (__arm_vcvtnq_u32_f32): New.
gcc/testsuite/
PR target/96914
* gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c: New test.
(cherry picked from commit 5a448362da6133c3b16ffdb0c795b657af7fa5a4)
### Attachment also inlined for ease of reply###
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
f0de29477abd9a1474eaaf028aa9a6ea57b58142..6c0d1e2e634a32196eb31079166a7733dcd3a4b6
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -645,6 +645,7 @@
#define vcvtpq_u16_f16(__a) __arm_vcvtpq_u16_f16(__a)
#define vcvtpq_u32_f32(__a) __arm_vcvtpq_u32_f32(__a)
#define vcvtnq_u16_f16(__a) __arm_vcvtnq_u16_f16(__a)
+#define vcvtnq_u32_f32(__a) __arm_vcvtnq_u32_f32(__a)
#define vcvtmq_u16_f16(__a) __arm_vcvtmq_u16_f16(__a)
#define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a)
#define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a)
@@ -16966,6 +16967,13 @@ __arm_vcvtnq_u16_f16 (float16x8_t __a)
return __builtin_mve_vcvtnq_uv8hi (__a);
}
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_u32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtnq_uv4si (__a);
+}
+
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vcvtmq_u16_f16 (float16x8_t __a)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
new file mode 100644
index
..b6d5eb90493143857159995d78f53df8ced0c667
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
@@ -0,0 +1,13 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (float32x4_t a)
+{
+ return vcvtnq_u32_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vcvtn.u32.f32" } } */
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
f0de29477abd9a1474eaaf028aa9a6ea57b58142..6c0d1e2e634a32196eb31079166a7733dcd3a4b6
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -645,6 +645,7 @@
#define vcvtpq_u16_f16(__a) __arm_vcvtpq_u16_f16(__a)
#define vcvtpq_u32_f32(__a) __arm_vcvtpq_u32_f32(__a)
#define vcvtnq_u16_f16(__a) __arm_vcvtnq_u16_f16(__a)
+#define vcvtnq_u32_f32(__a) __arm_vcvtnq_u32_f32(__a)
#define vcvtmq_u16_f16(__a) __arm_vcvtmq_u16_f16(__a)
#define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a)
#define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a)
@@ -16966,6 +16967,13 @@ __arm_vcvtnq_u16_f16 (float16x8_t __a)
return __builtin_mve_vcvtnq_uv8hi (__a);
}
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_u32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtnq_uv4si (__a);
+}
+
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vcvtmq_u16_f16 (float16x8_t __a)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
new file mode 100644
index
..b6d5eb90493143857159995d78f53df8ced0c667
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u32_f32.c
@@ -0,0 +1,13 @@
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (float32x4_t a)
+{
+ return vcvtnq_u32_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vcvtn.u32.f32" } } */
[PATCH][COMMITTED][GCC-10 backport] arm: Fix wrong code generated for mve scatter store with writeback intrinsics with -O2 (PR97271).
This patch fixes (PR97271) the wrong code-gen for mve scatter store with
writeback intrinsics with -O2.
$cat bug.c
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
vstrwq_scatter_base_wb_s32 (addr, 8, value);
}
$ arm-none-eabi-gcc bug.c -S -O2 -march=armv8.1-m.main+mve -mfloat-abi=hard -o
-
Without this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! ---> (A)
vldr.64 d4, .L3
vldr.64 d5, .L3+8
vldrw.32q3, [r0]
vstrw.u32 q2, [q3, #8]! ---> (B)
bx lr
...
With this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! --> (C)
vstrw.32q3, [r0]
bx lr
...
Without this patch 2 vstrw assembly instructions (A and B) are generated for
vstrwq_scatter_base_wb_s32
intrinsic where as fix generates only one vstrw assembly instruction (C).
Patch backport approved here
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556373.html
gcc/ChangeLog:
2020-10-06 Srinath Parvathaneni
PR target/97271
* config/arm/arm-builtins.c (arm_strsbwbs_qualifiers): Modify array.
(arm_strsbwbu_qualifiers): Likewise.
(arm_strsbwbs_p_qualifiers): Likewise.
(arm_strsbwbu_p_qualifiers): Likewise.
* config/arm/arm_mve.h (__arm_vstrdq_scatter_base_wb_s64): Modify
function definition.
(__arm_vstrdq_scatter_base_wb_u64): Likewise.
(__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
(__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
(__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
(__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
(__arm_vstrwq_scatter_base_wb_s32): Likewise.
(__arm_vstrwq_scatter_base_wb_u32): Likewise.
(__arm_vstrwq_scatter_base_wb_f32): Likewise.
(__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
* config/arm/arm_mve_builtins.def (vstrwq_scatter_base_wb_add_u): Remove
expansion for the builtin.
(vstrwq_scatter_base_wb_add_s): Likewise.
(vstrwq_scatter_base_wb_add_f): Likewise.
(vstrdq_scatter_base_wb_add_u): Likewise.
(vstrdq_scatter_base_wb_add_s): Likewise.
(vstrwq_scatter_base_wb_p_add_u): Likewise.
(vstrwq_scatter_base_wb_p_add_s): Likewise.
(vstrwq_scatter_base_wb_p_add_f): Likewise.
(vstrdq_scatter_base_wb_p_add_u): Likewise.
(vstrdq_scatter_base_wb_p_add_s): Likewise.
* config/arm/mve.md (mve_vstrwq_scatter_base_wb_v4si): Remove
expand.
(mve_vstrwq_scatter_base_wb_add_v4si): Likewise.
(mve_vstrwq_scatter_base_wb_v4si_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_v4si): This.
(mve_vstrwq_scatter_base_wb_p_v4si): Remove expand.
(mve_vstrwq_scatter_base_wb_p_add_v4si): Likewise.
(mve_vstrwq_scatter_base_wb_p_v4si_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_p_v4si): This.
(mve_vstrwq_scatter_base_wb_fv4sf): Remove expand.
(mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
(mve_vstrwq_scatter_base_wb_fv4sf_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_fv4sf): This.
(mve_vstrwq_scatter_base_wb_p_fv4sf): Remove expand.
(mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
(mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_p_fv4sf): This.
(mve_vstrdq_scatter_base_wb_v2di): Remove expand.
(mve_vstrdq_scatter_base_wb_add_v2di): Likewise.
(mve_vstrdq_scatter_base_wb_v2di_insn): Rename pattern to ...
(mve_vstrdq_scatter_base_wb_v2di): This.
(mve_vstrdq_scatter_base_wb_p_v2di): Remove expand.
(mve_vstrdq_scatter_base_wb_p_add_v2di): Likewise.
(mve_vstrdq_scatter_base_wb_p_v2di_insn): Rename pattern to ...
(mve_vstrdq_scatter_base_wb_p_v2di): This.
gcc/testsuite/ChangeLog:
PR target/97271
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Modify.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise.
(cherry picked from commit 377535881166969dba43794f298170978d797ef6)
### Attachment also inlined for ease of reply###
[PATCH][GCC] arm: Fix wrong code generated for mve scatter store with writeback intrinsics with -O2 (PR97271).
Hello,
This patch fixes (PR97271) the wrong code-gen for mve scatter store with
writeback intrinsics with -O2.
$cat bug.c
#include "arm_mve.h"
void
foo (uint32x4_t * addr, const int offset, int32x4_t value)
{
vstrwq_scatter_base_wb_s32 (addr, 8, value);
}
$ arm-none-eabi-gcc bug.c -S -O2 -march=armv8.1-m.main+mve -mfloat-abi=hard -o
-
Without this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! ---> (A)
vldr.64 d4, .L3
vldr.64 d5, .L3+8
vldrw.32q3, [r0]
vstrw.u32 q2, [q3, #8]! ---> (B)
bx lr
...
With this patch:
...
foo:
vldrw.32q3, [r0]
vstrw.u32 q0, [q3, #8]! --> (C)
vstrw.32q3, [r0]
bx lr
...
Without this patch 2 vstrw assembly instructions (A and B) are generated for
vstrwq_scatter_base_wb_s32
intrinsic where as fix generates only one vstrw assembly instruction (C).
Bootstrapped on arm-none-linux-gnueabihf and regression tested on arm-none-eabi
and found no regressions.
Ok for master? Ok for GCC-10 branch?
Regards,
Srinath.
gcc/ChangeLog:
2020-10-06 Srinath Parvathaneni
PR target/97291
* config/arm/arm-builtins.c (arm_strsbwbs_qualifiers): Modify array.
(arm_strsbwbu_qualifiers): Likewise.
(arm_strsbwbs_p_qualifiers): Likewise.
(arm_strsbwbu_p_qualifiers): Likewise.
* config/arm/arm_mve.h (__arm_vstrdq_scatter_base_wb_s64): Modify
function definition.
(__arm_vstrdq_scatter_base_wb_u64): Likewise.
(__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
(__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
(__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
(__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
(__arm_vstrwq_scatter_base_wb_s32): Likewise.
(__arm_vstrwq_scatter_base_wb_u32): Likewise.
(__arm_vstrwq_scatter_base_wb_f32): Likewise.
(__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
* config/arm/arm_mve_builtins.def (vstrwq_scatter_base_wb_add_u): Remove
expansion for the builtin.
(vstrwq_scatter_base_wb_add_s): Likewise.
(vstrwq_scatter_base_wb_add_f): Likewise.
(vstrdq_scatter_base_wb_add_u): Likewise.
(vstrdq_scatter_base_wb_add_s): Likewise.
(vstrwq_scatter_base_wb_p_add_u): Likewise.
(vstrwq_scatter_base_wb_p_add_s): Likewise.
(vstrwq_scatter_base_wb_p_add_f): Likewise.
(vstrdq_scatter_base_wb_p_add_u): Likewise.
(vstrdq_scatter_base_wb_p_add_s): Likewise.
* config/arm/mve.md (mve_vstrwq_scatter_base_wb_v4si): Remove
expand.
(mve_vstrwq_scatter_base_wb_add_v4si): Likewise.
(mve_vstrwq_scatter_base_wb_v4si_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_v4si): This.
(mve_vstrwq_scatter_base_wb_p_v4si): Remove expand.
(mve_vstrwq_scatter_base_wb_p_add_v4si): Likewise.
(mve_vstrwq_scatter_base_wb_p_v4si_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_p_v4si): This.
(mve_vstrwq_scatter_base_wb_fv4sf): Remove expand.
(mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
(mve_vstrwq_scatter_base_wb_fv4sf_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_fv4sf): This.
(mve_vstrwq_scatter_base_wb_p_fv4sf): Remove expand.
(mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
(mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Rename pattern to ...
(mve_vstrwq_scatter_base_wb_p_fv4sf): This.
(mve_vstrdq_scatter_base_wb_v2di): Remove expand.
(mve_vstrdq_scatter_base_wb_add_v2di): Likewise.
(mve_vstrdq_scatter_base_wb_v2di_insn): Rename pattern to ...
(mve_vstrdq_scatter_base_wb_v2di): This.
(mve_vstrdq_scatter_base_wb_p_v2di): Remove expand.
(mve_vstrdq_scatter_base_wb_p_add_v2di): Likewise.
(mve_vstrdq_scatter_base_wb_p_v2di_insn): Rename pattern to ...
(mve_vstrdq_scatter_base_wb_p_v2di): This.
gcc/testsuite/ChangeLog:
PR target/97291
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c: Modify.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise.
### Attachment also inlined for ease of
[PATCH][GCC-10 backport] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55.
Backport of Joe's patch wit no changes. This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve:equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp: equivalent to armv8.1-m.main+mve (+dsp is implied by +mve). - +nodsp:equivalent to armv8.1-m.main+fp.dp. Combinations of the above: - +nomve+nofp: equivalent to armv8.1-m.main+dsp. - +nodsp+nofp: equivalent to armv8.1-m.main. Due to MVE and FP sharing vfp_base, some new syntax was required in the CPU description to implement the concept of 'implied bits'. These are non-named features added to the ISA late, depending on whether one or more features which depend on them are present. This means vfp_base can be present when only one of MVE and FP is removed, but absent when both are removed. Ok for GCC-10 branch? gcc/ChangeLog: 2020-07-31 Joe Ramsay * config/arm/arm-cpus.in: (ALL_FPU_INTERNAL): Remove vfp_base. (VFPv2): Remove vfp_base. (MVE): Remove vfp_base. (vfp_base): Redefine as implied bit dependent on MVE or FP (cortex-m55): Add flags to disable MVE, MVE FP, FP and DSP extensions. * config/arm/arm.c (arm_configure_build_target): Add implied bits to ISA. * config/arm/parsecpu.awk: (gen_isa): Print implied bits and their dependencies to ISA header. (gen_data): Add parsing for implied feature bits. gcc/testsuite/ChangeLog: * gcc.target/arm/cortex-m55-nodsp-flag-hard.c: New test. * gcc.target/arm/cortex-m55-nodsp-flag-softfp.c: New test. * gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c: New test. * gcc.target/arm/cortex-m55-nofp-flag-hard.c: New test. * gcc.target/arm/cortex-m55-nofp-flag-softfp.c: New test. * gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c: New test. * gcc.target/arm/cortex-m55-nomve-flag-hard.c: New test. * gcc.target/arm/cortex-m55-nomve-flag-softfp.c: New test. * gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c: New test. * gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c: New test. * gcc.target/arm/multilib.exp: Add tests for -mcpu=cortex-m55. (cherry picked from commit 3e8fb15a8cfd0e62dd474af9f536863392ed7572) ### Attachment also inlined for ease of reply### diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index d609113e969d69505bc2f1b13fab8b1dfd622472..db0b93f6bb74f6ddf42636caa0d9a3db38692982 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -135,10 +135,6 @@ define feature armv8_1m_main # Floating point and Neon extensions. # VFPv1 is not supported in GCC. -# This feature bit is enabled for all VFP, MVE and -# MVE with floating point extensions. -define feature vfp_base - # Vector floating point v2. define feature vfpv2 @@ -251,7 +247,7 @@ define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL # List of all FPU bits to strip out if -mfpu is used to override the # default. fp16 is deliberately missing from this list. -define fgroup ALL_FPU_INTERNAL vfp_base vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL +define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL # Similarly, but including fp16 and other extensions that aren't part of # -mfpu support. define fgroup ALL_FPU_EXTERNAL fp16 bf16 @@ -296,11 +292,11 @@ define fgroup ARMv8r ARMv8a define fgroup ARMv8_1m_main ARMv8m_main armv8_1m_main # Useful combinations. -define fgroup VFPv2vfp_base vfpv2 +define fgroup VFPv2vfpv2 define fgroup VFPv3VFPv2 vfpv3 define fgroup VFPv4VFPv3 vfpv4 fp16conv define fgroup FPv5 VFPv4 fpv5 -define fgroup MVE mve vfp_base armv7em +define fgroup MVE mve armv7em define fgroup MVE_FP MVE FPv5 fp16 mve_float define fgroup FP_DBL fp_dbl @@ -310,6 +306,18 @@ define fgroup NEON FP_D32 neon define fgroup CRYPTO NEON crypto define fgroup DOTPROD NEON dotprod +# Implied feature bits. These are for non-named features shared between fgroups. +# Shared feature f belonging to fgroups A and B will be erroneously removed if: +# A and B are enabled by default AND A is disabled by a removal flag. +# To ensure that f is retained, we must add such bits to the ISA after +# processing the removal flags. This is implemented by 'implied bits': +# define implied []+ +# This indicates that, if any of the listed features are enabled, or if any +# member of a listed fgroup is enabled, then will be implicitly enabled. + +# Enabled for all VFP, MVE and MVE with floating point extensions. +define implied vfp_base MVE MVE_FP ALL_FP + # List of all quirk bits to strip out when comparing CPU features with # architectures. # xscale isn't really a 'quirk', but it isn't an architecture either and we @@ -1532,6 +1540,10 @@ begin cpu
[GCC-10 backport][COMMITTED] arm: Move iterators from mve.md to iterators.md to maintain consistency.
Backport approved here https://gcc.gnu.org/pipermail/gcc-patches/2020-October/555618.html . To maintain consistency with other Arm Architectures backend, iterators and iterator attributes are moved from mve.md file to iterators.md. Also move enumerators for MVE unspecs from mve.md file to unspecs.md file. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to iterators.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise. (MVE_3): Likewise. (MVE_2): Likewise. (MVE_5): Likewise. (MVE_6): Likewise. (MVE_CNVT): Move mode attribute iterator from mve.md to iterators.md. (MVE_LANES): Likewise. (MVE_constraint): Likewise. (MVE_constraint1): Likewise. (MVE_constraint2): Likewise. (MVE_constraint3): Likewise. (MVE_pred): Likewise. (MVE_pred1): Likewise. (MVE_pred2): Likewise. (MVE_pred3): Likewise. (MVE_B_ELEM): Likewise. (MVE_H_ELEM): Likewise. (V_sz_elem1): Likewise. (V_extr_elem): Likewise. (earlyclobber_32): Likewise. (supf): Move int attribute from mve.md to iterators.md. (mode1): Likewise. (VCVTQ_TO_F): Move int iterator from mve.md to iterators.md. (VMVNQ_N): Likewise. (VREV64Q): Likewise. (VCVTQ_FROM_F): Likewise. (VREV16Q): Likewise. (VCVTAQ): Likewise. (VMVNQ): Likewise. (VDUPQ_N): Likewise. (VCLZQ): Likewise. (VADDVQ): Likewise. (VREV32Q): Likewise. (VMOVLBQ): Likewise. (VMOVLTQ): Likewise. (VCVTPQ): Likewise. (VCVTNQ): Likewise. (VCVTMQ): Likewise. (VADDLVQ): Likewise. (VCTPQ): Likewise. (VCTPQ_M): Likewise. (VCVTQ_N_TO_F): Likewise. (VCREATEQ): Likewise. (VSHRQ_N): Likewise. (VCVTQ_N_FROM_F): Likewise. (VADDLVQ_P): Likewise. (VCMPNEQ): Likewise. (VSHLQ): Likewise. (VABDQ): Likewise. (VADDQ_N): Likewise. (VADDVAQ): Likewise. (VADDVQ_P): Likewise. (VANDQ): Likewise. (VBICQ): Likewise. (VBRSRQ_N): Likewise. (VCADDQ_ROT270): Likewise. (VCADDQ_ROT90): Likewise. (VCMPEQQ): Likewise. (VCMPEQQ_N): Likewise. (VCMPNEQ_N): Likewise. (VEORQ): Likewise. (VHADDQ): Likewise. (VHADDQ_N): Likewise. (VHSUBQ): Likewise. (VHSUBQ_N): Likewise. (VMAXQ): Likewise. (VMAXVQ): Likewise. (VMINQ): Likewise. (VMINVQ): Likewise. (VMLADAVQ): Likewise. (VMULHQ): Likewise. (VMULLBQ_INT): Likewise. (VMULLTQ_INT): Likewise. (VMULQ): Likewise. (VMULQ_N): Likewise. (VORNQ): Likewise. (VORRQ): Likewise. (VQADDQ): Likewise. (VQADDQ_N): Likewise. (VQRSHLQ): Likewise. (VQRSHLQ_N): Likewise. (VQSHLQ): Likewise. (VQSHLQ_N): Likewise. (VQSHLQ_R): Likewise. (VQSUBQ): Likewise. (VQSUBQ_N): Likewise. (VRHADDQ): Likewise. (VRMULHQ): Likewise. (VRSHLQ): Likewise. (VRSHLQ_N): Likewise. (VRSHRQ_N): Likewise. (VSHLQ_N): Likewise. (VSHLQ_R): Likewise. (VSUBQ): Likewise. (VSUBQ_N): Likewise. (VADDLVAQ): Likewise. (VBICQ_N): Likewise. (VMLALDAVQ): Likewise. (VMLALDAVXQ): Likewise. (VMOVNBQ): Likewise. (VMOVNTQ): Likewise. (VORRQ_N): Likewise. (VQMOVNBQ): Likewise. (VQMOVNTQ): Likewise. (VSHLLBQ_N): Likewise. (VSHLLTQ_N): Likewise. (VRMLALDAVHQ): Likewise. (VBICQ_M_N): Likewise. (VCVTAQ_M): Likewise. (VCVTQ_M_TO_F): Likewise. (VQRSHRNBQ_N): Likewise. (VABAVQ): Likewise. (VSHLCQ): Likewise. (VRMLALDAVHAQ): Likewise. (VADDVAQ_P): Likewise. (VCLZQ_M): Likewise. (VCMPEQQ_M_N): Likewise. (VCMPEQQ_M): Likewise. (VCMPNEQ_M_N): Likewise. (VCMPNEQ_M): Likewise. (VDUPQ_M_N): Likewise. (VMAXVQ_P): Likewise. (VMINVQ_P): Likewise. (VMLADAVAQ): Likewise. (VMLADAVQ_P): Likewise. (VMLAQ_N): Likewise. (VMLASQ_N): Likewise. (VMVNQ_M): Likewise. (VPSELQ): Likewise. (VQDMLAHQ_N): Likewise. (VQRDMLAHQ_N): Likewise. (VQRDMLASHQ_N): Likewise. (VQRSHLQ_M_N): Likewise. (VQSHLQ_M_R): Likewise. (VREV64Q_M): Likewise. (VRSHLQ_M_N): Likewise. (VSHLQ_M_R): Likewise. (VSLIQ_N): Likewise. (VSRIQ_N): Likewise. (VMLALDAVQ_P): Likewise. (VQMOVNBQ_M): Likewise. (VMOVLTQ_M): Likewise. (VMOVNBQ_M): Likewise. (VRSHRNTQ_N): Likewise.
RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md to maintain consistency.
Hi Kyrill, > -Original Message- > From: Kyrylo Tkachov > Sent: 06 October 2020 14:42 > To: Srinath Parvathaneni ; gcc- > patc...@gcc.gnu.org > Subject: RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md > to maintain consistency. > > > > > -Original Message- > > From: Srinath Parvathaneni > > Sent: 06 October 2020 13:27 > > To: gcc-patches@gcc.gnu.org > > Cc: Kyrylo Tkachov > > Subject: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md > > to maintain consistency. > > > > Hello, > > > > To maintain consistency with other Arm Architectures backend, > > iterators and iterator attributes are moved from mve.md file to > > iterators.md. Also move enumerators for MVE unspecs from mve.md file > > to unspecs.md file. > > > > Regression tested on arm-none-eabi and found no regressions. > > > > Ok for master? Ok for GCC-10 branch? > > Ok for trunk. > I'm not sure if this is needed for the GCC 10 branch (but am open to being > convinced otherwise?) Thanks for approving this patch. Backporting this patch avoid conflicts when backporting any bug fix modifying MVE Patterns (iterators and unspecs), I hope this convinces you. Regards, SRI. > > Thanks, > Kyrill > > > > > Regards, > > Srinath. > > > > gcc/ChangeLog: > > > > 2020-10-06 Srinath Parvathaneni > > > > * config/arm/iterators.md (MVE_types): Move mode iterator from > mve.md > > to > > iterators.md. > > (MVE_VLD_ST): Likewise. > > (MVE_0): Likewise. > > (MVE_1): Likewise. > > (MVE_3): Likewise. > > (MVE_2): Likewise. > > (MVE_5): Likewise. > > (MVE_6): Likewise. > > (MVE_CNVT): Move mode attribute iterator from mve.md to > iterators.md. > > (MVE_LANES): Likewise. > > (MVE_constraint): Likewise. > > (MVE_constraint1): Likewise. > > (MVE_constraint2): Likewise. > > (MVE_constraint3): Likewise. > > (MVE_pred): Likewise. > > (MVE_pred1): Likewise. > > (MVE_pred2): Likewise. > > (MVE_pred3): Likewise. > > (MVE_B_ELEM): Likewise. > > (MVE_H_ELEM): Likewise. > > (V_sz_elem1): Likewise. > > (V_extr_elem): Likewise. > > (earlyclobber_32): Likewise. > > (supf): Move int attribute from mve.md to iterators.md. > > (mode1): Likewise. > > (VCVTQ_TO_F): Move int iterator from mve.md to iterators.md. > > (VMVNQ_N): Likewise. > > (VREV64Q): Likewise. > > (VCVTQ_FROM_F): Likewise. > > (VREV16Q): Likewise. > > (VCVTAQ): Likewise. > > (VMVNQ): Likewise. > > (VDUPQ_N): Likewise. > > (VCLZQ): Likewise. > > (VADDVQ): Likewise. > > (VREV32Q): Likewise. > > (VMOVLBQ): Likewise. > > (VMOVLTQ): Likewise. > > (VCVTPQ): Likewise. > > (VCVTNQ): Likewise. > > (VCVTMQ): Likewise. > > (VADDLVQ): Likewise. > > (VCTPQ): Likewise. > > (VCTPQ_M): Likewise. > > (VCVTQ_N_TO_F): Likewise. > > (VCREATEQ): Likewise. > > (VSHRQ_N): Likewise. > > (VCVTQ_N_FROM_F): Likewise. > > (VADDLVQ_P): Likewise. > > (VCMPNEQ): Likewise. > > (VSHLQ): Likewise. > > (VABDQ): Likewise. > > (VADDQ_N): Likewise. > > (VADDVAQ): Likewise. > > (VADDVQ_P): Likewise. > > (VANDQ): Likewise. > > (VBICQ): Likewise. > > (VBRSRQ_N): Likewise. > > (VCADDQ_ROT270): Likewise. > > (VCADDQ_ROT90): Likewise. > > (VCMPEQQ): Likewise. > > (VCMPEQQ_N): Likewise. > > (VCMPNEQ_N): Likewise. > > (VEORQ): Likewise. > > (VHADDQ): Likewise. > > (VHADDQ_N): Likewise. > > (VHSUBQ): Likewise. > > (VHSUBQ_N): Likewise. > > (VMAXQ): Likewise. > > (VMAXVQ): Likewise. > > (VMINQ): Likewise. > > (VMINVQ): Likewise. > > (VMLADAVQ): Likewise. > > (VMULHQ): Likewise. > > (VMULLBQ_INT): Likewise. > > (VMULLTQ_INT): Likewise. > > (VMULQ): Likewise. > > (VMULQ_N): Likewise. > > (VORNQ): Likewise. > > (VORRQ): Likewise. > > (VQADDQ): Likewise. > > (VQADDQ_N): Likewise. > > (VQRSHLQ): Likewise. > > (VQRSHLQ_N): Likewise. > > (VQSHLQ): Likewise. > > (VQSHLQ_N): Likewise. > > (VQSHLQ_R): Likewise. > > (VQSUBQ): Likewise. > > (VQSUBQ_N): Likewise. > > (VRHADDQ): Likewise. > > (VRMULHQ): Likewise. > > (VRSHLQ): Likewise. > > (VRSHLQ_N): Likewise. > > (VRSHRQ_N): Likewise. > > (VSHLQ_N): Likewise. > > (VSHLQ_R): Likewise. > > (VSUBQ): Likewise. > > (VSUBQ_N): Likewise. > > (VADDLVAQ): Likewise. > > (VBICQ_N): Likewise. > > (VMLALDAVQ): Likewise. > > (VMLALDAVXQ): Likewise. > > (VMOVNBQ): Likewise. > > (VMOVNTQ): Likewise. > > (VORRQ_N): Likewise. > > (VQMOVNBQ): Likewise. > > (VQMOVNTQ): Likewise. > > (VSHLLBQ_N): Likewise. > > (VSHLLTQ_N): Likewise. > > (VRMLALDAVHQ): Likewise. > > (VBICQ_M_N): Likewise. > > (VCVTAQ_M): Likewise. > > (VCVTQ_M_TO_F): Likewise. > > (VQRSHRNBQ_N): Likewise. > > (VABAVQ): Likewise. > > (VSHLCQ): Likewise. > >
[PATCH][GCC-10 backport] arm: Remove coercion from scalar argument to vmin & vmax intrinsics.
Hello, Straight backport of Joe's patch with no changes. This patch fixes an issue with vmin* and vmax* intrinsics which accept a scalar argument. Previously when the scalar was of different width to the vector elements this would generate __ARM_undef. This change allows the scalar argument to be implicitly converted to the correct width. Also tidied up the relevant unit tests, some of which would have passed even if only one of two or three intrinsic calls had compiled correctly. Bootstrapped and tested on arm-none-eabi, gcc and CMSIS_DSP testsuites are clean. OK for trunk? Thanks, Joe gcc/ChangeLog: 2020-08-10 Joe Ramsay * config/arm/arm_mve.h (__arm_vmaxnmavq): Remove coercion of scalar argument. (__arm_vmaxnmvq): Likewise. (__arm_vminnmavq): Likewise. (__arm_vminnmvq): Likewise. (__arm_vmaxnmavq_p): Likewise. (__arm_vmaxnmvq_p): Likewise (and delete duplicate definition). (__arm_vminnmavq_p): Likewise. (__arm_vminnmvq_p): Likewise. (__arm_vmaxavq): Likewise. (__arm_vmaxavq_p): Likewise. (__arm_vmaxvq): Likewise. (__arm_vmaxvq_p): Likewise. (__arm_vminavq): Likewise. (__arm_vminavq_p): Likewise. (__arm_vminvq): Likewise. (__arm_vminvq_p): Likewise. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Add test for mismatched width of scalar argument. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. (cherry picked from commit 251950d899bc3c18b5775fe9fe20bebbdc8d15cb) ### Attachment also inlined for ease of reply### diff --git
[PATCH][GCC] arm: Move iterators from mve.md to iterators.md to maintain consistency.
Hello, To maintain consistency with other Arm Architectures backend, iterators and iterator attributes are moved from mve.md file to iterators.md. Also move enumerators for MVE unspecs from mve.md file to unspecs.md file. Regression tested on arm-none-eabi and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-10-06 Srinath Parvathaneni * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to iterators.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise. (MVE_3): Likewise. (MVE_2): Likewise. (MVE_5): Likewise. (MVE_6): Likewise. (MVE_CNVT): Move mode attribute iterator from mve.md to iterators.md. (MVE_LANES): Likewise. (MVE_constraint): Likewise. (MVE_constraint1): Likewise. (MVE_constraint2): Likewise. (MVE_constraint3): Likewise. (MVE_pred): Likewise. (MVE_pred1): Likewise. (MVE_pred2): Likewise. (MVE_pred3): Likewise. (MVE_B_ELEM): Likewise. (MVE_H_ELEM): Likewise. (V_sz_elem1): Likewise. (V_extr_elem): Likewise. (earlyclobber_32): Likewise. (supf): Move int attribute from mve.md to iterators.md. (mode1): Likewise. (VCVTQ_TO_F): Move int iterator from mve.md to iterators.md. (VMVNQ_N): Likewise. (VREV64Q): Likewise. (VCVTQ_FROM_F): Likewise. (VREV16Q): Likewise. (VCVTAQ): Likewise. (VMVNQ): Likewise. (VDUPQ_N): Likewise. (VCLZQ): Likewise. (VADDVQ): Likewise. (VREV32Q): Likewise. (VMOVLBQ): Likewise. (VMOVLTQ): Likewise. (VCVTPQ): Likewise. (VCVTNQ): Likewise. (VCVTMQ): Likewise. (VADDLVQ): Likewise. (VCTPQ): Likewise. (VCTPQ_M): Likewise. (VCVTQ_N_TO_F): Likewise. (VCREATEQ): Likewise. (VSHRQ_N): Likewise. (VCVTQ_N_FROM_F): Likewise. (VADDLVQ_P): Likewise. (VCMPNEQ): Likewise. (VSHLQ): Likewise. (VABDQ): Likewise. (VADDQ_N): Likewise. (VADDVAQ): Likewise. (VADDVQ_P): Likewise. (VANDQ): Likewise. (VBICQ): Likewise. (VBRSRQ_N): Likewise. (VCADDQ_ROT270): Likewise. (VCADDQ_ROT90): Likewise. (VCMPEQQ): Likewise. (VCMPEQQ_N): Likewise. (VCMPNEQ_N): Likewise. (VEORQ): Likewise. (VHADDQ): Likewise. (VHADDQ_N): Likewise. (VHSUBQ): Likewise. (VHSUBQ_N): Likewise. (VMAXQ): Likewise. (VMAXVQ): Likewise. (VMINQ): Likewise. (VMINVQ): Likewise. (VMLADAVQ): Likewise. (VMULHQ): Likewise. (VMULLBQ_INT): Likewise. (VMULLTQ_INT): Likewise. (VMULQ): Likewise. (VMULQ_N): Likewise. (VORNQ): Likewise. (VORRQ): Likewise. (VQADDQ): Likewise. (VQADDQ_N): Likewise. (VQRSHLQ): Likewise. (VQRSHLQ_N): Likewise. (VQSHLQ): Likewise. (VQSHLQ_N): Likewise. (VQSHLQ_R): Likewise. (VQSUBQ): Likewise. (VQSUBQ_N): Likewise. (VRHADDQ): Likewise. (VRMULHQ): Likewise. (VRSHLQ): Likewise. (VRSHLQ_N): Likewise. (VRSHRQ_N): Likewise. (VSHLQ_N): Likewise. (VSHLQ_R): Likewise. (VSUBQ): Likewise. (VSUBQ_N): Likewise. (VADDLVAQ): Likewise. (VBICQ_N): Likewise. (VMLALDAVQ): Likewise. (VMLALDAVXQ): Likewise. (VMOVNBQ): Likewise. (VMOVNTQ): Likewise. (VORRQ_N): Likewise. (VQMOVNBQ): Likewise. (VQMOVNTQ): Likewise. (VSHLLBQ_N): Likewise. (VSHLLTQ_N): Likewise. (VRMLALDAVHQ): Likewise. (VBICQ_M_N): Likewise. (VCVTAQ_M): Likewise. (VCVTQ_M_TO_F): Likewise. (VQRSHRNBQ_N): Likewise. (VABAVQ): Likewise. (VSHLCQ): Likewise. (VRMLALDAVHAQ): Likewise. (VADDVAQ_P): Likewise. (VCLZQ_M): Likewise. (VCMPEQQ_M_N): Likewise. (VCMPEQQ_M): Likewise. (VCMPNEQ_M_N): Likewise. (VCMPNEQ_M): Likewise. (VDUPQ_M_N): Likewise. (VMAXVQ_P): Likewise. (VMINVQ_P): Likewise. (VMLADAVAQ): Likewise. (VMLADAVQ_P): Likewise. (VMLAQ_N): Likewise. (VMLASQ_N): Likewise. (VMVNQ_M): Likewise. (VPSELQ): Likewise. (VQDMLAHQ_N): Likewise. (VQRDMLAHQ_N): Likewise. (VQRDMLASHQ_N): Likewise. (VQRSHLQ_M_N): Likewise. (VQSHLQ_M_R): Likewise. (VREV64Q_M): Likewise. (VRSHLQ_M_N): Likewise. (VSHLQ_M_R): Likewise. (VSLIQ_N): Likewise. (VSRIQ_N): Likewise. (VMLALDAVQ_P): Likewise. (VQMOVNBQ_M): Likewise. (VMOVLTQ_M): Likewise. (VMOVNBQ_M): Likewise.
[COMMITTED][GCC-10 backport] arm: Fix MVE intrinsics polymorphic variants wrongly generating __ARM_undef type (pr96795).
Hello, This patch fixes (PR96795) MVE intrinsic polymorphic variants vaddq, vaddq_m, vaddq_x, vcmpeqq_m, vcmpeqq, vcmpgeq_m, vcmpgeq, vcmpgtq_m, vcmpgtq, vcmpleq_m, vcmpleq, vcmpltq_m, vcmpltq, vcmpneq_m, vcmpneq, vfmaq_m, vfmaq, vfmasq_m, vfmasq, vmaxnmavq, vmaxnmavq_p, vmaxnmvq, vmaxnmvq_p, vminnmavq, vminnmavq_p, vminnmvq, vminnmvq_p, vmulq_m, vmulq, vmulq_x, vsetq_lane, vsubq_m, vsubq and vsubq_x which are incorrectly generating __ARM_undef and mismatching the passed floating point scalar arguments. This patch get cleanly applied on releases/gcc-10 branch. Bootstrapped on arm-none-linux-gnueabihf and regression tested on arm-none-eabi and found no regressions. Patch already approved in https://gcc.gnu.org/pipermail/gcc-patches/2020-September/555185.html , so committed this patch to releases/gcc-10 branch. Regards, Srinath. gcc/ChangeLog: 2020-09-30 Srinath Parvathaneni PR target/96795 * config/arm/arm_mve.h (__ARM_mve_coerce2): Define. (__arm_vaddq): Correct the scalar argument. (__arm_vaddq_m): Likewise. (__arm_vaddq_x): Likewise. (__arm_vcmpeqq_m): Likewise. (__arm_vcmpeqq): Likewise. (__arm_vcmpgeq_m): Likewise. (__arm_vcmpgeq): Likewise. (__arm_vcmpgtq_m): Likewise. (__arm_vcmpgtq): Likewise. (__arm_vcmpleq_m): Likewise. (__arm_vcmpleq): Likewise. (__arm_vcmpltq_m): Likewise. (__arm_vcmpltq): Likewise. (__arm_vcmpneq_m): Likewise. (__arm_vcmpneq): Likewise. (__arm_vfmaq_m): Likewise. (__arm_vfmaq): Likewise. (__arm_vfmasq_m): Likewise. (__arm_vfmasq): Likewise. (__arm_vmaxnmavq): Likewise. (__arm_vmaxnmavq_p): Likewise. (__arm_vmaxnmvq): Likewise. (__arm_vmaxnmvq_p): Likewise. (__arm_vminnmavq): Likewise. (__arm_vminnmavq_p): Likewise. (__arm_vminnmvq): Likewise. (__arm_vminnmvq_p): Likewise. (__arm_vmulq_m): Likewise. (__arm_vmulq): Likewise. (__arm_vmulq_x): Likewise. (__arm_vsetq_lane): Likewise. (__arm_vsubq_m): Likewise. (__arm_vsubq): Likewise. (__arm_vsubq_x): Likewise. gcc/testsuite/ChangeLog: PR target/96795 * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: New Test. * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Likewise. *
[GCC][PATCH] arm: Fix MVE intrinsics polymorphic variants wrongly generating __ARM_undef type (pr96795).
Hello, This patch fixes (PR96795) MVE intrinsic polymorphic variants vaddq, vaddq_m, vaddq_x, vcmpeqq_m, vcmpeqq, vcmpgeq_m, vcmpgeq, vcmpgtq_m, vcmpgtq, vcmpleq_m, vcmpleq, vcmpltq_m, vcmpltq, vcmpneq_m, vcmpneq, vfmaq_m, vfmaq, vfmasq_m, vfmasq, vmaxnmavq, vmaxnmavq_p, vmaxnmvq, vmaxnmvq_p, vminnmavq, vminnmavq_p, vminnmvq, vminnmvq_p, vmulq_m, vmulq, vmulq_x, vsetq_lane, vsubq_m, vsubq and vsubq_x which are incorrectly generating __ARM_undef and mismatching the passed floating point scalar arguments. Bootstrapped on arm-none-linux-gnueabihf and regression tested on arm-none-eabi and found no regressions. Ok for master? Ok for GCC-10 branch? Regards, Srinath. gcc/ChangeLog: 2020-09-30 Srinath Parvathaneni PR target/96795 * config/arm/arm_mve.h (__ARM_mve_coerce2): Define. (__arm_vaddq): Correct the scalar argument. (__arm_vaddq_m): Likewise. (__arm_vaddq_x): Likewise. (__arm_vcmpeqq_m): Likewise. (__arm_vcmpeqq): Likewise. (__arm_vcmpgeq_m): Likewise. (__arm_vcmpgeq): Likewise. (__arm_vcmpgtq_m): Likewise. (__arm_vcmpgtq): Likewise. (__arm_vcmpleq_m): Likewise. (__arm_vcmpleq): Likewise. (__arm_vcmpltq_m): Likewise. (__arm_vcmpltq): Likewise. (__arm_vcmpneq_m): Likewise. (__arm_vcmpneq): Likewise. (__arm_vfmaq_m): Likewise. (__arm_vfmaq): Likewise. (__arm_vfmasq_m): Likewise. (__arm_vfmasq): Likewise. (__arm_vmaxnmavq): Likewise. (__arm_vmaxnmavq_p): Likewise. (__arm_vmaxnmvq): Likewise. (__arm_vmaxnmvq_p): Likewise. (__arm_vminnmavq): Likewise. (__arm_vminnmavq_p): Likewise. (__arm_vminnmvq): Likewise. (__arm_vminnmvq_p): Likewise. (__arm_vmulq_m): Likewise. (__arm_vmulq): Likewise. (__arm_vmulq_x): Likewise. (__arm_vsetq_lane): Likewise. (__arm_vsubq_m): Likewise. (__arm_vsubq): Likewise. (__arm_vsubq_x): Likewise. gcc/testsuite/ChangeLog: PR target/96795 * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: New Test. * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Likewise. *
