[PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
From: Pan Li Fix the bug of the rvv bool mode precision with the adjustment. The bits size of vbool*_t will be adjusted to [1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The adjusted mode precison of vbool*_t will help underlying pass to make the right decision for both the correctness and optimization. Given below sample code: void test_1(int8_t * restrict in, int8_t * restrict out) { vbool8_t v2 = *(vbool8_t*)in; vbool16_t v5 = *(vbool16_t*)in; *(vbool16_t*)(out + 200) = v5; *(vbool8_t*)(out + 100) = v2; } Before the precision adjustment: addia4,a1,100 vsetvli a5,zero,e8,m1,ta,ma addia1,a1,200 vlm.v v24,0(a0) vsm.v v24,0(a4) // Need one vsetvli and vlm.v for correctness here. vsm.v v24,0(a1) After the precision adjustment: csrrt0,vlenb sllit1,t0,1 csrra3,vlenb sub sp,sp,t1 sllia4,a3,1 add a4,a4,sp sub a3,a4,a3 vsetvli a5,zero,e8,m1,ta,ma addia2,a1,200 vlm.v v24,0(a0) vsm.v v24,0(a3) addia1,a1,100 vsetvli a4,zero,e8,mf2,ta,ma csrrt0,vlenb vlm.v v25,0(a3) vsm.v v25,0(a2) sllit1,t0,1 vsetvli a5,zero,e8,m1,ta,ma vsm.v v24,0(a1) add sp,sp,t1 jr ra However, there may be some optimization opportunates after the mode precision adjustment. It can be token care of in the RISC-V backend in the underlying separted PR(s). PR 108185 PR 108654 gcc/ChangeLog: * config/riscv/riscv-modes.def (ADJUST_PRECISION): * config/riscv/riscv.cc (riscv_v_adjust_precision): * config/riscv/riscv.h (riscv_v_adjust_precision): * genmodes.cc (ADJUST_PRECISION): (emit_mode_adjustments): gcc/testsuite/ChangeLog: * gcc.target/riscv/pr108185-1.c: New test. * gcc.target/riscv/pr108185-2.c: New test. * gcc.target/riscv/pr108185-3.c: New test. * gcc.target/riscv/pr108185-4.c: New test. * gcc.target/riscv/pr108185-5.c: New test. * gcc.target/riscv/pr108185-6.c: New test. * gcc.target/riscv/pr108185-7.c: New test. * gcc.target/riscv/pr108185-8.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-modes.def| 8 +++ gcc/config/riscv/riscv.cc | 12 gcc/config/riscv/riscv.h| 1 + gcc/genmodes.cc | 25 ++- gcc/testsuite/gcc.target/riscv/pr108185-1.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-2.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-3.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-4.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-5.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-6.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-7.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-8.c | 77 + 12 files changed, 598 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-8.c diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index d5305efa8a6..110bddce851 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -72,6 +72,14 @@ ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8)); +ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1)); +ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2)); +ADJUST_PRECISION (VNx4BI, riscv_v_adjust_precision (VNx4BImode, 4)); +ADJUST_PRECISION (VNx8BI, riscv_v_adjust_precision (VNx8BImode, 8)); +ADJUST_PRECISION (VNx16BI, riscv_v_adjust_precision (VNx16BImode, 16)); +ADJUST_PRECISION (VNx32BI, riscv_v_adjust_precision (VNx32BImode, 32)); +ADJUST_PRECISION (VNx64BI, riscv_v_adjust_precision (VNx64BImode, 64)); + /* | Mode| MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | | | LMUL| SEW/LMUL| LMUL| SEW/LMUL| diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index de3e1f903c7
[PATCH] RISC-V: Bugfix for mode tieable of the rvv bool types
From: Pan Li Fix the bug for mode tieable of the rvv bool types. The vbool*_t cannot be tied as the actually load/store size is determinated by the vl. The mode size of rvv bool types are also adjusted for the underlying optimization pass. The rvv bool type is vbool*_t, aka vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, vbool32_t, and vbool64_t. PR 108185 PR 108654 gcc/ChangeLog: * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): * config/riscv/riscv.cc (riscv_v_adjust_bytesize): (riscv_modes_tieable_p): * config/riscv/riscv.h (riscv_v_adjust_bytesize): * machmode.h (VECTOR_BOOL_MODE_P): * tree-ssa-sccvn.cc (visit_reference_op_load): gcc/testsuite/ChangeLog: * gcc.target/riscv/pr108185-1.c: New test. * gcc.target/riscv/pr108185-2.c: New test. * gcc.target/riscv/pr108185-3.c: New test. * gcc.target/riscv/pr108185-4.c: New test. * gcc.target/riscv/pr108185-5.c: New test. * gcc.target/riscv/pr108185-6.c: New test. * gcc.target/riscv/pr108185-7.c: New test. * gcc.target/riscv/pr108185-8.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-modes.def| 14 ++-- gcc/config/riscv/riscv.cc | 34 - gcc/config/riscv/riscv.h| 2 + gcc/machmode.h | 3 + gcc/testsuite/gcc.target/riscv/pr108185-1.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-2.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-3.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-4.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-5.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-6.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-7.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-8.c | 77 + gcc/tree-ssa-sccvn.cc | 13 +++- 13 files changed, 608 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-8.c diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index d5305efa8a6..cc21d3c83a2 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1); ADJUST_ALIGNMENT (VNx32BI, 1); ADJUST_ALIGNMENT (VNx64BI, 1); -ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8)); +ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1)); +ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1)); +ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1)); +ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1)); +ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2)); +ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4)); +ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8)); /* | Mode| MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3b7804b7501..138c052e13c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1003,6 +1003,27 @@ riscv_v_adjust_nunits (machine_mode mode, int scale) return scale; } +/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct + BYTES size for corresponding machine_mode. */ + +poly_int64 +riscv_v_adjust_bytesize (machine_mode mode, int scale) +{ + gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL); + + if (riscv_v_ext_vector_mode_p (mode)) +{ + poly_uint16 mode_size = GET_MODE_SIZE (mode); + + if (known_lt (mode_size, BYTES_PER_RISCV_VECTOR)) + return mode_size; + else + return BYTES_PER_RISCV_VECTOR; +} + + return scale; +} + /* Return true if X is a valid address for machine mode MODE. If it is, fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */ @@
[PATCH] RISC-V: Optimize the code gen of VLM/VSM.
From: Pan Li PR 108185 PR 108654 The bytesize of the vbool*_t isn't well defined. This patch adjust the rvv bool modes with actually mode size in bytes. However, only allow mode tieable when exactly equal for the rvv bool types, aka vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, vbool32_t, and vbool64_t. gcc/ChangeLog: * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): * config/riscv/riscv.cc (riscv_v_adjust_bytesize): (riscv_modes_tieable_p): * config/riscv/riscv.h (riscv_v_adjust_bytesize): * machmode.h (VECTOR_BOOL_MODE_P): * tree-ssa-sccvn.cc (visit_reference_op_load): gcc/testsuite/ChangeLog: * gcc.target/riscv/pr108185-1.c: New test. * gcc.target/riscv/pr108185-2.c: New test. * gcc.target/riscv/pr108185-3.c: New test. * gcc.target/riscv/pr108185-4.c: New test. * gcc.target/riscv/pr108185-5.c: New test. * gcc.target/riscv/pr108185-6.c: New test. * gcc.target/riscv/pr108185-7.c: New test. * gcc.target/riscv/pr108185-8.c: New test. --- gcc/config/riscv/riscv-modes.def| 14 ++-- gcc/config/riscv/riscv.cc | 34 - gcc/config/riscv/riscv.h| 2 + gcc/machmode.h | 3 + gcc/testsuite/gcc.target/riscv/pr108185-1.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-2.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-3.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-4.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-5.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-6.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-7.c | 68 ++ gcc/testsuite/gcc.target/riscv/pr108185-8.c | 77 + gcc/tree-ssa-sccvn.cc | 13 +++- 13 files changed, 608 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-8.c diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index d5305efa8a6..cc21d3c83a2 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1); ADJUST_ALIGNMENT (VNx32BI, 1); ADJUST_ALIGNMENT (VNx64BI, 1); -ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8)); +ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1)); +ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1)); +ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1)); +ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1)); +ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2)); +ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4)); +ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8)); /* | Mode| MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3b7804b7501..995cdab108f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1003,6 +1003,27 @@ riscv_v_adjust_nunits (machine_mode mode, int scale) return scale; } +/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct + BYTES size for corresponding machine_mode. */ + +poly_int64 +riscv_v_adjust_bytesize (machine_mode mode, int scale) +{ + gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL); + + if (riscv_v_ext_vector_mode_p (mode)) +{ + poly_uint16 mode_size = GET_MODE_SIZE (mode); + + if (known_lt (mode_size, BYTES_PER_RISCV_VECTOR)) + return mode_size; + else + return BYTES_PER_RISCV_VECTOR; +} + + return scale; +} + /* Return true if X is a valid address for machine mode MODE. If it is, fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */ @@ -5807,11 +5828,22 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) /* Imp