回复：[PATCH] Asan changes for RISC-V.
Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is
still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in
to reconfigure, there are compiling errors.
Is it because # libsanitizer not supported rv32, but it will break the rv64
multi-lib build, so we disable that temporally until rv32 supported# in
Makefile.in?
--
发件人：Jim Wilson
发送时间：2020年10月29日(星期四) 07:59
收件人：gcc-patches
抄 送：cooper.joshua ; Jim Wilson
主 题：[PATCH] Asan changes for RISC-V.
We have only riscv64 asan support, there is no riscv32 support as yet. So I
need to be able to conditionally enable asan support for the riscv target. I
implemented this by returning zero from the asan_shadow_offset function. This
requires a change to toplev.c and docs in target.def.
The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel.
The problem is that the asan high memory region is a small wedge below
0x40. The new kernel puts shared libraries at 0x3f and going
down which works. But the old kernel puts shared libraries at 0x20
and going up which does not work, as it isn't in any recognized memory
region. This might be fixable with more asan work, but we don't really need
support for old kernel versions.
The asan port is curious in that it uses 1<<29 for the shadow offset, but all
other 64-bit targets use a number larger than 1<<32. But what we have is
working OK for now.
I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running on
qemu and the results look reasonable.
=== gcc Summary ===
# of expected passes 1905
# of unexpected failures 11
# of unsupported tests 224
=== g++ Summary ===
# of expected passes 2002
# of unexpected failures 6
# of unresolved testcases 1
# of unsupported tests 175
OK?
Jim
2020-10-28 Jim Wilson
gcc/
* config/riscv/riscv.c (riscv_asan_shadow_offset): New.
(TARGET_ASAN_SHADOW_OFFSET): New.
* doc/tm.texi: Regenerated.
* target.def (asan_shadow_offset); Mention that it can return zero.
* toplev.c (process_options): Check for and handle zero return from
targetm.asan_shadow_offset call.
Co-Authored-By: cooper.joshua
---
gcc/config/riscv/riscv.c | 16
gcc/doc/tm.texi | 3 ++-
gcc/target.def | 3 ++-
gcc/toplev.c | 3 ++-
4 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 989a9f15250..6909e200de1 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op)
return true;
}
+/* Implement TARGET_ASAN_SHADOW_OFFSET. */
+
+static unsigned HOST_WIDE_INT
+riscv_asan_shadow_offset (void)
+{
+ /* We only have libsanitizer support for RV64 at present.
+
+ This number must match kRiscv*_ShadowOffset* in the file
+ libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
+ even though 1<<36 makes more sense. */
+ return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op)
#undef TARGET_NEW_ADDRESS_PROFITABLE_P
#define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
+#undef TARGET_ASAN_SHADOW_OFFSET
+#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 24c37f655c8..39c596b647a 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -12078,7 +12078,8 @@ is zero, which disables this optimization.
@deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_ASAN_SHADOW_OFFSET
(void)
Return the offset bitwise ored into shifted address to get corresponding
Address Sanitizer shadow memory address. NULL if Address Sanitizer is not
-supported by the target.
+supported by the target. May return 0 if Address Sanitizer is not supported
+by a subtarget.
@end deftypefn
@deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK
(unsigned HOST_WIDE_INT @var{val})
diff --git a/gcc/target.def b/gcc/target.def
index ed2da154e30..268b56b6ebd 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -4452,7 +4452,8 @@ DEFHOOK
(asan_shadow_offset,
"Return the offset bitwise ored into shifted address to get corresponding\n\
Address Sanitizer shadow memory address. NULL if Address Sanitizer is not\n\
-supported by the target.",
+supported by the target. May return 0 if Address Sanitizer is not supported\n\
+by a subtarget.",
unsigned HOST_WIDE_INT, (void),
NULL)
diff --git a/gcc/toplev.c b/gcc/toplev.c
index 20e231f4d2a..cf89598252c 100644
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -1834,7 +1834,8 @@ process_options (void)
}
if ((flag_sanitize & SANITIZE_USER_ADDRESS)
- &&
回复：[PATCH] Asan changes for RISC-V.
Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is
still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in
to reconfigure, there are compiling errors.
Is it because # libsanitizer not supported rv32, but it will break the rv64
multi-lib build, so we disable that temporally until rv32 supported# in
Makefile.in?
--
发件人：Jim Wilson
发送时间：2020年10月29日(星期四) 07:59
收件人：gcc-patches
抄 送：cooper.joshua ; Jim Wilson
主 题：[PATCH] Asan changes for RISC-V.
We have only riscv64 asan support, there is no riscv32 support as yet. So I
need to be able to conditionally enable asan support for the riscv target. I
implemented this by returning zero from the asan_shadow_offset function. This
requires a change to toplev.c and docs in target.def.
The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel.
The problem is that the asan high memory region is a small wedge below
0x40. The new kernel puts shared libraries at 0x3f and going
down which works. But the old kernel puts shared libraries at 0x20
and going up which does not work, as it isn't in any recognized memory
region. This might be fixable with more asan work, but we don't really need
support for old kernel versions.
The asan port is curious in that it uses 1<<29 for the shadow offset, but all
other 64-bit targets use a number larger than 1<<32. But what we have is
working OK for now.
I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running on
qemu and the results look reasonable.
=== gcc Summary ===
# of expected passes 1905
# of unexpected failures 11
# of unsupported tests 224
=== g++ Summary ===
# of expected passes 2002
# of unexpected failures 6
# of unresolved testcases 1
# of unsupported tests 175
OK?
Jim
2020-10-28 Jim Wilson
gcc/
* config/riscv/riscv.c (riscv_asan_shadow_offset): New.
(TARGET_ASAN_SHADOW_OFFSET): New.
* doc/tm.texi: Regenerated.
* target.def (asan_shadow_offset); Mention that it can return zero.
* toplev.c (process_options): Check for and handle zero return from
targetm.asan_shadow_offset call.
Co-Authored-By: cooper.joshua
---
gcc/config/riscv/riscv.c | 16
gcc/doc/tm.texi | 3 ++-
gcc/target.def | 3 ++-
gcc/toplev.c | 3 ++-
4 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 989a9f15250..6909e200de1 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op)
return true;
}
+/* Implement TARGET_ASAN_SHADOW_OFFSET. */
+
+static unsigned HOST_WIDE_INT
+riscv_asan_shadow_offset (void)
+{
+ /* We only have libsanitizer support for RV64 at present.
+
+ This number must match kRiscv*_ShadowOffset* in the file
+ libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
+ even though 1<<36 makes more sense. */
+ return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op)
#undef TARGET_NEW_ADDRESS_PROFITABLE_P
#define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
+#undef TARGET_ASAN_SHADOW_OFFSET
+#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 24c37f655c8..39c596b647a 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -12078,7 +12078,8 @@ is zero, which disables this optimization.
@deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_ASAN_SHADOW_OFFSET
(void)
Return the offset bitwise ored into shifted address to get corresponding
Address Sanitizer shadow memory address. NULL if Address Sanitizer is not
-supported by the target.
+supported by the target. May return 0 if Address Sanitizer is not supported
+by a subtarget.
@end deftypefn
@deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK
(unsigned HOST_WIDE_INT @var{val})
diff --git a/gcc/target.def b/gcc/target.def
index ed2da154e30..268b56b6ebd 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -4452,7 +4452,8 @@ DEFHOOK
(asan_shadow_offset,
"Return the offset bitwise ored into shifted address to get corresponding\n\
Address Sanitizer shadow memory address. NULL if Address Sanitizer is not\n\
-supported by the target.",
+supported by the target. May return 0 if Address Sanitizer is not supported\n\
+by a subtarget.",
unsigned HOST_WIDE_INT, (void),
NULL)
diff --git a/gcc/toplev.c b/gcc/toplev.c
index 20e231f4d2a..cf89598252c 100644
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -1834,7 +1834,8 @@ process_options (void)
}
if ((flag_sanitize & SANITIZE_USER_ADDRESS)
- &&
回复：[PATCH] Asan changes for RISC-V.
Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is
still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in
to reconfigure, there are compiling errors.
Is it because # libsanitizer not supported rv32, but it will break the rv64
multi-lib build, so we disable that temporally until rv32 supported# in
Makefile.in?
--
发件人：Jim Wilson
发送时间：2020年10月29日(星期四) 07:59
收件人：gcc-patches
抄 送：cooper.joshua ; Jim Wilson
主 题：[PATCH] Asan changes for RISC-V.
We have only riscv64 asan support, there is no riscv32 support as yet. So I
need to be able to conditionally enable asan support for the riscv target. I
implemented this by returning zero from the asan_shadow_offset function. This
requires a change to toplev.c and docs in target.def.
The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel.
The problem is that the asan high memory region is a small wedge below
0x40. The new kernel puts shared libraries at 0x3f and going
down which works. But the old kernel puts shared libraries at 0x20
and going up which does not work, as it isn't in any recognized memory
region. This might be fixable with more asan work, but we don't really need
support for old kernel versions.
The asan port is curious in that it uses 1<<29 for the shadow offset, but all
other 64-bit targets use a number larger than 1<<32. But what we have is
working OK for now.
I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running on
qemu and the results look reasonable.
=== gcc Summary ===
# of expected passes 1905
# of unexpected failures 11
# of unsupported tests 224
=== g++ Summary ===
# of expected passes 2002
# of unexpected failures 6
# of unresolved testcases 1
# of unsupported tests 175
OK?
Jim
2020-10-28 Jim Wilson
gcc/
* config/riscv/riscv.c (riscv_asan_shadow_offset): New.
(TARGET_ASAN_SHADOW_OFFSET): New.
* doc/tm.texi: Regenerated.
* target.def (asan_shadow_offset); Mention that it can return zero.
* toplev.c (process_options): Check for and handle zero return from
targetm.asan_shadow_offset call.
Co-Authored-By: cooper.joshua
---
gcc/config/riscv/riscv.c | 16
gcc/doc/tm.texi | 3 ++-
gcc/target.def | 3 ++-
gcc/toplev.c | 3 ++-
4 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 989a9f15250..6909e200de1 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op)
return true;
}
+/* Implement TARGET_ASAN_SHADOW_OFFSET. */
+
+static unsigned HOST_WIDE_INT
+riscv_asan_shadow_offset (void)
+{
+ /* We only have libsanitizer support for RV64 at present.
+
+ This number must match kRiscv*_ShadowOffset* in the file
+ libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
+ even though 1<<36 makes more sense. */
+ return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op)
#undef TARGET_NEW_ADDRESS_PROFITABLE_P
#define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
+#undef TARGET_ASAN_SHADOW_OFFSET
+#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 24c37f655c8..39c596b647a 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -12078,7 +12078,8 @@ is zero, which disables this optimization.
@deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_ASAN_SHADOW_OFFSET
(void)
Return the offset bitwise ored into shifted address to get corresponding
Address Sanitizer shadow memory address. NULL if Address Sanitizer is not
-supported by the target.
+supported by the target. May return 0 if Address Sanitizer is not supported
+by a subtarget.
@end deftypefn
@deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK
(unsigned HOST_WIDE_INT @var{val})
diff --git a/gcc/target.def b/gcc/target.def
index ed2da154e30..268b56b6ebd 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -4452,7 +4452,8 @@ DEFHOOK
(asan_shadow_offset,
"Return the offset bitwise ored into shifted address to get corresponding\n\
Address Sanitizer shadow memory address. NULL if Address Sanitizer is not\n\
-supported by the target.",
+supported by the target. May return 0 if Address Sanitizer is not supported\n\
+by a subtarget.",
unsigned HOST_WIDE_INT, (void),
NULL)
diff --git a/gcc/toplev.c b/gcc/toplev.c
index 20e231f4d2a..cf89598252c 100644
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -1834,7 +1834,8 @@ process_options (void)
}
if ((flag_sanitize & SANITIZE_USER_ADDRESS)
- &&
回复：[RISC-V] Add support for AddressSanitizer on RISC-V GCC
Hi Palmer,
The 64-bit RISC-V Linux port has a minimum of 39-bit virtual addresses, so it
should be 1<<36 for 64-bit targets. In the implementation of address sanitizer,
we need a shadow memory that is 1/8th of the memory size, which is
where the 36 comes from. I don't think the choice of this value is arbitrary.
Jun
--
发件人：Palmer Dabbelt
发送时间：2020年8月21日(星期五) 00:04
收件人：gcc-patches
抄 送：Kito Cheng ; Andrew Waterman ;
gcc-patches ; cooper.joshua
主 题：Re: [RISC-V] Add support for AddressSanitizer on RISC-V GCC
On Wed, 19 Aug 2020 02:25:37 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> Hi Andrew:
>
> I am not sure the reason why some targets pick different numbers.
> It seems it's not only target dependent but also OS dependent[1].
>
> For RV32, I think using 1<<29 like other 32 bit targets is fine.
>
> [1]
> https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/asan/asan_mapping.h#L159
>
> Hi Joshua:
>
> Could you update that for RV32, and this patch will be pending until
> LLVM accepts the libsanitizer part.
This is ABI, and Linux only supports kasan on rv64 right now so it's
technically undefined. It's probably best to avoid picking an arbitrary number
for rv32, as we still have some open questions WRT the kernel memory map over
there. I doubt that will get sorted out for a while, as the rv32 doesn't get a
lot of attention (though hopefully the glibc stuff will help out).
> On Wed, Aug 19, 2020 at 4:48 PM Andrew Waterman wrote:
>>
>> I'm having trouble understanding why different ports chose their
>> various constants--e.g., SPARC uses 1<<29 for 32-bit and 1<<43 for
>> 64-bit, whereas x86 uses 1<<29 and 0x7fff8000, respectively. So I
>> can't comment on the choice of the constant 1<<36 for RISC-V. But
>> isn't it a problem that 1<<36 is not a valid Pmode value for ILP32?
This is for kasan (not regular asan), which requires some coordination between
the kernel's memory map and the compiler's inline address sanitizer (as you
can't just pick your own memory map). Essentially what's going on is that
there's an array of valid tags associated with each address, which is checked
in-line by the compiler for performance reasons (IIRC it used to be library
routines). The compiler needs to know how to map between addresses and tags,
which depends on the kernel's memory map -- essentially baking the kernel's
memory map into the compiler. That's why the constants seem somewhat
arbitrary.
In order to save memory there's some lossyness in the address->tag mapping.
Most 32-bit ports pick a tag array that's 1/8th of the memory size, which is
where the 29 comes from. I don't see any reason why that wouldn't be workable
on rv32, but it seems better to make sure that's the case rather than just
making up an ABI :)
>> On Wed, Aug 19, 2020 at 1:02 AM Joshua via Gcc-patches
>> wrote:
>> >
>> > From: cooper.joshua
>> >
>> > gcc/
>> >
>> > * config/riscv/riscv.c (asan_shadow_offset): Implement the offset
>> > of asan shadow memory for risc-v.
>> > (asan_shadow_offset): new macro definition.
>> > ---
>> >
>> > gcc/config/riscv/riscv.c | 11 +++
>> > 1 file changed, 11 insertions(+)
>> >
>> > diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
>> > index 63b0c38..b85b459 100644
>> > --- a/gcc/config/riscv/riscv.c
>> > +++ b/gcc/config/riscv/riscv.c
>> > @@ -5292,6 +5292,14 @@ riscv_gpr_save_operation_p (rtx op)
>> >return true;
>> > }
>> >
>> > +/* Implement TARGET_ASAN_SHADOW_OFFSET. */
>> > +
>> > +static unsigned HOST_WIDE_INT
>> > +riscv_asan_shadow_offset (void)
>> > +{
>> > + return HOST_WIDE_INT_1U << 36;
>> > +}
>> > +
>> > /* Initialize the GCC target structure. */
>> > #undef TARGET_ASM_ALIGNED_HI_OP
>> > #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
>> > @@ -5475,6 +5483,9 @@ riscv_gpr_save_operation_p (rtx op)
>> > #undef TARGET_NEW_ADDRESS_PROFITABLE_P
>> > #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
>> >
>> > +#undef TARGET_ASAN_SHADOW_OFFSET
>> > +#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
>> > +
>> > struct gcc_target targetm = TARGET_INITIALIZER;
>> >
>> > #include "gt-riscv.h"
>> > --
>> > 2.7.4
>> >
[RISC-V] Add support for AddressSanitizer on RISC-V GCC
From: cooper.joshua
gcc/
* config/riscv/riscv.c (asan_shadow_offset): Implement the offset of
asan shadow memory for risc-v.
(asan_shadow_offset): new macro definition.
---
gcc/config/riscv/riscv.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 63b0c38..b85b459 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5292,6 +5292,14 @@ riscv_gpr_save_operation_p (rtx op)
return true;
}
+/* Implement TARGET_ASAN_SHADOW_OFFSET. */
+
+static unsigned HOST_WIDE_INT
+riscv_asan_shadow_offset (void)
+{
+ return HOST_WIDE_INT_1U << 36;
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5475,6 +5483,9 @@ riscv_gpr_save_operation_p (rtx op)
#undef TARGET_NEW_ADDRESS_PROFITABLE_P
#define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
+#undef TARGET_ASAN_SHADOW_OFFSET
+#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
--
2.7.4
[RISC-V] Add support for AddressSanitizer on RISC-V GCC
From: cooper.joshua
gcc/
* config/riscv/riscv.c (asan_shadow_offset): Implement the offset of
asan shadow memory for risc-v.
(asan_shadow_offset): new macro definition.
libsanitizer/
* sanitizer_common/sanitizer_common.h (ModuleArch): New enumerator.
(ModuleArchToString): New architecture option.
* sanitizer_common/sanitizer_platform.h: New macro definition.
* sanitizer_common/sanitizer_symbolizer_libcdep.cpp (GetArgV): New
architecture option.
---
gcc/config/riscv/riscv.c | 11 +++
libsanitizer/sanitizer_common/sanitizer_common.h | 5 -
libsanitizer/sanitizer_common/sanitizer_platform.h| 6 ++
.../sanitizer_common/sanitizer_symbolizer_libcdep.cpp | 2 ++
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index bfb3885..05669c2 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5245,6 +5245,14 @@ riscv_gpr_save_operation_p (rtx op)linux.alibaba
return true;
}
+/* Implement TARGET_ASAN_SHADOW_OFFSET. */
+
+static unsigned HOST_WIDE_INT
+riscv_asan_shadow_offset (void)
+{
+ return HOST_WIDE_INT_UC (0x1000);
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5428,6 +5436,9 @@ riscv_gpr_save_operation_p (rtx op)
#undef TARGET_NEW_ADDRESS_PROFITABLE_P
#define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
+#undef TARGET_ASAN_SHADOW_OFFSET
+#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
diff --git a/libsanitizer/sanitizer_common/sanitizer_common.h
b/libsanitizer/sanitizer_common/sanitizer_common.h
index ac16e0e..ea7dff7 100644
--- a/libsanitizer/sanitizer_common/sanitizer_common.h
+++ b/libsanitizer/sanitizer_common/sanitizer_common.h
@@ -649,7 +649,8 @@ enum ModuleArch {
kModuleArchARMV7,
kModuleArchARMV7S,
kModuleArchARMV7K,
- kModuleArchARM64
+ kModuleArchARM64,
+ kModuleArchRISCV
};
// Opens the file 'file_name" and reads up to 'max_len' bytes.
@@ -693,6 +694,8 @@ inline const char *ModuleArchToString(ModuleArch arch) {
return "armv7k";
case kModuleArchARM64:
return "arm64";
+case kModuleArchRISCV:
+ return "riscv";
}
CHECK(0 && "Invalid module arch");
return "";
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform.h
b/libsanitizer/sanitizer_common/sanitizer_platform.h
index c68bfa2..bf52490 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform.h
+++ b/libsanitizer/sanitizer_common/sanitizer_platform.h
@@ -126,6 +126,12 @@
# define FIRST_32_SECOND_64(a, b) (a)
#endif
+#if defined(__riscv__)
+# define SANITIZER_RISCV 1
+#else
+# define SANITIZER_RISCV 0
+#endif
+
#if defined(__x86_64__) && !defined(_LP64)
# define SANITIZER_X32 1
#else
diff --git a/libsanitizer/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
b/libsanitizer/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
index 490c6fe..408f57d 100644
--- a/libsanitizer/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
+++ b/libsanitizer/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
@@ -270,6 +270,8 @@ class LLVMSymbolizerProcess : public SymbolizerProcess {
const char* const kSymbolizerArch = "--default-arch=s390x";
#elif defined(__s390__)
const char* const kSymbolizerArch = "--default-arch=s390";
+#elif defined(__riscv__)
+const char* const kSymbolizerArch = "--default-arch=riscv";
#else
const char* const kSymbolizerArch = "--default-arch=unknown";
#endif
--
2.7.4
