Re: [PATCHv2][ARM] -mpure-code option for ARM

[mickael guene]

Hi Andre,

 I can't see new testsuite files in trunk :
gcc.target/arm/pure-code/ffunction-sections.c
gcc.target/arm/pure-code/no-literal-pool.c
gcc.target/arm/pure-code/pure-code.exp

 It seems you forgot to include them in your patch.
Can you post a new one with those files ?

Regards
Mickael

On 09/23/2016 05:04 PM, Sandra Loosemore wrote:

On 09/23/2016 04:39 AM, Andre Vieira (lists) wrote:

Hi Sandra,

Is this better?

Cheers,
Andre

gcc/ChangeLog
2016-09-23  Andre Vieira  

 * target.def(elf_flags_numeric): Change documentation to
 present tense.


And here is the patch with the tm.texi regeneration.

Cheers,
Andre

gcc/ChangeLog
2016-09-23  Andre Vieira  

 * target.def(elf_flags_numeric): Change documentation to
 present tense.
 * doc/tm.texi: Regenerate.



This looks good to me.  Thanks.

-Sandra the grammar geek

Re: [PATCH][ARM] -mpure-code option for ARM

[mickael guene]

Hi Andre,

 Another feedback on your purecode patch.
 You have to disable casesi pattern since then it will
generate wrong code with -mpure-code option.
 Indeed it will generate an 'adr rx, .Lx' (aka
'subs rx, PC, #offset') which will not work in our
case since 'Lx' label is put in an .rodata section.
So offset value is unknown and can be impossible
to encode correctly.

Regards
Mickael

On 06/30/2016 04:32 PM, Andre Vieira (lists) wrote:

Hello,

This patch adds the -mpure-code option for ARM. This option ensures
functions are put into sections that contain only code and no data. To
ensure this throughout compilation we give these sections the ARM
processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
is only supported for non-pic code for armv7-m targets.

This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
This target hook enables a target to use the numeric value for elf
section attributes rather than their alphabetical representation. If
TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
'default_elf_asm_named_section', will print the numeric value of the
section attributes for the current section. This target hook has two
parameters:
unsigned int FLAGS, the input parameter that tells the function the
current section's attributes;
unsigned int *NUM, used to pass down the numerical representation of the
section's attributes.

The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
false, so existing behavior is not changed.

Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
arm-none-eabi with a Cortex-M3 target.


gcc/ChangeLog:
2016-06-30  Andre Vieira  
Terry Guo  

* target.def (elf_flags_numeric): New target hook.
* targhooks.h (default_asm_elf_flags_numeric): New.
* varasm.c (default_asm_elf_flags_numeric): New.
  (default_elf_asm_named_section): Use new target hook.
* config/arm/arm.opt (mpure-code): New.
* config/arm/arm.h (SECTION_ARM_PURECODE): New.
* config/arm/arm.c (arm_asm_init_sections): Add section
  attribute to default text section if -mpure-code.
  (arm_option_check_internal): Diagnose use of option with
  non supported targets and/or options.
  (arm_asm_elf_flags_numeric): New.
  (arm_function_section): New.
  (arm_elf_section_type_flags): New.
* config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
  for -mpure-code.
* gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
* gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.



gcc/testsuite/ChangeLog:
2016-06-30  Andre Vieira  
Terry Guo  

* gcc.target/arm/pure-code/ffunction-sections.c: New.
* gcc.target/arm/pure-code/no-literal-pool.c: New.
* gcc.target/arm/pure-code/pure-code.exp: New.

Re: [PATCH][ARM] -mpure-code option for ARM

[mickael guene]

Hi Andre,

 I think you have a typo in your patch. I need to change :
+text_section->unnamed.data = "\t.section 
.text,\"0x2006\",%%progbits";


into
+text_section->unnamed.data = "\t.section 
.text,\"0x2006\",%progbits";


to make it works.

Regards
Mickael

On 06/30/2016 04:32 PM, Andre Vieira (lists) wrote:

Hello,

This patch adds the -mpure-code option for ARM. This option ensures
functions are put into sections that contain only code and no data. To
ensure this throughout compilation we give these sections the ARM
processor-specific ELF section attribute "SHF_ARM_PURECODE". This option
is only supported for non-pic code for armv7-m targets.

This patch introduces a new target hook 'TARGET_ASM_ELF_FLAGS_NUMERIC'.
This target hook enables a target to use the numeric value for elf
section attributes rather than their alphabetical representation. If
TARGET_ASM_ELF_FLAGS_NUMERIC returns TRUE, the existing
'default_elf_asm_named_section', will print the numeric value of the
section attributes for the current section. This target hook has two
parameters:
unsigned int FLAGS, the input parameter that tells the function the
current section's attributes;
unsigned int *NUM, used to pass down the numerical representation of the
section's attributes.

The default implementation for TARGET_ASM_ELF_FLAGS_NUMERIC will return
false, so existing behavior is not changed.

Bootstrapped and tested for arm-none-linux-gnueabihf. Further tested for
arm-none-eabi with a Cortex-M3 target.


gcc/ChangeLog:
2016-06-30  Andre Vieira  
Terry Guo  

* target.def (elf_flags_numeric): New target hook.
* targhooks.h (default_asm_elf_flags_numeric): New.
* varasm.c (default_asm_elf_flags_numeric): New.
  (default_elf_asm_named_section): Use new target hook.
* config/arm/arm.opt (mpure-code): New.
* config/arm/arm.h (SECTION_ARM_PURECODE): New.
* config/arm/arm.c (arm_asm_init_sections): Add section
  attribute to default text section if -mpure-code.
  (arm_option_check_internal): Diagnose use of option with
  non supported targets and/or options.
  (arm_asm_elf_flags_numeric): New.
  (arm_function_section): New.
  (arm_elf_section_type_flags): New.
* config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Disable
  for -mpure-code.
* gcc/doc/texi (TARGET_ASM_ELF_FLAGS_NUMERIC): New.
* gcc/doc/texi.in (TARGET_ASM_ELF_FLAGS_NUMERIC): Likewise.



gcc/testsuite/ChangeLog:
2016-06-30  Andre Vieira  
Terry Guo  

* gcc.target/arm/pure-code/ffunction-sections.c: New.
* gcc.target/arm/pure-code/no-literal-pool.c: New.
* gcc.target/arm/pure-code/pure-code.exp: New.

Re: [PING] Add new mexecute-only arm option.

[mickael guene]

Hi Sandra,

 Thanks for your feedback.

On 02/02/2016 08:57 PM, Sandra Loosemore wrote:
> On 02/02/2016 02:06 AM, mickael guene wrote:
>> Hi All,
>>
>>Ping for following thread :
>>
>> https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01968.html
>> https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01969.html
>> https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01970.html
>
> Two comments:
>
> (1) MIPS has had a similar option for quite some time called
> -mcode-readable=.  It might be less confusing to use a similar name for
> the ARM option with the similar reversed sense to -mexecute-only, even
> if it doesn't need to be a tristate flag like for MIPS.
 I was unaware of this MIPS option. But anyway I would rather prefer to
stick with -mexecute-only since it's very similar to armcc option naming
for the same feature (--execute_only).

> (2) I suggest changing the help string for the command line option
>
>> +
>> +mexecute-only
>> +Target Report Var(target_execute_only) Init(0)
>> +Forbid load into text sections.
>
> to use the same wording as the documentation in the manual:
>
>> +@item -mexecute-only
>> +@opindex mexecute-only
>> +Disable read memory access inside code sections.  Only code fetching is
>> +allowed.
>> +This option is off by default.
>> +
>
> Or at least, "load into text sections" is confusing.  (You load *from*
> the text section, not *into* it, right?)

 You're right. I will reuse documentation sentence.

Regards
Mickael

[PING] Add new mexecute-only arm option.

[mickael guene]

Hi All,

 Ping for following thread :

https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01968.html
https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01969.html
https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01970.html

Thanks
Mickael

[PATCH ARM 2/2] Add -mexecute-only option.

[Mickael Guene]

gcc/ChangeLog:

* config/arm/arm-protos.h (arm_modes_tieable_p): New.
* config/arm/arm.c (arm_function_section): New.
(arm_section_type_flags): New.
(TARGET_ASM_FUNCTION_SECTION): Define.
(TARGET_SECTION_TYPE_FLAGS): Define.
(arm_option_override): Add mexecute-only new option.
(thumb1_gen_const_int): New.
(thumb1_legitimate_address_p): Disallow constant pool usage for thumb1
for arm_disable_literal_pool.
(thumb1_rtx_costs): Update cost for arm_disable_literal_pool.
(thumb1_size_rtx_costs): Likewise.
(arm_output_mi_thunk): Avoid literal usage for target_execute_only.
* config/arm/arm.md (casesi): Disable for target_execute_only.
* config/arm/arm.opt (target_execute_only): New option.
* config/arm/thumb1.md (define_insn "thumb1_movsi_symbol_ref"): New.
(define_insn "*thumb1_movsi_const_int"): New.
(define_split for generate integer constant): New.
(define_insn "*thumb1_movsi_insn"): Set use_literal_pool attribute so
it's enabled/disabled according to arm_disable_literal_pool.
(define_expand "tablejump"): Disable for target_execute_only.
* doc/invoke.texi (mexecute-only): New.

gcc/testsuite/ChangeLog:

* gcc.target/arm/thumb1-execute-only-switch.c: New.
* gcc.target/arm/thumb1-execute-only.c: New.
* gcc.target/arm/thumb2-execute-only-switch.c: New.
* gcc.target/arm/thumb2-execute-only.c: New.

 This option generate code that don't load no data from text section.
---
 gcc/config/arm/arm-protos.h|   1 +
 gcc/config/arm/arm.c   | 114 +++--
 gcc/config/arm/arm.md  |   2 +-
 gcc/config/arm/arm.opt |   4 +
 gcc/config/arm/thumb1.md   |  71 +++--
 gcc/doc/invoke.texi|   7 ++
 .../gcc.target/arm/thumb1-execute-only-switch.c|  23 +
 gcc/testsuite/gcc.target/arm/thumb1-execute-only.c |  69 +
 .../gcc.target/arm/thumb2-execute-only-switch.c|  23 +
 gcc/testsuite/gcc.target/arm/thumb2-execute-only.c |  68 
 10 files changed, 368 insertions(+), 14 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb1-execute-only-switch.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb1-execute-only.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-execute-only-switch.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-execute-only.c

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 28f2263..e08842e 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -59,6 +59,7 @@ extern bool arm_modes_tieable_p (machine_mode, machine_mode);
 extern int const_ok_for_arm (HOST_WIDE_INT);
 extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
 extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
+extern void thumb1_gen_const_int (rtx, HOST_WIDE_INT);
 extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
   HOST_WIDE_INT, rtx, rtx, int);
 extern int legitimate_pic_operand_p (rtx);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f152afa..fe8e018 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -300,6 +300,12 @@ static void arm_canonicalize_comparison (int *code, rtx 
*op0, rtx *op1,
 static unsigned HOST_WIDE_INT arm_asan_shadow_offset (void);
 
 static void arm_sched_fusion_priority (rtx_insn *, int, int *, int*);
+
+static section *arm_function_section (tree decl, enum node_frequency freq,
+ bool startup, bool exit);
+
+static unsigned int arm_section_type_flags (tree, const char *, int);
+
 
 /* Table of machine attributes.  */
 static const struct attribute_spec arm_attribute_table[] =
@@ -735,6 +741,12 @@ static const struct attribute_spec arm_attribute_table[] =
 #undef TARGET_SCHED_FUSION_PRIORITY
 #define TARGET_SCHED_FUSION_PRIORITY arm_sched_fusion_priority
 
+#undef  TARGET_ASM_FUNCTION_SECTION
+#define TARGET_ASM_FUNCTION_SECTION arm_function_section
+
+#undef  TARGET_SECTION_TYPE_FLAGS
+#define TARGET_SECTION_TYPE_FLAGS arm_section_type_flags
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 /* Obstack for minipool constant handling.  */
@@ -3428,6 +3440,15 @@ arm_option_override (void)
   if (target_slow_flash_data)
 arm_disable_literal_pool = true;
 
+  /* We only support -mexecute-only on M-profile targets.  */
+  if (target_execute_only && (flag_pic || !(!arm_arch_notm || arm_arch7em)))
+error ("-mexecute-only only supports non-pic code on M-profile targets");
+
+  /* In execute-only mode we don't want any memory read into text section and
+ so we disable literal pool.  */
+  if (target_execute_only)
+arm_disable_literal_pool = true;
+
   /* Disable scheduling fusion by default if it's not 

[PATCH ARM 1/2] Add support for section attribute letter 'y' when available

[Mickael Guene]

gcc/ChangeLog:

* configure.ac: Add detection of letter y support in assembler.
* config.in: Regenerate.
* configure: Regenerate.
* output.h (SECTION_NOREAD): Add new bit flag.
* varasm.c (default_elf_asm_named_section): Set y letter when we detect
SECTION_NOREAD.
---
 gcc/config.in|  6 ++
 gcc/configure| 34 +-
 gcc/configure.ac |  6 ++
 gcc/output.h |  3 ++-
 gcc/varasm.c |  6 +-
 5 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/gcc/config.in b/gcc/config.in
index 1796e1d..2aa2d1a 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -1266,6 +1266,12 @@
 #endif
 
 
+/* Define if your assembler supports specifying the section flag y. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_GAS_SECTION_NOREAD
+#endif
+
+
 /* Define 0/1 if your assembler supports marking sections with SHF_MERGE flag.
*/
 #ifndef USED_FOR_TARGET
diff --git a/gcc/configure b/gcc/configure
index ff646e8..e543732 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -22365,7 +22365,6 @@ else
 $as_echo "$gcc_cv_readelf" >&6; }
 fi
 
-# Figure out what assembler alignment features are present.
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler flags" >&5
 $as_echo_n "checking assembler flags... " >&6; }
 if test "${gcc_cv_as_flags+set}" = set; then :
@@ -22392,6 +22391,39 @@ fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_flags" >&5
 $as_echo "$gcc_cv_as_flags" >&6; }
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .section with 
y" >&5
+$as_echo_n "checking assembler for .section with y... " >&6; }
+if test "${gcc_cv_as_section_has_y+set}" = set; then :
+  $as_echo_n "(cached) " >&6
+else
+  gcc_cv_as_section_has_y=no
+  if test x$gcc_cv_as != x; then
+$as_echo '.section foo1,"y"
+.byte 0,0,0,0' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags  -o conftest.o conftest.s >&5'
+  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }
+then
+   gcc_cv_as_section_has_y=yes
+else
+  echo "configure: failed program was" >&5
+  cat conftest.s >&5
+fi
+rm -f conftest.o conftest.s
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_section_has_y" >&5
+$as_echo "$gcc_cv_as_section_has_y" >&6; }
+if test $gcc_cv_as_section_has_y = yes; then
+
+$as_echo "#define HAVE_GAS_SECTION_NOREAD 1" >>confdefs.h
+
+fi
+
+# Figure out what assembler alignment features are present.
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .balign and 
.p2align" >&5
 $as_echo_n "checking assembler for .balign and .p2align... " >&6; }
 if test "${gcc_cv_as_balign_and_p2align+set}" = set; then :
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 4dc7c10..d1717bf 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -2446,6 +2446,12 @@ else
AC_MSG_RESULT($gcc_cv_readelf)
 fi
 
+gcc_GAS_CHECK_FEATURE([.section with y], gcc_cv_as_section_has_y,,,
+[.section foo1,"y"
+.byte 0,0,0,0],,
+[AC_DEFINE(HAVE_GAS_SECTION_NOREAD, 1,
+  [Define if your assembler supports specifying the section flag y.])])
+
 # Figure out what assembler alignment features are present.
 gcc_GAS_CHECK_FEATURE([.balign and .p2align], gcc_cv_as_balign_and_p2align,
  [2,6,0],,
diff --git a/gcc/output.h b/gcc/output.h
index 0924499..1df3088 100644
--- a/gcc/output.h
+++ b/gcc/output.h
@@ -381,7 +381,8 @@ extern void no_asm_to_stream (FILE *);
 #define SECTION_COMMON   0x80  /* contains common data */
 #define SECTION_RELRO   0x100  /* data is readonly after relocation 
processing */
 #define SECTION_EXCLUDE  0x200 /* discarded by the linker */
-#define SECTION_MACH_DEP 0x400 /* subsequent bits reserved for target 
*/
+#define SECTION_NOREAD   0x400 /* section cannot be read but can be 
executed */
+#define SECTION_MACH_DEP 0x800 /* subsequent bits reserved for target 
*/
 
 /* This SECTION_STYLE is used for unnamed sections that we can switch
to using a special assembler directive.  */
diff --git a/gcc/varasm.c b/gcc/varasm.c
index 3a3573e..c0499b1 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -6233,7 +6233,7 @@ void
 default_elf_asm_named_section (const char *name, unsigned int flags,
   tree decl)
 {
-  char flagchars[10], *f = flagchars;
+  char flagchars[11], *f = flagchars;
 
   /* If we have already declared this section, we can use an
  abbreviated form to switch back to it -- unless this section is
@@ -6266,6 +6266,10 @@ default_elf_asm_named_section (const char *name, 
unsigned int flags,
 *f++ = TLS_SECTION_ASM_FLAG;
   if (HAVE_COMDAT_GROUP && (flags & SECTION_LINKONCE))
 *f++ = 'G';
+#if defined (HAVE_GAS_SECTION_NOREAD) && HAVE_GAS_SECTION_NOREAD == 1
+  if (flags & SECTION_NOREAD)
+*f++ = 'y';
+#endif
   *f = '\0';
 

[PATCH ARM 0/2] Add new mexecute-only arm option.

[Mickael Guene]

 Hi everybody,

  This is a proposal for a patch set that adds a new -mexecute-only arm
option for profile M targets.
  Some STM32 MCUs implement a security feature called 'Proprietary Code
Read-Out Protection' aka PCROP that forbids data read access to some
code areas (only fetch access is allowed).
This protection prevents usage of literal pools (since one cannot load
data from code sections), so compilers have to use a specific code
sequence to generate constants.
 The first patch adds generic support for the new binutils section letter
'y' that allows to specify a section as being no-readable.
 The second patch adds the new -mexecute-only arm option. This option disables
all memory read inside text section, and takes care to emit the corresponding
code in 'y' sections.

 Unit tests have been written to check for correct code generation.

 No regressions have been observed for aarch64-none-elf, aarch64-none-linux-gnu,
aarch64_be-none-elf, arm-none-eabi, arm-none-linux-gnueabi,
arm-none-linux-gnueabihf and armeb-none-linux-gnueabihf.

Mickael Guene (2):
  Add support for section attribute letter 'y' when available
  Add -mexecute-only option.

 gcc/config.in  |   6 ++
 gcc/config/arm/arm-protos.h|   1 +
 gcc/config/arm/arm.c   | 114 +++--
 gcc/config/arm/arm.md  |   2 +-
 gcc/config/arm/arm.opt |   4 +
 gcc/config/arm/thumb1.md   |  71 +++--
 gcc/configure  |  34 +-
 gcc/configure.ac   |   6 ++
 gcc/doc/invoke.texi|   7 ++
 gcc/output.h   |   3 +-
 .../gcc.target/arm/thumb1-execute-only-switch.c|  23 +
 gcc/testsuite/gcc.target/arm/thumb1-execute-only.c |  69 +
 .../gcc.target/arm/thumb2-execute-only-switch.c|  23 +
 gcc/testsuite/gcc.target/arm/thumb2-execute-only.c |  68 
 gcc/varasm.c   |   6 +-
 15 files changed, 420 insertions(+), 17 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb1-execute-only-switch.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb1-execute-only.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-execute-only-switch.c
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb2-execute-only.c

-- 
2.7.0.rc3

[PATCH] : Fix negative value in TEST_BIT from mem_overlaps_already_clobbered_arg_p()

[mickael guene]

Hi all,

 After applying patch from 
http://gcc.gnu.org/ml/gcc-patches/2012-02/msg00228.html we can
have a negative value in call to TEST_BIT() macro in 
mem_overlaps_already_clobbered_arg_p() function
for stored_args_map bitmap table.
 This can lead to reject a valid tail call optimization.

 This patch will ensure that i+k is positive before calling TEST_BIT() macro.

2012-03-12  Mickael Guene  mickael.gu...@st.com

* calls.c (mem_overlaps_already_clobbered_arg_p): Don't call TEST_BIT 
for
negative value.

Regards

Mickael
--- a/gcc/calls.c	2012-03-12 10:44:27.0 +0100
+++ b/gcc/calls.c	2012-03-12 10:46:16.0 +0100
@@ -1822,7 +1822,8 @@
   unsigned HOST_WIDE_INT k;
 
   for (k = 0; k  size; k++)
-	if (i + k  stored_args_map-n_bits
+	if (i + k = 0
+	 i + k  stored_args_map-n_bits
 	 TEST_BIT (stored_args_map, i + k))
 	  return true;
 }