[PATCH V2] RISC-V: Fix missing boolean_expression in zmmul extension

[Liao Shihua]

Update v1->v2
Add testcase for this patch.

Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() cause different 
instructions when 
multiplying an integer with a constant. ( 
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )

int foo(int *ib) {
*ib = *ib * 33938;
return 0;
}

rv64im:
lw  a4,0(a1)
li  a5,32768
addiw   a5,a5,1170
mulwa5,a5,a4
sw  a5,0(a1)
ret

rv64i_zmmul:
lw  a4,0(a1)
slliw   a5,a4,5
addwa5,a5,a4
slliw   a5,a5,3
addwa5,a5,a4
slliw   a5,a5,3
addwa5,a5,a4
slliw   a5,a5,3
addwa5,a5,a4
slliw   a5,a5,1
sw  a5,0(a1)
ret

Fixed.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zmmul-3.c: New test.

---
 gcc/config/riscv/riscv.cc| 2 +-
 gcc/testsuite/gcc.target/riscv/zmmul-3.c | 8 
 2 files changed, 9 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-3.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 85df5b7ab49..580ae007181 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3753,7 +3753,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
 case MULT:
   if (float_mode_p)
*total = tune_param->fp_mul[mode == DFmode];
-  else if (!TARGET_MUL)
+  else if (!(TARGET_MUL || TARGET_ZMMUL))
/* Estimate the cost of a library call.  */
*total = COSTS_N_INSNS (speed ? 32 : 6);
   else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-3.c 
b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
new file mode 100644
index 000..ae9752462e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64iafdc_zmmul -mabi=lp64d" } */
+int foo1(int a)
+{
+return a * 99;
+}
+
+/* { dg-final { scan-assembler-times "mulw\t" 1 } } */
\ No newline at end of file
-- 
2.34.1

[PATCH] RISC-V: Fix missing boolean_expression in zmmul extension

[Liao Shihua]

Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() casuse different 
instructions when multiplying an integer with a constant.
( https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )

int foo(int *ib) {
*ib = *ib * 33938;
return 0;
}

rv64im:
lw  a4,0(a1)
li  a5,32768
addiw   a5,a5,1170
mulwa5,a5,a4
sw  a5,0(a1)
ret

rv64i_zmmul:
lw  a4,0(a1)
slliw   a5,a4,5
addwa5,a5,a4
slliw   a5,a5,3
addwa5,a5,a4
slliw   a5,a5,3
addwa5,a5,a4
slliw   a5,a5,3
addwa5,a5,a4
slliw   a5,a5,1
sw  a5,0(a1)
ret

Fixed.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.

---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 85df5b7ab49..580ae007181 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3753,7 +3753,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
 case MULT:
   if (float_mode_p)
*total = tune_param->fp_mul[mode == DFmode];
-  else if (!TARGET_MUL)
+  else if (!(TARGET_MUL || TARGET_ZMMUL))
/* Estimate the cost of a library call.  */
*total = COSTS_N_INSNS (speed ? 32 : 6);
   else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
-- 
2.34.1

[PATCH v4 3/3] RISC-V: Add C intrinsic for Scalar Bitmanip Extension

[Liao Shihua]

This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi, 
clmul_si, 
brev8_si are both included in rv32 and rv64. Test them in 
scalar_bitmanip_intrinsic-64-emulated.c.

gcc/ChangeLog:

* config.gcc: Include riscv_bitmanip.h.
* config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and 
clmul pattern.
* config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
* config/riscv/riscv-builtins.cc (AVAIL): New AVAIL.
(RISCV_BUILTIN_NO_PREFIX): New riscv_builtin_description.
* config/riscv/riscv-cmo.def (RISCV_BUILTIN): New builtins.
* config/riscv/riscv-ftypes.def (2): New ftypes.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
(RISCV_BUILTIN_NO_PREFIX): Ditto.
* config/riscv/riscv_bitmanip.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_bitmanip_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c: New test.
* gcc.target/riscv/scalar_bitmanip_intrinsic-64.c: New test.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  10 +-
 gcc/config/riscv/crypto.md|   4 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-cmo.def|  12 +-
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  22 +-
 gcc/config/riscv/riscv_bitmanip.h | 297 ++
 .../riscv/scalar_bitmanip_intrinsic-32.c  |  97 ++
 .../scalar_bitmanip_intrinsic-64-emulated.c   |  33 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c  | 115 +++
 11 files changed, 600 insertions(+), 16 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 11c3a647b5e..00355509c92 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h riscv_crypto.h"
+   extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index fdab0017a2b..ccda25c01c1 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -443,8 +443,8 @@
 ;; orc.b (or-combine) is added as an unspec for the benefit of the support
 ;; for optimized string functions (such as strcmp).
 (define_insn "orcb2"
-  [(set (match_operand:X 0 "register_operand" "=r")
-   (unspec:X [(match_operand:X 1 "register_operand" "r")] UNSPEC_ORC_B))]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+   (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")] 
UNSPEC_ORC_B))]
   "TARGET_ZBB"
   "orc.b\t%0,%1"
   [(set_attr "type" "bitmanip")])
@@ -852,9 +852,9 @@
 
 ;; ZBKC or ZBC extension
 (define_insn "riscv_clmul_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")
-  (match_operand:X 2 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
+  (match_operand:GPR 2 "register_operand" "r")]
   UNSPEC_CLMUL))]
   "TARGET_ZBKC || TARGET_ZBC"
   "clmul\t%0,%1,%2"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index bf613fca056..dd2bc94ee88 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -72,8 +72,8 @@
 
 ;; ZBKB extension
 (define_insn "riscv_brev8_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")]
   UNSPEC_BREV8))]
   "TARGET_ZBKB"
   "brev8\t%0,%1"
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index e85169374eb..1932ff069c6 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -105,6 +105,7 @@ AVAIL (zero32,  

[PATCH v4 2/3] RISC-V: Add C intrinsic for Scalar Crypto Extension

[Liao Shihua]

This patch adds C intrinsics for Scalar Crypto Extension.

gcc/ChangeLog:

* config.gcc: Include riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_crypto_intrinsic-64.c: New test.
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv_crypto.h   | 309 ++
 .../riscv/scalar_crypto_intrinsic-32.c| 115 +++
 .../riscv/scalar_crypto_intrinsic-64.c| 123 +++
 4 files changed, 548 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index d17787bc9ad..11c3a647b5e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 000..1bfe3d7c675
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,309 @@
+/* RISC-V 'Scalar Crypto' Extension intrinsics include file.
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef __RISCV_SCALAR_CRYPTO_H
+#define __RISCV_SCALAR_CRYPTO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__riscv_zknd)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsi (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsmi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsmi (rs1,rs2,bs);
+}
+
+#else
+#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi (x, y, bs)
+#define __riscv_aes32dsmi(x, y, bs) __builtin_riscv_aes32dsmi (x, y, bs)
+#endif
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ds (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64ds (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64dsm (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64dsm (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64im (uint64_t rs1)
+{
+  return __builtin_riscv_aes64im (rs1);
+}
+#endif
+#endif // __riscv_zknd
+
+#if (defined (__riscv_zknd) || defined (__riscv_zkne)) && (__riscv_xlen == 64)
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks1i (uint64_t rs1, const int rnum)
+{
+  return __builtin_riscv_aes64ks1i (rs1,rnum);
+}
+
+#else
+#define __riscv_aes64ks1i(x, rnum) __builtin_riscv_aes64ks1i (x, rnum)
+#endif
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks2 (uint64_t rs1, uint64_t rs2)
+{
+return __builtin_riscv_aes64ks2 (rs1,rs2);
+}
+
+#endif // __riscv_zknd || __riscv_zkne
+
+#if defined (__riscv_zkne)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, 

[PATCH v4 1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites

[Liao Shihua]

The serials patch provides a mapping from the RV intrinsics to the builtin 
names.
There are some duplicates testsuites between intrinsic and built-in function.
Remove the Scalar Bitmanip and Scalar Crypto Built-In function testsuites
that will be included in the intrinsic functions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbb_32_bswap-2.c: Rename to zbb_bswap16.c and only 
test __builtin_bswap16.
* gcc.target/riscv/zbkb32.c: Remove 
__builtin_riscv_(un)zip,__builtin_riscv_brev8.
* gcc.target/riscv/zbkb64.c: Remove __builtin_riscv_brev8.
* gcc.target/riscv/zbb_32_bswap-1.c: Removed.
* gcc.target/riscv/zbb_bswap-1.c: Removed.
* gcc.target/riscv/zbb_bswap-2.c: Removed.
* gcc.target/riscv/zbbw.c: Removed.
* gcc.target/riscv/zbc32.c: Removed.
* gcc.target/riscv/zbc64.c: Removed.
* gcc.target/riscv/zbkc32.c: Removed.
* gcc.target/riscv/zbkc64.c: Removed.
* gcc.target/riscv/zbkx32.c: Removed.
* gcc.target/riscv/zbkx64.c: Removed.
* gcc.target/riscv/zknd32-2.c: Removed.
* gcc.target/riscv/zknd64-2.c: Removed.
* gcc.target/riscv/zkne32-2.c: Removed.
* gcc.target/riscv/zkne64-2.c: Removed.
* gcc.target/riscv/zknh-sha256-32.c: Removed.
* gcc.target/riscv/zknh-sha256-64.c: Removed.
* gcc.target/riscv/zknh-sha512-32.c: Removed.
* gcc.target/riscv/zknh-sha512-64.c: Removed.
* gcc.target/riscv/zksed32-2.c: Removed.
* gcc.target/riscv/zksed64-2.c: Removed.
* gcc.target/riscv/zksh32.c: Removed.
* gcc.target/riscv/zksh64.c: Removed.

---
 .../gcc.target/riscv/zbb_32_bswap-1.c | 11 -
 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c  | 11 -
 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c  | 12 --
 .../riscv/{zbb_32_bswap-2.c => zbb_bswap16.c} |  3 +-
 gcc/testsuite/gcc.target/riscv/zbbw.c | 26 
 gcc/testsuite/gcc.target/riscv/zbc32.c| 23 --
 gcc/testsuite/gcc.target/riscv/zbc64.c| 23 --
 gcc/testsuite/gcc.target/riscv/zbkb32.c   | 18 
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |  5 ---
 gcc/testsuite/gcc.target/riscv/zbkc32.c   | 17 
 gcc/testsuite/gcc.target/riscv/zbkc64.c   | 17 
 gcc/testsuite/gcc.target/riscv/zbkx32.c   | 18 
 gcc/testsuite/gcc.target/riscv/zbkx64.c   | 18 
 gcc/testsuite/gcc.target/riscv/zknd32-2.c | 28 -
 gcc/testsuite/gcc.target/riscv/zknd64-2.c | 42 ---
 gcc/testsuite/gcc.target/riscv/zkne32-2.c | 28 -
 gcc/testsuite/gcc.target/riscv/zkne64-2.c | 34 ---
 .../gcc.target/riscv/zknh-sha256-32.c | 10 -
 .../gcc.target/riscv/zknh-sha256-64.c | 28 -
 .../gcc.target/riscv/zknh-sha512-32.c | 42 ---
 .../gcc.target/riscv/zknh-sha512-64.c | 31 --
 gcc/testsuite/gcc.target/riscv/zksed32-2.c| 29 -
 gcc/testsuite/gcc.target/riscv/zksed64-2.c| 29 -
 gcc/testsuite/gcc.target/riscv/zksh32.c   | 19 -
 gcc/testsuite/gcc.target/riscv/zksh64.c   | 19 -
 25 files changed, 2 insertions(+), 539 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
 rename gcc/testsuite/gcc.target/riscv/{zbb_32_bswap-2.c => zbb_bswap16.c} (59%)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c 
b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
deleted file mode 100644
index 789dda17f05..000
--- a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { 

[PATCH v4 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

[Liao Shihua]

Update v3 -> v4:
  1.Typo fix.
  2.Only test *intrinsic-32 on rv32 and *intrinsic-64 on rv64.
  3.Update Copyright year to 2024.

Update v2 -> v3:
  1. Change pattern mode form X to GPR in orcb, clmul, and brev8.
  2. Add emulated testsuite.
  3. Removed duplicate testsuite between built-in and intrinsic. 
  4. Typo fix.

Update v1 -> v2:
  1. Rename *_intrinsic-* to *_intrinsic-XLEN.
  2. Typo fix.
  3. Intrinsics with immediate arguments will use marcos at O0 .

It's a little patch add just provides a mapping from the RV intrinsics to the 
builtin 
names within GCC.

Liao Shihua (3):
  RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function
testsuites
  RISC-V: Add C intrinsic for Scalar Crypto Extension
  RISC-V: Add C intrinsic for Scalar Bitmanip Extension

 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  10 +-
 gcc/config/riscv/crypto.md|   4 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-cmo.def|  12 +-
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  22 +-
 gcc/config/riscv/riscv_bitmanip.h | 297 +
 gcc/config/riscv/riscv_crypto.h   | 309 ++
 .../riscv/scalar_bitmanip_intrinsic-32.c  |  97 ++
 .../scalar_bitmanip_intrinsic-64-emulated.c   |  33 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c  | 115 +++
 .../riscv/scalar_crypto_intrinsic-32.c| 115 +++
 .../riscv/scalar_crypto_intrinsic-64.c| 123 +++
 .../gcc.target/riscv/zbb_32_bswap-1.c |  11 -
 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c  |  11 -
 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c  |  12 -
 .../riscv/{zbb_32_bswap-2.c => zbb_bswap16.c} |   3 +-
 gcc/testsuite/gcc.target/riscv/zbbw.c |  26 --
 gcc/testsuite/gcc.target/riscv/zbc32.c|  23 --
 gcc/testsuite/gcc.target/riscv/zbc64.c|  23 --
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  18 -
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |   5 -
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |  17 -
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 -
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |  18 -
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 -
 gcc/testsuite/gcc.target/riscv/zknd32-2.c |  28 --
 gcc/testsuite/gcc.target/riscv/zknd64-2.c |  42 ---
 gcc/testsuite/gcc.target/riscv/zkne32-2.c |  28 --
 gcc/testsuite/gcc.target/riscv/zkne64-2.c |  34 --
 .../gcc.target/riscv/zknh-sha256-32.c |  10 -
 .../gcc.target/riscv/zknh-sha256-64.c |  28 --
 .../gcc.target/riscv/zknh-sha512-32.c |  42 ---
 .../gcc.target/riscv/zknh-sha512-64.c |  31 --
 gcc/testsuite/gcc.target/riscv/zksed32-2.c|  29 --
 gcc/testsuite/gcc.target/riscv/zksed64-2.c|  29 --
 gcc/testsuite/gcc.target/riscv/zksh32.c   |  19 --
 gcc/testsuite/gcc.target/riscv/zksh64.c   |  19 --
 39 files changed, 1149 insertions(+), 555 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
 rename gcc/testsuite/gcc.target/riscv/{zbb_32_bswap-2.c => zbb_bswap16.c} (59%)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/z

[PATCH V3 3/3] RISC-V: Add C intrinsic for Scalar Bitmanip Extension

[Liao Shihua]

This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi, 
clmul_si, 
brev8_si are both included in rv32 and rv64. Test them in 
scalar_bitmanip_intrinsic-64-emulated.c.

gcc/ChangeLog:

* config.gcc: Include riscv_bitmanip.h.
* config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and 
clmul pattern.
* config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
* config/riscv/riscv-builtins.cc (AVAIL): New AVAIL.
(RISCV_BUILTIN_NO_PREFIX): New riscv_builtin_description.
* config/riscv/riscv-cmo.def (RISCV_BUILTIN): New builtins.
* config/riscv/riscv-ftypes.def (2): New ftypes.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
(RISCV_BUILTIN_NO_PREFIX): Ditto.
* config/riscv/riscv_bitmanip.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_bitmanip_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c: New test.
* gcc.target/riscv/scalar_bitmanip_intrinsic-64.c: New test.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  10 +-
 gcc/config/riscv/crypto.md|   4 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-cmo.def|  12 +-
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  22 +-
 gcc/config/riscv/riscv_bitmanip.h | 297 ++
 .../riscv/scalar_bitmanip_intrinsic-32.c  |  96 ++
 .../scalar_bitmanip_intrinsic-64-emulated.c   |  32 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c  | 114 +++
 11 files changed, 597 insertions(+), 16 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f8483d34ee9..5999ef5cbc8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h riscv_crypto.h"
+   extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 92bcdc30fe4..23a06514732 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -443,8 +443,8 @@
 ;; orc.b (or-combine) is added as an unspec for the benefit of the support
 ;; for optimized string functions (such as strcmp).
 (define_insn "orcb2"
-  [(set (match_operand:X 0 "register_operand" "=r")
-   (unspec:X [(match_operand:X 1 "register_operand" "r")] UNSPEC_ORC_B))]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+   (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")] 
UNSPEC_ORC_B))]
   "TARGET_ZBB"
   "orc.b\t%0,%1"
   [(set_attr "type" "bitmanip")])
@@ -852,9 +852,9 @@
 
 ;; ZBKC or ZBC extension
 (define_insn "riscv_clmul_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")
-  (match_operand:X 2 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
+  (match_operand:GPR 2 "register_operand" "r")]
   UNSPEC_CLMUL))]
   "TARGET_ZBKC || TARGET_ZBC"
   "clmul\t%0,%1,%2"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 2b65fadeb15..bf3d1cd9a3c 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -72,8 +72,8 @@
 
 ;; ZBKB extension
 (define_insn "riscv_brev8_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")]
   UNSPEC_BREV8))]
   "TARGET_ZBKB"
   "brev8\t%0,%1"
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 5ee11ebe3bc..fc6ff548b83 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -105,6 +105,7 @@ AVAIL (zero32,  

[PATCH V3 2/3] RISC-V: Add C intrinsic for Scalar Crypto Extension

[Liao Shihua]

This patch adds C intrinsics for Scalar Crypto Extension.

gcc/ChangeLog:

* config.gcc: Include riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_crypto_intrinsic-64.c: New test.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv_crypto.h   | 309 ++
 .../riscv/scalar_crypto_intrinsic-32.c| 114 +++
 .../riscv/scalar_crypto_intrinsic-64.c| 122 +++
 4 files changed, 546 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..f8483d34ee9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 000..14ccc24c98d
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,309 @@
+/* RISC-V 'Scalar Crypto' Extension intrinsics include file.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef __RISCV_SCALAR_CRYPTO_H
+#define __RISCV_SCALAR_CRYPTO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__riscv_zknd)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsi (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsmi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsmi (rs1,rs2,bs);
+}
+
+#else
+#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi (x, y, bs)
+#define __riscv_aes32dsmi(x, y, bs) __builtin_riscv_aes32dsmi (x, y, bs)
+#endif
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ds (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64ds (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64dsm (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64dsm (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64im (uint64_t rs1)
+{
+  return __builtin_riscv_aes64im (rs1);
+}
+#endif
+#endif // __riscv_zknd
+
+#if (defined (__riscv_zknd) || defined (__riscv_zkne)) && (__riscv_xlen == 64)
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks1i (uint64_t rs1, const int rnum)
+{
+  return __builtin_riscv_aes64ks1i (rs1,rnum);
+}
+
+#else
+#define __riscv_aes64ks1i(x, rnum) __builtin_riscv_aes64ks1i (x, rnum)
+#endif
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks2 (uint64_t rs1, uint64_t rs2)
+{
+return __builtin_riscv_aes64ks2 (rs1,rs2);
+}
+
+#endif // __riscv_zknd || __riscv_zkne
+
+#if defined (__riscv_zkne)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, 

[PATCH V3 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

[Liao Shihua]

Update v2 -> v3:
  1. Change pattern mode form X to GPR in orcb, clmul, and brev8.
  2. Add emulated testsuite.
  3. Removed duplicate testsuite between built-in and intrinsic. 
  4. Typo fix.

Update v1 -> v2:
  1. Rename *_intrinsic-* to *_intrinsic-XLEN.
  2. Typo fix.
  3. Intrinsics with immediate arguments will use marcos at O0 .

It's a little patch add just provides a mapping from the RV intrinsics to the 
builtin 
names within GCC.

Liao Shihua (3):
  RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function
testsuites
  RISC-V: Add C intrinsic for Scalar Crypto Extension
  RISC-V: Add C intrinsic for Scalar Bitmanip Extension

 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  10 +-
 gcc/config/riscv/crypto.md|   4 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-cmo.def|  12 +-
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  22 +-
 gcc/config/riscv/riscv_bitmanip.h | 297 +
 gcc/config/riscv/riscv_crypto.h   | 309 ++
 .../riscv/scalar_bitmanip_intrinsic-32.c  |  96 ++
 .../scalar_bitmanip_intrinsic-64-emulated.c   |  32 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c  | 114 +++
 .../riscv/scalar_crypto_intrinsic-32.c| 114 +++
 .../riscv/scalar_crypto_intrinsic-64.c| 122 +++
 gcc/testsuite/gcc.target/riscv/zbbw.c |  26 --
 gcc/testsuite/gcc.target/riscv/zbc32.c|  23 --
 gcc/testsuite/gcc.target/riscv/zbc64.c|  23 --
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  18 -
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |   5 -
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |  17 -
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 -
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |  18 -
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 -
 gcc/testsuite/gcc.target/riscv/zknd32-2.c |  28 --
 gcc/testsuite/gcc.target/riscv/zknd64-2.c |  42 ---
 gcc/testsuite/gcc.target/riscv/zkne32-2.c |  28 --
 gcc/testsuite/gcc.target/riscv/zkne64-2.c |  34 --
 .../gcc.target/riscv/zknh-sha256-32.c |  10 -
 .../gcc.target/riscv/zknh-sha256-64.c |  28 --
 .../gcc.target/riscv/zknh-sha512-32.c |  42 ---
 .../gcc.target/riscv/zknh-sha512-64.c |  31 --
 gcc/testsuite/gcc.target/riscv/zksed32-2.c|  29 --
 gcc/testsuite/gcc.target/riscv/zksed64-2.c|  29 --
 gcc/testsuite/gcc.target/riscv/zksh32.c   |  19 --
 gcc/testsuite/gcc.target/riscv/zksh64.c   |  19 --
 35 files changed, 1142 insertions(+), 520 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

-- 
2.34.1

[PATCH V3 1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites

[Liao Shihua]

The serials patch provides a mapping from the RV intrinsics to the builtin 
names.
There are some duplicates testsuites between intrinsic and built-in function.
Remove the Scalar Bitmanip and Scalar Crypto Built-In function testsuites 
that will be included in the intrinsic functions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbkb32.c: Remove 
__builtin_riscv_(un)zip,__builtin_riscv_brev8.
* gcc.target/riscv/zbkb64.c: Remove __builtin_riscv_brev8.
* gcc.target/riscv/zbbw.c: Removed.
* gcc.target/riscv/zbc32.c: Removed.
* gcc.target/riscv/zbc64.c: Removed.
* gcc.target/riscv/zbkc32.c: Removed.
* gcc.target/riscv/zbkc64.c: Removed.
* gcc.target/riscv/zbkx32.c: Removed.
* gcc.target/riscv/zbkx64.c: Removed.
* gcc.target/riscv/zknd32-2.c: Removed.
* gcc.target/riscv/zknd64-2.c: Removed.
* gcc.target/riscv/zkne32-2.c: Removed.
* gcc.target/riscv/zkne64-2.c: Removed.
* gcc.target/riscv/zknh-sha256-32.c: Removed.
* gcc.target/riscv/zknh-sha256-64.c: Removed.
* gcc.target/riscv/zknh-sha512-32.c: Removed.
* gcc.target/riscv/zknh-sha512-64.c: Removed.
* gcc.target/riscv/zksed32-2.c: Removed.
* gcc.target/riscv/zksed64-2.c: Removed.
* gcc.target/riscv/zksh32.c: Removed.
* gcc.target/riscv/zksh64.c: Removed.

---
 gcc/testsuite/gcc.target/riscv/zbbw.c | 26 
 gcc/testsuite/gcc.target/riscv/zbc32.c| 23 --
 gcc/testsuite/gcc.target/riscv/zbc64.c| 23 --
 gcc/testsuite/gcc.target/riscv/zbkb32.c   | 18 
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |  5 ---
 gcc/testsuite/gcc.target/riscv/zbkc32.c   | 17 
 gcc/testsuite/gcc.target/riscv/zbkc64.c   | 17 
 gcc/testsuite/gcc.target/riscv/zbkx32.c   | 18 
 gcc/testsuite/gcc.target/riscv/zbkx64.c   | 18 
 gcc/testsuite/gcc.target/riscv/zknd32-2.c | 28 -
 gcc/testsuite/gcc.target/riscv/zknd64-2.c | 42 ---
 gcc/testsuite/gcc.target/riscv/zkne32-2.c | 28 -
 gcc/testsuite/gcc.target/riscv/zkne64-2.c | 34 ---
 .../gcc.target/riscv/zknh-sha256-32.c | 10 -
 .../gcc.target/riscv/zknh-sha256-64.c | 28 -
 .../gcc.target/riscv/zknh-sha512-32.c | 42 ---
 .../gcc.target/riscv/zknh-sha512-64.c | 31 --
 gcc/testsuite/gcc.target/riscv/zksed32-2.c| 29 -
 gcc/testsuite/gcc.target/riscv/zksed64-2.c| 29 -
 gcc/testsuite/gcc.target/riscv/zksh32.c   | 19 -
 gcc/testsuite/gcc.target/riscv/zksh64.c   | 19 -
 21 files changed, 504 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c 
b/gcc/testsuite/gcc.target/riscv/zbbw.c
deleted file mode 100644
index bdf6b0c4ec5..000
--- a/gcc/testsuite/gcc.target/riscv/zbbw.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
-
-int
-clz (int i)
-{
-  return __builtin_clz (i);
-}
-
-int
-ctz (int i)
-{
-  return __builtin_ctz (i);
-}
-
-int
-popcount (int i)
-{
-  return __builtin_popcount (i);
-}
-
-
-/* { dg-final { scan-assembler-times {\mclzw} 1 } } */
-/* { dg-final { scan-assembler-times {\mctzw} 1 } } */
-/* { dg-final { scan-assembler-times {\mcpopw} 1 } } */
-/* { dg-final { scan-assembler-not "andi\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbc32.c 
b/gcc/testsuite/gcc.target/riscv/zbc32.c
deleted file mode 100644
index 049ea95c56b..000
--- a/gcc/testsuite/gcc.target/riscv/zbc32.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zbc -mabi=ilp32" } */
-/* { dg-skip-if "" { *-*-* } { 

Re: [PATCH] RISC-V: fix scalar crypto pattern

[Liao Shihua]

Sorry, I was not aware of this patch.
Since Jeff's patch was here first and also includes more tests, I
propose to move forward with his patch (but I'm not a maintainer!).
Therefore, I've reviewed Jeff's patch and replied to his email.

FWIW: Jeff's patch can be found here:
   https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622233.html


No problem.

And I would tend to remove the D03 constraint if we used const_0_3_operand.

BR

Liao  Shihua

[PATCH] RISC-V: fix scalar crypto pattern

[Liao Shihua]

In Scalar Crypto Built-In functions, some require immediate parameters,
But register_operand are incorrectly used in the pattern.

E.g.:
   __builtin_riscv_aes64ks1i(rs1,1)
   Before:
  li a5,1
  aes64ks1i a0,a0,a5
  
  Assembler messages:
  Error: instruction aes64ks1i requires absolute expression

   After:
  aes64ks1i a0,a0,1

gcc/ChangeLog:

* config/riscv/crypto.md: Use immediate_operand instead of 
register_operand.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknd32.c: Use immediate instead of parameter.
* gcc.target/riscv/zknd64.c: Ditto.
* gcc.target/riscv/zkne32.c: Ditto.
* gcc.target/riscv/zkne64.c: Ditto.
* gcc.target/riscv/zksed32.c: Ditto.
* gcc.target/riscv/zksed64.c: Ditto.

---
 gcc/config/riscv/crypto.md   | 16 
 gcc/testsuite/gcc.target/riscv/zknd32.c  |  8 
 gcc/testsuite/gcc.target/riscv/zknd64.c  |  4 ++--
 gcc/testsuite/gcc.target/riscv/zkne32.c  |  8 
 gcc/testsuite/gcc.target/riscv/zkne64.c  |  4 ++--
 gcc/testsuite/gcc.target/riscv/zksed32.c |  8 
 gcc/testsuite/gcc.target/riscv/zksed64.c |  8 
 7 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 03a1d03397d..c45f12e421f 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -148,7 +148,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
-   (match_operand:SI 3 "register_operand" "D03")]
+   (match_operand:SI 3 "immediate_operand" "D03")]
UNSPEC_AES_DSI))]
   "TARGET_ZKND && !TARGET_64BIT"
   "aes32dsi\t%0,%1,%2,%3"
@@ -158,7 +158,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
-   (match_operand:SI 3 "register_operand" "D03")]
+   (match_operand:SI 3 "immediate_operand" "D03")]
UNSPEC_AES_DSMI))]
   "TARGET_ZKND && !TARGET_64BIT"
   "aes32dsmi\t%0,%1,%2,%3"
@@ -193,7 +193,7 @@
 (define_insn "riscv_aes64ks1i"
   [(set (match_operand:DI 0 "register_operand" "=r")
 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
-   (match_operand:SI 2 "register_operand" "DsA")]
+   (match_operand:SI 2 "immediate_operand" "DsA")]
UNSPEC_AES_KS1I))]
   "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
   "aes64ks1i\t%0,%1,%2"
@@ -214,7 +214,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
-   (match_operand:SI 3 "register_operand" "D03")]
+   (match_operand:SI 3 "immediate_operand" "D03")]
UNSPEC_AES_ESI))]
   "TARGET_ZKNE && !TARGET_64BIT"
   "aes32esi\t%0,%1,%2,%3"
@@ -224,7 +224,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
-   (match_operand:SI 3 "register_operand" "D03")]
+   (match_operand:SI 3 "immediate_operand" "D03")]
UNSPEC_AES_ESMI))]
   "TARGET_ZKNE && !TARGET_64BIT"
   "aes32esmi\t%0,%1,%2,%3"
@@ -431,7 +431,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
-   (match_operand:SI 3 "register_operand" "D03")]
+   (match_operand:SI 3 "immediate_operand" "D03")]
SM4_OP))]
   "TARGET_ZKSED && !TARGET_64BIT"
   "\t%0,%1,%2,%3"
@@ -442,7 +442,7 @@
 (sign_extend:DI
  (unspec:SI [(match_operand:SI 1 "register_operand" "r")
 (match_operand:SI 2 "register_operand" "r")
-(match_operand:SI 3 "register_operand" "D03")]
+(match_operand:SI 3 "immediate_operand" "D03")]
 SM4_OP)))]
   "TARGET_ZKSED && TARGET_64BIT"
   "\t%0,%1,%2,%3"
@@ -452,7 +452,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
-   (match_operand:SI 3 "register_operand" "D03")]
+   (match_operand:SI 3 "immediate_operand" "D03")]
SM4_OP))]
   "TARGET_ZKSED"
   {
diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c 
b/gcc/testsuite/gcc.target/riscv/zknd32.c
index e60c027e091..9711b120001 100644
--- a/gcc/testsuite/gcc.target/riscv/zknd32.c
+++ 

[PATCH V2 2/2]RISC-V: Add C intrinsics of Bitmanip Extension

[Liao Shihua]

This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.

gcc/ChangeLog:

* config.gcc: Add riscv_bitmanip.h
* config/riscv/riscv-builtins.cc (AVAIL): New AVAIL.
(RISCV_BUILTIN_NO_PREFIX): new riscv_builtin_description.
* config/riscv/riscv-ftypes.def (2): New function type.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN_NO_PREFIX):New 
builtins.
* config/riscv/riscv_bitmanip.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_bitmanip_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_bitmanip_intrinsic-64.c: New test.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  18 ++
 gcc/config/riscv/riscv_bitmanip.h | 297 ++
 .../riscv/scalar_bitmanip_intrinsic-32.c  |  97 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c  | 115 +++
 7 files changed, 552 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index d67fe8b6a6f..37e66143c53 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h riscv_crypto.h"
+   extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..3a297b3742e 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -123,6 +123,12 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) 
&& !TARGET_64BIT)
 AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
 AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
 AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
+AVAIL (zbb, TARGET_ZBB)
+AVAIL (zbb32, TARGET_ZBB && !TARGET_64BIT)
+AVAIL (zbb64, TARGET_ZBB && TARGET_64BIT)
+AVAIL (zbb32_or_zbkb32, (TARGET_ZBKB || TARGET_ZBB) && !TARGET_64BIT)
+AVAIL (zbb64_or_zbkb64, (TARGET_ZBKB || TARGET_ZBB) && TARGET_64BIT)
+AVAIL (zbb_or_zbkb, (TARGET_ZBKB || TARGET_ZBB))
 AVAIL (hint_pause, (!0))
 
 // CORE-V AVAIL
@@ -145,6 +151,22 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
   { CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME,  \
 BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
 
+/* Construct a riscv_builtin_description from the given arguments like 
RISCV_BUILTIN.
+
+   INSN is the name of the associated instruction pattern, without the
+   leading CODE_FOR_.
+
+   NAME is the name of the function itself, without the leading
+   "__builtin_riscv_".
+
+   BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields.
+
+   AVAIL is the name of the availability predicate, without the leading
+   riscv_builtin_avail_.  */
+#define RISCV_BUILTIN_NO_PREFIX(INSN, NAME, BUILTIN_TYPE,  FUNCTION_TYPE, 
AVAIL)   \
+  { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME,\
+BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+
 /* Define __builtin_riscv_, which is a RISCV_BUILTIN_DIRECT function
mapped to instruction CODE_FOR_riscv_,  FUNCTION_TYPE and AVAIL
are as for RISCV_BUILTIN.  */
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..13221090e5f 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -39,9 +39,11 @@ DEF_RISCV_FTYPE (1, (SI, HI))
 DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (USI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (USI, USI, USI))
+DEF_RISCV_FTYPE (2, (USI, USI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (UDI, USI, USI))
+DEF_RISCV_FTYPE (2, (UDI, UDI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, USI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
 DEF_RISCV_FTYPE (2, (SI, USI, USI))
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def 
b/gcc/config/riscv/riscv-scalar-crypto.def
index 3db9ed4a03e..b1a71139d05 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -78,3 +78,21 @@ RISCV_BUILTIN (sm3p1_si, "sm3p1", 

[PATCH V2 1/2] RISC-V: Add C intrinsics of Scalar Crypto Extension

[Liao Shihua]

This patch adds C intrinsics for Scalar Crypto Extension.

gcc/ChangeLog:

* config.gcc: Add riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_crypto_intrinsic-64.c: New test.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv_crypto.h   | 309 ++
 .../riscv/scalar_crypto_intrinsic-32.c| 115 +++
 .../riscv/scalar_crypto_intrinsic-64.c| 122 +++
 4 files changed, 547 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index b88591b6fd8..d67fe8b6a6f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 000..14ccc24c98d
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,309 @@
+/* RISC-V 'Scalar Crypto' Extension intrinsics include file.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef __RISCV_SCALAR_CRYPTO_H
+#define __RISCV_SCALAR_CRYPTO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__riscv_zknd)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsi (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsmi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsmi (rs1,rs2,bs);
+}
+
+#else
+#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi (x, y, bs)
+#define __riscv_aes32dsmi(x, y, bs) __builtin_riscv_aes32dsmi (x, y, bs)
+#endif
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ds (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64ds (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64dsm (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64dsm (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64im (uint64_t rs1)
+{
+  return __builtin_riscv_aes64im (rs1);
+}
+#endif
+#endif // __riscv_zknd
+
+#if (defined (__riscv_zknd) || defined (__riscv_zkne)) && (__riscv_xlen == 64)
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks1i (uint64_t rs1, const int rnum)
+{
+  return __builtin_riscv_aes64ks1i (rs1,rnum);
+}
+
+#else
+#define __riscv_aes64ks1i(x, rnum) __builtin_riscv_aes64ks1i (x, rnum)
+#endif
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks2 (uint64_t rs1, uint64_t rs2)
+{
+return __builtin_riscv_aes64ks2 (rs1,rs2);
+}
+
+#endif // __riscv_zknd || __riscv_zkne
+
+#if defined (__riscv_zkne)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, 

[PATCH V2 0/2] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

[Liao Shihua]

In accordance with the suggestions of Christoph Müllner, the following 
amendments are made

Update v1 -> v2:
  1. Rename *_intrinsic-* to *_intrinsic-XLEN.
  2. Typo fix.
  3. Intrinsics with immediate arguments will use marcos at O0 .

It's a little patch add just provides a mapping from the RV intrinsics to the 
builtin 
names within GCC.


Liao Shihua (2):
  Add C intrinsics of Scalar Crypto Extension
  Add C intrinsics of Bitmanip Extension

 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  18 +
 gcc/config/riscv/riscv_bitmanip.h | 297 +
 gcc/config/riscv/riscv_crypto.h   | 309 ++
 .../riscv/scalar_bitmanip_intrinsic-32.c  |  97 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c  | 115 +++
 .../riscv/scalar_crypto_intrinsic-32.c| 115 +++
 .../riscv/scalar_crypto_intrinsic-64.c| 122 +++
 10 files changed, 1098 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c

-- 
2.34.1

[PATCH 2/2] RISC-V: Add C intrinsics of Bitmanip Extension

[Liao Shihua]

This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Some of the instructions are different to spec, see 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/59 for details.

gcc/ChangeLog:

* config.gcc: Add riscv_bitmanip.h
* config/riscv/riscv-builtins.cc (AVAIL): New AVAIL.
(RISCV_BUILTIN_NO_PREFIX): new riscv_builtin_description.
* config/riscv/riscv-ftypes.def (2): New function type.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN_NO_PREFIX):New 
builtins.
* config/riscv/riscv_bitmanip.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_bitmanip_intrinsic-1.c: New test.
* gcc.target/riscv/scalar_bitmanip_intrinsic-2.c: New test.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  18 ++
 gcc/config/riscv/riscv_bitmanip.h | 297 ++
 .../riscv/scalar_bitmanip_intrinsic-1.c   |  97 ++
 .../riscv/scalar_bitmanip_intrinsic-2.c   | 115 +++
 7 files changed, 552 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-2.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index d67fe8b6a6f..37e66143c53 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h riscv_crypto.h"
+   extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..3a297b3742e 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -123,6 +123,12 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) 
&& !TARGET_64BIT)
 AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
 AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
 AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
+AVAIL (zbb, TARGET_ZBB)
+AVAIL (zbb32, TARGET_ZBB && !TARGET_64BIT)
+AVAIL (zbb64, TARGET_ZBB && TARGET_64BIT)
+AVAIL (zbb32_or_zbkb32, (TARGET_ZBKB || TARGET_ZBB) && !TARGET_64BIT)
+AVAIL (zbb64_or_zbkb64, (TARGET_ZBKB || TARGET_ZBB) && TARGET_64BIT)
+AVAIL (zbb_or_zbkb, (TARGET_ZBKB || TARGET_ZBB))
 AVAIL (hint_pause, (!0))
 
 // CORE-V AVAIL
@@ -145,6 +151,22 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
   { CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME,  \
 BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
 
+/* Construct a riscv_builtin_description from the given arguments like 
RISCV_BUILTIN.
+
+   INSN is the name of the associated instruction pattern, without the
+   leading CODE_FOR_.
+
+   NAME is the name of the function itself, without the leading
+   "__builtin_riscv_".
+
+   BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields.
+
+   AVAIL is the name of the availability predicate, without the leading
+   riscv_builtin_avail_.  */
+#define RISCV_BUILTIN_NO_PREFIX(INSN, NAME, BUILTIN_TYPE,  FUNCTION_TYPE, 
AVAIL)   \
+  { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME,\
+BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+
 /* Define __builtin_riscv_, which is a RISCV_BUILTIN_DIRECT function
mapped to instruction CODE_FOR_riscv_,  FUNCTION_TYPE and AVAIL
are as for RISCV_BUILTIN.  */
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..13221090e5f 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -39,9 +39,11 @@ DEF_RISCV_FTYPE (1, (SI, HI))
 DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (USI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (USI, USI, USI))
+DEF_RISCV_FTYPE (2, (USI, USI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (UDI, USI, USI))
+DEF_RISCV_FTYPE (2, (UDI, UDI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, USI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
 DEF_RISCV_FTYPE (2, (SI, USI, USI))
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def 
b/gcc/config/riscv/riscv-scalar-crypto.def
index 3db9ed4a03e..5e66a1131c6 100644
--- 

[PATCH 1/2] RISC-V: Add C intrinsics of Scalar Crypto Extension

[Liao Shihua]

This patch adds C intrinsics for Scalar Crypto Extension.

gcc/ChangeLog:

* config.gcc: Add riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/scalar_crypto_intrinsic-1.c: New test.
* gcc.target/riscv/scalar_crypto_intrinsic-2.c: New test.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv_crypto.h   | 280 ++
 .../riscv/scalar_crypto_intrinsic-1.c | 115 +++
 .../riscv/scalar_crypto_intrinsic-2.c | 122 
 4 files changed, 518 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-2.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index b88591b6fd8..d67fe8b6a6f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 000..9335ffda20d
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,280 @@
+/* RISC-V 'Scalar Crypto' Extension intrinsics include file.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef __RISCV_SCALAR_CRYPTO_H
+#define __RISCV_SCALAR_CRYPTO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__riscv_zknd)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsi (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsmi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsmi (rs1,rs2,bs);
+}
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ds (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64ds (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64dsm (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64dsm (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64im (uint64_t rs1)
+{
+  return __builtin_riscv_aes64im (rs1);
+}
+#endif
+#endif // ZKND
+
+#if (defined(__riscv_zknd) || defined(__riscv_zkne)) && (__riscv_xlen == 64)
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks1i(uint64_t rs1, const int rnum)
+{
+  return __builtin_riscv_aes64ks1i(rs1,rnum);
+}
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks2(uint64_t rs1, uint64_t rs2)
+{
+return __builtin_riscv_aes64ks2(rs1,rs2);
+}
+
+#endif // ZKND || ZKNE
+
+#if defined(__riscv_zkne)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32esi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32esi (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32esmi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32esmi (rs1,rs2,bs);
+}
+#endif

[PATCH 0/2] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions.

[Liao Shihua]

It's a little patch add just provides a mapping from the RV intrinsics to the 
builtin 
names within GCC.

Liao Shihua (2):
  Add C intrinsics of Scalar Crypto Extension
  Add C intrinsics of Bitmanip Extension

 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-builtins.cc|  22 ++
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  18 ++
 gcc/config/riscv/riscv_bitmanip.h | 297 ++
 gcc/config/riscv/riscv_crypto.h   | 280 +
 .../riscv/scalar_bitmanip_intrinsic-1.c   |  97 ++
 .../riscv/scalar_bitmanip_intrinsic-2.c   | 115 +++
 .../riscv/scalar_crypto_intrinsic-1.c | 115 +++
 .../riscv/scalar_crypto_intrinsic-2.c | 122 +++
 10 files changed, 1069 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-2.c

-- 
2.34.1

Re: [PATCH] Add C intrinsics for scalar crypto extension

[Liao Shihua]

在 2023/11/29 23:03, Christoph Müllner 写道:

On Mon, Nov 27, 2023 at 9:36 AM Liao Shihua  wrote:

This patch add C intrinsics for scalar crypto extension.
Because of riscv-c-api 
(https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44/files) includes 
zbkb/zbkc/zbkx's
intrinsics in bit manipulation extension, this patch only support zkn*/zks*'s 
intrinsics.

Thanks for working on this!
Looking forward to seeing the second patch (covering bitmanip) soon as well!
A couple of comments can be found below.



Thanks for your comments, Christoph. Typos will be corrected in the next 
patch.


The implementation of intrinsic is belonged to the implementation in the 
LLVM.(It does look a little strange)


I will unify the implementation method in the next patch.





gcc/ChangeLog:

 * config.gcc: Add riscv_crypto.h
 * config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/zknd32.c: Use intrinsics instead of builtins.
 * gcc.target/riscv/zknd64.c: Likewise.
 * gcc.target/riscv/zkne32.c: Likewise.
 * gcc.target/riscv/zkne64.c: Likewise.
 * gcc.target/riscv/zknh-sha256-32.c: Likewise.
 * gcc.target/riscv/zknh-sha256-64.c: Likewise.
 * gcc.target/riscv/zknh-sha512-32.c: Likewise.
 * gcc.target/riscv/zknh-sha512-64.c: Likewise.
 * gcc.target/riscv/zksed32.c: Likewise.
 * gcc.target/riscv/zksed64.c: Likewise.
 * gcc.target/riscv/zksh32.c: Likewise.
 * gcc.target/riscv/zksh64.c: Likewise.

---
  gcc/config.gcc|   2 +-
  gcc/config/riscv/riscv_crypto.h   | 219 ++
  gcc/testsuite/gcc.target/riscv/zknd32.c   |   6 +-
  gcc/testsuite/gcc.target/riscv/zknd64.c   |  12 +-
  gcc/testsuite/gcc.target/riscv/zkne32.c   |   6 +-
  gcc/testsuite/gcc.target/riscv/zkne64.c   |  10 +-
  .../gcc.target/riscv/zknh-sha256-32.c |  22 +-
  .../gcc.target/riscv/zknh-sha256-64.c |  10 +-
  .../gcc.target/riscv/zknh-sha512-32.c |  14 +-
  .../gcc.target/riscv/zknh-sha512-64.c |  10 +-
  gcc/testsuite/gcc.target/riscv/zksed32.c  |   6 +-
  gcc/testsuite/gcc.target/riscv/zksed64.c  |   6 +-
  gcc/testsuite/gcc.target/riscv/zksh32.c   |   6 +-
  gcc/testsuite/gcc.target/riscv/zksh64.c   |   6 +-
  14 files changed, 288 insertions(+), 47 deletions(-)
  create mode 100644 gcc/config/riscv/riscv_crypto.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index b88591b6fd8..d67fe8b6a6f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
 extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 extra_objs="${extra_objs} thead.o riscv-target-attr.o"
 d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_crypto.h"
 target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
 target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
 ;;
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 000..149c1132e10
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,219 @@
+/* RISC-V 'K' Extension intrinsics include file.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+#ifndef __RISCV_CRYPTO_H
+#define __RISCV_CRYPTO_H
+
+#include 
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+#if defined(__riscv_zknd)
+#if __riscv_xlen == 32
+#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi(x, y, bs)
+#define __riscv_aes32dsmi(x, y, bs) __builtin_riscv_aes32dsmi(x, y, bs)
+#endif
+
+#if __riscv_xlen == 64
+static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug__))
+__riscv_aes64ds (uint64_t __x, uint64_t __y)
+{
+  return __builtin_riscv_aes64ds (__

[PATCH] Add C intrinsics for scalar crypto extension

[Liao Shihua]

This patch add C intrinsics for scalar crypto extension.
Because of riscv-c-api 
(https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44/files) includes 
zbkb/zbkc/zbkx's
intrinsics in bit manipulation extension, this patch only support zkn*/zks*'s 
intrinsics.

gcc/ChangeLog:

* config.gcc: Add riscv_crypto.h
* config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknd32.c: Use intrinsics instead of builtins.
* gcc.target/riscv/zknd64.c: Likewise.
* gcc.target/riscv/zkne32.c: Likewise.
* gcc.target/riscv/zkne64.c: Likewise.
* gcc.target/riscv/zknh-sha256-32.c: Likewise.
* gcc.target/riscv/zknh-sha256-64.c: Likewise.
* gcc.target/riscv/zknh-sha512-32.c: Likewise.
* gcc.target/riscv/zknh-sha512-64.c: Likewise.
* gcc.target/riscv/zksed32.c: Likewise.
* gcc.target/riscv/zksed64.c: Likewise.
* gcc.target/riscv/zksh32.c: Likewise.
* gcc.target/riscv/zksh64.c: Likewise.

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv_crypto.h   | 219 ++
 gcc/testsuite/gcc.target/riscv/zknd32.c   |   6 +-
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  12 +-
 gcc/testsuite/gcc.target/riscv/zkne32.c   |   6 +-
 gcc/testsuite/gcc.target/riscv/zkne64.c   |  10 +-
 .../gcc.target/riscv/zknh-sha256-32.c |  22 +-
 .../gcc.target/riscv/zknh-sha256-64.c |  10 +-
 .../gcc.target/riscv/zknh-sha512-32.c |  14 +-
 .../gcc.target/riscv/zknh-sha512-64.c |  10 +-
 gcc/testsuite/gcc.target/riscv/zksed32.c  |   6 +-
 gcc/testsuite/gcc.target/riscv/zksed64.c  |   6 +-
 gcc/testsuite/gcc.target/riscv/zksh32.c   |   6 +-
 gcc/testsuite/gcc.target/riscv/zksh64.c   |   6 +-
 14 files changed, 288 insertions(+), 47 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_crypto.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index b88591b6fd8..d67fe8b6a6f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 000..149c1132e10
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,219 @@
+/* RISC-V 'K' Extension intrinsics include file.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef __RISCV_CRYPTO_H
+#define __RISCV_CRYPTO_H
+
+#include 
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+#if defined(__riscv_zknd)
+#if __riscv_xlen == 32
+#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi(x, y, bs)
+#define __riscv_aes32dsmi(x, y, bs) __builtin_riscv_aes32dsmi(x, y, bs)
+#endif
+
+#if __riscv_xlen == 64
+static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug__))
+__riscv_aes64ds (uint64_t __x, uint64_t __y)
+{
+  return __builtin_riscv_aes64ds (__x, __y);
+}
+
+static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug__))
+__riscv_aes64dsm (uint64_t __x, uint64_t __y)
+{
+  return __builtin_riscv_aes64dsm (__x, __y);
+}
+
+static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug__))
+__riscv_aes64im (uint64_t __x)
+{
+  return __builtin_riscv_aes64im (__x);
+}
+#endif
+#endif // defined (__riscv_zknd)
+
+#if defined(__riscv_zkne)
+#if __riscv_xlen == 32
+#define __riscv_aes32esi(x, y, bs) __builtin_riscv_aes32esi(x, y, bs)
+#define __riscv_aes32esmi(x, y, bs) __builtin_riscv_aes32esmi(x, y, bs)
+#endif
+
+#if __riscv_xlen == 64

[PATCH] Add bfloat16_t support for riscv

[Liao Shihua]

x86_64/i686/AArch64 has for a few months working std::bfloat16_t
support, __bf16 there is no longer a storage only type, but can 
be used for arithmetics and is supported in libgcc and libstdc++. 
The patch adds similar support for RISC-V. __bf16 has been merged 
in psABI. The compiler handles all operations with __bf16 by 
converting to SFmode.

gcc/ChangeLog:

* config/riscv/iterators.md (ld):Add BFmode in iterators.
(sd):Ditto.
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):Add 
bfloat16_type_node in riscv.
* config/riscv/riscv-modes.def (FLOAT_MODE):Add BFmode in FLOAT_MODE.
(ADJUST_FLOAT_FORMAT):Ditto.
* config/riscv/riscv.cc (riscv_mangle_type):Add DF16b in mangle.
(riscv_scalar_mode_supported_p):Add BFmode in scalar_float_mode.
(riscv_libgcc_floating_mode_supported_p):Support BFmode in libgcc.
* config/riscv/riscv.md (mode" ):Support BFmode in machine description.
(movbf): Support BFmode in softfloat.
(*movbf_softfloat):Ditto.

libgcc/ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_B):Define.
(_FP_NANSIGN_B):
* config/riscv/t-softfp32:Add trunc{tfbf dfbf sfbf hfbf}, extendbfsf, 
floatdibf, floatundibf.
* config/riscv/t-softfp64:Add floattibf, floatuntibf.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/__bf16-soft.c: New test.

---
 gcc/config/riscv/iterators.md|  4 ++--
 gcc/config/riscv/riscv-builtins.cc   | 16 +++
 gcc/config/riscv/riscv-modes.def |  2 ++
 gcc/config/riscv/riscv.cc| 12 ---
 gcc/config/riscv/riscv.md| 21 +++-
 gcc/testsuite/gcc.target/riscv/__bf16-soft.c | 12 +++
 libgcc/config/riscv/sfp-machine.h|  3 +++
 libgcc/config/riscv/t-softfp32   |  7 ---
 libgcc/config/riscv/t-softfp64   |  2 +-
 9 files changed, 69 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/__bf16-soft.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index d374a10810c..c9148028ea3 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -87,13 +87,13 @@
 (define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
 
 ;; Mode attribute for FP loads into integer registers.
-(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
+(define_mode_attr softload [(BF "lh") (HF "lh") (SF "lw") (DF "ld")])
 
 ;; Instruction names for stores.
 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") 
(SF "fsw") (DF "fsd")])
 
 ;; Instruction names for FP stores from integer registers.
-(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")])
+(define_mode_attr softstore [(BF "sh") (HF "sh") (SF "sw") (DF "sd")])
 
 ;; This attribute gives the best constraint to use for registers of
 ;; a given mode.
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 79681d75962..398247a0ccb 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -194,6 +194,7 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
   riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
 
 tree riscv_float16_type_node = NULL_TREE;
+tree riscv_bfloat16_type_node = NULL_TREE;
 
 /* Return the function type associated with function prototype TYPE.  */
 
@@ -237,6 +238,21 @@ riscv_init_builtin_types (void)
   if (!maybe_get_identifier ("_Float16"))
 lang_hooks.types.register_builtin_type (riscv_float16_type_node,
"_Float16");
+
+  /* Provide the __bf16 type and bfloat16_type_node if needed.  */
+  if (!bfloat16_type_node)
+{
+  riscv_bfloat16_type_node = make_node (REAL_TYPE);
+  TYPE_PRECISION (riscv_bfloat16_type_node) = 16;
+  SET_TYPE_MODE (riscv_bfloat16_type_node, BFmode);
+  layout_type (riscv_bfloat16_type_node);
+}
+  else
+riscv_bfloat16_type_node = bfloat16_type_node;
+
+  if (!maybe_get_identifier ("__bf16"))
+lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node,
+   "__bf16");
 }
 
 /* Implement TARGET_INIT_BUILTINS.  */
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index 19a4f9fb3db..4bb03307840 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -21,6 +21,8 @@ along with GCC; see the file COPYING3.  If not see
 
 FLOAT_MODE (HF, 2, ieee_half_format);
 FLOAT_MODE (TF, 16, ieee_quad_format);
+FLOAT_MODE (BF, 2, 0);
+ADJUST_FLOAT_FORMAT (BF, _bfloat_half_format);
 
 /* Vector modes.  */
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e5ae4e81b7a..d5b1350d4bf 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7155,8 +7155,14 @@ static const char *
 riscv_mangle_type 

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Liao Shihua]

Hi, Ma Jin

    1. There are few developments since May in GCC because the spec of 
Zfbf <https://github.com/riscv/riscv-bfloat16> is constantly changing.


    2. We (PLCT lab) will implement Zvfbfmin and Zvfbfwma after Zvfh 
has been merged in GCC.


    3. I will send a patch to support bfloat16_t in RISC-V port, but 
Zfbf extension's patch will be sent after it released.


Liao Shihua

在 2023/6/1 14:51, Jin Ma 写道:

hi,

Are there any new developments about Zfb? Are there any plans to implement
the Zvfbfmin and Zvfbfwma expansion? I see that Zfb is being reviewed in
llvm, maybe we should do the same on gcc.

Ref:https://reviews.llvm.org/D151313
  https://reviews.llvm.org/D150929

Re: [RFC V2] RISC-V : Support rv64 ilp32

[Liao Shihua]

Thanks for your advice, Kito.

在 2023/5/19 15:35, Kito Cheng 写道:

I am concern about we didn't define POINTERS_EXTEND_UNSIGNED here, and
also concern about the code model stuffs, I know currently Guo-Ren's
implementation is rely on some MMU trick, but I am not sure does it
also applicable on embedded applications.




OK，we will verify this in the future.




-  /* We do not yet support ILP32 on RV64.  */
-  if (BITS_PER_WORD != POINTER_SIZE)
-error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);


It seems to also make -march=rv32g -mabi=lp64 become acceptable?


Oh, I was negligent and will make improvements in the next patch.

Best Regards
Liao Shihua

[RFC V2] RISC-V : Support rv64 ilp32

[Liao Shihua]

This patch support ilp32 on rv64.
It remove option check when -march=rv64* -mabi=ilp32. And replace XLEN_SPEC in 
LINK_SPEC by ABI_LEN_SPEC. In addition, it some machine descriptions. 

The series kernel support in this link. 
https://lore.kernel.org/linux-riscv/20230518131013.3366406-1-guo...@kernel.org/

gcc/ChangeLog:

* config.gcc:
* config/riscv/elf.h (LINK_SPEC):
* config/riscv/linux.h (LINK_SPEC):
* config/riscv/riscv.cc (riscv_option_override):
* config/riscv/riscv.h (TARGET_ILP32):
(POINTER_SIZE):
(Pmode):
(ABI_LEN_SPEC):
* config/riscv/riscv.md:
---
 gcc/config.gcc|  3 +++
 gcc/config/riscv/elf.h|  2 +-
 gcc/config/riscv/linux.h  |  2 +-
 gcc/config/riscv/riscv.cc |  4 
 gcc/config/riscv/riscv.h  | 12 ++--
 gcc/config/riscv/riscv.md |  8 ++--
 6 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6fd1594480a..db8e8f20791 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4658,6 +4658,9 @@ case "${target}" in
ilp32,rv32* | ilp32e,rv32e* \
| ilp32f,rv32*f* | ilp32f,rv32g* \
| ilp32d,rv32*d* | ilp32d,rv32g* \
+   | ilp32f,rv64*f* | ilp32f,rv64g* \
+   | ilp32d,rv64*d* | ilp32d,rv64g* \
+   | ilp32,rv64* \
| lp64,rv64* \
| lp64f,rv64*f* | lp64f,rv64g* \
| lp64d,rv64*d* | lp64d,rv64g*)
diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h
index a725c00b637..bea531ebe89 100644
--- a/gcc/config/riscv/elf.h
+++ b/gcc/config/riscv/elf.h
@@ -18,7 +18,7 @@ along with GCC; see the file COPYING3.  If not see
 .  */
 
 #define LINK_SPEC "\
--melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
+-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
 %{mno-relax:--no-relax} \
 %{mbig-endian:-EB} \
 %{mlittle-endian:-EL} \
diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
index b9557a75dc7..4f33c88ef6e 100644
--- a/gcc/config/riscv/linux.h
+++ b/gcc/config/riscv/linux.h
@@ -58,7 +58,7 @@ along with GCC; see the file COPYING3.  If not see
   "%{mabi=ilp32:_ilp32}"
 
 #define LINK_SPEC "\
--melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \
+-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \
 %{mno-relax:--no-relax} \
 %{mbig-endian:-EB} \
 %{mlittle-endian:-EL} \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f44f6dc5c9..09ab940447d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6291,10 +6291,6 @@ riscv_option_override (void)
   && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
 error ("z*inx requires ABI ilp32, ilp32e or lp64");
 
-  /* We do not yet support ILP32 on RV64.  */
-  if (BITS_PER_WORD != POINTER_SIZE)
-error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-
   /* Validate -mpreferred-stack-boundary= value.  */
   riscv_stack_boundary = ABI_STACK_BOUNDARY;
   if (riscv_preferred_stack_boundary_arg)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 66fb07d6652..54fd328b5b0 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -77,6 +77,10 @@ extern const char *riscv_multi_lib_check (int argc, const 
char **argv);
 #define TARGET_64BIT   (__riscv_xlen == 64)
 #endif /* IN_LIBGCC2 */
 
+#ifndef TARGET_ILP32
+#define TARGET_ILP32   (riscv_abi <= ABI_ILP32D)
+#endif /*TARGET_ILP32*/
+
 #ifdef HAVE_AS_MISA_SPEC
 #define ASM_MISA_SPEC "%{misa-spec=*}"
 #else
@@ -172,7 +176,7 @@ ASM_MISA_SPEC
 #define SHORT_TYPE_SIZE 16
 #define INT_TYPE_SIZE 32
 #define LONG_LONG_TYPE_SIZE 64
-#define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
+#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
 #define LONG_TYPE_SIZE POINTER_SIZE
 
 #define FLOAT_TYPE_SIZE 32
@@ -789,7 +793,7 @@ typedef struct {
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode.  */
 
-#define Pmode word_mode
+#define Pmode (TARGET_ILP32 ? SImode : DImode)
 
 /* Give call MEMs SImode since it is the "most permissive" mode
for both 32-bit and 64-bit targets.  */
@@ -1039,6 +1043,10 @@ extern poly_int64 riscv_v_adjust_bytesize (enum 
machine_mode, int);
   "%{march=rv32*:32}" \
   "%{march=rv64*:64}" \
 
+#define ABI_LEN_SPEC \
+  "%{mabi=ilp32*:32}" \
+  "%{mabi=lp64*:64}" \
+
 #define ABI_SPEC \
   "%{mabi=ilp32:ilp32}" \
   "%{mabi=ilp32e:ilp32e}" \
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index bc384d9aedf..260b0907cf5 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2737,6 +2737,10 @@
   "reload_completed"
   [(const_int 0)]
 {
+  if (GET_MODE (operands[0]) != Pmode)
+operands[0] = convert_to_mode (Pmode, operands[0], 0);  
+  if (GET_MODE (operands[1]) != Pmode)
+operands[1] = convert_to_mode (Pmode, operands[1], 0);
   

[RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Liao Shihua]

   According to https://github.com/riscv/riscv-bfloat16 , zfbfmin extension 
depends on zfh/zfhmin extension.

   According to the discussion 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367, this use __bf16 
and use DF16b in riscv_mangle_type like x86.


gcc\ChangeLog:

* common/config/riscv/riscv-common.cc: Add ZFBFMIN extension.
* config/riscv/iterators.md (TARGET_ZFHMIN):Add iterator BF.
(fld):Likewise.
(ld):Likewise
(fsd):Likewise
(sd):Likewise
(d):Likewise
(DF):Likewise
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types): Add 
bfloat16 type in riscv .
(riscv_fp16_builtin_type):Likewise
(riscv_bf16_builtin_type):Likewise
* config/riscv/riscv-modes.def (FLOAT_MODE):Likewise
(ADJUST_FLOAT_FORMAT):Likewise
* config/riscv/riscv-opts.h (MASK_ZFBFMIN):Add ZFBFMIN extension.
(TARGET_ZFBFMIN):
* config/riscv/riscv-vector-switch.def (ENTRY):
* config/riscv/riscv.cc (riscv_emit_float_compare):Add bfloat16 type in 
riscv .
(riscv_mangle_type):
(riscv_scalar_mode_supported_p):
(riscv_libgcc_floating_mode_supported_p):
(riscv_init_libfuncs):
* config/riscv/riscv.md (mode" ):Add bfloat16 type in riscv .
(truncdfhf2):
(truncsfbf2):
(truncdf2):
(extendbfsf2):
(extendhfdf2):
(extenddf2):
(movbf):
(*movbf_hardfloat):
(*movbf_softfloat):

libgcc\ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_B):Add bfloat16 type in riscv 
.
(_FP_NANSIGN_B):
* config/riscv/t-softfp32:

---
 gcc/common/config/riscv/riscv-common.cc  |  4 ++
 gcc/config/riscv/iterators.md| 21 +---
 gcc/config/riscv/riscv-builtins.cc   | 29 +-
 gcc/config/riscv/riscv-modes.def |  2 +
 gcc/config/riscv/riscv-opts.h|  2 +
 gcc/config/riscv/riscv-vector-switch.def |  4 +-
 gcc/config/riscv/riscv.cc| 37 +++--
 gcc/config/riscv/riscv.md| 69 
 libgcc/config/riscv/sfp-machine.h|  3 ++
 libgcc/config/riscv/t-softfp32   |  8 +--
 10 files changed, 150 insertions(+), 29 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index ebc1ed7d7e4..2b3ff1f5b8e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -102,6 +102,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvl32768b", "zvl16384b"},
   {"zvl65536b", "zvl32768b"},
 
+  {"zfbfmin", "zfhmin"},
+
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
   
@@ -1239,6 +1241,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl16384b", _options::x_riscv_zvl_flags, MASK_ZVL16384B},
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
+  
+  {"zfbfmin",_options::x_riscv_zf_subext, MASK_ZFBFMIN},
 
   {"zfhmin",_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   _options::x_riscv_zf_subext, MASK_ZFH},
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 5b70ab20758..6349f032bc8 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -61,10 +61,15 @@
 ;; Iterator for hardware-supported floating-point modes.
 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
(DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
-   (HF "TARGET_ZFH || TARGET_ZHINX")])
+   (HF "TARGET_ZFH || TARGET_ZHINX") 
+   (BF "TARGET_ZFBFMIN")])
+
+;; Iterator for HImode constant generation.
+(define_mode_iterator BFHF [BF HF])
 
 ;; Iterator for floating-point modes that can be loaded into X registers.
-(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
+(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")
+   (BF "TARGET_ZFBFMIN")])
 
 
 ;; ---
@@ -76,27 +81,27 @@
 (define_mode_attr size [(QI "b") (HI "h")])
 
 ;; Mode attributes for loads.
-(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (HF "flh") (SF 
"flw") (DF "fld")])
+(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (BF "flh") (HF 
"flh") (SF "flw") (DF "fld")])
 
 ;; Instruction names for integer loads that aren't explicitly sign or zero
 ;; extended.  See riscv_output_move and LOAD_EXTEND_OP.
 (define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
 
 ;; Mode attribute for FP loads into integer registers.
-(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
+(define_mode_attr softload [(BF "lh") (HF "lh") (SF "lw") (DF "ld")])
 
 ;; Instruction names for stores.
-(define_mode_attr store [(QI "sb") 

[PATCH V3 4/5] RISC-V: Implement ZKNH extension

[Liao Shihua]

This patch supports Zknh extension. 
It includes instruction's machine description and built-in funtions. 

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sha256sig0_): Add ZKNH's 
instructions.
(riscv_sha256sig1_):
(riscv_sha256sum0_):
(riscv_sha256sum1_):
(riscv_sha512sig0h):
(riscv_sha512sig0l):
(riscv_sha512sig1h):
(riscv_sha512sig1l):
(riscv_sha512sum0r):
(riscv_sha512sum1r):
(riscv_sha512sig0):
(riscv_sha512sig1):
(riscv_sha512sum0):
(riscv_sha512sum1):
* config/riscv/riscv-builtins.cc (AVAIL): And ZKNH's AVAIL.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): And ZKNH's 
built-in functions.
(DIRECT_BUILTIN):

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknh-sha256.c: New test.
* gcc.target/riscv/zknh-sha512-32.c: New test.
* gcc.target/riscv/zknh-sha512-64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md| 138 ++
 gcc/config/riscv/riscv-builtins.cc|   2 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  22 +++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  28 
 .../gcc.target/riscv/zknh-sha512-32.c |  42 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 
 6 files changed, 263 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 7568466ec97..17e7440c0b5 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
 UNSPEC_AES_ESM
 UNSPEC_AES_ESI
 UNSPEC_AES_ESMI
+
+;; Zknh unspecs
+UNSPEC_SHA_256_SIG0
+UNSPEC_SHA_256_SIG1
+UNSPEC_SHA_256_SUM0
+UNSPEC_SHA_256_SUM1
+UNSPEC_SHA_512_SIG0
+UNSPEC_SHA_512_SIG0H
+UNSPEC_SHA_512_SIG0L
+UNSPEC_SHA_512_SIG1
+UNSPEC_SHA_512_SIG1H
+UNSPEC_SHA_512_SIG1L
+UNSPEC_SHA_512_SUM0
+UNSPEC_SHA_512_SUM0R
+UNSPEC_SHA_512_SUM1
+UNSPEC_SHA_512_SUM1R
 ])
 
 ;; ZBKB extension
@@ -247,3 +263,125 @@
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64esm\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG1H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG1L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1l\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+

[PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions

[Liao Shihua]

This patch supports Zkbk, Zbkc and Zkbx extension. 
It includes instruction's machine description and built-in funtions. 
It is worth mentioning that this patch only adds instructions in Zbkb but no 
longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code 
generator instead of built-in functions.

gcc/ChangeLog:

* config/riscv/bitmanip.md: Add ZBKB's instructions.
* config/riscv/riscv-builtins.cc (AVAIL): 
* config/riscv/riscv.md:
* config/riscv/crypto.md: Add Scalar Cryptography extension's machine 
description file.
* config/riscv/riscv-scalar-crypto.def: Add Scalar Cryptography 
extension's built-in function file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbkb32.c: New test.
* gcc.target/riscv/zbkb64.c: New test.
* gcc.target/riscv/zbkc32.c: New test.
* gcc.target/riscv/zbkc64.c: New test.
* gcc.target/riscv/zbkx32.c: New test.
* gcc.target/riscv/zbkx64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/bitmanip.md |  20 ++--
 gcc/config/riscv/crypto.md   | 128 +++
 gcc/config/riscv/riscv-builtins.cc   |   7 ++
 gcc/config/riscv/riscv-scalar-crypto.def |  45 
 gcc/config/riscv/riscv.md|   4 +-
 gcc/testsuite/gcc.target/riscv/zbkb32.c  |  36 +++
 gcc/testsuite/gcc.target/riscv/zbkb64.c  |  28 +
 gcc/testsuite/gcc.target/riscv/zbkc32.c  |  17 +++
 gcc/testsuite/gcc.target/riscv/zbkc64.c  |  17 +++
 gcc/testsuite/gcc.target/riscv/zbkx32.c  |  18 
 gcc/testsuite/gcc.target/riscv/zbkx64.c  |  18 
 11 files changed, 327 insertions(+), 11 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-scalar-crypto.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 14d18edbe62..f076ba35832 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
 (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -203,7 +203,7 @@
   (const_int 0)))
(match_operand:DI 2 "register_operand")))
(clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (not:X (xor:X (match_operand:X 1 "register_operand" "r")
   (match_operand:X 2 "register_operand" "r"]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
(rotatert:DI (match_operand:DI 1 "register_operand" "r")
 (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "ror%i2\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -293,7 +293,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 (match_operand:QI 2 "register_operand" 
"r"]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rorw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -301,7 +301,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "r")
   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rol%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -309,7 +309,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
(rotate:DI (match_operand:DI 1 "register_operand" "r")
   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT 

[PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions

[Liao Shihua]

This patch supports Zkne and Zknd extension. 
It includes instruction's machine description and built-in funtions. 

gcc/ChangeLog:

* config/riscv/constraints.md (D03): Add constants of bs and rnum.
(DsA):
* config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's 
instructions.
(riscv_aes32dsmi):
(riscv_aes64ds):
(riscv_aes64dsm):
(riscv_aes64im):
(riscv_aes64ks1i):
(riscv_aes64ks2):
(riscv_aes32esi):
(riscv_aes32esmi):
(riscv_aes64es):
(riscv_aes64esm):
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL.
* config/riscv/riscv-scalar-crypto.def (DIRECT_BUILTIN): Add ZKND's and 
ZKNE's built-in functions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknd32.c: New test.
* gcc.target/riscv/zknd64.c: New test.
* gcc.target/riscv/zkne32.c: New test.
* gcc.target/riscv/zkne64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/constraints.md  |   8 ++
 gcc/config/riscv/crypto.md   | 121 +++
 gcc/config/riscv/riscv-builtins.cc   |   5 +
 gcc/config/riscv/riscv-scalar-crypto.def |  15 +++
 gcc/testsuite/gcc.target/riscv/zknd32.c  |  18 
 gcc/testsuite/gcc.target/riscv/zknd64.c  |  36 +++
 gcc/testsuite/gcc.target/riscv/zkne32.c  |  18 
 gcc/testsuite/gcc.target/riscv/zkne64.c  |  30 ++
 8 files changed, 251 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 3637380ee47..3f46f14b10f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -83,6 +83,14 @@
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
 
+(define_constraint "D03"
+  "0, 1, 2 or 3 immediate"
+  (match_test "IN_RANGE (ival, 0, 3)"))
+
+(define_constraint "DsA"
+  "0 - 10 immediate"
+  (match_test "IN_RANGE (ival, 0, 10)"))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index a270036e39b..7568466ec97 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -33,6 +33,21 @@
 ;; Zbkx unspecs
 UNSPEC_XPERM8
 UNSPEC_XPERM4
+
+;; Zknd unspecs
+UNSPEC_AES_DSI
+UNSPEC_AES_DSMI
+UNSPEC_AES_DS
+UNSPEC_AES_DSM
+UNSPEC_AES_IM
+UNSPEC_AES_KS1I
+UNSPEC_AES_KS2
+
+;; Zkne unspecs
+UNSPEC_AES_ES
+UNSPEC_AES_ESM
+UNSPEC_AES_ESI
+UNSPEC_AES_ESMI
 ])
 
 ;; ZBKB extension
@@ -126,3 +141,109 @@
   "TARGET_ZBKX"
   "xperm8\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKND extension
+
+(define_insn "riscv_aes32dsi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32dsmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSMI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ds"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 2 "register_operand" "r")]
+   UNSPEC_AES_DS))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64ds\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64dsm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 2 "register_operand" "r")]
+   UNSPEC_AES_DSM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64dsm\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64im"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+   UNSPEC_AES_IM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64im\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ks1i"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:SI 2 

[PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions

[Liao Shihua]

This patch adds prototypes for RISC-V Crypto built-in functions.

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
(RISCV_FTYPE_NAME3):
(RISCV_ATYPE_QI):
(RISCV_ATYPE_HI):
(RISCV_FTYPE_ATYPES2):
(RISCV_FTYPE_ATYPES3):
* config/riscv/riscv-ftypes.def (2):
(3):

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/riscv-builtins.cc |  8 
 gcc/config/riscv/riscv-ftypes.def  | 10 ++
 2 files changed, 18 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..ded91e17554 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,8 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -132,6 +134,8 @@ AVAIL (always, (!0))
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_QI intQI_type_node
+#define RISCV_ATYPE_HI intHI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
@@ -142,6 +146,10 @@ AVAIL (always, (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..3b518195a29 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, QI, QI))
+DEF_RISCV_FTYPE (2, (SI, HI, HI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, QI, QI))
+DEF_RISCV_FTYPE (2, (DI, HI, HI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
+DEF_RISCV_FTYPE (3, (DI, DI, DI, SI))
-- 
2.38.1.windows.1

[PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension

[Liao Shihua]

This series adds basic support for the Scalar Cryptography extensions:
* Zbkb
* Zbkc
* Zbkx
* Zknd
* Zkne
* Zknh
* Zksed
* Zksh

The implementation follows the version Scalar Cryptography v1.0.0 of the 
specification,
which can be found here:
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar

It works by Wu Siyu and Liao Shihua .
Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extension
  Implement ZKSH and ZKSED extensions

 gcc/config/riscv/bitmanip.md  |  20 +-
 gcc/config/riscv/constraints.md   |   8 +
 gcc/config/riscv/crypto.md| 435 ++
 gcc/config/riscv/riscv-builtins.cc|  26 ++
 gcc/config/riscv/riscv-ftypes.def |  10 +
 gcc/config/riscv/riscv-scalar-crypto.def  |  94 
 gcc/config/riscv/riscv.md |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c   |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  28 ++
 .../gcc.target/riscv/zknh-sha512-32.c |  42 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed32.c  |  19 +
 gcc/testsuite/gcc.target/riscv/zksed64.c  |  19 +
 gcc/testsuite/gcc.target/riscv/zksh32.c   |  19 +
 gcc/testsuite/gcc.target/riscv/zksh64.c   |  19 +
 24 files changed, 999 insertions(+), 11 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-scalar-crypto.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

-- 
2.38.1.windows.1

[PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions

[Liao Shihua]

This patch supports Zksh and Zksed extension. 
It includes instruction's machine description and built-in funtions. 

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSED's and ZKSH's 
instructions.
(riscv_sm3p1_):
(riscv_sm4ed_):
(riscv_sm4ks_):
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKSED's and ZKSH's AVAIL.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): Add ZKSED's and 
ZKSH's built-in functions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zksed32.c: New test.
* gcc.target/riscv/zksed64.c: New test.
* gcc.target/riscv/zksh32.c: New test.
* gcc.target/riscv/zksh64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md   | 48 
 gcc/config/riscv/riscv-builtins.cc   |  4 ++
 gcc/config/riscv/riscv-scalar-crypto.def | 12 ++
 gcc/testsuite/gcc.target/riscv/zksed32.c | 19 ++
 gcc/testsuite/gcc.target/riscv/zksed64.c | 19 ++
 gcc/testsuite/gcc.target/riscv/zksh32.c  | 19 ++
 gcc/testsuite/gcc.target/riscv/zksh64.c  | 19 ++
 7 files changed, 140 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 17e7440c0b5..777aa529005 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@
 UNSPEC_SHA_512_SUM0R
 UNSPEC_SHA_512_SUM1
 UNSPEC_SHA_512_SUM1R
+
+;; Zksh unspecs
+UNSPEC_SM3_P0
+UNSPEC_SM3_P1
+
+;; Zksed unspecs
+UNSPEC_SM4_ED
+UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -385,3 +393,43 @@
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
   [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED
+
+(define_insn "riscv_sm4ed_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index ab5bd52ee7f..390f8a38309 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always, (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def 
b/gcc/config/riscv/riscv-scalar-crypto.def
index d38aad122e5..139793c6360 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, 
crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI_SI, 

Re: Re: [PATCH V2 0/5] RISC-V: Implement Scalar Cryptography Extension

[shihua]

OK, I will send another one which remove riscv_scalar_crypto.h and update 
testcases with __builtin_riscv_XX


 -原始邮件-
 发件人: "Kito Cheng" 
 发送时间: 2023-02-16 21:28:34 (星期四)
 收件人: "Liao Shihua" 
 抄送: gcc-patches@gcc.gnu.org, jia...@iscas.ac.cn, m...@iki.fi, 
pal...@dabbelt.com, shiyul...@iscas.ac.cn, ben.marsh...@pqshield.com, 
christoph.muell...@vrull.eu
 主题: Re: [PATCH V2 0/5] RISC-V: Implement Scalar Cryptography Extension
 
 Hi Shihua:
 
 Thanks for your patches! This patch set is generally in good shape,
 but I would prefer to remove riscv_scalar_crypto.h at this moment
 since it's NOT standardized yet.
 
 Do you mind sending a new version of this patch set which does not
 include that and also update the testcases?
 
 
 
 On Thu, Feb 16, 2023 at 3:52 PM Liao Shihua  wrote:
 
  This series adds basic support for the Scalar Cryptography extensions:
  * Zbkb
  * Zbkc
  * Zbkx
  * Zknd
  * Zkne
  * Zknh
  * Zksed
  * Zksh
 
  The implementation follows the version Scalar Cryptography v1.0.0 of 
the specification,
  and the intrinsic of Scalar Cryptography extensions follows 
riscv-c-api
  which can be found here:
  https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar
  https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31
 
  It works by Wu Siyu and Liao Shihua .
 
  Liao Shihua (5):
Add prototypes for RISC-V Crypto built-in functions
Implement ZBKB, ZBKC and ZBKX extensions
Implement ZKND and ZKNE extensions
Implement ZKNH extensions
Implement ZKSH and ZKSED extensions
 
   gcc/config.gcc|   2 +-
   gcc/config/riscv/bitmanip.md  |  20 +-
   gcc/config/riscv/constraints.md   |   8 +
   gcc/config/riscv/crypto.md| 435 
++
   gcc/config/riscv/riscv-builtins.cc|  26 ++
   gcc/config/riscv/riscv-crypto.def |  94 
   gcc/config/riscv/riscv-ftypes.def |  10 +
   gcc/config/riscv/riscv.md |   4 +-
   gcc/config/riscv/riscv_scalar_crypto.h| 218 +
   gcc/testsuite/gcc.target/riscv/zbkb32.c   |  36 ++
   gcc/testsuite/gcc.target/riscv/zbkb64.c   |  28 ++
   gcc/testsuite/gcc.target/riscv/zbkc32.c   |  17 +
   gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 +
   gcc/testsuite/gcc.target/riscv/zbkx32.c   |  18 +
   gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 +
   gcc/testsuite/gcc.target/riscv/zknd32.c   |  18 +
   gcc/testsuite/gcc.target/riscv/zknd64.c   |  36 ++
   gcc/testsuite/gcc.target/riscv/zkne32.c   |  18 +
   gcc/testsuite/gcc.target/riscv/zkne64.c   |  30 ++
   gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++
   .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
   .../gcc.target/riscv/zknh-sha512-64.c |  31 ++
   gcc/testsuite/gcc.target/riscv/zksed.c|  20 +
   gcc/testsuite/gcc.target/riscv/zksh.c |  19 +
   24 files changed, 1183 insertions(+), 12 deletions(-)
   create mode 100644 gcc/config/riscv/crypto.md
   create mode 100644 gcc/config/riscv/riscv-crypto.def
   create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
   create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
   create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c
 
  --
  2.38.1.windows.1
 

[PATCH V2 2/5] Implement ZBKB, ZBKC and ZBKX extensions

[Liao Shihua]

This patch support Zkbk, Zbkc and Zkbx extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 
It is worth mentioning that this patch only adds instructions in Zbkb but no 
longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code 
generator instead of built-in functions and intrinsics.

gcc/ChangeLog:

* config.gcc: Add intrinsics header in extra_headers.
* config/riscv/bitmanip.md: Add TARGET_ZBKB if these instructions are 
included in ZBKB extension.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZBKB's,ZBKC's,ZBKX's 
AVAIL. 
* config/riscv/riscv.md: include crypto.md.
* config/riscv/crypto.md: Scalar Cryptography Machine description file.
* config/riscv/riscv-crypto.def: Scalar Cryptography built-in function 
file.
* config/riscv/riscv_scalar_crypto.h: Scalar Cryptography intrinsics 
header.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbkb32.c: New test.
* gcc.target/riscv/zbkb64.c: New test.
* gcc.target/riscv/zbkc32.c: New test.
* gcc.target/riscv/zbkc64.c: New test.
* gcc.target/riscv/zbkx32.c: New test.
* gcc.target/riscv/zbkx64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config.gcc  |   2 +-
 gcc/config/riscv/bitmanip.md|  20 ++--
 gcc/config/riscv/crypto.md  | 130 
 gcc/config/riscv/riscv-builtins.cc  |   7 ++
 gcc/config/riscv/riscv-crypto.def   |  45 
 gcc/config/riscv/riscv.md   |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h  | 104 +++
 gcc/testsuite/gcc.target/riscv/zbkb32.c |  36 +++
 gcc/testsuite/gcc.target/riscv/zbkb64.c |  28 +
 gcc/testsuite/gcc.target/riscv/zbkc32.c |  17 
 gcc/testsuite/gcc.target/riscv/zbkc64.c |  17 
 gcc/testsuite/gcc.target/riscv/zbkx32.c |  18 
 gcc/testsuite/gcc.target/riscv/zbkx64.c |  18 
 13 files changed, 434 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0958e1c959..951b92b2028 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ riscv*)
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_scalar_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 14d18edbe62..f076ba35832 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
 (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -203,7 +203,7 @@
   (const_int 0)))
(match_operand:DI 2 "register_operand")))
(clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (not:X (xor:X (match_operand:X 1 "register_operand" "r")
   (match_operand:X 2 "register_operand" "r"]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
(rotatert:DI (match_operand:DI 1 "register_operand" "r")
 

[PATCH V2 4/5] Implement ZKNH extensions

[Liao Shihua]

This patch support Zknh extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's 
instructions.
(riscv_sha256sig1_): Likewise.
(riscv_sha256sum0_): Likewise.
(riscv_sha256sum1_): Likewise.
(riscv_sha512sig0h): Likewise.
(riscv_sha512sig0l): Likewise.
(riscv_sha512sig1h): Likewise.
(riscv_sha512sig1l): Likewise.
(riscv_sha512sum0r): Likewise.
(riscv_sha512sum1r): Likewise.
(riscv_sha512sig0): Likewise.
(riscv_sha512sig1): Likewise.
(riscv_sha512sum0): Likewise.
(riscv_sha512sum1): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL.
* config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in 
functions.
(DIRECT_BUILTIN): Likewise.
* config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's 
intrinsics.
(__riscv_sha256sig1): Likewise.
(__riscv_sha256sum0): Likewise.
(__riscv_sha256sum1): Likewise.
(__riscv_sha512sig0h): Likewise.
(__riscv_sha512sig0l): Likewise.
(__riscv_sha512sig1h): Likewise.
(__riscv_sha512sig1l): Likewise.
(__riscv_sha512sum0r): Likewise.
(__riscv_sha512sum1r): Likewise.
(__riscv_sha512sig0): Likewise.
(__riscv_sha512sig1): Likewise.
(__riscv_sha512sum0): Likewise.
(__riscv_sha512sum1): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknh-sha256.c: New test.
* gcc.target/riscv/zknh-sha512-32.c: New test.
* gcc.target/riscv/zknh-sha512-64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md| 138 ++
 gcc/config/riscv/riscv-builtins.cc|   2 +
 gcc/config/riscv/riscv-crypto.def |  22 +++
 gcc/config/riscv/riscv_scalar_crypto.h|  48 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 
 .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 
 7 files changed, 313 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index d76a872775f..063a8025f20 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
 UNSPEC_AES_ESM
 UNSPEC_AES_ESI
 UNSPEC_AES_ESMI
+
+;; ZKNH unspecs
+UNSPEC_SHA_256_SIG0
+UNSPEC_SHA_256_SIG1
+UNSPEC_SHA_256_SUM0
+UNSPEC_SHA_256_SUM1
+UNSPEC_SHA_512_SIG0
+UNSPEC_SHA_512_SIG0H
+UNSPEC_SHA_512_SIG0L
+UNSPEC_SHA_512_SIG1
+UNSPEC_SHA_512_SIG1H
+UNSPEC_SHA_512_SIG1L
+UNSPEC_SHA_512_SUM0
+UNSPEC_SHA_512_SUM0R
+UNSPEC_SHA_512_SUM1
+UNSPEC_SHA_512_SUM1R
 ])
 
 ;; ZBKB extension
@@ -247,3 +263,125 @@
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64esm\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2"
+  [(set_attr "type" 

[PATCH V2 3/5] Implement ZKND and ZKNE extensions

[Liao Shihua]

This patch support Zkne and Zknd extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 

gcc/ChangeLog:

* config/riscv/constraints.md (D03): New constraints of bs.
(DsA):New constraints of rnum.
* config/riscv/crypto.md (riscv_aes32dsi):Add ZKND,ZKNE instructions.
(riscv_aes32dsmi): Likewise.
(riscv_aes64ds): Likewise.
(riscv_aes64dsm): Likewise.
(riscv_aes64im): Likewise.
(riscv_aes64ks1i): Likewise.
(riscv_aes64ks2): Likewise.
(riscv_aes32esi): Likewise.
(riscv_aes32esmi): Likewise.
(riscv_aes64es): Likewise.
(riscv_aes64esm): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL. 
* config/riscv/riscv-crypto.def (DIRECT_BUILTIN):Add ZKND's and ZKNE's 
built-in functions. 
* config/riscv/riscv_scalar_crypto.h (__riscv_aes32dsi):Add ZKND's and 
ZKNE's intrinsics. 
(__riscv_aes32dsmi): Likewise.
(__riscv_aes64ds): Likewise.
(__riscv_aes64dsm): Likewise.
(__riscv_aes64im): Likewise.
(__riscv_aes64ks1i): Likewise.
(__riscv_aes64ks2): Likewise.
(__riscv_aes32esi): Likewise.
(__riscv_aes32esmi): Likewise.
(__riscv_aes64es): Likewise.
(__riscv_aes64esm): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknd32.c: New test.
* gcc.target/riscv/zknd64.c: New test.
* gcc.target/riscv/zkne32.c: New test.
* gcc.target/riscv/zkne64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/constraints.md |   8 ++
 gcc/config/riscv/crypto.md  | 121 +++-
 gcc/config/riscv/riscv-builtins.cc  |   5 +
 gcc/config/riscv/riscv-crypto.def   |  15 +++
 gcc/config/riscv/riscv_scalar_crypto.h  |  46 +
 gcc/testsuite/gcc.target/riscv/zknd32.c |  18 
 gcc/testsuite/gcc.target/riscv/zknd64.c |  36 +++
 gcc/testsuite/gcc.target/riscv/zkne32.c |  18 
 gcc/testsuite/gcc.target/riscv/zkne64.c |  30 ++
 9 files changed, 296 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 3637380ee47..3f46f14b10f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -83,6 +83,14 @@
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
 
+(define_constraint "D03"
+  "0, 1, 2 or 3 immediate"
+  (match_test "IN_RANGE (ival, 0, 3)"))
+
+(define_constraint "DsA"
+  "0 - 10 immediate"
+  (match_test "IN_RANGE (ival, 0, 10)"))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 6792f19ed68..d76a872775f 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -34,7 +34,20 @@
 UNSPEC_XPERM8
 UNSPEC_XPERM4
 
-
+;; ZKND unspecs
+UNSPEC_AES_DSI
+UNSPEC_AES_DSMI
+UNSPEC_AES_DS
+UNSPEC_AES_DSM
+UNSPEC_AES_IM
+UNSPEC_AES_KS1I
+UNSPEC_AES_KS2
+
+;; ZKNE unspecs
+UNSPEC_AES_ES
+UNSPEC_AES_ESM
+UNSPEC_AES_ESI
+UNSPEC_AES_ESMI
 ])
 
 ;; ZBKB extension
@@ -128,3 +141,109 @@
   "TARGET_ZBKX"
   "xperm8\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKND extension
+
+(define_insn "riscv_aes32dsi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32dsmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSMI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ds"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 2 "register_operand" "r")]
+   UNSPEC_AES_DS))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64ds\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64dsm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 

[PATCH V2 0/5] RISC-V: Implement Scalar Cryptography Extension

[Liao Shihua]

This series adds basic support for the Scalar Cryptography extensions:
* Zbkb
* Zbkc
* Zbkx
* Zknd
* Zkne
* Zknh
* Zksed
* Zksh

The implementation follows the version Scalar Cryptography v1.0.0 of the 
specification,
and the intrinsic of Scalar Cryptography extensions follows riscv-c-api
which can be found here:
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31

It works by Wu Siyu and Liao Shihua .

Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extensions
  Implement ZKSH and ZKSED extensions

 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  20 +-
 gcc/config/riscv/constraints.md   |   8 +
 gcc/config/riscv/crypto.md| 435 ++
 gcc/config/riscv/riscv-builtins.cc|  26 ++
 gcc/config/riscv/riscv-crypto.def |  94 
 gcc/config/riscv/riscv-ftypes.def |  10 +
 gcc/config/riscv/riscv.md |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h| 218 +
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c   |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++
 .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed.c|  20 +
 gcc/testsuite/gcc.target/riscv/zksh.c |  19 +
 24 files changed, 1183 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

-- 
2.38.1.windows.1

[PATCH V2 5/5] Implement ZKSH and ZKSED extensions

[Liao Shihua]

This patch support Zksh and Zksed extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSH's and ZKSED's 
instructions.
(riscv_sm3p1_): Likewise.
(riscv_sm4ed_): Likewise.
(riscv_sm4ks_): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKSH's and ZKSED's AVAIL.
* config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKSH's and ZKSED's 
built-in functions.
* config/riscv/riscv_scalar_crypto.h (__riscv_sm4ks): Add ZKSH's and 
ZKSED's intrinsics.
(__riscv_sm4ed): Likewise.
(__riscv_sm3p0): Likewise.
(__riscv_sm3p1): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zksed.c: New test.
* gcc.target/riscv/zksh.c: New test.


Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md | 50 +-
 gcc/config/riscv/riscv-builtins.cc |  4 +++
 gcc/config/riscv/riscv-crypto.def  | 12 +++
 gcc/config/riscv/riscv_scalar_crypto.h | 20 +++
 gcc/testsuite/gcc.target/riscv/zksed.c | 20 +++
 gcc/testsuite/gcc.target/riscv/zksh.c  | 19 ++
 6 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 063a8025f20..e28bdd91078 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@
 UNSPEC_SHA_512_SUM0R
 UNSPEC_SHA_512_SUM1
 UNSPEC_SHA_512_SUM1R
+
+;; ZKSH unspecs
+UNSPEC_SM3_P0
+UNSPEC_SM3_P1
+
+;; ZKSED unspecs
+UNSPEC_SM4_ED
+UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -384,4 +392,44 @@
UNSPEC_SHA_512_SUM1))]
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
-  [(set_attr "type" "crypto")])
\ No newline at end of file
+  [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED
+
+(define_insn "riscv_sm4ed_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 2a35167e6fb..18c0cce6b8b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always, (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def 
b/gcc/config/riscv/riscv-crypto.def
index 831ab8c0d01..7774b801aec 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, 
crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", 

[PATCH V2 1/5] Add prototypes for RISC-V Crypto built-in functions

[Liao Shihua]

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New enumeration 
identifier.
(RISCV_FTYPE_NAME3): Likewise.
(RISCV_ATYPE_QI): New Argument types.
(RISCV_ATYPE_HI): Likewise.
(RISCV_FTYPE_ATYPES2): New RISCV_ATYPE.
(RISCV_FTYPE_ATYPES3): Likewise.
* config/riscv/riscv-ftypes.def (2): New Definitions of prototypes.
(3):Likewise

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/riscv-builtins.cc |  8 
 gcc/config/riscv/riscv-ftypes.def  | 10 ++
 2 files changed, 18 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..ded91e17554 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,8 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -132,6 +134,8 @@ AVAIL (always, (!0))
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_QI intQI_type_node
+#define RISCV_ATYPE_HI intHI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
@@ -142,6 +146,10 @@ AVAIL (always, (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..3b518195a29 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, QI, QI))
+DEF_RISCV_FTYPE (2, (SI, HI, HI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, QI, QI))
+DEF_RISCV_FTYPE (2, (DI, HI, HI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
+DEF_RISCV_FTYPE (3, (DI, DI, DI, SI))
-- 
2.38.1.windows.1

[PATCH V2 2/5] Implement ZBKB, ZBKC and ZBKX extensions

[Liao Shihua]

This patch support Zkbk, Zbkc and Zkbx extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 
It is worth mentioning that this patch only adds instructions in Zbkb but no 
longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code 
generator instead of built-in functions and intrinsics.

gcc/ChangeLog:

* config.gcc: Add intrinsics header in extra_headers.
* config/riscv/bitmanip.md: Add TARGET_ZBKB if these instructions are 
included in ZBKB extension.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZBKB's,ZBKC's,ZBKX's 
AVAIL. 
* config/riscv/riscv.md: include crypto.md.
* config/riscv/crypto.md: Scalar Cryptography Machine description file.
* config/riscv/riscv-crypto.def: Scalar Cryptography built-in function 
file.
* config/riscv/riscv_scalar_crypto.h: Scalar Cryptography intrinsics 
header.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbkb32.c: New test.
* gcc.target/riscv/zbkb64.c: New test.
* gcc.target/riscv/zbkc32.c: New test.
* gcc.target/riscv/zbkc64.c: New test.
* gcc.target/riscv/zbkx32.c: New test.
* gcc.target/riscv/zbkx64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config.gcc  |   2 +-
 gcc/config/riscv/bitmanip.md|  20 ++--
 gcc/config/riscv/crypto.md  | 130 
 gcc/config/riscv/riscv-builtins.cc  |   7 ++
 gcc/config/riscv/riscv-crypto.def   |  45 
 gcc/config/riscv/riscv.md   |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h  | 104 +++
 gcc/testsuite/gcc.target/riscv/zbkb32.c |  36 +++
 gcc/testsuite/gcc.target/riscv/zbkb64.c |  28 +
 gcc/testsuite/gcc.target/riscv/zbkc32.c |  17 
 gcc/testsuite/gcc.target/riscv/zbkc64.c |  17 
 gcc/testsuite/gcc.target/riscv/zbkx32.c |  18 
 gcc/testsuite/gcc.target/riscv/zbkx64.c |  18 
 13 files changed, 434 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0958e1c959..951b92b2028 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ riscv*)
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_scalar_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 14d18edbe62..f076ba35832 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
 (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -203,7 +203,7 @@
   (const_int 0)))
(match_operand:DI 2 "register_operand")))
(clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (not:X (xor:X (match_operand:X 1 "register_operand" "r")
   (match_operand:X 2 "register_operand" "r"]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
(rotatert:DI (match_operand:DI 1 "register_operand" "r")
 

[PATCH V2 4/5] Implement ZKNH extensions

[Liao Shihua]

This patch support Zknh extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's 
instructions.
(riscv_sha256sig1_): Likewise.
(riscv_sha256sum0_): Likewise.
(riscv_sha256sum1_): Likewise.
(riscv_sha512sig0h): Likewise.
(riscv_sha512sig0l): Likewise.
(riscv_sha512sig1h): Likewise.
(riscv_sha512sig1l): Likewise.
(riscv_sha512sum0r): Likewise.
(riscv_sha512sum1r): Likewise.
(riscv_sha512sig0): Likewise.
(riscv_sha512sig1): Likewise.
(riscv_sha512sum0): Likewise.
(riscv_sha512sum1): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL.
* config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in 
functions.
(DIRECT_BUILTIN): Likewise.
* config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's 
intrinsics.
(__riscv_sha256sig1): Likewise.
(__riscv_sha256sum0): Likewise.
(__riscv_sha256sum1): Likewise.
(__riscv_sha512sig0h): Likewise.
(__riscv_sha512sig0l): Likewise.
(__riscv_sha512sig1h): Likewise.
(__riscv_sha512sig1l): Likewise.
(__riscv_sha512sum0r): Likewise.
(__riscv_sha512sum1r): Likewise.
(__riscv_sha512sig0): Likewise.
(__riscv_sha512sig1): Likewise.
(__riscv_sha512sum0): Likewise.
(__riscv_sha512sum1): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknh-sha256.c: New test.
* gcc.target/riscv/zknh-sha512-32.c: New test.
* gcc.target/riscv/zknh-sha512-64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md| 138 ++
 gcc/config/riscv/riscv-builtins.cc|   2 +
 gcc/config/riscv/riscv-crypto.def |  22 +++
 gcc/config/riscv/riscv_scalar_crypto.h|  48 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 
 .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 
 7 files changed, 313 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index d76a872775f..063a8025f20 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
 UNSPEC_AES_ESM
 UNSPEC_AES_ESI
 UNSPEC_AES_ESMI
+
+;; ZKNH unspecs
+UNSPEC_SHA_256_SIG0
+UNSPEC_SHA_256_SIG1
+UNSPEC_SHA_256_SUM0
+UNSPEC_SHA_256_SUM1
+UNSPEC_SHA_512_SIG0
+UNSPEC_SHA_512_SIG0H
+UNSPEC_SHA_512_SIG0L
+UNSPEC_SHA_512_SIG1
+UNSPEC_SHA_512_SIG1H
+UNSPEC_SHA_512_SIG1L
+UNSPEC_SHA_512_SUM0
+UNSPEC_SHA_512_SUM0R
+UNSPEC_SHA_512_SUM1
+UNSPEC_SHA_512_SUM1R
 ])
 
 ;; ZBKB extension
@@ -247,3 +263,125 @@
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64esm\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2"
+  [(set_attr "type" 

[PATCH V2 0/5] RISC-V: Implement Scalar Cryptography Extension

[Liao Shihua]

This series adds basic support for the Scalar Cryptography extensions:
* Zbkb
* Zbkc
* Zbkx
* Zknd
* Zkne
* Zknh
* Zksed
* Zksh

The implementation follows the version Scalar Cryptography v1.0.0 of the 
specification,
and the intrinsic of Scalar Cryptography extensions follows riscv-c-api
which can be found here:
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31

It works by Wu Siyu and Liao Shihua .

Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extensions
  Implement ZKSH and ZKSED extensions

 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  20 +-
 gcc/config/riscv/constraints.md   |   8 +
 gcc/config/riscv/crypto.md| 435 ++
 gcc/config/riscv/riscv-builtins.cc|  26 ++
 gcc/config/riscv/riscv-crypto.def |  94 
 gcc/config/riscv/riscv-ftypes.def |  10 +
 gcc/config/riscv/riscv.md |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h| 218 +
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c   |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++
 .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed.c|  20 +
 gcc/testsuite/gcc.target/riscv/zksh.c |  19 +
 24 files changed, 1183 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

-- 
2.38.1.windows.1

[PATCH V2 5/5] Implement ZKSH and ZKSED extensions

[Liao Shihua]

This patch support Zksh and Zksed extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSH's and ZKSED's 
instructions.
(riscv_sm3p1_): Likewise.
(riscv_sm4ed_): Likewise.
(riscv_sm4ks_): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKSH's and ZKSED's AVAIL.
* config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKSH's and ZKSED's 
built-in functions.
* config/riscv/riscv_scalar_crypto.h (__riscv_sm4ks): Add ZKSH's and 
ZKSED's intrinsics.
(__riscv_sm4ed): Likewise.
(__riscv_sm3p0): Likewise.
(__riscv_sm3p1): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zksed.c: New test.
* gcc.target/riscv/zksh.c: New test.


Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md | 50 +-
 gcc/config/riscv/riscv-builtins.cc |  4 +++
 gcc/config/riscv/riscv-crypto.def  | 12 +++
 gcc/config/riscv/riscv_scalar_crypto.h | 20 +++
 gcc/testsuite/gcc.target/riscv/zksed.c | 20 +++
 gcc/testsuite/gcc.target/riscv/zksh.c  | 19 ++
 6 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 063a8025f20..e28bdd91078 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@
 UNSPEC_SHA_512_SUM0R
 UNSPEC_SHA_512_SUM1
 UNSPEC_SHA_512_SUM1R
+
+;; ZKSH unspecs
+UNSPEC_SM3_P0
+UNSPEC_SM3_P1
+
+;; ZKSED unspecs
+UNSPEC_SM4_ED
+UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -384,4 +392,44 @@
UNSPEC_SHA_512_SUM1))]
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
-  [(set_attr "type" "crypto")])
\ No newline at end of file
+  [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED
+
+(define_insn "riscv_sm4ed_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 2a35167e6fb..18c0cce6b8b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always, (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def 
b/gcc/config/riscv/riscv-crypto.def
index 831ab8c0d01..7774b801aec 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, 
crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", 

[PATCH V2 3/5] Implement ZKND and ZKNE extensions

[Liao Shihua]

This patch support Zkne and Zknd extension. 
It includes instruction's machine description, built-in funtion, and 
intrinsics. 

gcc/ChangeLog:

* config/riscv/constraints.md (D03): New constraints of bs.
(DsA):New constraints of rnum.
* config/riscv/crypto.md (riscv_aes32dsi):Add ZKND,ZKNE instructions.
(riscv_aes32dsmi): Likewise.
(riscv_aes64ds): Likewise.
(riscv_aes64dsm): Likewise.
(riscv_aes64im): Likewise.
(riscv_aes64ks1i): Likewise.
(riscv_aes64ks2): Likewise.
(riscv_aes32esi): Likewise.
(riscv_aes32esmi): Likewise.
(riscv_aes64es): Likewise.
(riscv_aes64esm): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL. 
* config/riscv/riscv-crypto.def (DIRECT_BUILTIN):Add ZKND's and ZKNE's 
built-in functions. 
* config/riscv/riscv_scalar_crypto.h (__riscv_aes32dsi):Add ZKND's and 
ZKNE's intrinsics. 
(__riscv_aes32dsmi): Likewise.
(__riscv_aes64ds): Likewise.
(__riscv_aes64dsm): Likewise.
(__riscv_aes64im): Likewise.
(__riscv_aes64ks1i): Likewise.
(__riscv_aes64ks2): Likewise.
(__riscv_aes32esi): Likewise.
(__riscv_aes32esmi): Likewise.
(__riscv_aes64es): Likewise.
(__riscv_aes64esm): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknd32.c: New test.
* gcc.target/riscv/zknd64.c: New test.
* gcc.target/riscv/zkne32.c: New test.
* gcc.target/riscv/zkne64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/constraints.md |   8 ++
 gcc/config/riscv/crypto.md  | 121 +++-
 gcc/config/riscv/riscv-builtins.cc  |   5 +
 gcc/config/riscv/riscv-crypto.def   |  15 +++
 gcc/config/riscv/riscv_scalar_crypto.h  |  46 +
 gcc/testsuite/gcc.target/riscv/zknd32.c |  18 
 gcc/testsuite/gcc.target/riscv/zknd64.c |  36 +++
 gcc/testsuite/gcc.target/riscv/zkne32.c |  18 
 gcc/testsuite/gcc.target/riscv/zkne64.c |  30 ++
 9 files changed, 296 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 3637380ee47..3f46f14b10f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -83,6 +83,14 @@
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
 
+(define_constraint "D03"
+  "0, 1, 2 or 3 immediate"
+  (match_test "IN_RANGE (ival, 0, 3)"))
+
+(define_constraint "DsA"
+  "0 - 10 immediate"
+  (match_test "IN_RANGE (ival, 0, 10)"))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 6792f19ed68..d76a872775f 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -34,7 +34,20 @@
 UNSPEC_XPERM8
 UNSPEC_XPERM4
 
-
+;; ZKND unspecs
+UNSPEC_AES_DSI
+UNSPEC_AES_DSMI
+UNSPEC_AES_DS
+UNSPEC_AES_DSM
+UNSPEC_AES_IM
+UNSPEC_AES_KS1I
+UNSPEC_AES_KS2
+
+;; ZKNE unspecs
+UNSPEC_AES_ES
+UNSPEC_AES_ESM
+UNSPEC_AES_ESI
+UNSPEC_AES_ESMI
 ])
 
 ;; ZBKB extension
@@ -128,3 +141,109 @@
   "TARGET_ZBKX"
   "xperm8\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKND extension
+
+(define_insn "riscv_aes32dsi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32dsmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSMI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ds"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 2 "register_operand" "r")]
+   UNSPEC_AES_DS))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64ds\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64dsm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 

[PATCH 1/5] Add prototypes for RISC-V Crypto built-in functions

[Liao Shihua]

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/riscv-builtins.cc |  8 
 gcc/config/riscv/riscv-ftypes.def  | 10 ++
 2 files changed, 18 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..ded91e17554 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,8 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -132,6 +134,8 @@ AVAIL (always, (!0))
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_QI intQI_type_node
+#define RISCV_ATYPE_HI intHI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
@@ -142,6 +146,10 @@ AVAIL (always, (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..3b518195a29 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, QI, QI))
+DEF_RISCV_FTYPE (2, (SI, HI, HI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, QI, QI))
+DEF_RISCV_FTYPE (2, (DI, HI, HI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
+DEF_RISCV_FTYPE (3, (DI, DI, DI, SI))
-- 
2.38.1.windows.1

[PATCH 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions

[Liao Shihua]

   Implement ZBKB, ZBKC and ZBKX extensions. 
   ZBKB is Bitmanip instructions for Cryptography.
   ZBKC is Carry-less multiply instructions.
   ZBKX is Crossbar permutation instructions.
   Only add Machine description and intrinsics of these instructions which are 
not defined in the first Bitmanip ratification package.
   If them defined in Bitmanip extension, it will generate by Manchine 
description in bitmanip.md.

gcc/ChangeLog:

* config.gcc: Add intrinsics header in extra_headers.
* config/riscv/bitmanip.md: Add TARGET_ZBKB if these instructions are 
included in ZBKB extension.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZBKB's,ZBKC's,ZBKX's 
AVAIL. 
* config/riscv/riscv.md: include crypto.md.
* config/riscv/crypto.md: Scalar Cryptography Machine description file.
* config/riscv/riscv-crypto.def: Scalar Cryptography built-in function 
file.
* config/riscv/riscv_scalar_crypto.h: Scalar Cryptography intrinsics 
header.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbkb32.c: New test.
* gcc.target/riscv/zbkb64.c: New test.
* gcc.target/riscv/zbkc32.c: New test.
* gcc.target/riscv/zbkc64.c: New test.
* gcc.target/riscv/zbkx32.c: New test.
* gcc.target/riscv/zbkx64.c: New test.

---
 gcc/config.gcc  |   2 +-
 gcc/config/riscv/bitmanip.md|  20 ++--
 gcc/config/riscv/crypto.md  | 133 
 gcc/config/riscv/riscv-builtins.cc  |   7 ++
 gcc/config/riscv/riscv-crypto.def   |  46 
 gcc/config/riscv/riscv.md   |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h  | 106 +++
 gcc/testsuite/gcc.target/riscv/zbkb32.c |  36 +++
 gcc/testsuite/gcc.target/riscv/zbkb64.c |  28 +
 gcc/testsuite/gcc.target/riscv/zbkc32.c |  18 
 gcc/testsuite/gcc.target/riscv/zbkc64.c |  17 +++
 gcc/testsuite/gcc.target/riscv/zbkx32.c |  19 
 gcc/testsuite/gcc.target/riscv/zbkx64.c |  18 
 13 files changed, 442 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0958e1c959..951b92b2028 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ riscv*)
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_scalar_crypto.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 14d18edbe62..f076ba35832 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
 (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -203,7 +203,7 @@
   (const_int 0)))
(match_operand:DI 2 "register_operand")))
(clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
 (not:X (xor:X (match_operand:X 1 "register_operand" "r")
   (match_operand:X 2 "register_operand" "r"]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
(rotatert:DI (match_operand:DI 1 

[PATCH 3/5] RISC-V: Implement ZKND and ZKNE extensions

[Liao Shihua]

  Implement ZKND and ZKNE extensions.
  ZKND is NIST Suite: AES Decryption.
  ZKNE is NIST Suite: AES Encryption.
  
gcc/ChangeLog:

* config/riscv/constraints.md (D03): New constraints of bs.
(DsA):New constraints of rnum.
* config/riscv/crypto.md (riscv_aes32dsi):Add ZKND,ZKNE instructions.
(riscv_aes32dsmi): Likewise.
(riscv_aes64ds): Likewise.
(riscv_aes64dsm): Likewise.
(riscv_aes64im): Likewise.
(riscv_aes64ks1i): Likewise.
(riscv_aes64ks2): Likewise.
(riscv_aes32esi): Likewise.
(riscv_aes32esmi): Likewise.
(riscv_aes64es): Likewise.
(riscv_aes64esm): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL. 
* config/riscv/riscv-crypto.def (DIRECT_BUILTIN):Add ZKND's and ZKNE's 
built-in functions. 
* config/riscv/riscv_scalar_crypto.h (__riscv_aes32dsi):Add ZKND's and 
ZKNE's intrinsics. 
(__riscv_aes32dsmi): Likewise.
(__riscv_aes64ds): Likewise.
(__riscv_aes64dsm): Likewise.
(__riscv_aes64im): Likewise.
(__riscv_aes64ks1i): Likewise.
(__riscv_aes64ks2): Likewise.
(__riscv_aes32esi): Likewise.
(__riscv_aes32esmi): Likewise.
(__riscv_aes64es): Likewise.
(__riscv_aes64esm): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknd32.c: New test.
* gcc.target/riscv/zknd64.c: New test.
* gcc.target/riscv/zkne32.c: New test.
* gcc.target/riscv/zkne64.c: New test.

---
 gcc/config/riscv/constraints.md |   8 ++
 gcc/config/riscv/crypto.md  | 120 +++-
 gcc/config/riscv/riscv-builtins.cc  |   5 +
 gcc/config/riscv/riscv-crypto.def   |  15 +++
 gcc/config/riscv/riscv_scalar_crypto.h  |  45 +
 gcc/testsuite/gcc.target/riscv/zknd32.c |  18 
 gcc/testsuite/gcc.target/riscv/zknd64.c |  36 +++
 gcc/testsuite/gcc.target/riscv/zkne32.c |  18 
 gcc/testsuite/gcc.target/riscv/zkne64.c |  30 ++
 9 files changed, 294 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 3637380ee47..3f46f14b10f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -83,6 +83,14 @@
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
 
+(define_constraint "D03"
+  "0, 1, 2 or 3 immediate"
+  (match_test "IN_RANGE (ival, 0, 3)"))
+
+(define_constraint "DsA"
+  "0 - 10 immediate"
+  (match_test "IN_RANGE (ival, 0, 10)"))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 048db920bb6..a97fd398217 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -34,7 +34,20 @@
 UNSPEC_XPERM8
 UNSPEC_XPERM4
 
-
+;; ZKND unspecs
+UNSPEC_AES_DSI
+UNSPEC_AES_DSMI
+UNSPEC_AES_DS
+UNSPEC_AES_DSM
+UNSPEC_AES_IM
+UNSPEC_AES_KS1I
+UNSPEC_AES_KS2
+
+;; ZKNE unspecs
+UNSPEC_AES_ES
+UNSPEC_AES_ESM
+UNSPEC_AES_ESI
+UNSPEC_AES_ESMI
 ])
 
 ;; ZBKB extension
@@ -129,5 +142,110 @@
   "xperm8\t%0,%1,%2"
   [(set_attr "type" "crypto")])
 
+;; ZKND extension
+
+(define_insn "riscv_aes32dsi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32dsmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")
+   (match_operand:SI 3 "register_operand" "D03")]
+   UNSPEC_AES_DSMI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ds"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 2 "register_operand" "r")]
+   UNSPEC_AES_DS))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64ds\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64dsm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+   (match_operand:DI 2 "register_operand" "r")]
+  

[PATCH 5/5] RISC-V: Implement ZKSH and ZKSED extensions

[Liao Shihua]

  Implement ZKSH and ZKSED extensions.
  ZKSH  is  ShangMi Suite: SM3 Hash Function Instructions.
  ZKSED is ShangMi Suite: SM4 Block Cipher Instructions.

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSH's and ZKSED's 
instructions.
(riscv_sm3p1_): Likewise.
(riscv_sm4ed_): Likewise.
(riscv_sm4ks_): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKSH's and ZKSED's AVAIL.
* config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKSH's and ZKSED's 
built-in functions.
* config/riscv/riscv_scalar_crypto.h (__riscv_sm4ks): Add ZKSH's and 
ZKSED's intrinsics.
(__riscv_sm4ed): Likewise.
(__riscv_sm3p0): Likewise.
(__riscv_sm3p1): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zksed.c: New test.
* gcc.target/riscv/zksh.c: New test.
---
 gcc/config/riscv/crypto.md | 48 ++
 gcc/config/riscv/riscv-builtins.cc |  4 +++
 gcc/config/riscv/riscv-crypto.def  | 12 +++
 gcc/config/riscv/riscv_scalar_crypto.h | 19 ++
 gcc/testsuite/gcc.target/riscv/zksed.c | 20 +++
 gcc/testsuite/gcc.target/riscv/zksh.c  | 19 ++
 6 files changed, 122 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 236eba69e46..564a685d690 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@
 UNSPEC_SHA_512_SUM0R
 UNSPEC_SHA_512_SUM1
 UNSPEC_SHA_512_SUM1R
+
+;; ZKSH unspecs
+UNSPEC_SM3_P0
+UNSPEC_SM3_P1
+
+;; ZKSED unspecs
+UNSPEC_SM4_ED
+UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -387,3 +395,43 @@
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
   [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED 
+
+(define_insn "riscv_sm4ed_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")
+  (match_operand:SI 3 "register_operand" "D03")]
+  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 2a35167e6fb..18c0cce6b8b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always, (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def 
b/gcc/config/riscv/riscv-crypto.def
index 831ab8c0d01..7774b801aec 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, 
crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ed_di, "sm4ed", 

[PATCH 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions

[Liao Shihua]

Add prototypes for RISC-V Crypto built-in functions .

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New enumeration 
identifier.
(RISCV_FTYPE_NAME3): Likewise.
(RISCV_ATYPE_QI): New Argument types.
(RISCV_ATYPE_HI): Likewise.
(RISCV_FTYPE_ATYPES2): New RISCV_ATYPE.
(RISCV_FTYPE_ATYPES3): Likewise.
* config/riscv/riscv-ftypes.def (2): New Definitions of prototypes.
(3):Likewise
---
 gcc/config/riscv/riscv-builtins.cc |  8 
 gcc/config/riscv/riscv-ftypes.def  | 10 ++
 2 files changed, 18 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..ded91e17554 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,8 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -132,6 +134,8 @@ AVAIL (always, (!0))
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_QI intQI_type_node
+#define RISCV_ATYPE_HI intHI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
@@ -142,6 +146,10 @@ AVAIL (always, (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..3b518195a29 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, QI, QI))
+DEF_RISCV_FTYPE (2, (SI, HI, HI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, QI, QI))
+DEF_RISCV_FTYPE (2, (DI, HI, HI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
+DEF_RISCV_FTYPE (3, (DI, DI, DI, SI))
-- 
2.38.1.windows.1

[PATCH 4/5] RISC-V: Implement ZKNH extensions

[Liao Shihua]

  Implement ZKNH extensions.
  ZKNH is NIST Suite: Hash Function Instructions.

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's 
instructions.
(riscv_sha256sig1_): Likewise.
(riscv_sha256sum0_): Likewise.
(riscv_sha256sum1_): Likewise.
(riscv_sha512sig0h): Likewise.
(riscv_sha512sig0l): Likewise.
(riscv_sha512sig1h): Likewise.
(riscv_sha512sig1l): Likewise.
(riscv_sha512sum0r): Likewise.
(riscv_sha512sum1r): Likewise.
(riscv_sha512sig0): Likewise.
(riscv_sha512sig1): Likewise.
(riscv_sha512sum0): Likewise.
(riscv_sha512sum1): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL.
* config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in 
functions.
(DIRECT_BUILTIN): Likewise.
* config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's 
intrinsics.
(__riscv_sha256sig1): Likewise.
(__riscv_sha256sum0): Likewise.
(__riscv_sha256sum1): Likewise.
(__riscv_sha512sig0h): Likewise.
(__riscv_sha512sig0l): Likewise.
(__riscv_sha512sig1h): Likewise.
(__riscv_sha512sig1l): Likewise.
(__riscv_sha512sum0r): Likewise.
(__riscv_sha512sum1r): Likewise.
(__riscv_sha512sig0): Likewise.
(__riscv_sha512sig1): Likewise.
(__riscv_sha512sum0): Likewise.
(__riscv_sha512sum1): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknh-sha256.c: New test.
* gcc.target/riscv/zknh-sha512-32.c: New test.
* gcc.target/riscv/zknh-sha512-64.c: New test.

---
 gcc/config/riscv/crypto.md| 138 ++
 gcc/config/riscv/riscv-builtins.cc|   2 +
 gcc/config/riscv/riscv-crypto.def |  21 +++
 gcc/config/riscv/riscv_scalar_crypto.h|  48 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 
 .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 
 7 files changed, 312 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index a97fd398217..236eba69e46 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
 UNSPEC_AES_ESM
 UNSPEC_AES_ESI
 UNSPEC_AES_ESMI
+
+;; ZKNH unspecs
+UNSPEC_SHA_256_SIG0
+UNSPEC_SHA_256_SIG1
+UNSPEC_SHA_256_SUM0
+UNSPEC_SHA_256_SUM1
+UNSPEC_SHA_512_SIG0
+UNSPEC_SHA_512_SIG0H
+UNSPEC_SHA_512_SIG0L
+UNSPEC_SHA_512_SIG1
+UNSPEC_SHA_512_SIG1H
+UNSPEC_SHA_512_SIG1L
+UNSPEC_SHA_512_SUM0
+UNSPEC_SHA_512_SUM0R
+UNSPEC_SHA_512_SUM1
+UNSPEC_SHA_512_SUM1R
 ])
 
 ;; ZBKB extension
@@ -249,3 +265,125 @@
   [(set_attr "type" "crypto")])
 
 
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r")]
+   UNSPEC_SHA_512_SIG0L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+

[PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension

[Liao Shihua]

This patch implement RISC-V Scalar Cryptography extension.
It includes machine descrption , intrinsic and testcase .

Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extensions
  Implement ZKSH and ZKSED extensions

 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  20 +-
 gcc/config/riscv/constraints.md   |   8 +
 gcc/config/riscv/crypto.md| 437 ++
 gcc/config/riscv/riscv-builtins.cc|  26 ++
 gcc/config/riscv/riscv-crypto.def |  94 
 gcc/config/riscv/riscv-ftypes.def |  10 +
 gcc/config/riscv/riscv.md |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h| 218 +
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |  19 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c   |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++
 .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed.c|  20 +
 gcc/testsuite/gcc.target/riscv/zksh.c |  19 +
 24 files changed, 1187 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

-- 
2.38.1.windows.1

[PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension

[Liao Shihua]

This patch implement RISC-V Scalar Cryptography extension.
It includes machine descrption , intrinsic and testcase .

Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extensions
  Implement ZKSH and ZKSED extensions

 gcc/config.gcc|   2 +-
 gcc/config/riscv/bitmanip.md  |  20 +-
 gcc/config/riscv/constraints.md   |   8 +
 gcc/config/riscv/crypto.md| 437 ++
 gcc/config/riscv/riscv-builtins.cc|  26 ++
 gcc/config/riscv/riscv-crypto.def |  94 
 gcc/config/riscv/riscv-ftypes.def |  10 +
 gcc/config/riscv/riscv.md |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h| 218 +
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |  19 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c   |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c   |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++
 .../gcc.target/riscv/zknh-sha512-32.c |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed.c|  20 +
 gcc/testsuite/gcc.target/riscv/zksh.c |  19 +
 24 files changed, 1187 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

-- 
2.38.1.windows.1

Re: [RFC]RISC-V: Support RV64-ILP32

[Liao Shihua]

I had send gcc and binutils patch to mainlist . But I only support them 
in newlib , not in glibc and qemu. As I know, qemu not support this now.


在 2022/12/28 9:40, Kito Cheng 写道:

I would suggest you could send all necessary parts like binutils,
glibc and/or qemu together future, so that we could easier test that?


On Wed, Dec 28, 2022 at 2:25 AM Palmer Dabbelt  wrote:

On Tue, 27 Dec 2022 10:24:10 PST (-0800), gcc-patches@gcc.gnu.org wrote:


On 12/12/22 23:49, shi...@iscas.ac.cn wrote:

From: Liao Shihua 

This patch support rv64 insn in ilp32 ABI. It was inspired by aarch64 
both
 support 64-bit and 32-bit ABI with the same set of instructions.


gcc/ChangeLog:

  * config.gcc:  Implememt ilp32* with rv64*.
  * config/riscv/riscv.cc (riscv_option_override): Remove the 
constraint between RV64 and ILP32.
  * config/riscv/riscv.h (TARGET_ILP32): Define TARGET_ILP32 with 
riscv_abi.
  (POINTER_SIZE):POINTER_SIZE will change with TARGET_ILP32.
  (Pmode):Likewise.
  * config/riscv/riscv.md: Convert split mode with Pmode and change 
mode form Xmode to Pmode in stack_tie.

This is a new feature and thus I think we should defer to gcc-14 unless
there is a compelling need.

I agree.  This is a pretty big one with a lot of ABI-related
complications, so let's just play it safe.

[RFC v2] Support RV64-ILP32

[shihua]

From: Liao Shihua 

patch v1<https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608370.html>

1. use ABI_LEN_SPEC instead of ABI_LEN_SPEC


  This patch support rv64 insn in ilp32 ABI. It was inspired by aarch64 
both 
   support 64-bit and 32-bit ABI with the same set of instructions.

gcc/ChangeLog:

* config.gcc: Implememt ilp32* with rv64*.
* config/riscv/elf.h (LINK_SPEC): use ABI_LEN_SPEC instead of XLEN_SPEC
* config/riscv/freebsd.h (LINK_SPEC): Likewise
(STARTFILE_PREFIX_SPEC): Likewise
* config/riscv/linux.h (GLIBC_DYNAMIC_LINKER): Likewise
(MUSL_DYNAMIC_LINKER): Likewise
(LINK_SPEC): Likewise
(STARTFILE_PREFIX_SPEC): Likewise
* config/riscv/riscv.cc (riscv_option_override): Remove the constraint 
between RV64 and ILP32.
* config/riscv/riscv.h (TARGET_ILP32): Define TARGET_ILP32 with 
riscv_abi.
(POINTER_SIZE): POINTER_SIZE will change with TARGET_ILP32.
(Pmode): Likewise.
(XLEN_SPEC): Remove
(ABI_LEN_SPEC): Define ABI_LEN_SPEC with -mabi option .
* config/riscv/riscv.md: Convert split mode with Pmode and change mode 
form Xmode to Pmode in stack_tie.
---
 gcc/config.gcc |  3 +++
 gcc/config/riscv/elf.h |  2 +-
 gcc/config/riscv/freebsd.h |  6 +++---
 gcc/config/riscv/linux.h   | 10 +-
 gcc/config/riscv/riscv.cc  |  4 
 gcc/config/riscv/riscv.h   | 14 +-
 gcc/config/riscv/riscv.md  |  8 ++--
 7 files changed, 27 insertions(+), 20 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index c5064dd3766..069293a6e19 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4748,6 +4748,9 @@ case "${target}" in
ilp32,rv32* | ilp32e,rv32e* \
| ilp32f,rv32*f* | ilp32f,rv32g* \
| ilp32d,rv32*d* | ilp32d,rv32g* \
+   | ilp32f,rv64*f* | ilp32f,rv64g* \
+   | ilp32d,rv64*d* | ilp32d,rv64g* \
+   | ilp32,rv64* \
| lp64,rv64* \
| lp64f,rv64*f* | lp64f,rv64g* \
| lp64d,rv64*d* | lp64d,rv64g*)
diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h
index f0e865d6ef4..efc79f3147b 100644
--- a/gcc/config/riscv/elf.h
+++ b/gcc/config/riscv/elf.h
@@ -18,7 +18,7 @@ along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
 #define LINK_SPEC "\
--melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
+-melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
 %{mno-relax:--no-relax} \
 %{mbig-endian:-EB} \
 %{mlittle-endian:-EL} \
diff --git a/gcc/config/riscv/freebsd.h b/gcc/config/riscv/freebsd.h
index 5e5cbe03166..8d72611db7b 100644
--- a/gcc/config/riscv/freebsd.h
+++ b/gcc/config/riscv/freebsd.h
@@ -40,7 +40,7 @@ along with GCC; see the file COPYING3.  If not see
 
 #undef LINK_SPEC
 #define LINK_SPEC "\
-  -melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv  \
+  -melf" ABI_LEN_SPEC DEFAULT_ENDIAN_SPEC "riscv   \
   %{p:%nconsider using `-pg' instead of `-p' with gprof (1)}   \
   %{v:-V}  \
   %{assert*} %{R*} %{rpath*} %{defsym*}\
@@ -56,7 +56,7 @@ along with GCC; see the file COPYING3.  If not see
 %{static:-static}}"
 
 #define STARTFILE_PREFIX_SPEC  \
-   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "  \
-   "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "  \
+   "/lib" ABI_LEN_SPEC "/" ABI_SPEC "/ "   \
+   "/usr/lib" ABI_LEN_SPEC "/" ABI_SPEC "/ "   \
"/lib/ "\
"/usr/lib/ "
diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
index 38803723ba9..0953809976a 100644
--- a/gcc/config/riscv/linux.h
+++ b/gcc/config/riscv/linux.h
@@ -22,7 +22,7 @@ along with GCC; see the file COPYING3.  If not see
 GNU_USER_TARGET_OS_CPP_BUILTINS(); \
   } while (0)
 
-#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-riscv" XLEN_SPEC "-" ABI_SPEC 
".so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-riscv" ABI_LEN_SPEC "-" ABI_SPEC 
".so.1"
 
 #define MUSL_ABI_SUFFIX \
   "%{mabi=ilp32:-sf}" \
@@ -33,7 +33,7 @@ along with GCC; see the file COPYING3.  If not see
   "%{mabi=lp64d:}"
 
 #undef MUSL_DYNAMIC_LINKER
-#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX 
".so.1"
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-riscv" ABI_LEN_SPEC MUSL_ABI_SUFFIX 
".so.1"
 
 /* Because RISC-V only has word-sized atomics, it requries libatomic where
others do not.  So link libatomic by default, as needed.  

[RFC]RISC-V: Support RV64-ILP32

[shihua]

From: Liao Shihua 

  This patch support rv64 insn in ilp32 ABI. It was inspired by aarch64 
both 
   support 64-bit and 32-bit ABI with the same set of instructions.


gcc/ChangeLog:

* config.gcc:  Implememt ilp32* with rv64*.
* config/riscv/riscv.cc (riscv_option_override): Remove the constraint 
between RV64 and ILP32.
* config/riscv/riscv.h (TARGET_ILP32): Define TARGET_ILP32 with 
riscv_abi.
(POINTER_SIZE):POINTER_SIZE will change with TARGET_ILP32.
(Pmode):Likewise.
* config/riscv/riscv.md: Convert split mode with Pmode and change mode 
form Xmode to Pmode in stack_tie.

---
 gcc/config.gcc| 3 +++
 gcc/config/riscv/riscv.cc | 4 
 gcc/config/riscv/riscv.h  | 8 ++--
 gcc/config/riscv/riscv.md | 8 ++--
 4 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index c5064dd3766..069293a6e19 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4748,6 +4748,9 @@ case "${target}" in
ilp32,rv32* | ilp32e,rv32e* \
| ilp32f,rv32*f* | ilp32f,rv32g* \
| ilp32d,rv32*d* | ilp32d,rv32g* \
+   | ilp32f,rv64*f* | ilp32f,rv64g* \
+   | ilp32d,rv64*d* | ilp32d,rv64g* \
+   | ilp32,rv64* \
| lp64,rv64* \
| lp64f,rv64*f* | lp64f,rv64g* \
| lp64d,rv64*d* | lp64d,rv64g*)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aab694..03f313e2b28 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5026,10 +5026,6 @@ riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
 error ("rv32e requires ilp32e ABI");
 
-  /* We do not yet support ILP32 on RV64.  */
-  if (BITS_PER_WORD != POINTER_SIZE)
-error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-
   /* Validate -mpreferred-stack-boundary= value.  */
   riscv_stack_boundary = ABI_STACK_BOUNDARY;
   if (riscv_preferred_stack_boundary_arg)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 8a4d2cf7f85..63aece89878 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -79,6 +79,10 @@ extern const char *riscv_default_mtune (int argc, const char 
**argv);
 #define TARGET_64BIT   (__riscv_xlen == 64)
 #endif /* IN_LIBGCC2 */
 
+#ifndef TARGET_ILP32
+#define TARGET_ILP32   (riscv_abi <= ABI_ILP32D)
+#endif /*TARGET_ILP32*/
+
 #ifdef HAVE_AS_MISA_SPEC
 #define ASM_MISA_SPEC "%{misa-spec=*}"
 #else
@@ -167,7 +171,7 @@ ASM_MISA_SPEC
 #define SHORT_TYPE_SIZE 16
 #define INT_TYPE_SIZE 32
 #define LONG_LONG_TYPE_SIZE 64
-#define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
+#define POINTER_SIZE   (TARGET_ILP32 ? 32 : 64)
 #define LONG_TYPE_SIZE POINTER_SIZE
 
 #define FLOAT_TYPE_SIZE 32
@@ -729,7 +733,7 @@ typedef struct {
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode.  */
 
-#define Pmode word_mode
+#define Pmode (TARGET_ILP32 ? SImode : DImode)
 
 /* Give call MEMs SImode since it is the "most permissive" mode
for both 32-bit and 64-bit targets.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b3c5bce842a..34034aec8c0 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2559,6 +2559,10 @@
   "reload_completed"
   [(const_int 0)]
 {
+  if (GET_MODE (operands[0]) != Pmode)
+operands[0] = convert_to_mode (Pmode, operands[0], 0);
+  if (GET_MODE (operands[1]) != Pmode)
+operands[1] = convert_to_mode (Pmode, operands[1], 0);
   riscv_set_return_address (operands[0], operands[1]);
   DONE;
 })
@@ -2759,8 +2763,8 @@
 
 (define_insn "stack_tie"
   [(set (mem:BLK (scratch))
-   (unspec:BLK [(match_operand:X 0 "register_operand" "r")
-(match_operand:X 1 "register_operand" "r")]
+   (unspec:BLK [(match_operand:P 0 "register_operand" "r")
+(match_operand:P 1 "register_operand" "r")]
UNSPEC_TIE))]
   ""
   ""
-- 
2.38.0.windows.1

Re:[PATCH 1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard

[shihua]

LGTM,and I think it would be better to have a test example.





> From: zengxiao 
>
> This patch makes R_RISCV_SUB6 conforms to riscv abi standard.
> R_RISCV_SUB6 only the lower 6 bits of the code are valid.
> The proposed specification which can be found in 8.5. Relocations of,
> https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_elf_add_sub_reloc): Take the lower
> 6 bits as the significant bit
>
> reviewed-by: gao...@eswincomputing.com
>  jinyanji...@eswincomputing.com
>
> Signed-off-by: zengxiao 
> ---
>  bfd/elfxx-riscv.c | 7 +++
>  1 file changed, 7 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index f0c91cc97f7..0fbfedd17fe 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -994,6 +994,13 @@ riscv_elf_add_sub_reloc (bfd *abfd,
>relocation = old_value + relocation;
>break;
>  case R_RISCV_SUB6:
> +  {
> +bfd_vma six_bit_valid_value = old_value & howto->dst_mask;
> +six_bit_valid_value -= relocation;
> +relocation = (six_bit_valid_value & howto->dst_mask) |
> +  (old_value & ~howto->dst_mask);
> +  }
> +  break;
>  case R_RISCV_SUB8:
>  case R_RISCV_SUB16:
>  case R_RISCV_SUB32:
> -- 
> 2.34.1









logo

[PATCH 1/1 V5] RISC-V: Support Zmmul extension

[shihua]

From: LiaoShihua 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add Zmmul.
* config/riscv/riscv-opts.h (MASK_ZMMUL): New.
(TARGET_ZMMUL): Ditto.
* config/riscv/riscv.cc (riscv_option_override):Ditto.
* config/riscv/riscv.md: Add Zmmul
* config/riscv/riscv.opt: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zmmul-1.c: New test.
* gcc.target/riscv/zmmul-2.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  |  3 +++
 gcc/config/riscv/riscv-opts.h|  3 +++
 gcc/config/riscv/riscv.cc|  8 +--
 gcc/config/riscv/riscv.md| 28 
 gcc/config/riscv/riscv.opt   |  3 +++
 gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 +
 gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 +
 7 files changed, 69 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0e5be2ce105..20acc590b30 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -193,6 +193,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1148,6 +1150,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zmmul", _options::x_riscv_zm_subext, MASK_ZMMUL},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1e153b3a6e7..9c7d69a6ea3 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -153,6 +153,9 @@ enum stack_protector_guard {
 #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
 #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
 
+#define MASK_ZMMUL  (1 << 0)
+#define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
+
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN.  */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2e83ca07394..9ad4181f35f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4999,10 +4999,14 @@ riscv_option_override (void)
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
   if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
-target_flags |= MASK_DIV;
+if(!TARGET_ZMMUL)
+  target_flags |= MASK_DIV;
   else if (!TARGET_MUL && TARGET_DIV)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
-
+  
+  if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV)
+warning (0, "%<-mdiv%> cannot be used when % extension is 
present");
+  
   /* Likewise floating-point division and square root.  */
   if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
 target_flags |= MASK_FDIV;
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 308b64dd30d..d4e171464ea 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -763,7 +763,7 @@
   [(set (match_operand:SI  0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r")))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
   { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -772,7 +772,7 @@
   [(set (match_operand:DI  0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "register_operand" " r")
 (match_operand:DI 2 "register_operand" " r")))]
-  "TARGET_MUL && TARGET_64BIT"
+  "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT"
   "mul\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -782,7 +782,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
  (match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
 {
   if (TARGET_64BIT && mode == SImode)
 {
@@ -827,7 +827,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
  (match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
 {
   if (TARGET_64BIT && mode == SImode)
 {
@@ -873,7 +873,7 @@
(sign_extend:DI
(mult:SI 

[PATCH 0/1 V5] RISC-V: Support Zmmul extension

[shihua]

From: LiaoShihua 

Zmmul extension is Multiply only extension for RISC-V.It implements the 
multiplication subset of the M extension. 
The encodings are identical to those of the corresponding M-extension 
instructions.

LiaoShihua (1):
  RISC-V: Support Zmmul extension

 gcc/common/config/riscv/riscv-common.cc  |  3 +++
 gcc/config/riscv/riscv-opts.h|  3 +++
 gcc/config/riscv/riscv.cc|  8 +--
 gcc/config/riscv/riscv.md| 28 
 gcc/config/riscv/riscv.opt   |  3 +++
 gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 +
 gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 +
 7 files changed, 69 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-2.c

-- 
2.31.1.windows.1

[PATCH 0/1 V4] RISC-V: Support Zmmul extension

[shihua]

From: LiaoShihua 

Zmmul extension is Multiply only extension for RISC-V.It implements the 
multiplication subset of the M extension. 
The encodings are identical to those of the corresponding M-extension 
instructions.
When You both use M extension add Zmmul extension, it will warning "-mdiv 
cannot use when the ZMMUL extension is present"

LiaoShihua (1):
  RISC-V: Support Zmmul extension

 gcc/common/config/riscv/riscv-common.cc  |  3 +++
 gcc/config/riscv/riscv-opts.h|  3 +++
 gcc/config/riscv/riscv.cc|  8 +--
 gcc/config/riscv/riscv.md| 28 
 gcc/config/riscv/riscv.opt   |  3 +++
 gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 +
 gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 +
 7 files changed, 69 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-2.c

-- 
2.31.1.windows.1

[PATCH 1/1 V4] RISC-V: Support Zmmul extension

[shihua]

From: LiaoShihua 

gcc\ChangeLog:

* common/config/riscv/riscv-common.cc: Add zmmul.
* config/riscv/riscv-opts.h (MASK_ZMMUL): New.
(TARGET_ZMMUL): Ditto.
* config/riscv/riscv.cc (riscv_option_override): Prohibit division if 
Zmmul is present.
* config/riscv/riscv.md: Add zmmul
* config/riscv/riscv.opt: Ditto.

gcc\testsuite\ChangeLog:

* gcc.target/riscv/zmmul-1.c: New test.
* gcc.target/riscv/zmmul-2.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  |  3 +++
 gcc/config/riscv/riscv-opts.h|  3 +++
 gcc/config/riscv/riscv.cc|  8 +--
 gcc/config/riscv/riscv.md| 28 
 gcc/config/riscv/riscv.opt   |  3 +++
 gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 +
 gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 +
 7 files changed, 69 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0e5be2ce105..20acc590b30 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -193,6 +193,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1148,6 +1150,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zmmul", _options::x_riscv_zm_subext, MASK_ZMMUL},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1e153b3a6e7..9c7d69a6ea3 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -153,6 +153,9 @@ enum stack_protector_guard {
 #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
 #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
 
+#define MASK_ZMMUL  (1 << 0)
+#define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
+
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN.  */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2e83ca07394..9bf57980024 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4999,10 +4999,14 @@ riscv_option_override (void)
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
   if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
-target_flags |= MASK_DIV;
+if(!TARGET_ZMMUL)
+  target_flags |= MASK_DIV;
   else if (!TARGET_MUL && TARGET_DIV)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
-
+  
+  if(TARGET_ZMMUL && TARGET_MUL)
+warning (0, "%<-mdiv%> cannot use when the % extension is 
present");
+  
   /* Likewise floating-point division and square root.  */
   if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
 target_flags |= MASK_FDIV;
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 308b64dd30d..d4e171464ea 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -763,7 +763,7 @@
   [(set (match_operand:SI  0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r")))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
   { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -772,7 +772,7 @@
   [(set (match_operand:DI  0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "register_operand" " r")
 (match_operand:DI 2 "register_operand" " r")))]
-  "TARGET_MUL && TARGET_64BIT"
+  "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT"
   "mul\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -782,7 +782,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
  (match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
 {
   if (TARGET_64BIT && mode == SImode)
 {
@@ -827,7 +827,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
  (match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
 {
   if (TARGET_64BIT && mode == SImode)
 {
@@ -873,7 +873,7 @@
(sign_extend:DI
   

[PATCH 1/1 V3] RISC-V: Support Zmmul extension

[shihua]

From: LiaoShihua 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
* config/riscv/riscv-opts.h (MASK_ZMMUL):
(TARGET_ZMMUL):
* config/riscv/riscv.cc (riscv_option_override):
* config/riscv/riscv.md:
* config/riscv/riscv.opt:

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zmmul-1.c: New test.
* gcc.target/riscv/zmmul-2.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  |  3 +++
 gcc/config/riscv/riscv-c.cc  |  4 ++--
 gcc/config/riscv/riscv-opts.h|  3 +++
 gcc/config/riscv/riscv.cc|  4 +++-
 gcc/config/riscv/riscv.md| 28 
 gcc/config/riscv/riscv.opt   |  3 +++
 gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 +
 gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 +
 8 files changed, 68 insertions(+), 17 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0e5be2ce105..a4539067403 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -193,6 +193,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1148,6 +1150,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zmmul", _options::x_riscv_zmmul_subext, MASK_ZMMUL},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index eb7ef09297e..fb52f69c44c 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -47,11 +47,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_ATOMIC)
 builtin_define ("__riscv_atomic");
 
-  if (TARGET_MUL)
+  if (TARGET_MUL || TARGET_ZMMUL)
 builtin_define ("__riscv_mul");
   if (TARGET_DIV)
 builtin_define ("__riscv_div");
-  if (TARGET_DIV && TARGET_MUL)
+  if (!TARGET_ZMMUL && TARGET_DIV && TARGET_MUL)
 builtin_define ("__riscv_muldiv");
 
   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1e153b3a6e7..55d9fa49782 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -153,6 +153,9 @@ enum stack_protector_guard {
 #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
 #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
 
+#define MASK_ZMMUL  (1 << 0)
+#define TARGET_ZMMUL((riscv_zmmul_subext & MASK_ZMMUL) != 0)
+
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN.  */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2e83ca07394..f11941e1653 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4998,8 +4998,10 @@ riscv_option_override (void)
 
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
-  if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
+  if (!TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
 target_flags |= MASK_DIV;
+  else if(TARGET_ZMMUL && TARGET_MUL)
+warning (0, "%<-mdiv%> cannot use when the % extension is 
present");
   else if (!TARGET_MUL && TARGET_DIV)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 308b64dd30d..d4e171464ea 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -763,7 +763,7 @@
   [(set (match_operand:SI  0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r")))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
   { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -772,7 +772,7 @@
   [(set (match_operand:DI  0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "register_operand" " r")
 (match_operand:DI 2 "register_operand" " r")))]
-  "TARGET_MUL && TARGET_64BIT"
+  "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT"
   "mul\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -782,7 +782,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
  

[PATCH 0/1 V3] RISC-V: Support Zmmul extension

[shihua]

From: LiaoShihua 

Zmmul extension is Multiply only extension for RISC-V.It implements the 
multiplication subset of the M extension. 
The encodings are identical to those of the corresponding M-extension 
instructions.
When You both use M extension add Zmmul extension, it will warning "-mdiv 
cannot use when the ZMMUL extension is present"

LiaoShihua (1):
  RISC-V: Support Zmmul extension

 gcc/common/config/riscv/riscv-common.cc  |  3 +++
 gcc/config/riscv/riscv-c.cc  |  4 ++--
 gcc/config/riscv/riscv-opts.h|  3 +++
 gcc/config/riscv/riscv.cc|  4 +++-
 gcc/config/riscv/riscv.md| 28 
 gcc/config/riscv/riscv.opt   |  3 +++
 gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 +
 gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 +
 8 files changed, 68 insertions(+), 17 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-2.c

-- 
2.31.1.windows.1

[PATCH] RISC-V: Implement ZTSO extension.

[shihua]

From: LiaoShihua 

  ZTSO is the extension of tatol store order model.
  This extension adds no new instructions to the ISA, and you can use it 
with arch "ztso".
  If you use it, TSO flag will be generate in the ELF header.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: define new arch.
* config/riscv/riscv-opts.h (MASK_ZTSO): Ditto.
(TARGET_ZTSO):Ditto.
* config/riscv/riscv.opt:Ditto.

---
 gcc/common/config/riscv/riscv-common.cc | 4 +++-
 gcc/config/riscv/riscv-opts.h   | 3 +++
 gcc/config/riscv/riscv.opt  | 3 +++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index a904893b9ed..f4730b991d7 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -185,6 +185,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"ztso", ISA_SPEC_CLASS_NONE, 0, 1},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
-
+  {"ztso", _options::x_riscv_ztso_subext, MASK_ZTSO},
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 929e4e3a7c5..9cb5f2a550a 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -136,4 +136,7 @@ enum stack_protector_guard {
 #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
 #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
 
+#define MASK_ZTSO(1 <<  0)
+#define TARGET_ZTSO((riscv_ztso_subext & MASK_ZTSO) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 9fffc08220d..6128bfa31dc 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -209,6 +209,9 @@ int riscv_vector_eew_flags
 TargetVariable
 int riscv_zvl_flags
 
+TargetVariable
+int riscv_ztso_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.31.1.windows.1

[PATCH] RISC-V: Handle combine extension in canonical ordering.

[shihua]

From: LiaoShihua 

The crypto extension have several shorthand extensions that don't consist of 
any extra instructions.
Take zk for example, while the extension would imply zkn, zkr, zkt. 
The 3 extensions should also combine back into zk to maintain the canonical 
order in isa strings.
This patch addresses the above.
And if the other extension has the same situation, you can add them in 
riscv_combine_info[]



gcc/ChangeLog:

* common/config/riscv/riscv-common.cc 
(riscv_subset_list::handle_combine_ext):Combine back into zk to maintain the 
canonical order in isa strings.
(riscv_subset_list::parse):Ditto.
* config/riscv/riscv-subset.h:Declare handle_combine_ext();

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-17.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc| 56 +++
 gcc/config/riscv/riscv-subset.h|  1 +
 gcc/testsuite/gcc.target/riscv/predef-17.c | 63 ++
 3 files changed, 120 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-17.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index a904893b9ed..1c06f83cc1c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -189,6 +189,16 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* Combine extensions defined in this table  */
+static const struct riscv_ext_version riscv_combine_info[] =
+{
+  {"zk",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zkn",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zks",  ISA_SPEC_CLASS_NONE, 1, 0},
+  /* Terminate the list.  */
+  {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -813,6 +823,50 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
 }
 }
 
+/* Check any combine extensions for EXT.  */
+void
+riscv_subset_list::handle_combine_ext (riscv_subset_list *subset_list)
+{
+  const riscv_ext_version *combine_info;
+  const riscv_implied_info_t *implied_info;
+  bool IsCombined = false;
+
+  for (combine_info = _combine_info[0]; combine_info->name; 
++combine_info)
+  {
+
+/* Skip if combine extensions are present */
+if (subset_list->lookup(combine_info->name))
+  continue;
+
+/* Find all extensions of the combine extension   */
+for (implied_info = _implied_info[0]; implied_info->ext; 
++implied_info)
+{
+  /* Skip if implied extension don't match combine extension */
+  if (strcmp(combine_info->name, implied_info->ext) != 0)
+continue; 
+
+  if (subset_list->lookup(implied_info->implied_ext))
+  {
+IsCombined = true;
+  }
+  else
+  {
+IsCombined = false;
+break;
+  }
+}
+
+/* Add combine extensions */
+if (IsCombined)
+{
+  if (subset_list->lookup(combine_info->name) == NULL)
+  {
+subset_list->add (combine_info->name, combine_info->major_version, 
combine_info->minor_version, false, true);
+  }
+}
+  }
+}
+
 /* Parsing function for multi-letter extensions.
 
Return Value:
@@ -992,6 +1046,8 @@ riscv_subset_list::parse (const char *arch, location_t loc)
   subset_list->handle_implied_ext (itr);
 }
 
+  subset_list->handle_combine_ext (subset_list);
+
   return subset_list;
 
 fail:
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index 4f3556a8d9b..da2e22d34f2 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -68,6 +68,7 @@ private:
 const char *);
 
   void handle_implied_ext (riscv_subset_t *);
+  void handle_combine_ext (riscv_subset_list *);
 
 public:
   ~riscv_subset_list ();
diff --git a/gcc/testsuite/gcc.target/riscv/predef-17.c 
b/gcc/testsuite/gcc.target/riscv/predef-17.c
new file mode 100644
index 000..68f5f95a66c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-17.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_zkr_zkt 
-mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_zk)
+#error "__riscv_zk"
+#endif
+
+#if !defined(__riscv_zkr)
+#error "__riscv_zkr"
+#endif
+
+#if !defined(__riscv_zkn)
+#error "__riscv_zkn"
+#endif
+
+#if !defined(__riscv_zks)
+#error "__riscv_zks"
+#endif
+
+#if !defined(__riscv_zbkb)
+#error "__riscv_zbkb"
+#endif
+
+#if !defined(__riscv_zbkc)
+#error "__riscv_zbkc"
+#endif
+
+#if !defined(__riscv_zbkx)
+#error "__riscv_zbkx"
+#endif
+
+#if !defined(__riscv_zknd)
+#error "__riscv_zknd"
+#endif
+
+#if !defined(__riscv_zkne)
+#error "__riscv_zkne"
+#endif
+
+#if 

[PATCH 3/5 V1] RISC-V:Implement intrinsics for Crypto extension

[shihua]

From: LiaoShihua 

These headers are in https://github.com/rvkrypto/rvkrypto-fips .

gcc/ChangeLog:

* config.gcc: Add extra_headers.
* config/riscv/riscv_crypto.h: New file.
* config/riscv/riscv_crypto_scalar.h: New file.
* config/riscv/rvk_asm_intrin.h: New file.
* config/riscv/rvk_emu_intrin.h: New file.

Co-Authored-By: mjosaarinen 
---
 gcc/config.gcc |   1 +
 gcc/config/riscv/riscv_crypto.h|  12 +
 gcc/config/riscv/riscv_crypto_scalar.h | 247 ++
 gcc/config/riscv/rvk_asm_intrin.h  | 187 
 gcc/config/riscv/rvk_emu_intrin.h  | 594 +
 5 files changed, 1041 insertions(+)
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/config/riscv/riscv_crypto_scalar.h
 create mode 100644 gcc/config/riscv/rvk_asm_intrin.h
 create mode 100644 gcc/config/riscv/rvk_emu_intrin.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2cc5aeec9e4..caf673f1cb0 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -510,6 +510,7 @@ pru-*-*)
 riscv*)
cpu_type=riscv
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o"
+   extra_headers="riscv_crypto.h riscv_crypto_scalar.h rvk_asm_intrin.h 
rvk_emu_intrin.h"
d_target_objs="riscv-d.o"
;;
 rs6000*-*-*)
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 000..d06c777b7af
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,12 @@
+// riscv_crypto.h
+// 2022-02-12  Markku-Juhani O. Saarinen 
+// Copyright (c) 2022, PQShield Ltd. All rights reserved.
+
+// === Master crypto intrinsics header. Currently Just includes scalar 
crypto.
+
+#ifndef _RISCV_CRYPTO_H
+#define _RISCV_CRYPTO_H
+
+#include "riscv_crypto_scalar.h"
+
+#endif //  _RISCV_CRYPTO_H
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv_crypto_scalar.h 
b/gcc/config/riscv/riscv_crypto_scalar.h
new file mode 100644
index 000..0ed627856fd
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto_scalar.h
@@ -0,0 +1,247 @@
+// riscv_crypto_scalar.h
+// 2021-11-08  Markku-Juhani O. Saarinen 
+// Copyright (c) 2021, PQShield Ltd. All rights reserved.
+
+// === Scalar crypto: General mapping from intrinsics to compiler builtins,
+// inline assembler, or to an (insecure) porting / emulation layer.
+
+/*
+ * _rv_*(...)
+ *   RV32/64 intrinsics that return the "long" data type
+ *
+ * _rv32_*(...)
+ *   RV32/64 intrinsics that return the "int32_t" data type
+ *
+ * _rv64_*(...)
+ *   RV64-only intrinsics that return the "int64_t" data type
+ *
+ */
+
+#ifndef _RISCV_CRYPTO_SCALAR_H
+#define _RISCV_CRYPTO_SCALAR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__riscv_xlen) && !defined(RVKINTRIN_EMULATE)
+#warning "Target is not RISC-V. Enabling insecure emulation."
+#define RVKINTRIN_EMULATE 1
+#endif
+
+#if defined(RVKINTRIN_EMULATE)
+
+// intrinsics via emulation (insecure -- porting / debug option)
+#include "rvk_emu_intrin.h"
+#define _RVK_INTRIN_IMPL(s) _rvk_emu_##s
+
+#elif defined(RVKINTRIN_ASSEMBLER)
+
+// intrinsics via inline assembler (builtins not available)
+#include "rvk_asm_intrin.h"
+#define _RVK_INTRIN_IMPL(s) _rvk_asm_##s
+#else
+
+// intrinsics via compiler builtins
+#include 
+#define _RVK_INTRIN_IMPL(s) __builtin_riscv_##s
+
+#endif
+
+// set type if not already set
+#if !defined(RVKINTRIN_RV32) && !defined(RVKINTRIN_RV64)
+#if __riscv_xlen == 32
+#define RVKINTRIN_RV32
+#elif __riscv_xlen == 64
+#define RVKINTRIN_RV64
+#else
+#error "__riscv_xlen not valid."
+#endif
+#endif
+
+// Mappings to implementation
+
+// === (mapping)   Zbkb:   Bitmanipulation instructions for Cryptography
+
+static inline int32_t _rv32_ror(int32_t rs1, int32_t rs2)
+   { return _RVK_INTRIN_IMPL(ror_32)(rs1, rs2); }  //  
ROR[W] ROR[W]I
+
+static inline int32_t _rv32_rol(int32_t rs1, int32_t rs2)
+   { return _RVK_INTRIN_IMPL(rol_32)(rs1, rs2); }  //  
ROL[W] ROR[W]I
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t _rv64_ror(int64_t rs1, int64_t rs2)
+   { return _RVK_INTRIN_IMPL(ror_64)(rs1, rs2); }  //  
ROR or RORI
+
+static inline int64_t _rv64_rol(int64_t rs1, int64_t rs2)
+   { return _RVK_INTRIN_IMPL(rol_64)(rs1, rs2); }  //  
ROL or RORI
+#endif
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t _rv32_brev8(int32_t rs1)
+   { return _RVK_INTRIN_IMPL(brev8_32)(rs1); } 
//  BREV8 (GREVI)
+#endif
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t _rv64_brev8(int64_t rs1)
+   { return _RVK_INTRIN_IMPL(brev8_64)(rs1); } 
//  BREV8 (GREVI)
+#endif
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t _rv32_zip(int32_t rs1)
+   { return _RVK_INTRIN_IMPL(zip_32)(rs1); }  

[PATCH 4/5 V1] RISC-V:Implement testcases for Crypto extension

[shihua]

From: LiaoShihua 

These testcases use intrinsics .

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbkb32.c: New test.
* gcc.target/riscv/zbkb64.c: New test.
* gcc.target/riscv/zbkc32.c: New test.
* gcc.target/riscv/zbkc64.c: New test.
* gcc.target/riscv/zbkx32.c: New test.
* gcc.target/riscv/zbkx64.c: New test.
* gcc.target/riscv/zknd32.c: New test.
* gcc.target/riscv/zknd64.c: New test.
* gcc.target/riscv/zkne64.c: New test.
* gcc.target/riscv/zknh.c: New test.
* gcc.target/riscv/zknh32.c: New test.
* gcc.target/riscv/zknh64.c: New test.
* gcc.target/riscv/zksed.c: New test.
* gcc.target/riscv/zksh.c: New test.

---
 gcc/testsuite/gcc.target/riscv/zbkb32.c | 34 +
 gcc/testsuite/gcc.target/riscv/zbkb64.c | 21 +
 gcc/testsuite/gcc.target/riscv/zbkc32.c | 16 ++
 gcc/testsuite/gcc.target/riscv/zbkc64.c | 16 ++
 gcc/testsuite/gcc.target/riscv/zbkx32.c | 16 ++
 gcc/testsuite/gcc.target/riscv/zbkx64.c | 16 ++
 gcc/testsuite/gcc.target/riscv/zknd32.c | 18 +++
 gcc/testsuite/gcc.target/riscv/zknd64.c | 35 ++
 gcc/testsuite/gcc.target/riscv/zkne64.c | 29 ++
 gcc/testsuite/gcc.target/riscv/zknh.c   | 28 +
 gcc/testsuite/gcc.target/riscv/zknh32.c | 40 +
 gcc/testsuite/gcc.target/riscv/zknh64.c | 29 ++
 gcc/testsuite/gcc.target/riscv/zksed.c  | 20 +
 gcc/testsuite/gcc.target/riscv/zksh.c   | 17 +++
 14 files changed, 335 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c 
b/gcc/testsuite/gcc.target/riscv/zbkb32.c
new file mode 100644
index 000..5bf588d58b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include"riscv_crypto.h"
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+return _rv32_ror(rs1,rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+return _rv32_rol(rs1,rs2);
+}
+
+int32_t foo3(int32_t rs1)
+{
+return _rv32_brev8(rs1);
+}
+
+int32_t foo4(int32_t rs1)
+{
+return _rv32_zip(rs1);
+}
+
+int32_t foo5(int32_t rs1)
+{
+return _rv32_unzip(rs1);
+}
+
+/* { dg-final { scan-assembler-times "ror" 1 } } */
+/* { dg-final { scan-assembler-times "rol" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
+/* { dg-final { scan-assembler-times "zip" 2 } } */
+/* { dg-final { scan-assembler-times "unzip" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c 
b/gcc/testsuite/gcc.target/riscv/zbkb64.c
new file mode 100644
index 000..2cd76a29750
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include"riscv_crypto.h"
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+return _rv64_ror(rs1,rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+return _rv64_rol(rs1,rs2);
+}
+
+int64_t foo3(int64_t rs1, int64_t rs2)
+{
+return _rv64_brev8(rs1);
+}
+/* { dg-final { scan-assembler-times "ror" 1 } } */
+/* { dg-final { scan-assembler-times "rol" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c 
b/gcc/testsuite/gcc.target/riscv/zbkc32.c
new file mode 100644
index 000..237085bfc7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include"riscv_crypto.h"
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+return _rv32_clmul(rs1,rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+return _rv32_clmulh(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul" 2 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
\ No 

[PATCH 1/5 V1] RISC-V:Implement instruction patterns for Crypto extension

[shihua]

From: LiaoShihua 


gcc/ChangeLog:

* config/riscv/predicates.md (bs_operand): operand for bs
(rnum_operand): 
* config/riscv/riscv.md: include crypto.md
* config/riscv/crypto.md: New file. 

Co-Authored-By: Wu 
---
 gcc/config/riscv/crypto.md | 383 +
 gcc/config/riscv/predicates.md |   8 +
 gcc/config/riscv/riscv.md  |   1 +
 3 files changed, 392 insertions(+)
 create mode 100644 gcc/config/riscv/crypto.md

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
new file mode 100644
index 000..591066fac3b
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,383 @@
+;; Machine description for K extension.
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+;; Contributed by SiYu Wu (s...@isrc.iscas.ac.cn) and ShiHua Liao 
(shi...@iscas.ac.cn).
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_c_enum "unspec" [
+;;ZBKB unspecs
+UNSPEC_ROR
+UNSPEC_ROL
+UNSPEC_BREV8
+UNSPEC_BSWAP
+UNSPEC_ZIP
+UNSPEC_UNZIP
+
+;; Zbkc unspecs
+UNSPEC_CLMUL
+UNSPEC_CLMULH
+
+;; Zbkx unspecs
+UNSPEC_XPERM8
+UNSPEC_XPERM4
+
+;; Zknd unspecs
+UNSPEC_AES_DSI
+UNSPEC_AES_DSMI
+UNSPEC_AES_DS
+UNSPEC_AES_DSM
+UNSPEC_AES_IM
+UNSPEC_AES_KS1I
+UNSPEC_AES_KS2
+
+;; Zkne unspecs
+UNSPEC_AES_ES
+UNSPEC_AES_ESM
+UNSPEC_AES_ESI
+UNSPEC_AES_ESMI
+
+;; Zknh unspecs
+UNSPEC_SHA_256_SIG0
+UNSPEC_SHA_256_SIG1
+UNSPEC_SHA_256_SUM0
+UNSPEC_SHA_256_SUM1
+UNSPEC_SHA_512_SIG0
+UNSPEC_SHA_512_SIG0H
+UNSPEC_SHA_512_SIG0L
+UNSPEC_SHA_512_SIG1
+UNSPEC_SHA_512_SIG1H
+UNSPEC_SHA_512_SIG1L
+UNSPEC_SHA_512_SUM0
+UNSPEC_SHA_512_SUM0R
+UNSPEC_SHA_512_SUM1
+UNSPEC_SHA_512_SUM1R
+
+;; Zksh
+UNSPEC_SM3_P0
+UNSPEC_SM3_P1
+
+;;Zksed
+UNSPEC_SM4_ED
+UNSPEC_SM4_KS
+])
+
+(define_insn "riscv_ror_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")]
+  UNSPEC_ROR))]
+  "TARGET_ZBKB"
+  "ror\t%0,%1,%2")
+
+(define_insn "riscv_rol_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")]
+  UNSPEC_ROL))]
+  "TARGET_ZBKB"
+  "rol\t%0,%1,%2")
+
+(define_insn "riscv_brev8_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_BREV8))]
+  "TARGET_ZBKB"
+  "brev8\t%0,%1")
+
+(define_insn "riscv_bswap"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")]
+  UNSPEC_BSWAP))]
+  "TARGET_ZBKB"
+  "bswap\t%0,%1")
+
+(define_insn "riscv_zip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+  UNSPEC_ZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "zip\t%0,%1")
+
+(define_insn "riscv_unzip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+  UNSPEC_UNZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "unzip\t%0,%1")
+
+(define_insn "riscv_clmul_"
+  [(set (match_operand:X 0 "register_operand" "=r")
+(unspec:X [(match_operand:X 1 "register_operand" "r")
+  (match_operand:X 2 "register_operand" "r")]
+  UNSPEC_CLMUL))]
+  "TARGET_ZBKC"
+  "clmul\t%0,%1,%2")
+
+(define_insn "riscv_clmulh_"
+  [(set (match_operand:X 0 "register_operand&qu

[PATCH 2/5 V1] RISC-V:Implement built-in instructions for Crypto extension

[shihua]

From: LiaoShihua 

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): Defined new 
function prototypes.
(RISCV_FTYPE_NAME3): Ditto.
(AVAIL): Defined new riscv_builtin_avail for crypto extension.
(RISCV_ATYPE_SI): Defined new argument type.
(RISCV_ATYPE_DI): Ditto.
(RISCV_FTYPE_ATYPES2): Defined new RISCV_FTYPE_ATYPESN
(RISCV_FTYPE_ATYPES3): Ditto.
* config/riscv/riscv-ftypes.def (1): Defined new prototypes for RISC-V 
built-in functions.
(2): Ditto.
(3): Ditto.
* config/riscv/riscv-builtins-crypto.def: Defined new RISC-V built-in 
functions for crypto extension.

Co-Authored-By: Wu 
---
 gcc/config/riscv/riscv-builtins-crypto.def | 93 ++
 gcc/config/riscv/riscv-builtins.cc | 35 
 gcc/config/riscv/riscv-ftypes.def  |  7 ++
 3 files changed, 135 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-builtins-crypto.def

diff --git a/gcc/config/riscv/riscv-builtins-crypto.def 
b/gcc/config/riscv/riscv-builtins-crypto.def
new file mode 100644
index 000..91dcf457dd5
--- /dev/null
+++ b/gcc/config/riscv/riscv-builtins-crypto.def
@@ -0,0 +1,93 @@
+/* Builtin definitions for K extension
+   Copyright (C) 2022 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+// Zbkb
+RISCV_BUILTIN (ror_si, "ror_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, 
crypto_zbkb32),
+RISCV_BUILTIN (ror_di, "ror_64", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, 
crypto_zbkb64),
+RISCV_BUILTIN (rol_si, "rol_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, 
crypto_zbkb32),
+RISCV_BUILTIN (rol_di, "rol_64", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, 
crypto_zbkb64),
+RISCV_BUILTIN (bswapsi, "bswap32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, 
crypto_zbkb32),
+RISCV_BUILTIN (bswapdi, "bswap64", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, 
crypto_zbkb64),
+RISCV_BUILTIN (zip, "zip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zbkb32),
+RISCV_BUILTIN (unzip, "unzip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zbkb32),
+RISCV_BUILTIN (brev8_si, "brev8_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, 
crypto_zbkb32),
+RISCV_BUILTIN (brev8_di, "brev8_64", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, 
crypto_zbkb64),
+
+//Zbkc
+RISCV_BUILTIN (clmul_si, "clmul_32", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmul_di, "clmul_64", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+RISCV_BUILTIN (clmulh_si, "clmulh_32", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmulh_di, "clmulh_64", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+
+// Zbkx
+RISCV_BUILTIN (xperm4_si, "xperm4_32", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm4_di, "xperm4_64", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+RISCV_BUILTIN (xperm8_si, "xperm8_32", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm8_di, "xperm8_64", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+
+// Zknd
+DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne_or_zknd),
+DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne_or_zknd),
+
+// Zkne
+DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+
+// Zknh - SHA256
+RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, 

[PATCH 0/5 V1] RISC-V:Implement Crypto extension's instruction patterns and it's intrinsics

[shihua]

From: LiaoShihua 

This patch set is the implementation of Crypto extension, which includes 
zbkb, zbkc, zbkx,
zknd, zknh, zkne,zksed and zksh extension.
It includes instruction/md patterns, intrinsic functions, testcases for 
intrinsic functions, 
and test macros.
The definitions of intrinsic functions come from 
https://github.com/rvkrypto/rvkrypto-fips .
This work is done by Liao Shihua and Wu Siyu.

LiaoShihua (5):
  RISC-V:Implement instruction patterns for Crypto extensions
  RISC-V:Implement built-in instructions for Crypto extensions
  RISC-V:Implement intrinsics for Crypto extensions
  RISC-V:Implement testcases for Crypto extensions
  RISC-V:Implement architecture extension test macros for Crypto extensions

 gcc/config.gcc |   1 +
 gcc/config/riscv/crypto.md | 383 +
 gcc/config/riscv/predicates.md |   8 +
 gcc/config/riscv/riscv-builtins-crypto.def |  93 
 gcc/config/riscv/riscv-builtins.cc |  35 ++
 gcc/config/riscv/riscv-c.cc|   9 +
 gcc/config/riscv/riscv-ftypes.def  |   7 +
 gcc/config/riscv/riscv.md  |   1 +
 gcc/config/riscv/riscv_crypto.h|  12 +
 gcc/config/riscv/riscv_crypto_scalar.h | 247 +
 gcc/config/riscv/rvk_asm_intrin.h  | 187 +++
 gcc/config/riscv/rvk_emu_intrin.h  | 594 +
 gcc/testsuite/gcc.target/riscv/predef-17.c |  59 ++
 gcc/testsuite/gcc.target/riscv/zbkb32.c|  34 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c|  21 +
 gcc/testsuite/gcc.target/riscv/zbkc32.c|  16 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c|  16 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c|  16 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c|  16 +
 gcc/testsuite/gcc.target/riscv/zknd32.c|  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c|  35 ++
 gcc/testsuite/gcc.target/riscv/zkne64.c|  29 +
 gcc/testsuite/gcc.target/riscv/zknh.c  |  28 +
 gcc/testsuite/gcc.target/riscv/zknh32.c|  40 ++
 gcc/testsuite/gcc.target/riscv/zknh64.c|  29 +
 gcc/testsuite/gcc.target/riscv/zksed.c |  20 +
 gcc/testsuite/gcc.target/riscv/zksh.c  |  17 +
 27 files changed, 1971 insertions(+)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-builtins-crypto.def
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/config/riscv/riscv_crypto_scalar.h
 create mode 100644 gcc/config/riscv/rvk_asm_intrin.h
 create mode 100644 gcc/config/riscv/rvk_emu_intrin.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

-- 
2.31.1.windows.1

[PATCH 5/5 V1] RISC-V:Implement architecture extension test macros for Crypto extension

[shihua]

From: LiaoShihua 

gcc/ChangeLog:

* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):Add __riscv_zks, 
__riscv_zk, __riscv_zkn

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-17.c: New test.

---
 gcc/config/riscv/riscv-c.cc|  9 
 gcc/testsuite/gcc.target/riscv/predef-17.c | 59 ++
 2 files changed, 68 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-17.c

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 73c62f41274..d6c153e8d7c 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -63,6 +63,15 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   builtin_define ("__riscv_fdiv");
   builtin_define ("__riscv_fsqrt");
 }
+  
+  if (TARGET_ZBKB && TARGET_ZBKC && TARGET_ZBKX && TARGET_ZKNE && TARGET_ZKND 
&& TARGET_ZKNH)
+{
+  builtin_define ("__riscv_zk");
+  builtin_define ("__riscv_zkn");
+}
+
+  if (TARGET_ZBKB && TARGET_ZBKC && TARGET_ZBKX && TARGET_ZKSED && TARGET_ZKSH)
+  builtin_define ("__riscv_zks");
 
   switch (riscv_abi)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/predef-17.c 
b/gcc/testsuite/gcc.target/riscv/predef-17.c
new file mode 100644
index 000..4366dee1016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-17.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh 
-mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_zk)
+#error "__riscv_zk"
+#endif
+
+#if !defined(__riscv_zkn)
+#error "__riscv_zkn"
+#endif
+
+#if !defined(__riscv_zks)
+#error "__riscv_zks"
+#endif
+
+#if !defined(__riscv_zbkb)
+#error "__riscv_zbkb"
+#endif
+
+#if !defined(__riscv_zbkc)
+#error "__riscv_zbkc"
+#endif
+
+#if !defined(__riscv_zbkx)
+#error "__riscv_zbkx"
+#endif
+
+#if !defined(__riscv_zknd)
+#error "__riscv_zknd"
+#endif
+
+#if !defined(__riscv_zkne)
+#error "__riscv_zkne"
+#endif
+
+#if !defined(__riscv_zknh)
+#error "__riscv_zknh"
+#endif
+
+#if !defined(__riscv_zksh)
+#error "__riscv_zksh"
+#endif
+
+  return 0;
+}
\ No newline at end of file
-- 
2.31.1.windows.1

[PATCH] RISC-V:Add support for ZMMUL extension

[shihua]

From: LiaoShihua 

  ZMMUL extension is Multiply only extension for RISC-V.It implements the 
multiplication subset of the M extension. 
  The encodings are identical to those of the corresponding M-extension 
instructions.
  When You both use M extension add ZMMUL extension, it will warning "-mdiv 
cannot use when the ZMMUL extension is present"

gcc\ChangeLog:

* common/config/riscv/riscv-common.cc:Add support for ZMMUL extension
* config/riscv/riscv-opts.h (MASK_ZMMUL):Likewise
(TARGET_ZMMUL):Likewise
* config/riscv/riscv.cc (riscv_option_override):Likewise
* config/riscv/riscv.md:Likewise
* config/riscv/riscv.opt:Likewise
---
 gcc/common/config/riscv/riscv-common.cc |  3 +++
 gcc/config/riscv/riscv-opts.h   |  3 +++
 gcc/config/riscv/riscv.cc   |  4 +++-
 gcc/config/riscv/riscv.md   | 28 -
 gcc/config/riscv/riscv.opt  |  3 +++
 5 files changed, 26 insertions(+), 15 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index a904893b9ed..fec6c25eb04 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -185,6 +185,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zmmul", ISA_SPEC_CLASS_NONE, 0, 1},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1080,6 +1082,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zmmul",_options::x_riscv_zmmul_subext, MASK_ZMMUL},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 929e4e3a7c5..47e25628635 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -136,4 +136,7 @@ enum stack_protector_guard {
 #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
 #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
 
+#define MASK_ZMMUL  (1 << 0)
+#define TARGET_ZMMUL((riscv_zmmul_subext & MASK_ZMMUL) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6885b4bbad2..bbd5c288da9 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4974,8 +4974,10 @@ riscv_option_override (void)
 
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
-  if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
+  if (!TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
 target_flags |= MASK_DIV;
+  else if(TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 
0)
+warning (0, "%<-mdiv%> cannot use when the % extension is 
present");
   else if (!TARGET_MUL && TARGET_DIV)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b3c5bce842a..6dee2fb681a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -756,7 +756,7 @@
   [(set (match_operand:SI  0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r")))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
   { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -765,7 +765,7 @@
   [(set (match_operand:DI  0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "register_operand" " r")
 (match_operand:DI 2 "register_operand" " r")))]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
   "mul\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -775,7 +775,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
  (match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
 {
   if (TARGET_64BIT && mode == SImode)
 {
@@ -820,7 +820,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
  (match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
-  "TARGET_MUL"
+  "TARGET_ZMMUL || TARGET_MUL"
 {
   if (TARGET_64BIT && mode == SImode)
 {
@@ -866,7 +866,7 @@
(sign_extend:DI
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r"]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
   "mulw\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ 

[PATCH] RISC-V: Update testcases info with new implement info

[shihua]

From: LiaoShihua 

After commit 591b6e00d1bfe12932ca31530d5859f95db8a35a " riscv: fix 
-Wformat-diag errors ", some strings in implement was changed. 
This patch update the check info in testcases to sync with it.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-9.c: Update the check info.
* gcc.target/riscv/arch-10.c: Ditto.
* gcc.target/riscv/arch-12.c: Ditto.


---
 gcc/testsuite/gcc.target/riscv/arch-10.c | 2 +-
 gcc/testsuite/gcc.target/riscv/arch-12.c | 2 +-
 gcc/testsuite/gcc.target/riscv/arch-9.c  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/arch-10.c 
b/gcc/testsuite/gcc.target/riscv/arch-10.c
index 47dbda333c9..1052f2e0c14 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-10.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-10.c
@@ -3,4 +3,4 @@
 int foo()
 {
 }
-/* { dg-error "Extension `f' appear more than one time." "" { target *-*-* } 0 
} */
+/* { dg-error "extension 'f' appear more than one time" "" { target *-*-* } 0 
} */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-12.c 
b/gcc/testsuite/gcc.target/riscv/arch-12.c
index 29e16c30815..5ee9a1da5bb 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-12.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-12.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -march=rv64im1p2p3 -mabi=lp64" } */
 int foo() {}
-/* { dg-error "'-march=rv64im1p2p3': For 'm1p2p\\?', version number with more 
than 2 level is not supported." "" { target *-*-* } 0 } */
+/* { dg-error "'-march=rv64im1p2p3': for 'm1p2p\\?', version number with more 
than 2 level is not supported" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-9.c 
b/gcc/testsuite/gcc.target/riscv/arch-9.c
index 74e64103563..d00e99d3534 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-9.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-9.c
@@ -3,4 +3,4 @@
 int foo()
 {
 }
-/* { dg-warning "version of `g` will be omitted, please specify version for 
individual extension." "" { target *-*-* } 0 } */
+/* { dg-warning "version of 'g' will be omitted, please specify version for 
individual extension" "" { target *-*-* } 0 } */
-- 
2.31.1.windows.1

[PATCH 1/1] Fixed fast_float build error in NEWLIB

[shihua]

From: LiaoShihua 

When I built riscv-gcc with newlib, it will be terminated with message "fatal 
error: endian.h: No such file or directory".
So, fixed it in fast_float.h.

libstdc++-v3\ChangeLog:

* src/c++17/fast_float/fast_float.h (defined):fast_float.h will include 
 with using newlib

---
 libstdc++-v3/src/c++17/fast_float/fast_float.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/src/c++17/fast_float/fast_float.h 
b/libstdc++-v3/src/c++17/fast_float/fast_float.h
index 97d28940944..0308f7b35af 100644
--- a/libstdc++-v3/src/c++17/fast_float/fast_float.h
+++ b/libstdc++-v3/src/c++17/fast_float/fast_float.h
@@ -131,7 +131,7 @@ from_chars_result from_chars_advanced(const char *first, 
const char *last,
 #ifdef _WIN32
 #define FASTFLOAT_IS_BIG_ENDIAN 0
 #else
-#if defined(__APPLE__) || defined(__FreeBSD__)
+#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NEWLIB__)
 #include 
 #elif defined(sun) || defined(__sun)
 #include 
-- 
2.31.1.windows.1

[PATCH] fixed testcase fail in pr102892-2.c fixed tesccase fail in gcc.dg/pr102892-1.c

[shihua]

From: LiaoShihua 

* gcc.dg/pr102892-2.c: Add definition of function foo() which declared 
in pr102892-1.c
---
 gcc/testsuite/gcc.dg/pr102892-2.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/pr102892-2.c 
b/gcc/testsuite/gcc.dg/pr102892-2.c
index b39bd6c97b3..b179b26680c 100644
--- a/gcc/testsuite/gcc.dg/pr102892-2.c
+++ b/gcc/testsuite/gcc.dg/pr102892-2.c
@@ -5,3 +5,8 @@ void
 bar (void)
 {
 }
+
+void 
+foo (void)
+{
+}
\ No newline at end of file
-- 
2.31.1.windows.1

[PATCH] fixed testcase fail gcc.dg/analyzer/pr103526.c leak

[shihua]

From: LiaoShihua 

following 'false' branch in line 20, 'tmp.word_state' leaks in line 26. So 
free 'tmp.word_state' before return 'rval'.
  
gcc/testsuite\ChangeLog:

* gcc.dg/analyzer/pr103526.c:

---
 gcc/testsuite/gcc.dg/analyzer/pr103526.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/analyzer/pr103526.c 
b/gcc/testsuite/gcc.dg/analyzer/pr103526.c
index 39d60fd853e..7df2e4e7576 100644
--- a/gcc/testsuite/gcc.dg/analyzer/pr103526.c
+++ b/gcc/testsuite/gcc.dg/analyzer/pr103526.c
@@ -22,7 +22,8 @@ game_new(void)
if ((rval = malloc(sizeof(*rval))) == NULL)
goto err;
memcpy(rval, , sizeof(*rval));
-
+   
+   free(tmp.word_state);
return (rval);
 err:
free(tmp.word_state);
-- 
2.31.1.windows.1

[PATCH V2] fixed testcase riscv/pr103302.c

[shihua]

From: LiaoShihua 

because riscv32 not support __int128, so skip if int128 not support.

gcc/testsuite\ChangeLog:
* gcc.target/riscv/pr103302.c: skip if int128 not support

---
 gcc/testsuite/gcc.target/riscv/pr103302.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr103302.c 
b/gcc/testsuite/gcc.target/riscv/pr103302.c
index 822c4087416..cfaa47c 100644
--- a/gcc/testsuite/gcc.target/riscv/pr103302.c
+++ b/gcc/testsuite/gcc.target/riscv/pr103302.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target int128 } } */
 /* { dg-options "-Og -fharden-compares -fno-tree-dce -fno-tree-fre " } */
 
 typedef unsigned char u8;
-- 
2.31.1.windows.1

[PATCH] fixed testcase riscv/pr103302.c

[shihua]

From: LiaoShihua 

because riscv32 not support __int128, so skip if -march=rv32*.

gcc/testsuite\ChangeLog:
* gcc.target/riscv/pr103302.c: skip if -march=rv32*
---
 gcc/testsuite/gcc.target/riscv/pr103302.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.target/riscv/pr103302.c 
b/gcc/testsuite/gcc.target/riscv/pr103302.c
index 822c4087416..2cfb12498a2 100644
--- a/gcc/testsuite/gcc.target/riscv/pr103302.c
+++ b/gcc/testsuite/gcc.target/riscv/pr103302.c
@@ -1,4 +1,5 @@
 /* { dg-do run } */
+/* { dg-skip-if "rv32 not support _int128" { *-*-* } { "-march=rv32*" } } */
 /* { dg-options "-Og -fharden-compares -fno-tree-dce -fno-tree-fre " } */
 
 typedef unsigned char u8;
-- 
2.31.1.windows.1

RISCV: Add zmmul extension

[shihua]

From: Liaoshihua 

---
 gcc/common/config/riscv/riscv-common.c |  3 +++
 gcc/config/riscv/riscv-c.c |  2 +-
 gcc/config/riscv/riscv-opts.h  |  3 +++
 gcc/config/riscv/riscv.c   |  5 -
 gcc/config/riscv/riscv.md  | 30 +-
 gcc/config/riscv/riscv.opt |  3 +++
 6 files changed, 29 insertions(+), 17 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.c 
b/gcc/common/config/riscv/riscv-common.c
index 34b74e52a2d..ad3180677be 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -101,6 +101,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
 
+  {"zmmul",  ISA_SPEC_CLASS_NONE, 0, 1},
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -904,6 +905,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zicsr",_options::x_riscv_zi_subext, MASK_ZICSR},
   {"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
 
+  {"zmmul", _options::x_riscv_zmmul_subext, MASK_ZMMUL},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index efd4a61ea29..72aa4e389c0 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_ATOMIC)
 builtin_define ("__riscv_atomic");
 
-  if (TARGET_MUL)
+  if (TARGET_MUL || TARGET_ZMMUL)
 builtin_define ("__riscv_mul");
   if (TARGET_DIV)
 builtin_define ("__riscv_div");
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f4cf6ca4b82..c52b18ebd80 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -73,4 +73,7 @@ enum stack_protector_guard {
 #define TARGET_ZICSR((riscv_zi_subext & MASK_ZICSR) != 0)
 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
 
+#define MASK_ZMMUL (1 << 0)
+#define TARGET_ZMMUL ((riscv_zmmul_subext & MASK_ZMMUL) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 17cdf705c32..4f5cb35e625 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1872,7 +1872,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
 case MULT:
   if (float_mode_p)
*total = tune_param->fp_mul[mode == DFmode];
-  else if (!TARGET_MUL)
+  else if (!TARGET_MUL && !TARGET_ZMMUL)
/* Estimate the cost of a library call.  */
*total = COSTS_N_INSNS (speed ? 32 : 6);
   else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
@@ -4736,6 +4736,9 @@ riscv_option_override (void)
   if (flag_pic)
 g_switch_value = 0;
 
+  /* zmmul */
+  if (TARGET_ZMMUL && TARGET_MUL)
+error ("can not use both the % and the % extension");
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
   if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c3687d57047..2ee7d801f1a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -600,7 +600,7 @@
   [(set (match_operand:SI  0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r")))]
-  "TARGET_MUL"
+  "(TARGET_MUL || TARGET_ZMMUL)"
   { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -609,7 +609,7 @@
   [(set (match_operand:DI  0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "register_operand" " r")
 (match_operand:DI 2 "register_operand" " r")))]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT"
   "mul\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -619,7 +619,7 @@
(sign_extend:DI
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r"]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT"
   "mulw\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -630,7 +630,7 @@
  (match_operator:SI 3 "subreg_lowpart_operator"
[(mult:DI (match_operand:DI 1 "register_operand" " r")
  (match_operand:DI 2 "register_operand" " r"))])))]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT"
   "mulw\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -648,7 +648,7 @@
   [(set (match_operand:TI 0 "register_operand")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
 (any_extend:TI (match_operand:DI 2