Re: Re: [Committed] RISC-V: Support VLS INT <-> FP conversions

2023-09-22 Thread 钟居哲 
Confirm it is a latent bug already existed long time ago but we were lucky that 
we didn't trigger this issue before.

This patch didn't involve a new bug.

Li pan from intel will send a patch fix it soon.

Thanks for report.



juzhe.zh...@rivai.ai
 
From: Edwin Lu
Date: 2023-09-23 06:38
To: Juzhe-Zhong; gcc-patches
CC: patrick; gnu-toolchain
Subject: Re: [Committed] RISC-V: Support VLS INT <-> FP conversions
Hi Juzhe,
 
I was testing this patch and found it introduced a gfortran regression 
in gfortran.dg/host_assoc_function_7.f90. More info here: 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545
 
Edwin
 
On 9/20/2023 7:17 PM, Juzhe-Zhong wrote:
> Support INT <-> FP VLS auto-vectorization patterns.
> 
> Regression passed.
> Committed.
> 
> gcc/ChangeLog:
> 
> * config/riscv/autovec.md: Extend VLS modes.
> * config/riscv/vector-iterators.md: Ditto.
> * config/riscv/vector.md: Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
> * gcc.target/riscv/rvv/autovec/vls/convert-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-10.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-11.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-12.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-7.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-8.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/convert-9.c: New test.
> 
> ---
>   gcc/config/riscv/autovec.md   |  12 +-
>   gcc/config/riscv/vector-iterators.md  | 202 ++
>   gcc/config/riscv/vector.md|  20 +-
>   .../riscv/rvv/autovec/vls/convert-1.c |  74 +++
>   .../riscv/rvv/autovec/vls/convert-10.c|  80 +++
>   .../riscv/rvv/autovec/vls/convert-11.c|  54 +
>   .../riscv/rvv/autovec/vls/convert-12.c|  36 
>   .../riscv/rvv/autovec/vls/convert-2.c |  74 +++
>   .../riscv/rvv/autovec/vls/convert-3.c |  58 +
>   .../riscv/rvv/autovec/vls/convert-4.c |  36 
>   .../riscv/rvv/autovec/vls/convert-5.c |  80 +++
>   .../riscv/rvv/autovec/vls/convert-6.c |  55 +
>   .../riscv/rvv/autovec/vls/convert-7.c |  37 
>   .../riscv/rvv/autovec/vls/convert-8.c |  58 +
>   .../riscv/rvv/autovec/vls/convert-9.c |  22 ++
>   15 files changed, 882 insertions(+), 16 deletions(-)
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
>   create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c
> 
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 75ed7ae4f2e..55c0a04df3b 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -847,7 +847,7 @@
>   (define_insn_and_split "2"
> [(set (match_operand: 0 "register_operand")
>   (any_fix:
> -   (match_operand:VF 1 "register_operand")))]
> +   (match_operand:V_VLSF 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -868,8 +868,8 @@
>   ;; -
>   
>   (define_insn_and_split "2"
> -  [(set (match_operand:VF 0 "register_operand")
> - (any_float:VF
> +  [(set (match_operand:V_VLSF 0 "register_operand")
> + (any_float:V_VLSF
> (match_operand: 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
>

Re: [Committed] RISC-V: Support VLS INT <-> FP conversions

2023-09-22 Thread Edwin Lu 

Hi Juzhe,

I was testing this patch and found it introduced a gfortran regression 
in gfortran.dg/host_assoc_function_7.f90. More info here: 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545


Edwin

On 9/20/2023 7:17 PM, Juzhe-Zhong wrote:

Support INT <-> FP VLS auto-vectorization patterns.

Regression passed.
Committed.

gcc/ChangeLog:

* config/riscv/autovec.md: Extend VLS modes.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/convert-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-9.c: New test.

---
  gcc/config/riscv/autovec.md   |  12 +-
  gcc/config/riscv/vector-iterators.md  | 202 ++
  gcc/config/riscv/vector.md|  20 +-
  .../riscv/rvv/autovec/vls/convert-1.c |  74 +++
  .../riscv/rvv/autovec/vls/convert-10.c|  80 +++
  .../riscv/rvv/autovec/vls/convert-11.c|  54 +
  .../riscv/rvv/autovec/vls/convert-12.c|  36 
  .../riscv/rvv/autovec/vls/convert-2.c |  74 +++
  .../riscv/rvv/autovec/vls/convert-3.c |  58 +
  .../riscv/rvv/autovec/vls/convert-4.c |  36 
  .../riscv/rvv/autovec/vls/convert-5.c |  80 +++
  .../riscv/rvv/autovec/vls/convert-6.c |  55 +
  .../riscv/rvv/autovec/vls/convert-7.c |  37 
  .../riscv/rvv/autovec/vls/convert-8.c |  58 +
  .../riscv/rvv/autovec/vls/convert-9.c |  22 ++
  15 files changed, 882 insertions(+), 16 deletions(-)
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 75ed7ae4f2e..55c0a04df3b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -847,7 +847,7 @@
  (define_insn_and_split "2"
[(set (match_operand: 0 "register_operand")
(any_fix:
- (match_operand:VF 1 "register_operand")))]
+ (match_operand:V_VLSF 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -868,8 +868,8 @@
  ;; -
  
  (define_insn_and_split "2"

-  [(set (match_operand:VF 0 "register_operand")
-   (any_float:VF
+  [(set (match_operand:V_VLSF 0 "register_operand")
+   (any_float:V_VLSF
  (match_operand: 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -916,8 +916,8 @@
  ;; - vfwcvt.f.x.v
  ;; -
  (define_insn_and_split "2"
-  [(set (match_operand:VF 0 "register_operand")
-   (any_float:VF
+  [(set (match_operand:V_VLSF 0 "register_operand")
+   (any_float:V_VLSF
  (match_operand: 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -940,7 +940,7 @@
  (define_insn_and_split "2"
[(set (match_operand: 0 "register_operand")
(any_fix:
- (match_operand:VF 1 "register_operand")))]
+ (match_operand:V_VLSF 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 053d84c0c7d..19f3ec3ef74 100644
--- a/gcc/config/riscv/vector-iterators.md
+++

[Committed] RISC-V: Support VLS INT <-> FP conversions

2023-09-20 Thread Juzhe-Zhong 
Support INT <-> FP VLS auto-vectorization patterns.

Regression passed.
Committed.

gcc/ChangeLog:

* config/riscv/autovec.md: Extend VLS modes.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/convert-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-9.c: New test.

---
 gcc/config/riscv/autovec.md   |  12 +-
 gcc/config/riscv/vector-iterators.md  | 202 ++
 gcc/config/riscv/vector.md|  20 +-
 .../riscv/rvv/autovec/vls/convert-1.c |  74 +++
 .../riscv/rvv/autovec/vls/convert-10.c|  80 +++
 .../riscv/rvv/autovec/vls/convert-11.c|  54 +
 .../riscv/rvv/autovec/vls/convert-12.c|  36 
 .../riscv/rvv/autovec/vls/convert-2.c |  74 +++
 .../riscv/rvv/autovec/vls/convert-3.c |  58 +
 .../riscv/rvv/autovec/vls/convert-4.c |  36 
 .../riscv/rvv/autovec/vls/convert-5.c |  80 +++
 .../riscv/rvv/autovec/vls/convert-6.c |  55 +
 .../riscv/rvv/autovec/vls/convert-7.c |  37 
 .../riscv/rvv/autovec/vls/convert-8.c |  58 +
 .../riscv/rvv/autovec/vls/convert-9.c |  22 ++
 15 files changed, 882 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 75ed7ae4f2e..55c0a04df3b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -847,7 +847,7 @@
 (define_insn_and_split "2"
   [(set (match_operand: 0 "register_operand")
(any_fix:
- (match_operand:VF 1 "register_operand")))]
+ (match_operand:V_VLSF 1 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -868,8 +868,8 @@
 ;; -
 
 (define_insn_and_split "2"
-  [(set (match_operand:VF 0 "register_operand")
-   (any_float:VF
+  [(set (match_operand:V_VLSF 0 "register_operand")
+   (any_float:V_VLSF
  (match_operand: 1 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
@@ -916,8 +916,8 @@
 ;; - vfwcvt.f.x.v
 ;; -
 (define_insn_and_split "2"
-  [(set (match_operand:VF 0 "register_operand")
-   (any_float:VF
+  [(set (match_operand:V_VLSF 0 "register_operand")
+   (any_float:V_VLSF
  (match_operand: 1 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
@@ -940,7 +940,7 @@
 (define_insn_and_split "2"
   [(set (match_operand: 0 "register_operand")
(any_fix:
- (match_operand:VF 1 "register_operand")))]
+ (match_operand:V_VLSF 1 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 053d84c0c7d..19f3ec3ef74 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1037,6 +1037,28 @@
   (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
   (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
   (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
+
+  (V1SI "TARGET_VECTOR_VLS && TARGET_ZVFH")
+  (V2SI