Re: [GCC, ARM] Backport trunk patch to 4.8 to reclassify ARM preload insn
ChangeLog is messed up with other one. On Thu, Jan 16, 2014 at 3:33 PM, Terry Guo terry@arm.com wrote: Hi, Current 4.8 branch will assign alu_reg attribute to the type of arm preload insn, which is clearly wrong. The attached patch intends to back port trunk patch to reclassify the type attribute as load1. With this back port, the 4.8 bug PR59826 can be fixed too. Tested with gcc regression test on QEMU Cortex-M3, no new regressions. Is it OK to back port this patch http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00322.html? BR, Terry
Re: [GCC, ARM] Backport trunk patch to 4.8 to reclassify ARM preload insn
On 16/01/14 07:33, Terry Guo wrote: Hi, Current 4.8 branch will assign alu_reg attribute to the type of arm preload insn, which is clearly wrong. The attached patch intends to back port trunk patch to reclassify the type attribute as load1. With this back port, the 4.8 bug PR59826 can be fixed too. Tested with gcc regression test on QEMU Cortex-M3, no new regressions. Is it OK to back port this patch http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00322.html? BR, Terry The patch to arm.md is OK. The ChangeLog entry should just describe the change you're making. Don't call this a back-port - it isn't really. R. backport-202323.txt Index: gcc/ChangeLog === --- gcc/ChangeLog (revision 206657) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,271 @@ +2014-01-16 Terry Guo terry@arm.com + + PR target/59826 + Partial Backport from mainline r202323. + 2013-09-06 James Greenhalgh james.greenha...@arm.com + + * config/arm/types.md: Add no_insn, multiple and untyped + types. + * config/arm/arm-fixed.md: Add type attribute to all insn + patterns. + (addmode3): Add type attribute. + (addmode3): Likewise. + (usaddmode3): Likewise. + (ssaddmode3): Likewise. + (submode3): Likewise. + (submode3): Likewise. + (ussubmode3): Likewise. + (sssubmode3): Likewise. + (ssmulsa3): Likewise. + (usmulusa3): Likewise. + (arm_usatsihi): Likewise. + * config/arm/vfp.md + (*movdi_vfp): Add types for all instructions. + (*movdi_vfp_cortexa8): Likewise. + (*movhf_vfp_neon): Likewise. + (*movhf_vfp): Likewise. + (*movdf_vfp): Likewise. + (*thumb2_movdf_vfp): Likewise. + (*thumb2_movdfcc_vfp): Likewise. + * config/arm/arm.md: Add type attribute to all insn patterns. + (*thumb1_adddi3): Add type attribute. + (*arm_adddi3): Likewise. + (*adddi_sesidi_di): Likewise. + (*adddi_zesidi_di): Likewise. + (*thumb1_addsi3): Likewise. + (addsi3_compare0): Likewise. + (*addsi3_compare0_scratch): Likewise. + (*compare_negsi_si): Likewise. + (cmpsi2_addneg): Likewise. + (*addsi3_carryin_optab): Likewise. + (*addsi3_carryin_alt2_optab): Likewise. + (*addsi3_carryin_clobercc_optab): Likewise. + (*subsi3_carryin): Likewise. + (*subsi3_carryin_const): Likewise. + (*subsi3_carryin_compare): Likewise. + (*subsi3_carryin_compare_const): Likewise. + (*arm_subdi3): Likewise. + (*thumb_subdi3): Likewise. + (*subdi_di_zesidi): Likewise. + (*subdi_di_sesidi): Likewise. + (*subdi_zesidi_di): Likewise. + (*subdi_sesidi_di): Likewise. + (*subdi_zesidi_ze): Likewise. + (thumb1_subsi3_insn): Likewise. + (*arm_subsi3_insn): Likewise. + (*anddi3_insn): Likewise. + (*anddi_zesidi_di): Likewise. + (*anddi_sesdi_di): Likewise. + (*ne_zeroextracts): Likewise. + (*ne_zeroextracts): Likewise. + (*ite_ne_zeroextr): Likewise. + (*ite_ne_zeroextr): Likewise. + (*anddi_notdi_di): Likewise. + (*anddi_notzesidi): Likewise. + (*anddi_notsesidi): Likewise. + (andsi_notsi_si): Likewise. + (thumb1_bicsi3): Likewise. + (*iordi3_insn): Likewise. + (*iordi_zesidi_di): Likewise. + (*iordi_sesidi_di): Likewise. + (*thumb1_iorsi3_insn): Likewise. + (*xordi3_insn): Likewise. + (*xordi_zesidi_di): Likewise. + (*xordi_sesidi_di): Likewise. + (*arm_xorsi3): Likewise. + (*andsi_iorsi3_no): Likewise. + (*smax_0): Likewise. + (*smax_m1): Likewise. + (*arm_smax_insn): Likewise. + (*smin_0): Likewise. + (*arm_smin_insn): Likewise. + (*arm_umaxsi3): Likewise. + (*arm_uminsi3): Likewise. + (*minmax_arithsi): Likewise. + (*minmax_arithsi_): Likewise. + (*satsi_SAT:code): Likewise. + (arm_ashldi3_1bit): Likewise. + (arm_ashrdi3_1bit): Likewise. + (arm_lshrdi3_1bit): Likewise. + (*arm_negdi2): Likewise. + (*thumb1_negdi2): Likewise. + (*arm_negsi2): Likewise. + (*thumb1_negsi2): Likewise. + (*negdi_extendsid): Likewise. + (*negdi_zero_extend): Likewise. + (*arm_abssi2): Likewise. + (*thumb1_abssi2): Likewise. + (*arm_neg_abssi2): Likewise. + (*thumb1_neg_abss): Likewise. + (one_cmpldi2): Likewise. + (extendmodedi2): Likewise. + (*compareqi_eq0): Likewise. + (*arm_extendhisi2addsi): Likewise. + (*arm_movdi): Likewise. + (*thumb1_movdi_insn): Likewise. + (*arm_movt): Likewise. + (*thumb1_movsi_insn): Likewise. + (pic_add_dot_plus_four): Likewise. + (pic_add_dot_plus_eight): Likewise. + (tls_load_dot_plus_eight): Likewise. + (*thumb1_movhi_insn): Likewise. + (*thumb1_movsf_insn): Likewise. + (*movdf_soft_insn): Likewise. + (*thumb_movdf_insn): Likewise. +
RE: [GCC, ARM] Backport trunk patch to 4.8 to reclassify ARM preload insn
-Original Message- From: Richard Earnshaw Sent: Friday, January 17, 2014 12:22 AM To: Terry Guo Cc: gcc-patches@gcc.gnu.org Subject: Re: [GCC, ARM] Backport trunk patch to 4.8 to reclassify ARM preload insn On 16/01/14 07:33, Terry Guo wrote: Hi, Current 4.8 branch will assign alu_reg attribute to the type of arm preload insn, which is clearly wrong. The attached patch intends to back port trunk patch to reclassify the type attribute as load1. With this back port, the 4.8 bug PR59826 can be fixed too. Tested with gcc regression test on QEMU Cortex-M3, no new regressions. Is it OK to back port this patch http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00322.html? BR, Terry The patch to arm.md is OK. The ChangeLog entry should just describe the change you're making. Don't call this a back-port - it isn't really. R. OK. The updated patch is committed at http://gcc.gnu.org/ml/gcc-cvs/2014-01/msg00436.html. BR, Terry
[GCC, ARM] Backport trunk patch to 4.8 to reclassify ARM preload insn
Hi, Current 4.8 branch will assign alu_reg attribute to the type of arm preload insn, which is clearly wrong. The attached patch intends to back port trunk patch to reclassify the type attribute as load1. With this back port, the 4.8 bug PR59826 can be fixed too. Tested with gcc regression test on QEMU Cortex-M3, no new regressions. Is it OK to back port this patch http://gcc.gnu.org/ml/gcc-patches/2013-09/msg00322.html? BR, TerryIndex: gcc/ChangeLog === --- gcc/ChangeLog (revision 206657) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,271 @@ +2014-01-16 Terry Guo terry@arm.com + + PR target/59826 + Partial Backport from mainline r202323. + 2013-09-06 James Greenhalgh james.greenha...@arm.com + + * config/arm/types.md: Add no_insn, multiple and untyped + types. + * config/arm/arm-fixed.md: Add type attribute to all insn + patterns. + (addmode3): Add type attribute. + (addmode3): Likewise. + (usaddmode3): Likewise. + (ssaddmode3): Likewise. + (submode3): Likewise. + (submode3): Likewise. + (ussubmode3): Likewise. + (sssubmode3): Likewise. + (ssmulsa3): Likewise. + (usmulusa3): Likewise. + (arm_usatsihi): Likewise. + * config/arm/vfp.md + (*movdi_vfp): Add types for all instructions. + (*movdi_vfp_cortexa8): Likewise. + (*movhf_vfp_neon): Likewise. + (*movhf_vfp): Likewise. + (*movdf_vfp): Likewise. + (*thumb2_movdf_vfp): Likewise. + (*thumb2_movdfcc_vfp): Likewise. + * config/arm/arm.md: Add type attribute to all insn patterns. + (*thumb1_adddi3): Add type attribute. + (*arm_adddi3): Likewise. + (*adddi_sesidi_di): Likewise. + (*adddi_zesidi_di): Likewise. + (*thumb1_addsi3): Likewise. + (addsi3_compare0): Likewise. + (*addsi3_compare0_scratch): Likewise. + (*compare_negsi_si): Likewise. + (cmpsi2_addneg): Likewise. + (*addsi3_carryin_optab): Likewise. + (*addsi3_carryin_alt2_optab): Likewise. + (*addsi3_carryin_clobercc_optab): Likewise. + (*subsi3_carryin): Likewise. + (*subsi3_carryin_const): Likewise. + (*subsi3_carryin_compare): Likewise. + (*subsi3_carryin_compare_const): Likewise. + (*arm_subdi3): Likewise. + (*thumb_subdi3): Likewise. + (*subdi_di_zesidi): Likewise. + (*subdi_di_sesidi): Likewise. + (*subdi_zesidi_di): Likewise. + (*subdi_sesidi_di): Likewise. + (*subdi_zesidi_ze): Likewise. + (thumb1_subsi3_insn): Likewise. + (*arm_subsi3_insn): Likewise. + (*anddi3_insn): Likewise. + (*anddi_zesidi_di): Likewise. + (*anddi_sesdi_di): Likewise. + (*ne_zeroextracts): Likewise. + (*ne_zeroextracts): Likewise. + (*ite_ne_zeroextr): Likewise. + (*ite_ne_zeroextr): Likewise. + (*anddi_notdi_di): Likewise. + (*anddi_notzesidi): Likewise. + (*anddi_notsesidi): Likewise. + (andsi_notsi_si): Likewise. + (thumb1_bicsi3): Likewise. + (*iordi3_insn): Likewise. + (*iordi_zesidi_di): Likewise. + (*iordi_sesidi_di): Likewise. + (*thumb1_iorsi3_insn): Likewise. + (*xordi3_insn): Likewise. + (*xordi_zesidi_di): Likewise. + (*xordi_sesidi_di): Likewise. + (*arm_xorsi3): Likewise. + (*andsi_iorsi3_no): Likewise. + (*smax_0): Likewise. + (*smax_m1): Likewise. + (*arm_smax_insn): Likewise. + (*smin_0): Likewise. + (*arm_smin_insn): Likewise. + (*arm_umaxsi3): Likewise. + (*arm_uminsi3): Likewise. + (*minmax_arithsi): Likewise. + (*minmax_arithsi_): Likewise. + (*satsi_SAT:code): Likewise. + (arm_ashldi3_1bit): Likewise. + (arm_ashrdi3_1bit): Likewise. + (arm_lshrdi3_1bit): Likewise. + (*arm_negdi2): Likewise. + (*thumb1_negdi2): Likewise. + (*arm_negsi2): Likewise. + (*thumb1_negsi2): Likewise. + (*negdi_extendsid): Likewise. + (*negdi_zero_extend): Likewise. + (*arm_abssi2): Likewise. + (*thumb1_abssi2): Likewise. + (*arm_neg_abssi2): Likewise. + (*thumb1_neg_abss): Likewise. + (one_cmpldi2): Likewise. + (extendmodedi2): Likewise. + (*compareqi_eq0): Likewise. + (*arm_extendhisi2addsi): Likewise. + (*arm_movdi): Likewise. + (*thumb1_movdi_insn): Likewise. + (*arm_movt): Likewise. + (*thumb1_movsi_insn): Likewise. + (pic_add_dot_plus_four): Likewise. + (pic_add_dot_plus_eight): Likewise. + (tls_load_dot_plus_eight): Likewise. + (*thumb1_movhi_insn): Likewise. + (*thumb1_movsf_insn): Likewise. + (*movdf_soft_insn): Likewise. + (*thumb_movdf_insn): Likewise. + (cbranchsi4_insn): Likewise. + (cbranchsi4_scratch): Likewise. + (*negated_cbranchsi4): Likewise. +
