[PATCH, AArch64] Implement ctz and clrsb standard patterns

[Ian Bolton]

I've implemented the following standard patterns:

* clrsb
* ctz

Regression runs passed and I have added compilation tests for them,
and clz as well.   (Execution tests are covered by
gcc/testsuite/gcc.c-torture/execute/builtin-bitops-1.c.)

OK for aarch64-branch and aarch64-4.7-branch?

Cheers,
Ian


2012-09-18  Ian Bolton  ian.bol...@arm.com

gcc/
* config/aarch64/aarch64.h: Define CTZ_DEFINED_VALUE_AT_ZERO.
* config/aarch64/aarch64.md (clrsbmode2): New pattern.
* config/aarch64/aarch64.md (rbitmode2): New pattern.
* config/aarch64/aarch64.md (ctzmode2): New pattern.

gcc/testsuite/
* gcc.target/aarch64/clrsb.c: New test.
* gcc.target/aarch64/clz.c: New test.
* gcc.target/aarch64/ctz.c: New test.diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 5d121fa..abf96c5 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -703,6 +703,8 @@ do {
 \
 
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
   ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+  ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
 
 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 33815ff..5278957 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -153,6 +153,8 @@
 (UNSPEC_CMTST   83) ; Used in aarch64-simd.md.
 (UNSPEC_FMAX83) ; Used in aarch64-simd.md.
 (UNSPEC_FMIN84) ; Used in aarch64-simd.md.
+(UNSPEC_CLS 85) ; Used in aarch64-simd.md.
+(UNSPEC_RBIT86) ; Used in aarch64-simd.md.
   ]
 )
 
@@ -2128,6 +2130,33 @@
   [(set_attr v8type clz)
(set_attr mode MODE)])
 
+(define_insn clrsbmode2
+  [(set (match_operand:GPI 0 register_operand =r)
+   (unspec:GPI [(match_operand:GPI 1 register_operand r)] UNSPEC_CLS))]
+  
+  cls\\t%w0, %w1
+  [(set_attr v8type clz)
+   (set_attr mode MODE)])
+
+(define_insn rbitmode2
+  [(set (match_operand:GPI 0 register_operand =r)
+   (unspec:GPI [(match_operand:GPI 1 register_operand r)] 
UNSPEC_RBIT))]
+  
+  rbit\\t%w0, %w1
+  [(set_attr v8type rbit)
+   (set_attr mode MODE)])
+
+(define_expand ctzmode2
+  [(match_operand:GPI 0 register_operand)
+   (match_operand:GPI 1 register_operand)]
+  
+  {
+emit_insn (gen_rbitmode2 (operands[0], operands[1]));
+emit_insn (gen_clzmode2 (operands[0], operands[0]));
+DONE;
+  }
+)
+
 (define_insn *andmode3nr_compare0
   [(set (reg:CC CC_REGNUM)
(compare:CC
diff --git a/gcc/testsuite/gcc.target/aarch64/clrsb.c 
b/gcc/testsuite/gcc.target/aarch64/clrsb.c
new file mode 100644
index 000..a75dfa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clrsb.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest(unsigned int x)
+{
+   return __builtin_clrsb(x);
+}
+
+/* { dg-final { scan-assembler cls\tw } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/clz.c 
b/gcc/testsuite/gcc.target/aarch64/clz.c
new file mode 100644
index 000..66e2d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clz.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest(unsigned int x)
+{
+   return __builtin_clz(x);
+}
+
+/* { dg-final { scan-assembler clz\tw } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ctz.c 
b/gcc/testsuite/gcc.target/aarch64/ctz.c
new file mode 100644
index 000..15a2473
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ctz.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest(unsigned int x)
+{
+  return __builtin_ctz(x);
+}
+
+/* { dg-final { scan-assembler rbit\tw } } */
+/* { dg-final { scan-assembler clz\tw } } */
+

Re: [PATCH, AArch64] Implement ctz and clrsb standard patterns

[Andreas Schwab]

Ian Bolton ian.bol...@arm.com writes:

 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
 index 33815ff..5278957 100644
 --- a/gcc/config/aarch64/aarch64.md
 +++ b/gcc/config/aarch64/aarch64.md
 @@ -153,6 +153,8 @@
  (UNSPEC_CMTST 83) ; Used in aarch64-simd.md.
  (UNSPEC_FMAX  83) ; Used in aarch64-simd.md.
  (UNSPEC_FMIN  84) ; Used in aarch64-simd.md.
 +(UNSPEC_CLS   85) ; Used in aarch64-simd.md.
 +(UNSPEC_RBIT  86) ; Used in aarch64-simd.md.

The comment doesn't appear to be true.

Andreas.

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
And now for something completely different.

RE: [PATCH, AArch64] Implement ctz and clrsb standard patterns

[Ian Bolton]

  diff --git a/gcc/config/aarch64/aarch64.md
 b/gcc/config/aarch64/aarch64.md
  index 33815ff..5278957 100644
  --- a/gcc/config/aarch64/aarch64.md
  +++ b/gcc/config/aarch64/aarch64.md
  @@ -153,6 +153,8 @@
   (UNSPEC_CMTST   83) ; Used in aarch64-simd.md.
   (UNSPEC_FMAX83) ; Used in aarch64-simd.md.
   (UNSPEC_FMIN84) ; Used in aarch64-simd.md.
  +(UNSPEC_CLS 85) ; Used in aarch64-simd.md.
  +(UNSPEC_RBIT86) ; Used in aarch64-simd.md.
 
 The comment doesn't appear to be true.
 

Fair point!  I will fix that.

RE: [PATCH, AArch64] Implement ctz and clrsb standard patterns

[Ian Bolton]

   diff --git a/gcc/config/aarch64/aarch64.md
  b/gcc/config/aarch64/aarch64.md
   index 33815ff..5278957 100644
   --- a/gcc/config/aarch64/aarch64.md
   +++ b/gcc/config/aarch64/aarch64.md
   @@ -153,6 +153,8 @@
(UNSPEC_CMTST 83) ; Used in aarch64-simd.md.
(UNSPEC_FMAX  83) ; Used in aarch64-simd.md.
(UNSPEC_FMIN  84) ; Used in aarch64-simd.md.
   +(UNSPEC_CLS   85) ; Used in aarch64-simd.md.
   +(UNSPEC_RBIT  86) ; Used in aarch64-simd.md.
 
  The comment doesn't appear to be true.
 
 
 Fair point!  I will fix that.
 

New patch with comment fixed is attached.

Now good to commit to aarch64-branch and aarch64-4.7-branch?

Cheers,
Iandiff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 5d121fa..abf96c5 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -703,6 +703,8 @@ do {
 \
 
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
   ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+  ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
 
 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 33815ff..5278957 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -153,6 +153,8 @@
 (UNSPEC_CMTST   83) ; Used in aarch64-simd.md.
 (UNSPEC_FMAX83) ; Used in aarch64-simd.md.
 (UNSPEC_FMIN84) ; Used in aarch64-simd.md.
+(UNSPEC_CLS 85) ; Used in aarch64.md.
+(UNSPEC_RBIT86) ; Used in aarch64.md.
   ]
 )
 
@@ -2128,6 +2130,33 @@
   [(set_attr v8type clz)
(set_attr mode MODE)])
 
+(define_insn clrsbmode2
+  [(set (match_operand:GPI 0 register_operand =r)
+   (unspec:GPI [(match_operand:GPI 1 register_operand r)] UNSPEC_CLS))]
+  
+  cls\\t%w0, %w1
+  [(set_attr v8type clz)
+   (set_attr mode MODE)])
+
+(define_insn rbitmode2
+  [(set (match_operand:GPI 0 register_operand =r)
+   (unspec:GPI [(match_operand:GPI 1 register_operand r)] 
UNSPEC_RBIT))]
+  
+  rbit\\t%w0, %w1
+  [(set_attr v8type rbit)
+   (set_attr mode MODE)])
+
+(define_expand ctzmode2
+  [(match_operand:GPI 0 register_operand)
+   (match_operand:GPI 1 register_operand)]
+  
+  {
+emit_insn (gen_rbitmode2 (operands[0], operands[1]));
+emit_insn (gen_clzmode2 (operands[0], operands[0]));
+DONE;
+  }
+)
+
 (define_insn *andmode3nr_compare0
   [(set (reg:CC CC_REGNUM)
(compare:CC
diff --git a/gcc/testsuite/gcc.target/aarch64/clrsb.c 
b/gcc/testsuite/gcc.target/aarch64/clrsb.c
new file mode 100644
index 000..a75dfa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clrsb.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest(unsigned int x)
+{
+   return __builtin_clrsb(x);
+}
+
+/* { dg-final { scan-assembler cls\tw } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/clz.c 
b/gcc/testsuite/gcc.target/aarch64/clz.c
new file mode 100644
index 000..66e2d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clz.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest(unsigned int x)
+{
+   return __builtin_clz(x);
+}
+
+/* { dg-final { scan-assembler clz\tw } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ctz.c 
b/gcc/testsuite/gcc.target/aarch64/ctz.c
new file mode 100644
index 000..15a2473
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ctz.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest(unsigned int x)
+{
+  return __builtin_ctz(x);
+}
+
+/* { dg-final { scan-assembler rbit\tw } } */
+/* { dg-final { scan-assembler clz\tw } } */
+

RE: [PATCH, AArch64] Implement ctz and clrsb standard patterns

[Ian Bolton]

New version attached with better formatted test cases.

OK for aarch64-branch and aarch64-4.7-branch?

Cheers,
Ian


-

2012-09-18  Ian Bolton  ian.bol...@arm.com

gcc/
* config/aarch64/aarch64.h: Define CTZ_DEFINED_VALUE_AT_ZERO.
* config/aarch64/aarch64.md (clrsbmode2): New pattern.
* config/aarch64/aarch64.md (rbitmode2): New pattern.
* config/aarch64/aarch64.md (ctzmode2): New pattern.

gcc/testsuite/
* gcc.target/aarch64/clrsb.c: New test.
* gcc.target/aarch64/clz.c: New test.
* gcc.target/aarch64/ctz.c: New test.diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 5d121fa..abf96c5 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -703,6 +703,8 @@ do {
 \
 
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
   ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+  ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
 
 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 33815ff..5278957 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -153,6 +153,8 @@
 (UNSPEC_CMTST   83) ; Used in aarch64-simd.md.
 (UNSPEC_FMAX83) ; Used in aarch64-simd.md.
 (UNSPEC_FMIN84) ; Used in aarch64-simd.md.
+(UNSPEC_CLS 85) ; Used in aarch64.md.
+(UNSPEC_RBIT86) ; Used in aarch64.md.
   ]
 )
 
@@ -2128,6 +2130,33 @@
   [(set_attr v8type clz)
(set_attr mode MODE)])
 
+(define_insn clrsbmode2
+  [(set (match_operand:GPI 0 register_operand =r)
+   (unspec:GPI [(match_operand:GPI 1 register_operand r)] UNSPEC_CLS))]
+  
+  cls\\t%w0, %w1
+  [(set_attr v8type clz)
+   (set_attr mode MODE)])
+
+(define_insn rbitmode2
+  [(set (match_operand:GPI 0 register_operand =r)
+   (unspec:GPI [(match_operand:GPI 1 register_operand r)] 
UNSPEC_RBIT))]
+  
+  rbit\\t%w0, %w1
+  [(set_attr v8type rbit)
+   (set_attr mode MODE)])
+
+(define_expand ctzmode2
+  [(match_operand:GPI 0 register_operand)
+   (match_operand:GPI 1 register_operand)]
+  
+  {
+emit_insn (gen_rbitmode2 (operands[0], operands[1]));
+emit_insn (gen_clzmode2 (operands[0], operands[0]));
+DONE;
+  }
+)
+
 (define_insn *andmode3nr_compare0
   [(set (reg:CC CC_REGNUM)
(compare:CC
diff --git a/gcc/testsuite/gcc.target/aarch64/clrsb.c 
b/gcc/testsuite/gcc.target/aarch64/clrsb.c
new file mode 100644
index 000..a75dfa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clrsb.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest (unsigned int x)
+{
+  return __builtin_clrsb (x);
+}
+
+/* { dg-final { scan-assembler cls\tw } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/clz.c 
b/gcc/testsuite/gcc.target/aarch64/clz.c
new file mode 100644
index 000..66e2d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clz.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest (unsigned int x)
+{
+  return __builtin_clz (x);
+}
+
+/* { dg-final { scan-assembler clz\tw } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ctz.c 
b/gcc/testsuite/gcc.target/aarch64/ctz.c
new file mode 100644
index 000..15a2473
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ctz.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+unsigned int functest (unsigned int x)
+{
+  return __builtin_ctz (x);
+}
+
+/* { dg-final { scan-assembler rbit\tw } } */
+/* { dg-final { scan-assembler clz\tw } } */
+

Re: [PATCH, AArch64] Implement ctz and clrsb standard patterns

[Richard Earnshaw]

On 18/09/12 14:24, Ian Bolton wrote:
 New version attached with better formatted test cases.
 
 OK for aarch64-branch and aarch64-4.7-branch?
 
 Cheers,
 Ian
 
 
 -
 
 2012-09-18  Ian Bolton  ian.bol...@arm.com
 
 gcc/
   * config/aarch64/aarch64.h: Define CTZ_DEFINED_VALUE_AT_ZERO.
   * config/aarch64/aarch64.md (clrsbmode2): New pattern.
   * config/aarch64/aarch64.md (rbitmode2): New pattern.
   * config/aarch64/aarch64.md (ctzmode2): New pattern.
 
 gcc/testsuite/
   * gcc.target/aarch64/clrsb.c: New test.
   * gcc.target/aarch64/clz.c: New test.
   * gcc.target/aarch64/ctz.c: New test.
 
 

OK.

R.