Re: [PATCH, ARM] Avoid element-order-dependent operations for quad-word vectors in big-endian mode for NEON

2011-06-30 Thread Richard Earnshaw
On 12/01/11 17:38, Julian Brown wrote:
 On Thu, 9 Dec 2010 14:56:39 +
 Julian Brown jul...@codesourcery.com wrote:
 
 On Thu, 9 Dec 2010 14:40:59 + (UTC)
 Joseph S. Myers jos...@codesourcery.com wrote:

 On Thu, 9 Dec 2010, Julian Brown wrote:

 Unfortunately for C only, since building C++ was broken at the
 time I started testing. Some tests fail to vectorize post-patch
 in BE mode (predictably, since fewer things end up vectorizable),
 but many execution tests transition from FAIL to PASS.

 Do any tests (scan, not execution) now fail for big endian in ways
 that indicate some of the check_effective_target_vect_* functions
 in target-supports.exp should be updated to know that certain
 features are only supported for little endian?

 Possibly, yes: I suspect a few of those may need updating, really. One
 awkward bit is that I'm still allowing some of the operations for
 double-word registers only -- I don't think the
 check_effective_target_* tests will suffice to distinguish between
 D-reg  Q-reg cases.
 
 This version of the patch tweaks target-supports.exp to say that
 various operations are not available in big-endian mode (removing some
 of the FAILs from the previous version -- though in big-endian mode
 without -mvectorize-with-neon-quad, some tests have transitioned from
 PASS to XPASS. I'm not sure that's worth worrying about).
 
 The main part of the patch remains unchanged.
 
 OK to apply?
 
 Cheers,
 
 Julian
 
 ChangeLog
 
 gcc/
 * config/arm/neon.md (vec_shr_mode, vec_shl_mode): Disable in
 big-endian mode.
 (reduc_splus_mode, reduc_uplus_mode, reduc_smin_mode)
 (reduc_smax_mode, reduc_umin_mode, reduc_umax_mode)
 (neon_vec_unpackUS_lo_mode, neon_vec_unpackUS_hi_mode)
 (vec_unpackUS_hi_mode, vec_unpackUS_lo_mode)
 (neon_vec_USmult_lo_mode, vec_widen_USmult_lo_mode)
 (neon_vec_USmult_hi_mode, vec_widen_USmult_hi_mode)
 (vec_pack_trunc_mode, neon_vec_pack_trunc_mode): Disable for Q
 registers in big-endian mode.
 
 gcc/testsuite/
 * lib/target-supports.exp
 (check_effective_target_arm_little_endian): New.
 (check_effective_target_vect_pack_trunc): Use above.
 (check_effective_target_vect_unpack): Likewise.
 (check_effective_target_vect_element_align): Test
 check_effective_target_arm_vect_no_misalign for ARM.
 
 

OK.

R.



Re: [PATCH, ARM] Avoid element-order-dependent operations for quad-word vectors in big-endian mode for NEON

2011-04-05 Thread Julian Brown
On Wed, 9 Feb 2011 12:11:35 +
Julian Brown jul...@codesourcery.com wrote:

 On Wed, 12 Jan 2011 17:38:22 +
 Julian Brown jul...@codesourcery.com wrote:
 
  This version of the patch tweaks target-supports.exp to say that
  various operations are not available in big-endian mode (removing
  some of the FAILs from the previous version -- though in big-endian
  mode without -mvectorize-with-neon-quad, some tests have
  transitioned from PASS to XPASS. I'm not sure that's worth worrying
  about).
  
  The main part of the patch remains unchanged.
 
 Ping?

Ping?

(Patch: http://gcc.gnu.org/ml/gcc-patches/2011-01/msg00768.html)

Thanks,

Julian