Re: [PATCH, MIPS] DSP ALU scheduling

2012-08-16 Thread Sandra Loosemore 

On 08/16/2012 01:27 PM, Richard Sandiford wrote:

Sandra Loosemoresan...@codesourcery.com  writes:

@@ -569,7 +569,7 @@
   UNSPEC_DPAU_H_QBL))]
ISA_HAS_DSP  !TARGET_64BIT
dpau.h.qbl\t%q0,%2,%3
-  [(set_attr type  imadd)
+  [(set_attr type  dspmac)
 (set_attr mode SI)])

  (define_insn mips_dpau_h_qbr
[etc]


I think all these want (set_attr accum_in 1) too.


Eeek, you are right.  I have checked in the obvious patch to correct this.

-Sandra

2012-08-16  Sandra Loosemore  san...@codesourcery.com

gcc/
* config/mips/mips-dsp.md (mips_dpau_h_qbl, mips_dpau_h_qbr)
(mips_dpsu_h_qbl, mips_dpsu_h_qbr, mips_dpaq_s_w_ph)
(mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph, mips_dpaq_sa_l_w)
(mips_dpsq_sa_l_w, mips_maq_s_w_phl, mips_maq_s_w_phr)
(mips_maq_sa_w_phl, mips_maq_sa_w_phr): Add accum_in attribute.
Index: gcc/config/mips/mips-dsp.md
===
--- gcc/config/mips/mips-dsp.md	(revision 190453)
+++ gcc/config/mips/mips-dsp.md	(working copy)
@@ -570,6 +570,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpau.h.qbl\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 (define_insn mips_dpau_h_qbr
@@ -581,6 +582,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpau.h.qbr\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; DPSU*
@@ -593,6 +595,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpsu.h.qbl\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 (define_insn mips_dpsu_h_qbr
@@ -604,6 +607,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpsu.h.qbr\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; DPAQ*
@@ -620,6 +624,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpaq_s.w.ph\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; DPSQ*
@@ -636,6 +641,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpsq_s.w.ph\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; MULSAQ*
@@ -652,6 +658,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   mulsaq_s.w.ph\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; DPAQ*
@@ -668,6 +675,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpaq_sa.l.w\t%q0,%2,%3
   [(set_attr type	dspmacsat)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; DPSQ*
@@ -684,6 +692,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   dpsq_sa.l.w\t%q0,%2,%3
   [(set_attr type	dspmacsat)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; MAQ*
@@ -700,6 +709,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   maq_s.w.phl\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 (define_insn mips_maq_s_w_phr
@@ -715,6 +725,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   maq_s.w.phr\t%q0,%2,%3
   [(set_attr type	dspmac)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; MAQ_SA*
@@ -731,6 +742,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   maq_sa.w.phl\t%q0,%2,%3
   [(set_attr type	dspmacsat)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 (define_insn mips_maq_sa_w_phr
@@ -746,6 +758,7 @@
   ISA_HAS_DSP  !TARGET_64BIT
   maq_sa.w.phr\t%q0,%2,%3
   [(set_attr type	dspmacsat)
+   (set_attr accum_in 1)
(set_attr mode	SI)])
 
 ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation

Re: [PATCH, MIPS] DSP ALU scheduling

2012-08-15 Thread Sandra Loosemore 
On 08/04/2012 07:55 AM, Richard Sandiford wrote:
 Sandra Loosemoresan...@codesourcery.com  writes:
 This is another patch that has been present in our local source base for some
 years now.  It originally came from MIPS; I've verified that we have legal
 permission to contribute it to the FSF.

 The 74k.md parts of this patch depend on the not-yet-reviewed 74k madd 
 scheduler
 tweaks patch I posted the other day:

 http://gcc.gnu.org/ml/gcc-patches/2012-08/msg00062.html

 Assuming that one gets approved, is this patch OK for mainline?
 
 OK with:
 
 +/* DSP ALU can bypass data with no delays for the following pairs. */
 +enum insn_code dspalu_bypass_table[][2] =
 +{
 +  {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
 +  {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
 +  {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
 +  {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
 +  {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
 +  {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
 +  {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
 +  {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
 +};
 +
 +int
 +mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
 +{
 +  int i;
 +  int num_bypass = (sizeof (dspalu_bypass_table)
 +/ (2 * sizeof (enum insn_code)));
 
 this changed to ARRAY_SIZE (dspalu_bypass_table);

Here's the version I've checked in.  In addition to the change above, I 
implemented the suggestion here

http://gcc.gnu.org/ml/gcc-patches/2012-08/msg00463.html

to remove the uses of mips_mult_madd_chain_bypass_p.

-Sandra


2012-08-15  Sandra Loosemore  san...@codesourcery.com
Maxim Kuvyrkov  ma...@codesourcery.com
Julian Brown  jul...@codesourcery.com
MIPS Technologies, Inc.

gcc/
* config/mips/mips.md (dspmac, dspmacsat, accext, accmod, dspalu)
(dspalusat): Add insn types.
* config/mips/mips-dsp.md (addDSPV:mode3)
(mips_addDSP:dspfmt1_s_DSP:dspfmt2)
(subDSPV:mode3, mips_subDSP:dspfmt1_s_DSP:dspfmt2, mips_addsc)
(mips_addwc, mips_modsub, mips_raddu_w_qb, mips_absq_s_DSPQ:dspfmt2)
(mips_precrq_qb_ph, mips_precrq_ph_w, mips_precrq_rs_ph_w)
(mips_precrqu_s_qb_ph, mips_preceq_w_phl, mips_preceq_w_phr)
(mips_precequ_ph_qbl, mips_precequ_ph_qbr, mips_precequ_ph_qbla)
(mips_precequ_ph_qbra, mips_preceu_ph_qbl, mips_preceu_ph_qbr)
(mips_preceu_ph_qbla, mips_preceu_ph_qbra, mips_shll_DSPV:dspfmt2)
(mips_shll_s_DSPQ:dspfmt2, mips_shll_s_DSPQ:dspfmt2, mips_shrl_qb)
(mips_shra_ph, mips_shra_r_DSPQ:dspfmt2, mips_bitrev, mips_insv)
(mips_repl_qb, mips_repl_ph)
(mips_cmpDSPV:dspfmt1_1_eq_DSPV:dspfmt2)
(mips_cmpDSPV:dspfmt1_1_lt_DSPV:dspfmt2)
(mips_cmpDSPV:dspfmt1_1_le_DSPV:dspfmt2, mips_cmpgu_eq_qb)
(mips_cmpgu_lt_qb, mips_cmpgu_le_qb, mips_pick_DSPV:dspfmt2)
(mips_packrl_ph, mips_wrdsp, mips_rddsp): Change type to dspalu.
(mips_dpau_h_qbl, mips_dpau_h_qbr, mips_dpsu_h_qbl, mips_dpsu_h_qbr)
(mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph)
(mips_maq_s_w_phl, mips_maq_s_w_phr, mips_maq_sa_w_phr): Set type to
dspmac.
(mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_sa_w_phl): Set type to
dspmacsat.
(mips_extr_w, mips_extr_r_w, mips_extr_rs_w, mips_extp, mips_extpdp):
Set type to accext.
(mips_shilo, mips_mthlip): Set type to accmod.
* config/mips/mips-dspr2.md (mips_absq_s_qb, mips_addu_s_ph)
(mips_adduh_r_qb): Set type to dspalusat.
(mips_addu_ph, mips_adduh_qb, mips_append, mips_balign)
(mips_cmpgdu_eq_qb, mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb)
(mips_precr_qb_ph, mips_precr_sra_ph_w, mips_precr_sra_r_ph_w)
(mips_prepend, mips_shra_qb, mips_shra_r_qb, mips_shrl_ph)
(mips_subu_ph, mips_subuh_qb, mips_subuh_r_qb, mips_addqh_ph)
(mips_addqh_r_ph, mips_addqh_w, mips_addqh_r_w, mips_subqh_ph)
(mips_subqh_r_ph, mips_subqh_w, mips_subqh_r_w): Set type to dspalu.
(mips_dpa_w_ph, mips_dps_w_ph, mips_mulsa_w_ph, mips_dpax_w_ph)
(mips_dpsx_w_ph, mips_dpaqx_s_w_ph, mips_dpsqx_s_w_ph): Set type to
dspmac.  Set accum_in attribute.
(mips_subu_s_ph): Set type to dspalusat. 
(mips_dpaqx_sa_w_ph, mips_dpsqx_sa_w_ph): Set type to dspmacsat.
Set accum_in attribute.
* config/mips/mips-protos.h (mips_dspalu_bypass_p): Add prototype.
* config/mips/mips.c (dspalu_bypass_table): New.
(mips_dspalu_bypass_p): New.
* config/mips/24k.md (r24k_dsp_alu, r24k_dsp_mac, r24k_dsp_mac_sat)
(r24k_dsp_acc_ext, r24k_dsp_acc_mod): New insn reservations.
(r24k_int_mult, r24k_int_mthilo, r24k_dsp_mac, r24k_dsp_mac_sat)
(r24k_dsp_acc_ext, r24k_dsp_acc_mod, r24k_dsp_alu): New bypasses.
* config/mips/74k.md (r74k_dsp_alu, r74k_dsp_alu_sat, r74k_dsp_mac)
(r74k_dsp_mac_sat, r74k_dsp_acc_ext,

Re: [PATCH, MIPS] DSP ALU scheduling

2012-08-04 Thread Richard Sandiford 
Sandra Loosemore san...@codesourcery.com writes:
 This is another patch that has been present in our local source base for some
 years now.  It originally came from MIPS; I've verified that we have legal 
 permission to contribute it to the FSF.

 The 74k.md parts of this patch depend on the not-yet-reviewed 74k madd 
 scheduler 
 tweaks patch I posted the other day:

 http://gcc.gnu.org/ml/gcc-patches/2012-08/msg00062.html

 Assuming that one gets approved, is this patch OK for mainline?

OK with:

 +/* DSP ALU can bypass data with no delays for the following pairs. */
 +enum insn_code dspalu_bypass_table[][2] =
 +{
 +  {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
 +  {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
 +  {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
 +  {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
 +  {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
 +  {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
 +  {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
 +  {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
 +};
 +
 +int
 +mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
 +{
 +  int i;
 +  int num_bypass = (sizeof (dspalu_bypass_table)
 + / (2 * sizeof (enum insn_code)));

this changed to ARRAY_SIZE (dspalu_bypass_table);

Richard

[PATCH, MIPS] DSP ALU scheduling

2012-08-02 Thread Sandra Loosemore 
This is another patch that has been present in our local source base for some
years now.  It originally came from MIPS; I've verified that we have legal 
permission to contribute it to the FSF.

The 74k.md parts of this patch depend on the not-yet-reviewed 74k madd 
scheduler 
tweaks patch I posted the other day:

http://gcc.gnu.org/ml/gcc-patches/2012-08/msg00062.html

Assuming that one gets approved, is this patch OK for mainline?

-Sandra


2012-08-02  Sandra Loosemore  san...@codesourcery.com
Maxim Kuvyrkov  ma...@codesourcery.com
Julian Brown  jul...@codesourcery.com
MIPS Technologies, Inc.

gcc/
* config/mips/mips.md (dspmac, dspmacsat, accext, accmod, dspalu)
(dspalusat): Add insn types.
* config/mips/mips-dsp.md (addDSPV:mode3)
(mips_addDSP:dspfmt1_s_DSP:dspfmt2)
(subDSPV:mode3, mips_subDSP:dspfmt1_s_DSP:dspfmt2, mips_addsc)
(mips_addwc, mips_modsub, mips_raddu_w_qb, mips_absq_s_DSPQ:dspfmt2)
(mips_precrq_qb_ph, mips_precrq_ph_w, mips_precrq_rs_ph_w)
(mips_precrqu_s_qb_ph, mips_preceq_w_phl, mips_preceq_w_phr)
(mips_precequ_ph_qbl, mips_precequ_ph_qbr, mips_precequ_ph_qbla)
(mips_precequ_ph_qbra, mips_preceu_ph_qbl, mips_preceu_ph_qbr)
(mips_preceu_ph_qbla, mips_preceu_ph_qbra, mips_shll_DSPV:dspfmt2)
(mips_shll_s_DSPQ:dspfmt2, mips_shll_s_DSPQ:dspfmt2, mips_shrl_qb)
(mips_shra_ph, mips_shra_r_DSPQ:dspfmt2, mips_bitrev, mips_insv)
(mips_repl_qb, mips_repl_ph, mips_cmpDSPV:dspfmt1_1_eq_DSPV:dspfmt2)
(mips_cmpDSPV:dspfmt1_1_lt_DSPV:dspfmt2)
(mips_cmpDSPV:dspfmt1_1_le_DSPV:dspfmt2, mips_cmpgu_eq_qb)
(mips_cmpgu_lt_qb, mips_cmpgu_le_qb, mips_pick_DSPV:dspfmt2)
(mips_packrl_ph, mips_wrdsp, mips_rddsp): Change type to dspalu.
(mips_dpau_h_qbl, mips_dpau_h_qbr, mips_dpsu_h_qbl, mips_dpsu_h_qbr)
(mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph)
(mips_maq_s_w_phl, mips_maq_s_w_phr, mips_maq_sa_w_phr): Set type to
dspmac.
(mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_sa_w_phl): Set type to
dspmacsat.
(mips_extr_w, mips_extr_r_w, mips_extr_rs_w, mips_extp, mips_extpdp):
Set type to accext.
(mips_shilo, mips_mthlip): Set type to accmod.
* config/mips/mips-dspr2.md (mips_absq_s_qb, mips_addu_s_ph)
(mips_adduh_r_qb): Set type to dspalusat.
(mips_addu_ph, mips_adduh_qb, mips_append, mips_balign)
(mips_cmpgdu_eq_qb, mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb)
(mips_precr_qb_ph, mips_precr_sra_ph_w, mips_precr_sra_r_ph_w)
(mips_prepend, mips_shra_qb, mips_shra_r_qb, mips_shrl_ph)
(mips_subu_ph, mips_subuh_qb, mips_subuh_r_qb, mips_addqh_ph)
(mips_addqh_r_ph, mips_addqh_w, mips_addqh_r_w, mips_subqh_ph)
(mips_subqh_r_ph, mips_subqh_w, mips_subqh_r_w): Set type to dspalu.
(mips_dpa_w_ph, mips_dps_w_ph, mips_mulsa_w_ph, mips_dpax_w_ph)
(mips_dpsx_w_ph, mips_dpaqx_s_w_ph, mips_dpsqx_s_w_ph): Set type to
dspmac.
(mips_subu_s_ph): Set type to dspalusat.
(mips_dpaqx_sa_w_ph, mips_dpsqx_sa_w_ph): Set type to dspmacsat.
* config/mips/mips-protos.h (mips_dspalu_bypass_p): Add prototype.
* config/mips/mips.c (dspalu_bypass_table): New.
(mips_dspalu_bypass_p): New.
* config/mips/24k.md (r24k_dsp_alu, r24k_dsp_mac, r24k_dsp_mac_sat)
(r24k_dsp_acc_ext, r24k_dsp_acc_mod): New insn reservations.
(r24k_int_mult, r24k_int_mthilo, r24k_dsp_mac, r24k_dsp_mac_sat)
(r24k_dsp_acc_ext, r24k_dsp_acc_mod, r24k_dsp_alu): New bypasses.
* config/mips/74k.md (r74k_dsp_alu, r74k_dsp_alu_sat, r74k_dsp_mac)
(r74k_dsp_mac_sat, r74k_dsp_acc_ext, r74k_dsp_acc_mod): New insn
reservations.
(r74k_dsp_mac, r74k_dsp_mac_sat, r74k_int_mult, r74k_int_mul3)
(r74k_dsp_mac, r74k_dsp_mac_sat): New bypasses.
Index: gcc/config/mips/mips.md
===
--- gcc/config/mips/mips.md	(revision 190052)
+++ gcc/config/mips/mips.md	(working copy)
@@ -326,6 +326,12 @@
 ;; frsqrt   floating point reciprocal square root
 ;; frsqrt1  floating point reciprocal square root step1
 ;; frsqrt2  floating point reciprocal square root step2
+;; dspmac   DSP MAC instructions not saturating the accumulator
+;; dspmacsatDSP MAC instructions that saturate the accumulator
+;; accext   DSP accumulator extract instructions
+;; accmod   DSP accumulator modify instructions
+;; dspalu   DSP ALU instructions not saturating the result
+;; dspalusatDSP ALU instructions that saturate the result
 ;; multi	multiword sequence (or user asm statements)
 ;; atomic	atomic memory update instruction
 ;; syncloop	memory atomic operation implemented as a sync loop
@@ -336,7 +342,8 @@