subject:"\[PATCH, rs6000\] Add vec

Re: [PATCH, rs6000] Add vec_reve support

2017-06-21 Thread Segher Boessenkool

Hi Carl,

On Tue, Jun 20, 2017 at 06:23:33PM -0700, Carl Love wrote:
>   * config/rs6000/rs6000-builtin.def (VREVE_V2DI, VREVE_V4SI,
>   VREVE_V8HI, VREVE_V16QI, VREVE_V2DF, VREVE_V4SF, VREVE): New

"New." or "New builtin.".

>   * config/rs6000/altivec.md (UNSPEC_VREVEV, VEC_A_size,
>   altivec_vrev): New
>   UNSPEC, new mode_attr, new patterns.

This wrapped oddly...  mail client problem?

Please put these things in separate entries.

>   * config/rs6000/altivec.h (vec_reve): New define

Dot.

>   * gcc.target/powerpc/builtins-3-vec_reve-runable.c (test_results,
>   main): Add new runnable test file for the vec_rev built-ins.

You misspelled the filename.

> diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
> index d542315..98ccfd2 100644
> --- a/gcc/config/rs6000/altivec.h
> +++ b/gcc/config/rs6000/altivec.h
> @@ -142,6 +142,7 @@
>  #define vec_madd __builtin_vec_madd
>  #define vec_madds __builtin_vec_madds
>  #define vec_mtvscr __builtin_vec_mtvscr
> +#define vec_reve   __builtin_vec_vreve
>  #define vec_vmaxfp __builtin_vec_vmaxfp
>  #define vec_vmaxsw __builtin_vec_vmaxsw
>  #define vec_vmaxsh __builtin_vec_vmaxsh

All the rest here use just a single space, please do the same.

> UNSPEC_VPACK_UNS_UNS_SAT
> UNSPEC_VPACK_UNS_UNS_MOD
> UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
> +   UNSPEC_VREVEV
> UNSPEC_VSLV4SI
> UNSPEC_VSLO
> UNSPEC_VSR
> @@ -231,6 +232,11 @@
>  ;; Vector negate
>  (define_mode_iterator VNEG [V4SI V2DI])
>  
> +;; Vector reverse elements, uses define_mode_iterator VEC_A
> +;; size in bytes of the vector element
> +(define_mode_attr VEC_A_size [(V2DI "8") (V4SI "4") (V8HI "2")
> +  (V16QI "1") (V2DF "8") (V4SF "4")])

I think you want to use GET_MODE_UNIT_SIZE instead, no need for a new
attribute.

> +  size = ;

size = GET_MODE_UNIT_SIZE (mode);

> +  num_elements = 16 / size;

num_elements = GET_MODE_NUNITS (mode);

> +  for (j = num_elements-1; j >= 0; j--)
> +for (i = 0; i < size; i++)
> +  RTVEC_ELT (v, i + j*size) = gen_rtx_CONST_INT (QImode, k++);

Why does j walk backwards?  Oh, because of k++.  Write that one as
something with i and j as well?


Segher

[PATCH, rs6000] Add vec_reve support

2017-06-20 Thread Carl Love

GCC maintainers:

This patch adds support for the various vec_reve builtins.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
and on powerpc64-unknown-linux-gnu (Power 8 BE) with no regressions.

Is the patch OK for gcc mainline?

  Carl Love

---

gcc/ChangeLog:

2017-06-20  Carl Love  

* config/rs6000/rs6000-c.c: Add support for built-in functions
vector bool char vec_reve (vector bool char);
vector signed char vec_reve (vector signed char);
vector unsigned char vec_reve (vector unsigned char);
vector bool int vec_reve (vector bool int);
vector signed int vec_reve (vector signed int);
vector unsigned int vec_reve (vector unsigned int);
vector bool long long vec_reve (vector bool long long);
vector signed long long vec_reve (vector signed long long);
vector unsigned long long vec_reve (vector unsigned long long);
vector bool short vec_reve (vector bool short);
vector signed short vec_reve (vector signed short);
vector double vec_reve (vector double);
vector float vec_reve (vector float);
* config/rs6000/rs6000-builtin.def (VREVE_V2DI, VREVE_V4SI,
VREVE_V8HI, VREVE_V16QI, VREVE_V2DF, VREVE_V4SF, VREVE): New
* config/rs6000/altivec.md (UNSPEC_VREVEV, VEC_A_size,
altivec_vrev): New
UNSPEC, new mode_attr, new patterns.
* config/rs6000/altivec.h (vec_reve): New define
* doc/extend.texi (vec_rev): Update the built-in documentation file
for the new built-in functions.

gcc/testsuite/ChangeLog:

2017-06-20  Carl Love  

* gcc.target/powerpc/builtins-3-vec_reve-runable.c (test_results,
main): Add new runnable test file for the vec_rev built-ins.
---
 gcc/config/rs6000/altivec.h|   1 +
 gcc/config/rs6000/altivec.md   |  31 +++
 gcc/config/rs6000/rs6000-builtin.def   |   9 +
 gcc/config/rs6000/rs6000-c.c   |  29 +++
 gcc/doc/extend.texi|  13 ++
 .../powerpc/builtins-3-vec_reve-runnable.c | 251 +
 6 files changed, 334 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index d542315..98ccfd2 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -142,6 +142,7 @@
 #define vec_madd __builtin_vec_madd
 #define vec_madds __builtin_vec_madds
 #define vec_mtvscr __builtin_vec_mtvscr
+#define vec_reve   __builtin_vec_vreve
 #define vec_vmaxfp __builtin_vec_vmaxfp
 #define vec_vmaxsw __builtin_vec_vmaxsw
 #define vec_vmaxsh __builtin_vec_vmaxsh
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 25b2768..800d70c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -46,6 +46,7 @@
UNSPEC_VPACK_UNS_UNS_SAT
UNSPEC_VPACK_UNS_UNS_MOD
UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
+   UNSPEC_VREVEV
UNSPEC_VSLV4SI
UNSPEC_VSLO
UNSPEC_VSR
@@ -231,6 +232,11 @@
 ;; Vector negate
 (define_mode_iterator VNEG [V4SI V2DI])
 
+;; Vector reverse elements, uses define_mode_iterator VEC_A
+;; size in bytes of the vector element
+(define_mode_attr VEC_A_size [(V2DI "8") (V4SI "4") (V8HI "2")
+  (V16QI "1") (V2DF "8") (V4SF "4")])
+
 ;; Vector move instructions.
 (define_insn "*altivec_mov"
   [(set (match_operand:VM2 0 "nonimmediate_operand" 
"=Z,v,v,?Y,?*r,?*r,v,v,?*r")
@@ -3727,6 +3733,31 @@
   DONE;
 }")
 
+;; Vector reverse elements
+(define_expand "altivec_vreve2"
+  [(set (match_operand:VEC_A 0 "register_operand" "=v")
+   (unspec:VEC_A [(match_operand:VEC_A 1 "register_operand" "v")]
+ UNSPEC_VREVEV))]
+  "TARGET_ALTIVEC"
+{
+  int i, j, k, size, num_elements;
+  rtvec v = rtvec_alloc (16);
+  rtx mask = gen_reg_rtx (V16QImode);
+
+  size = ;
+  num_elements = 16 / size;
+  k = 0;
+
+  for (j = num_elements-1; j >= 0; j--)
+for (i = 0; i < size; i++)
+  RTVEC_ELT (v, i + j*size) = gen_rtx_CONST_INT (QImode, k++);
+
+  emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
+  emit_insn (gen_altivec_vperm_ (operands[0], operands[1],
+operands[1], mask));
+  DONE;
+})
+
 ;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
 ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
 (define_insn "altivec_lvlx"
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 4682628..20974b4 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1130,6 +1130,13 @@ BU_ALTIVEC_1 (VUPKLSB, "vupklsb",CONST,  
altivec_vupklsb)
 BU_ALTIVEC_1 (VUPKLPX,   "vupklpx",CONST,  altivec_vupklpx)
 BU_ALTIVEC_1

Re: [PATCH, rs6000] Add vec_reve support

[PATCH, rs6000] Add vec_reve support

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