Re: [PATCH/RFC 15 / 14+2][RS6000] Remove vec_shl and (hopefully) fix vec_shr

[David Edelsohn]

On Thu, Sep 18, 2014 at 8:57 AM, Alan Lawrence alan.lawre...@arm.com wrote:
 Patch 12 of 14 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01475.html)
 will break bigendian targets implementing vec_shr. This is a PowerPC
 parallel of patch 13 of 14
 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01477.html) for AArch64. I've
 checked I can build a stage 1 compiler for powerpc-none-eabi and that the
 assembly output looks plausible but no further than that.

 In fact I find BYTES_BIG_ENDIAN is defined to true on powerpcle-none-eabi as
 well as powerpc-none-eabi (and also on ppc64-none-elf, but to false on
 ppc64le-none-elf), so I'm not quite sure how your backend works in this
 regard - nonetheless I hope this is a helpful starting point even if not
 definitive.

 gcc/ChangeLog:

 * config/rs6000/vector.md (vec_shl_mode): Remove.
 (vec_shr_mode): Reverse shift if BYTES_BIG_ENDIAN.

This patch is okay if no regressions on a PowerLinux system (either
you or Segher can test on the GCC Compile Farm).

Thanks, David

[PATCH/RFC 15 / 14+2][RS6000] Remove vec_shl and (hopefully) fix vec_shr

[Alan Lawrence]

Patch 12 of 14 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01475.html) will 
break bigendian targets implementing vec_shr. This is a PowerPC parallel of 
patch 13 of 14 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01477.html) for 
AArch64. I've checked I can build a stage 1 compiler for powerpc-none-eabi and 
that the assembly output looks plausible but no further than that.


In fact I find BYTES_BIG_ENDIAN is defined to true on powerpcle-none-eabi as 
well as powerpc-none-eabi (and also on ppc64-none-elf, but to false on 
ppc64le-none-elf), so I'm not quite sure how your backend works in this regard - 
nonetheless I hope this is a helpful starting point even if not definitive.


gcc/ChangeLog:

* config/rs6000/vector.md (vec_shl_mode): Remove.
(vec_shr_mode): Reverse shift if BYTES_BIG_ENDIAN.
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index edbb83161d142b1a562735635fe90ef65b09fbbf..8bc010eb26526e2997d02ea7aef655e60eca8707 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -972,53 +972,11 @@
  VECTOR_MEM_VSX_P (MODEmode)  TARGET_ALLOW_MOVMISALIGN
  )
 
-
-;; Vector shift left in bits.  Currently supported ony for shift
-;; amounts that can be expressed as byte shifts (divisible by 8).
-;; General shift amounts can be supported using vslo + vsl. We're
-;; not expecting to see these yet (the vectorizer currently
-;; generates only shifts divisible by byte_size).
-(define_expand vec_shl_mode
-  [(match_operand:VEC_L 0 vlogical_operand )
-   (match_operand:VEC_L 1 vlogical_operand )
-   (match_operand:QI 2 reg_or_short_operand )]
-  TARGET_ALTIVEC
-  
-{
-  rtx bitshift = operands[2];
-  rtx shift;
-  rtx insn;
-  HOST_WIDE_INT bitshift_val;
-  HOST_WIDE_INT byteshift_val;
-
-  if (! CONSTANT_P (bitshift))
-FAIL;
-  bitshift_val = INTVAL (bitshift);
-  if (bitshift_val  0x7)
-FAIL;
-  byteshift_val = bitshift_val  3;
-  if (TARGET_VSX  (byteshift_val  0x3) == 0)
-{
-  shift = gen_rtx_CONST_INT (QImode, byteshift_val  2);
-  insn = gen_vsx_xxsldwi_mode (operands[0], operands[1], operands[1],
- shift);
-}
-  else
-{
-  shift = gen_rtx_CONST_INT (QImode, byteshift_val);
-  insn = gen_altivec_vsldoi_mode (operands[0], operands[1], operands[1],
-	shift);
-}
-
-  emit_insn (insn);
-  DONE;
-})
-
 ;; Vector shift right in bits. Currently supported ony for shift
 ;; amounts that can be expressed as byte shifts (divisible by 8).
 ;; General shift amounts can be supported using vsro + vsr. We're
 ;; not expecting to see these yet (the vectorizer currently
-;; generates only shifts divisible by byte_size).
+;; generates only shifts by a whole number of vector elements).
 (define_expand vec_shr_mode
   [(match_operand:VEC_L 0 vlogical_operand )
(match_operand:VEC_L 1 vlogical_operand )
@@ -1037,7 +995,9 @@
   bitshift_val = INTVAL (bitshift);
   if (bitshift_val  0x7)
 FAIL;
-  byteshift_val = 16 - (bitshift_val  3);
+  byteshift_val = (bitshift_val  3);
+  if (!BYTES_BIG_ENDIAN)
+byteshift_val = 16 - byteshift_val;
   if (TARGET_VSX  (byteshift_val  0x3) == 0)
 {
   shift = gen_rtx_CONST_INT (QImode, byteshift_val  2);