Hi all,
This patch adds the rtx costs table for Cortex-A57 and sets its issue rate
properly in the arm backend.
Tested on arm-none-eabi on a model.
Ok for trunk?
Thanks,
Kyrill
2014-01-30 Kyrylo Tkachov
* config/arm/aarch-cost-tables.h (cortexa57_extra_costs): New table.
Remove extra newline at end of file.
* config/arm/arm.c (arm_cortex_a57_tune): New tuning struct.
(arm_issue_rate): Handle cortexa57.
* config/arm/arm-cores.def (cortex-a57): Use cortex_a57 tuning.
(cortex-a57.cortex-a53): Likewise.commit cb854a87cdee667d2042228600a221cffbef70ab
Author: Kyrylo Tkachov
Date: Mon Jan 20 09:55:31 2014 +
[ARM] a57 costs
diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h
index 58addaf..c30ea2f 100644
--- a/gcc/config/arm/aarch-cost-tables.h
+++ b/gcc/config/arm/aarch-cost-tables.h
@@ -222,6 +222,104 @@ const struct cpu_cost_table cortexa53_extra_costs =
}
};
+const struct cpu_cost_table cortexa57_extra_costs =
+{
+ /* ALU */
+ {
+0, /* arith. */
+0, /* logical. */
+0, /* shift. */
+COSTS_N_INSNS (1), /* shift_reg. */
+COSTS_N_INSNS (1), /* arith_shift. */
+COSTS_N_INSNS (1), /* arith_shift_reg. */
+COSTS_N_INSNS (1), /* log_shift. */
+COSTS_N_INSNS (1), /* log_shift_reg. */
+0, /* extend. */
+COSTS_N_INSNS (1), /* extend_arith. */
+COSTS_N_INSNS (1), /* bfi. */
+0, /* bfx. */
+0, /* clz. */
+0, /* non_exec. */
+true /* non_exec_costs_exec. */
+ },
+ {
+/* MULT SImode */
+{
+ COSTS_N_INSNS (2), /* simple. */
+ COSTS_N_INSNS (3), /* flag_setting. */
+ COSTS_N_INSNS (2), /* extend. */
+ COSTS_N_INSNS (2), /* add. */
+ COSTS_N_INSNS (2), /* extend_add. */
+ COSTS_N_INSNS (18) /* idiv. */
+},
+/* MULT DImode */
+{
+ COSTS_N_INSNS (4), /* simple. */
+ 0, /* flag_setting (N/A). */
+ COSTS_N_INSNS (2), /* extend. */
+ COSTS_N_INSNS (4), /* add. */
+ COSTS_N_INSNS (2), /* extend_add. */
+ COSTS_N_INSNS (34) /* idiv. */
+}
+ },
+ /* LD/ST */
+ {
+COSTS_N_INSNS (3), /* load. */
+COSTS_N_INSNS (3), /* load_sign_extend. */
+COSTS_N_INSNS (3), /* ldrd. */
+COSTS_N_INSNS (2), /* ldm_1st. */
+1, /* ldm_regs_per_insn_1st. */
+2, /* ldm_regs_per_insn_subsequent. */
+COSTS_N_INSNS (4), /* loadf. */
+COSTS_N_INSNS (4), /* loadd. */
+COSTS_N_INSNS (5), /* load_unaligned. */
+0, /* store. */
+0, /* strd. */
+0, /* stm_1st. */
+1, /* stm_regs_per_insn_1st. */
+2, /* stm_regs_per_insn_subsequent. */
+0, /* storef. */
+0, /* stored. */
+COSTS_N_INSNS (1) /* store_unaligned. */
+ },
+ {
+/* FP SFmode */
+{
+ COSTS_N_INSNS (17), /* div. */
+ COSTS_N_INSNS (5), /* mult. */
+ COSTS_N_INSNS (9), /* mult_addsub. */
+ COSTS_N_INSNS (9), /* fma. */
+ COSTS_N_INSNS (4), /* addsub. */
+ COSTS_N_INSNS (2), /* fpconst. */
+ COSTS_N_INSNS (2), /* neg. */
+ COSTS_N_INSNS (2), /* compare. */
+ COSTS_N_INSNS (4), /* widen. */
+ COSTS_N_INSNS (4), /* narrow. */
+ COSTS_N_INSNS (4), /* toint. */
+ COSTS_N_INSNS (4), /* fromint. */
+ COSTS_N_INSNS (4)/* roundint. */
+},
+/* FP DFmode */
+{
+ COSTS_N_INSNS (31), /* div. */
+ COSTS_N_INSNS (5), /* mult. */
+ COSTS_N_INSNS (9), /* mult_addsub. */
+ COSTS_N_INSNS (9), /* fma. */
+ COSTS_N_INSNS (4), /* addsub. */
+ COSTS_N_INSNS (2), /* fpconst. */
+ COSTS_N_INSNS (2), /* neg. */
+ COSTS_N_INSNS (2), /* compare. */
+ COSTS_N_INSNS (4), /* widen. */
+ COSTS_N_INSNS (4), /* narrow. */
+ COSTS_N_INSNS (4), /* toint. */
+ COSTS_N_INSNS (4), /* fromint. */
+ COSTS_N_INSNS (4)/* roundint. */
+}
+ },
+ /* Vector */
+ {
+COSTS_N_INSNS (1) /* alu. */
+ }
+};
#endif /* GCC_AARCH_COST_TABLES_H */
-
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 1e97273..42f00b4 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -153,7 +153,7 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSCHED |
/* V8 Architecture Processors */
ARM_CORE("cortex-a53", cortexa53, cortexa