Re: [PATCH][AVX512][PR96246] Merge two define_insn: _blendm, _load_mask.
Hello, On 22 июл 12:59, Hongtao Liu via Gcc-patches wrote: > Those two define_insns have same pattern, and > _load_mask would always be matched since it show up > earlier in the md file, and it may lose some opportunity in > pass_reload since _load_mask only have constraint "0C" > for operand2, and "v" constraint in _vblendm would never > be matched. > > 2020-07-21 Hongtao Liu > > gcc/ >PR target/96246 > * config/i386/sse.md (_load_mask, > _load_mask): Extend to generate blendm > instructions. > (_blendm, _blendm): Change > define_insn to define_expand. > > gcc/testsuite/ > * gcc.target/i386/avx512bw-pr96246-1.c: New test. > * gcc.target/i386/avx512bw-pr96246-2.c: New test. > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > * gcc.target/i386/avx512bw-vmovdqu16-1.c: New test. > * gcc.target/i386/avx512bw-vmovdqu8-1.c: New test. > * gcc.target/i386/avx512f-vmovapd-1.c: New test. > * gcc.target/i386/avx512f-vmovaps-1.c: New test. > * gcc.target/i386/avx512f-vmovdqa32-1.c: New test. > * gcc.target/i386/avx512f-vmovdqa64-1.c: New test. > * gcc.target/i386/avx512vl-pr92686-movcc-1.c: New test. > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > * gcc.target/i386/avx512vl-vmovapd-1.c: New test. > * gcc.target/i386/avx512vl-vmovaps-1.c: New test. > * gcc.target/i386/avx512vl-vmovdqa32-1.c: New test. > * gcc.target/i386/avx512vl-vmovdqa64-1.c: New test. Your patch is OK for trunk. -- K
Re: [PATCH][AVX512][PR96246] Merge two define_insn: _blendm, _load_mask.
Ping^3 On Tue, Aug 4, 2020 at 4:21 PM Hongtao Liu wrote: > > ping ^2 > > On Mon, Jul 27, 2020 at 5:31 PM Hongtao Liu wrote: > > > > ping > > > > On Wed, Jul 22, 2020 at 12:59 PM Hongtao Liu wrote: > > > > > > Those two define_insns have same pattern, and > > > _load_mask would always be matched since it show up > > > earlier in the md file, and it may lose some opportunity in > > > pass_reload since _load_mask only have constraint "0C" > > > for operand2, and "v" constraint in _vblendm would never > > > be matched. > > > > > > 2020-07-21 Hongtao Liu > > > > > > gcc/ > > >PR target/96246 > > > * config/i386/sse.md (_load_mask, > > > _load_mask): Extend to generate blendm > > > instructions. > > > (_blendm, _blendm): Change > > > define_insn to define_expand. > > > > > > gcc/testsuite/ > > > * gcc.target/i386/avx512bw-pr96246-1.c: New test. > > > * gcc.target/i386/avx512bw-pr96246-2.c: New test. > > > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > > > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > > > * gcc.target/i386/avx512bw-vmovdqu16-1.c: New test. > > > * gcc.target/i386/avx512bw-vmovdqu8-1.c: New test. > > > * gcc.target/i386/avx512f-vmovapd-1.c: New test. > > > * gcc.target/i386/avx512f-vmovaps-1.c: New test. > > > * gcc.target/i386/avx512f-vmovdqa32-1.c: New test. > > > * gcc.target/i386/avx512f-vmovdqa64-1.c: New test. > > > * gcc.target/i386/avx512vl-pr92686-movcc-1.c: New test. > > > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > > > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > > > * gcc.target/i386/avx512vl-vmovapd-1.c: New test. > > > * gcc.target/i386/avx512vl-vmovaps-1.c: New test. > > > * gcc.target/i386/avx512vl-vmovdqa32-1.c: New test. > > > * gcc.target/i386/avx512vl-vmovdqa64-1.c: New test. > > > > > > > > > -- > > > BR, > > > Hongtao > > > > > > > > -- > > BR, > > Hongtao > > > > -- > BR, > Hongtao -- BR, Hongtao
Re: [PATCH][AVX512][PR96246] Merge two define_insn: _blendm, _load_mask.
ping ^2 On Mon, Jul 27, 2020 at 5:31 PM Hongtao Liu wrote: > > ping > > On Wed, Jul 22, 2020 at 12:59 PM Hongtao Liu wrote: > > > > Those two define_insns have same pattern, and > > _load_mask would always be matched since it show up > > earlier in the md file, and it may lose some opportunity in > > pass_reload since _load_mask only have constraint "0C" > > for operand2, and "v" constraint in _vblendm would never > > be matched. > > > > 2020-07-21 Hongtao Liu > > > > gcc/ > >PR target/96246 > > * config/i386/sse.md (_load_mask, > > _load_mask): Extend to generate blendm > > instructions. > > (_blendm, _blendm): Change > > define_insn to define_expand. > > > > gcc/testsuite/ > > * gcc.target/i386/avx512bw-pr96246-1.c: New test. > > * gcc.target/i386/avx512bw-pr96246-2.c: New test. > > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > > * gcc.target/i386/avx512bw-vmovdqu16-1.c: New test. > > * gcc.target/i386/avx512bw-vmovdqu8-1.c: New test. > > * gcc.target/i386/avx512f-vmovapd-1.c: New test. > > * gcc.target/i386/avx512f-vmovaps-1.c: New test. > > * gcc.target/i386/avx512f-vmovdqa32-1.c: New test. > > * gcc.target/i386/avx512f-vmovdqa64-1.c: New test. > > * gcc.target/i386/avx512vl-pr92686-movcc-1.c: New test. > > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > > * gcc.target/i386/avx512vl-vmovapd-1.c: New test. > > * gcc.target/i386/avx512vl-vmovaps-1.c: New test. > > * gcc.target/i386/avx512vl-vmovdqa32-1.c: New test. > > * gcc.target/i386/avx512vl-vmovdqa64-1.c: New test. > > > > > > -- > > BR, > > Hongtao > > > > -- > BR, > Hongtao -- BR, Hongtao
Re: [PATCH][AVX512][PR96246] Merge two define_insn: _blendm, _load_mask.
ping On Wed, Jul 22, 2020 at 12:59 PM Hongtao Liu wrote: > > Those two define_insns have same pattern, and > _load_mask would always be matched since it show up > earlier in the md file, and it may lose some opportunity in > pass_reload since _load_mask only have constraint "0C" > for operand2, and "v" constraint in _vblendm would never > be matched. > > 2020-07-21 Hongtao Liu > > gcc/ >PR target/96246 > * config/i386/sse.md (_load_mask, > _load_mask): Extend to generate blendm > instructions. > (_blendm, _blendm): Change > define_insn to define_expand. > > gcc/testsuite/ > * gcc.target/i386/avx512bw-pr96246-1.c: New test. > * gcc.target/i386/avx512bw-pr96246-2.c: New test. > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > * gcc.target/i386/avx512bw-vmovdqu16-1.c: New test. > * gcc.target/i386/avx512bw-vmovdqu8-1.c: New test. > * gcc.target/i386/avx512f-vmovapd-1.c: New test. > * gcc.target/i386/avx512f-vmovaps-1.c: New test. > * gcc.target/i386/avx512f-vmovdqa32-1.c: New test. > * gcc.target/i386/avx512f-vmovdqa64-1.c: New test. > * gcc.target/i386/avx512vl-pr92686-movcc-1.c: New test. > * gcc.target/i386/avx512vl-pr96246-1.c: New test. > * gcc.target/i386/avx512vl-pr96246-2.c: New test. > * gcc.target/i386/avx512vl-vmovapd-1.c: New test. > * gcc.target/i386/avx512vl-vmovaps-1.c: New test. > * gcc.target/i386/avx512vl-vmovdqa32-1.c: New test. > * gcc.target/i386/avx512vl-vmovdqa64-1.c: New test. > > > -- > BR, > Hongtao -- BR, Hongtao
[PATCH][AVX512][PR96246] Merge two define_insn: _blendm, _load_mask.
Those two define_insns have same pattern, and
_load_mask would always be matched since it show up
earlier in the md file, and it may lose some opportunity in
pass_reload since _load_mask only have constraint "0C"
for operand2, and "v" constraint in _vblendm would never
be matched.
2020-07-21 Hongtao Liu
gcc/
PR target/96246
* config/i386/sse.md (_load_mask,
_load_mask): Extend to generate blendm
instructions.
(_blendm, _blendm): Change
define_insn to define_expand.
gcc/testsuite/
* gcc.target/i386/avx512bw-pr96246-1.c: New test.
* gcc.target/i386/avx512bw-pr96246-2.c: New test.
* gcc.target/i386/avx512vl-pr96246-1.c: New test.
* gcc.target/i386/avx512vl-pr96246-2.c: New test.
* gcc.target/i386/avx512bw-vmovdqu16-1.c: New test.
* gcc.target/i386/avx512bw-vmovdqu8-1.c: New test.
* gcc.target/i386/avx512f-vmovapd-1.c: New test.
* gcc.target/i386/avx512f-vmovaps-1.c: New test.
* gcc.target/i386/avx512f-vmovdqa32-1.c: New test.
* gcc.target/i386/avx512f-vmovdqa64-1.c: New test.
* gcc.target/i386/avx512vl-pr92686-movcc-1.c: New test.
* gcc.target/i386/avx512vl-pr96246-1.c: New test.
* gcc.target/i386/avx512vl-pr96246-2.c: New test.
* gcc.target/i386/avx512vl-vmovapd-1.c: New test.
* gcc.target/i386/avx512vl-vmovaps-1.c: New test.
* gcc.target/i386/avx512vl-vmovdqa32-1.c: New test.
* gcc.target/i386/avx512vl-vmovdqa64-1.c: New test.
--
BR,
Hongtao
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d3ad5833e1f..35801a847ef 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1057,11 +1057,15 @@
(define_insn "_load_mask"
[(set (match_operand:V48_AVX512VL 0 "register_operand" "=v,v")
(vec_merge:V48_AVX512VL
- (match_operand:V48_AVX512VL 1 "nonimmediate_operand" "v,m")
- (match_operand:V48_AVX512VL 2 "nonimm_or_0_operand" "0C,0C")
+ (match_operand:V48_AVX512VL 1 "nonimmediate_operand" "vm,vm")
+ (match_operand:V48_AVX512VL 2 "nonimm_or_0_operand" "0C,v")
(match_operand: 3 "register_operand" "Yk,Yk")))]
"TARGET_AVX512F"
{
+ if (REG_P (operands[2])
+ && REGNO (operands[2]) != REGNO (operands[0]))
+return "vblendm\t{%1, %2, %0%{%3%}|%0%{%3%}, %2, %1}";
+
if (FLOAT_MODE_P (GET_MODE_INNER (mode)))
{
if (misaligned_operand (operands[1], mode))
@@ -1079,20 +1083,20 @@
}
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
- (set_attr "memory" "none,load")
(set_attr "mode" "")])
(define_insn "_load_mask"
[(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v,v")
(vec_merge:VI12_AVX512VL
- (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "v,m")
- (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C,0C")
+ (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm,vm")
+ (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C,v")
(match_operand: 3 "register_operand" "Yk,Yk")))]
"TARGET_AVX512BW"
- "vmovdqu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
+ "@
+vmovdqu\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}
+vpblendm\t{%1, %2, %0%{%3%}|%0%{%3%}, %2, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
- (set_attr "memory" "none,load")
(set_attr "mode" "")])
(define_insn "avx512f_mov_mask"
@@ -1156,29 +1160,21 @@
(set_attr "memory" "store")
(set_attr "mode" "")])
-(define_insn "_blendm"
+(define_expand "_blendm"
[(set (match_operand:V48_AVX512VL 0 "register_operand" "=v")
(vec_merge:V48_AVX512VL
(match_operand:V48_AVX512VL 2 "nonimmediate_operand" "vm")
(match_operand:V48_AVX512VL 1 "register_operand" "v")
(match_operand: 3 "register_operand" "Yk")))]
- "TARGET_AVX512F"
- "vblendm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "evex")
- (set_attr "mode" "")])
+ "TARGET_AVX512F")
-(define_insn "_blendm"
+(define_expand "_blendm"
[(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI12_AVX512VL
(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
(match_operand:VI12_AVX512VL 1 "register_operand" "v")
(match_operand: 3 "register_operand" "Yk")))]
- "TARGET_AVX512BW"
- "vpblendm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "prefix" "evex")
- (set_attr "mode" "")])
+ "TARGET_AVX512BW")
(define_insn "_store_mask"
[(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m")
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr96246-1.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr96246-1.c
new file mode 100644
index 000..2bfcc840a91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr96246-1.c
@@ -0,0 +1,30 @@
+/* PR target/96246 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512bw" } */
+/* { dg-final { scan-assembler-times "vpblendm\[bwdq\]\[\t ]" 4 } } */
+/* { dg-final {
