Re: [PATCH][x86] march aliases

2013-12-26 Thread Ryan Hill 
On Mon, 23 Dec 2013 05:10:06 -0800
H.J. Lu hjl.to...@gmail.com wrote:

 This is the patch I checked in.  I will submit separate patches for
 other parts.

Please be sure to update changes.html.


-- 
Ryan Hillpsn: dirtyepic_sk
   gcc-porting/toolchain/wxwidgets @ gentoo.org

47C3 6D62 4864 0E49 8E9E  7F92 ED38 BD49 957A 8463


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Re: [PATCH][x86] march aliases

2013-12-23 Thread H.J. Lu 
On Mon, Dec 23, 2013 at 5:10 AM, H.J. Lu hjl.to...@gmail.com wrote:
 On Sun, Dec 22, 2013 at 11:11:12PM +0100, Uros Bizjak wrote:
 On Sun, Dec 22, 2013 at 8:28 PM, H.J. Lu hjl.to...@gmail.com wrote:

  Perhaps we should add sandybridge, ivybridge and haswell 
  aliases for
  corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare 
  to remember
  which one has the i7 in and which doesn't even for me.

 Yes please, I think this is a good idea.

 I've added aliases for haswell, sandybridge, ivybridge, bonnell,
 nehalem and silvermont.

 Old names, like corei7, core-avx-i, atom, .. don't have precise
 description for the processor.  I think gcc driver should keep
 accepting them.  But they should be marked as undocumented
 or deprecated.  They should be removed from documentation.
   
How about we leave these as -march=... to refer to the architecture,
and reintroduce -mcpu= to refer to the exact cpu? Internally, the
-mcpu would use some architecture specific base PTA_ attributes (as
Jakub suggested) and would add some fine-tuning PTA_ attributes, based
on -mcpu selection. This way, -march stays as is, and can still be
used for some generally distributed binaries.
  
   -mcpu is problematic, because it means various things among different
   targets, and even on i?86/x86_64 it used to mean something already in 
   the
   past.  Sometimes -mcpu= is what -march= is now on i?86/x86_64, sometimes
   what -mtune= is.  I'd say we don't need to deprecate anything, just add 
   new
   aliases for the sometimes harder to remember names.  But everything just
   IMHO.
  
   Jakub
 
  There are many problems with the current -march=xxx/-mtune=xxx for
  Intel processors, which aren't faults of GCC:
 
  1. Atom processors can be Bonnell or Silvermont processors.  -mtune=atom
  may not optimize for the Atom CPU being targeted.
  2. Core I7 processors can be Nehalem, Westmere, Sandy Bridge, Ivy Bridge,
  Haswell or Broadwell. It is hard to tell which -mtune= to use for saying
  Core i7-3820QM.
  3. There are Core i3/i5, Xeon, Celeron, Pentium processors which aren't
  called Core I7.  They may be Nehalem, Westmere, Sandy Bridge, Ivy Bridge,
  Haswell or even Silvermont.
 
  We should move away from corei7, corei7-avx, core-avx-i, core-avx2, atom.
  Instead, we should use the actual processor names.  We must accept those
  old names.  But we should remove them from GCC manual to avoid any
  confusions.  This patch adds -march=/mtune={nehalem,westmere,sandybridge,
  ivybridge,haswell,broadwell,bonnell,silvermont}.  It also adds
  --with-arch=/--with-cpu= support as well as adds ivybridge, haswell,
  bonnell, silvermont to multi-arch function versioning.
 
  Any comments?
 
  This is the updated patch to add PTA_XXX as well as fix
 
  http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59580
 
  to properly check --with-arch=/--with-cpu= options. Now we only need
  to add a new processor to x86_64_archs, which will enable its
  --with-arch=/--with-cpu= support.
 
 
  H.J.
  ---
  gcc/
 
  2013-12-22   H.J. Lu  hongjiu...@intel.com
   Tocar Ilya  ilya.to...@intel.com
 
  * config.gcc (x86_archs): New variable.
  (x86_64_archs): Likewise.
  (x86_cpus): Likewise.
  Use $x86_archs, $x86_64_archs and $x86_cpus to check valid
  --with-arch/--with-cpu= options.
  Support --with-arch=/--with-cpu={nehalem,westmere,
  sandybridge,ivybridge,haswell,broadwell,bonnell,silvermont}.
 
  * config/i386/core2.md: Replace corei7 with nehalem.
 
  * config/i386/driver-i386.c (host_detect_local_cpu): Use nehalem,
  westmere, sandybridge, ivybridge, haswell, bonnell, silvermont
  for cpu names.
 
  * config/i386/i386-c.c (ix86_target_macros_internal): Replace
  PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM,
  PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE,
  PROCESSOR_BONNELL, PROCESSOR_SILVERMONT.  Define
  __nehalem/__nehalem__, __sandybridge/__sandybridge__,
  __haswell/__haswell__, __tune_nehalem__, __tune_sandybridge__,
  __tune_haswell__, __bonnell/__bonnell__,
  __silvermont/__silvermont__, __tune_bonnell__,
  __tune_silvermont__.
 
  * config/i386/i386.c (m_COREI7): Renamed to ...
  (m_NEHALEM): This.
  (m_COREI7_AVX): Renamed to ...
  (m_SANDYBRIDGE): This.
  (m_ATOM): Renamed to ...
  (m_BONNELL): This.
  (m_SLM): Renamed to ...
  (m_SILVERMONT): This.
  (m_CORE_ALL): Updated.
  (cpu_names): Add nehalem, westmere, sandybridge,
  ivybridge, haswell, broadwell, bonnell, silvermont.
  (PTA_CORE2): New.
  (PTA_NEHALEM): Likewise.
  (PTA_WESTMERE): Likewise.
  (PTA_SANDYBRIDGE): Likewise.
  (PTA_IVYBRIDGE): Likewise.
  (PTA_HASWELL):

Re: [PATCH][x86] march aliases

2013-12-22 Thread Uros Bizjak 
On Fri, Dec 20, 2013 at 5:47 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
  Perhaps we should add sandybridge, ivybridge and haswell aliases for
  corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
  which one has the i7 in and which doesn't even for me.

 Yes please, I think this is a good idea.

 I've added aliases for haswell, sandybridge, ivybridge, bonnell,
 nehalem and silvermont.

BTW, I wonder if we add a bunch of new names to the table it isn't a right
time to also introduce macros for some common PTA_* flag combinations,

 IMO full list of PTA_* helps quickly identify what is supported.

 2013-12-20  Tocar Ilya  ilya.to...@intel.com

 * config/i386/i386.c (ix86_option_override_internal): Add
 haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
 * doc/invoke.texi: Document them.

 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
 index dcc1893..365ddbf 100644
 --- a/gcc/doc/invoke.texi
 +++ b/gcc/doc/invoke.texi
 @@ -14645,19 +14645,41 @@ SSE2 and SSE3 instruction set support.
  Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
  instruction set support.

 +@item nehalem
 +Same as corei7.
 +Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 +SSE4.1, SSE4.2 and POPCNT instruction set support.
 +
  @item corei7
  Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
  SSE4.1, SSE4.2 and POPCNT instruction set support.

If these are the same, will it work to just add new @item under
existing one, like:

 @item corei7
+@item nehalem
 Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2 and POPCNT instruction set support.

Uros.

Re: [PATCH][x86] march aliases

2013-12-22 Thread Uros Bizjak 
On Fri, Dec 20, 2013 at 5:55 PM, H.J. Lu hjl.to...@gmail.com wrote:
 On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar tocarip.in...@gmail.com wrote:
  Perhaps we should add sandybridge, ivybridge and haswell aliases for
  corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
  which one has the i7 in and which doesn't even for me.

 Yes please, I think this is a good idea.

 I've added aliases for haswell, sandybridge, ivybridge, bonnell,
 nehalem and silvermont.

 Old names, like corei7, core-avx-i, atom, .. don't have precise
 description for the processor.  I think gcc driver should keep
 accepting them.  But they should be marked as undocumented
 or deprecated.  They should be removed from documentation.

How about we leave these as -march=... to refer to the architecture,
and reintroduce -mcpu= to refer to the exact cpu? Internally, the
-mcpu would use some architecture specific base PTA_ attributes (as
Jakub suggested) and would add some fine-tuning PTA_ attributes, based
on -mcpu selection. This way, -march stays as is, and can still be
used for some generally distributed binaries.

Uros.

Re: [PATCH][x86] march aliases

2013-12-22 Thread Jakub Jelinek 
On Sun, Dec 22, 2013 at 12:19:56PM +0100, Uros Bizjak wrote:
 On Fri, Dec 20, 2013 at 5:55 PM, H.J. Lu hjl.to...@gmail.com wrote:
  On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar tocarip.in...@gmail.com wrote:
   Perhaps we should add sandybridge, ivybridge and haswell aliases for
   corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to 
   remember
   which one has the i7 in and which doesn't even for me.
 
  Yes please, I think this is a good idea.
 
  I've added aliases for haswell, sandybridge, ivybridge, bonnell,
  nehalem and silvermont.
 
  Old names, like corei7, core-avx-i, atom, .. don't have precise
  description for the processor.  I think gcc driver should keep
  accepting them.  But they should be marked as undocumented
  or deprecated.  They should be removed from documentation.
 
 How about we leave these as -march=... to refer to the architecture,
 and reintroduce -mcpu= to refer to the exact cpu? Internally, the
 -mcpu would use some architecture specific base PTA_ attributes (as
 Jakub suggested) and would add some fine-tuning PTA_ attributes, based
 on -mcpu selection. This way, -march stays as is, and can still be
 used for some generally distributed binaries.

-mcpu is problematic, because it means various things among different
targets, and even on i?86/x86_64 it used to mean something already in the
past.  Sometimes -mcpu= is what -march= is now on i?86/x86_64, sometimes
what -mtune= is.  I'd say we don't need to deprecate anything, just add new
aliases for the sometimes harder to remember names.  But everything just
IMHO.

Jakub

[PATCH][x86] march aliases

2013-12-20 Thread Ilya Tocar 
  Perhaps we should add sandybridge, ivybridge and haswell aliases for
  corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
  which one has the i7 in and which doesn't even for me.
 
 Yes please, I think this is a good idea.

I've added aliases for haswell, sandybridge, ivybridge, bonnell,
nehalem and silvermont.

BTW, I wonder if we add a bunch of new names to the table it isn't a right
time to also introduce macros for some common PTA_* flag combinations,

IMO full list of PTA_* helps quickly identify what is supported.

2013-12-20  Tocar Ilya  ilya.to...@intel.com 

* config/i386/i386.c (ix86_option_override_internal): Add
haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
* doc/invoke.texi: Document them.
---
 gcc/config/i386/i386.c | 27 +++
 gcc/doc/invoke.texi| 32 
 2 files changed, 59 insertions(+)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1710e8c..fcf2afe 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3111,9 +3111,17 @@ ix86_option_override_internal (bool main_args_p,
   {core2, PROCESSOR_CORE2, CPU_CORE2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
+  {nehalem, PROCESSOR_COREI7, CPU_COREI7,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
+   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
   {corei7, PROCESSOR_COREI7, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
+  {sandybridge, PROCESSOR_COREI7_AVX, CPU_COREI7,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
+   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
+   | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
   {corei7-avx, PROCESSOR_COREI7_AVX, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
@@ -3124,6 +3132,11 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
| PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+  {ivybridge, PROCESSOR_COREI7_AVX, CPU_COREI7,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
+   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
+   | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
   {core-avx2, PROCESSOR_HASWELL, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
@@ -3131,6 +3144,13 @@ ix86_option_override_internal (bool main_args_p,
| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
| PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
| PTA_XSAVEOPT},
+  {haswell, PROCESSOR_HASWELL, CPU_COREI7,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
+   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
+   | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
+   | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
+   | PTA_XSAVEOPT},
   {broadwell, PROCESSOR_HASWELL, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
@@ -3138,9 +3158,16 @@ ix86_option_override_internal (bool main_args_p,
| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
| PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
| PTA_XSAVEOPT | PTA_ADX | PTA_PRFCHW | PTA_RDSEED},
+  {bonnell, PROCESSOR_ATOM, CPU_ATOM,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+   | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
   {atom, PROCESSOR_ATOM, CPU_ATOM,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
+  {silvermont, PROCESSOR_SLM, CPU_SLM,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
+   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
+   | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
   {slm, PROCESSOR_SLM, CPU_SLM,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dcc1893..365ddbf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14645,19 +14645,41 @@ SSE2 and SSE3 instruction set support.
 Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set

Re: [PATCH][x86] march aliases

2013-12-20 Thread H.J. Lu 
On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar tocarip.in...@gmail.com wrote:
  Perhaps we should add sandybridge, ivybridge and haswell aliases for
  corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
  which one has the i7 in and which doesn't even for me.

 Yes please, I think this is a good idea.

 I've added aliases for haswell, sandybridge, ivybridge, bonnell,
 nehalem and silvermont.

BTW, I wonder if we add a bunch of new names to the table it isn't a right
time to also introduce macros for some common PTA_* flag combinations,

 IMO full list of PTA_* helps quickly identify what is supported.

 2013-12-20  Tocar Ilya  ilya.to...@intel.com

 * config/i386/i386.c (ix86_option_override_internal): Add
 haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
 * doc/invoke.texi: Document them.
 ---
  gcc/config/i386/i386.c | 27 +++
  gcc/doc/invoke.texi| 32 
  2 files changed, 59 insertions(+)

 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
 index 1710e8c..fcf2afe 100644
 --- a/gcc/config/i386/i386.c
 +++ b/gcc/config/i386/i386.c
 @@ -3111,9 +3111,17 @@ ix86_option_override_internal (bool main_args_p,
{core2, PROCESSOR_CORE2, CPU_CORE2,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
 +  {nehalem, PROCESSOR_COREI7, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 +   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
{corei7, PROCESSOR_COREI7, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
 +  {sandybridge, PROCESSOR_COREI7_AVX, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 +   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
 +   | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
{corei7-avx, PROCESSOR_COREI7_AVX, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 @@ -3124,6 +3132,11 @@ ix86_option_override_internal (bool main_args_p,
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
 +  {ivybridge, PROCESSOR_COREI7_AVX, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 +   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 +   | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
{core-avx2, PROCESSOR_HASWELL, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 @@ -3131,6 +3144,13 @@ ix86_option_override_internal (bool main_args_p,
 | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 | PTA_XSAVEOPT},
 +  {haswell, PROCESSOR_HASWELL, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 +   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 +   | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 +   | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 +   | PTA_XSAVEOPT},
{broadwell, PROCESSOR_HASWELL, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 @@ -3138,9 +3158,16 @@ ix86_option_override_internal (bool main_args_p,
 | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 | PTA_XSAVEOPT | PTA_ADX | PTA_PRFCHW | PTA_RDSEED},
 +  {bonnell, PROCESSOR_ATOM, CPU_ATOM,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
{atom, PROCESSOR_ATOM, CPU_ATOM,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
 +  {silvermont, PROCESSOR_SLM, CPU_SLM,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 +   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
 +   | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
{slm, PROCESSOR_SLM, CPU_SLM,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
 index dcc1893..365ddbf 100644
 --- a/gcc/doc/invoke.texi
 +++ b/gcc/doc/invoke.texi

Re: [PATCH][x86] march aliases

2013-12-20 Thread H.J. Lu 
On Fri, Dec 20, 2013 at 8:55 AM, H.J. Lu hjl.to...@gmail.com wrote:
 On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar tocarip.in...@gmail.com wrote:
  Perhaps we should add sandybridge, ivybridge and haswell aliases for
  corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
  which one has the i7 in and which doesn't even for me.

 Yes please, I think this is a good idea.

 I've added aliases for haswell, sandybridge, ivybridge, bonnell,
 nehalem and silvermont.

BTW, I wonder if we add a bunch of new names to the table it isn't a right
time to also introduce macros for some common PTA_* flag combinations,

 IMO full list of PTA_* helps quickly identify what is supported.

 2013-12-20  Tocar Ilya  ilya.to...@intel.com

 * config/i386/i386.c (ix86_option_override_internal): Add
 haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
 * doc/invoke.texi: Document them.
 ---
  gcc/config/i386/i386.c | 27 +++
  gcc/doc/invoke.texi| 32 
  2 files changed, 59 insertions(+)

 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
 index 1710e8c..fcf2afe 100644
 --- a/gcc/config/i386/i386.c
 +++ b/gcc/config/i386/i386.c
 @@ -3111,9 +3111,17 @@ ix86_option_override_internal (bool main_args_p,
{core2, PROCESSOR_CORE2, CPU_CORE2,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
 +  {nehalem, PROCESSOR_COREI7, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 +   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
{corei7, PROCESSOR_COREI7, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
 +  {sandybridge, PROCESSOR_COREI7_AVX, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 +   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
 +   | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
{corei7-avx, PROCESSOR_COREI7_AVX, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 @@ -3124,6 +3132,11 @@ ix86_option_override_internal (bool main_args_p,
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
 +  {ivybridge, PROCESSOR_COREI7_AVX, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 +   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 +   | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
{core-avx2, PROCESSOR_HASWELL, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 @@ -3131,6 +3144,13 @@ ix86_option_override_internal (bool main_args_p,
 | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 | PTA_XSAVEOPT},
 +  {haswell, PROCESSOR_HASWELL, CPU_COREI7,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 +   | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 +   | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 +   | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 +   | PTA_XSAVEOPT},
{broadwell, PROCESSOR_HASWELL, CPU_COREI7,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
 @@ -3138,9 +3158,16 @@ ix86_option_override_internal (bool main_args_p,
 | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 | PTA_XSAVEOPT | PTA_ADX | PTA_PRFCHW | PTA_RDSEED},
 +  {bonnell, PROCESSOR_ATOM, CPU_ATOM,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 +   | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
{atom, PROCESSOR_ATOM, CPU_ATOM,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
 +  {silvermont, PROCESSOR_SLM, CPU_SLM,
 +   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 +   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
 +   | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
{slm, PROCESSOR_SLM, CPU_SLM,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
 index