Re: [PATCH] AArch64: Update system register database.
Victor Do Nascimento writes:
> [...]
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index 157a0b9dfa5..45e901cda64 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -297,6 +297,26 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE =
> AARCH64_FL_SM_OFF;
> #define AARCH64_FL_SCXTNUM AARCH64_FL_V8_5A
> #define AARCH64_FL_ID_PFR2 AARCH64_FL_V8_5A
>
> +/* Armv8.9-A extension feature bits defined in Binutils but absent from GCC,
> + aliased to their base architecture. */
> +#define AARCH64_FL_AIE AARCH64_FL_V8_9A
> +#define AARCH64_FL_DEBUGv8p9AARCH64_FL_V8_9A
> +#define AARCH64_FL_FGT2 AARCH64_FL_V8_9A
> +#define AARCH64_FL_ITE AARCH64_FL_V8_9A
For the record, I think this leaves things in a bit of an inconsistent
state. Something like:
#include
unsigned long long f1() {
return __arm_rsr64 ("trcitecr_el1");
}
unsigned long long f2() {
unsigned long long x;
asm volatile ("mrs %0, trcitecr_el1" : "=r" (x));
return x;
}
compiles OK with -march=armv8.9-a, but doesn't assemble. GAS treats ITE
as an independent feature than can be enabled for armv8.8-a, but is not
enabled by default for armv8.9-a. GCC instead treats it as something
that is enabled by default for armv8.9-a but that cannot be used with
armv8.8-a.
Thanks,
Richard
> +#define AARCH64_FL_PFAR AARCH64_FL_V8_9A
> +#define AARCH64_FL_PMUv3_ICNTR AARCH64_FL_V8_9A
> +#define AARCH64_FL_PMUv3_SS AARCH64_FL_V8_9A
> +#define AARCH64_FL_PMUv3p9 AARCH64_FL_V8_9A
> +#define AARCH64_FL_RASv2AARCH64_FL_V8_9A
> +#define AARCH64_FL_S1PIEAARCH64_FL_V8_9A
> +#define AARCH64_FL_S1POEAARCH64_FL_V8_9A
> +#define AARCH64_FL_S2PIEAARCH64_FL_V8_9A
> +#define AARCH64_FL_S2POEAARCH64_FL_V8_9A
> +#define AARCH64_FL_SCTLR2 AARCH64_FL_V8_9A
> +#define AARCH64_FL_SEBEPAARCH64_FL_V8_9A
> +#define AARCH64_FL_SPE_FDS AARCH64_FL_V8_9A
> +#define AARCH64_FL_TCR2 AARCH64_FL_V8_9A
> +
> /* SHA2 is an optional extension to AdvSIMD. */
> #define TARGET_SHA2 (AARCH64_ISA_SHA2)
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
> b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
> new file mode 100644
> index 000..e2f297bbeeb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
> @@ -0,0 +1,99 @@
> +/* Ensure support is present for all armv8.9-a system registers. */
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=armv8.9-a" } */
> +#include
> +void
> +readwrite_armv8p9a_sysregs ()
> +{
> + long long int a;
> +
> + /* Write-only system registers. */
> + __arm_wsr64 ("pmzr_el0", a); /* { dg-final { scan-assembler
> "msr\ts3_3_c9_c13_4, x0" } } */
> +
> + /* Read/write or write-only system registers. */
> + a = __arm_rsr64 ("amair2_el1");/* { { dg-final {
> scan-assembler "s3_0_c10_c3_1" } } */
> + a = __arm_rsr64 ("amair2_el12"); /* { { dg-final { scan-assembler
> "mrs\tx0, s3_5_c10_c3_1" } } */
> + a = __arm_rsr64 ("amair2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_4_c10_c3_1" } } */
> + a = __arm_rsr64 ("amair2_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_6_c10_c3_1" } } */
> + a = __arm_rsr64 ("erxgsr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_0_c5_c3_2" } } */
> + a = __arm_rsr64 ("hdfgrtr2_el2"); /* { { dg-final { scan-assembler
> "mrs\tx0, s3_4_c3_c1_0" } } */
> + a = __arm_rsr64 ("hdfgwtr2_el2"); /* { { dg-final { scan-assembler
> "mrs\tx0, s3_4_c3_c1_1" } } */
> + a = __arm_rsr64 ("hfgrtr2_el2"); /* { { dg-final { scan-assembler
> "mrs\tx0, s3_4_c3_c1_2" } } */
> + a = __arm_rsr64 ("hfgwtr2_el2"); /* { { dg-final { scan-assembler
> "mrs\tx0, s3_4_c3_c1_3" } } */
> + a = __arm_rsr64 ("id_aa64mmfr3_el1"); /* { { dg-final { scan-assembler
> "mrs\tx0, s3_0_c0_c7_3" } } */
> + a = __arm_rsr64 ("id_aa64mmfr4_el1"); /* { { dg-final { scan-assembler
> "mrs\tx0, s3_0_c0_c7_4" } } */
> + a = __arm_rsr64 ("mair2_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_0_c10_c2_1" } } */
> + a = __arm_rsr64 ("mair2_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_5_c10_c2_1" } } */
> + a = __arm_rsr64 ("mair2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_4_c10_c1_1" } } */
> + a = __arm_rsr64 ("mair2_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_6_c10_c1_1" } } */
> + a = __arm_rsr64 ("mdselr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
> s2_0_c0_c4_2" } } */
> + a = __arm_rsr64 ("pir_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_0_c10_c2_3" } } */
> + a = __arm_rsr64 ("pir_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_5_c10_c2_3" } } */
> + a = __arm_rsr64 ("pir_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_4_c10_c2_3" } } */
> + a = __arm_rsr64 ("pir_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
> s3_6_c10_c2_3" } } */
> + a = __arm_rsr64 (
[PATCH] AArch64: Update system register database.
With the release of Binutils 2.42, this brings the level of
system-register support in GCC in line with the current
state-of-the-art in Binutils, ensuring everything available in
Binutils is plainly accessible from GCC.
Where Binutils uses a more detailed description of which features are
responsible for enabling a given system register, GCC aliases the
binutils-equivalent feature flag macro constant to that of the base
architecture implementing the feature, resulting in entries such as
#define AARCH64_FL_S2PIE AARCH64_FL_V8_9A
in `aarch64.h', thus ensuring that the Binutils `aarch64-sys-regs.def'
file can be understood by GCC without the need for modification.
To accompany the addition of the new system registers, a new test is
added confirming they were successfully added to the list of
recognized registers.
gcc/ChangeLog:
* gcc/config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
* /config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
(AARCH64_FL_DEBUGv8p9): Likewise.
(AARCH64_FL_FGT2): Likewise.Likewise.
(AARCH64_FL_ITE): Likewise.
(AARCH64_FL_PFAR): Likewise.
(AARCH64_FL_PMUv3_ICNTR): Likewise.
(AARCH64_FL_PMUv3_SS): Likewise.
(AARCH64_FL_PMUv3p9): Likewise.
(AARCH64_FL_RASv2): Likewise.
(AARCH64_FL_S1PIE): Likewise.
(AARCH64_FL_S1POE): Likewise.
(AARCH64_FL_S2PIE): Likewise.
(AARCH64_FL_S2POE): Likewise.
(AARCH64_FL_SCTLR2): Likewise.
(AARCH64_FL_SEBEP): Likewise.
(AARCH64_FL_SPE_FDS): Likewise.
(AARCH64_FL_TCR2): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/rwsr-armv8p9.c: New.
---
gcc/config/aarch64/aarch64-sys-regs.def | 85
gcc/config/aarch64/aarch64.h | 20
.../gcc.target/aarch64/acle/rwsr-armv8p9.c| 99 +++
3 files changed, 204 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
diff --git a/gcc/config/aarch64/aarch64-sys-regs.def
b/gcc/config/aarch64/aarch64-sys-regs.def
index fffc35f72c8..6a948171d6e 100644
--- a/gcc/config/aarch64/aarch64-sys-regs.def
+++ b/gcc/config/aarch64/aarch64-sys-regs.def
@@ -54,6 +54,10 @@
SYSREG ("amair_el12",CPENC (3,5,10,3,0), F_ARCHEXT,
AARCH64_FEATURE (V8_1A))
SYSREG ("amair_el2", CPENC (3,4,10,3,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("amair_el3", CPENC (3,6,10,3,0), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("amair2_el1",CPENC (3,0,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el12", CPENC (3,5,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el2",CPENC (3,4,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el3",CPENC (3,6,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
SYSREG ("amcfgr_el0",CPENC (3,3,13,2,1),
F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("amcg1idr_el0", CPENC (3,3,13,2,6), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
SYSREG ("amcgcr_el0",CPENC (3,3,13,2,2),
F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
@@ -400,6 +404,7 @@
SYSREG ("erxaddr_el1", CPENC (3,0,5,4,3), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxctlr_el1", CPENC (3,0,5,4,1), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxfr_el1", CPENC (3,0,5,4,0), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (RAS))
+ SYSREG ("erxgsr_el1",CPENC (3,0,5,3,2),
F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (RASv2))
SYSREG ("erxmisc0_el1", CPENC (3,0,5,5,0), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxmisc1_el1", CPENC (3,0,5,5,1), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxmisc2_el1", CPENC (3,0,5,5,2), F_ARCHEXT,
AARCH64_FEATURE (RAS))
@@ -438,10 +443,14 @@
SYSREG ("hcr_el2", CPENC (3,4,1,1,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("hcrx_el2", CPENC (3,4,1,2,2), F_ARCHEXT,
AARCH64_FEATURE (V8_7A))
SYSREG ("hdfgrtr_el2", CPENC (3,4,3,1,4), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
+ SYSREG ("hdfgrtr2_el2", CPENC (3,4,3,1,0), F_ARCHEXT,
AARCH64_FEATURE (FGT2))
SYSREG ("hdfgwtr_el2", CPENC (3,4,3,1,5), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
+ SYSREG ("hdfgwtr2_el2", CPENC (3,4,3,1,1), F_ARCHEXT,
AARCH64_FEATURE (FGT2))
SYSREG ("hfgitr_el2",CPENC (3,4,1,1,6), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
SYSREG ("hfgrtr_el2",CPENC (3,4,1,1,4), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
+ SYSREG ("hfgrt
