Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the pic instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib with newlib/linux.
gcc/Changelog:
* config/riscv/pic.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/pic.md | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md
index da636e31619..cfaa670caf0 100644
--- a/gcc/config/riscv/pic.md
+++ b/gcc/config/riscv/pic.md
@@ -27,21 +27,24 @@ (define_insn "*local_pic_load"
(mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
"USE_LOAD_ADDRESS_MACRO (operands[1])"
"\t%0,%1"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "load")
+ (set (attr "length") (const_int 8))])
(define_insn "*local_pic_load_s"
[(set (match_operand:SUPERQI 0 "register_operand" "=r")
(sign_extend:SUPERQI (mem:SUBX (match_operand 1
"absolute_symbolic_operand" ""]
"USE_LOAD_ADDRESS_MACRO (operands[1])"
"\t%0,%1"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "load")
+ (set (attr "length") (const_int 8))])
(define_insn "*local_pic_load_u"
[(set (match_operand:SUPERQI 0 "register_operand" "=r")
(zero_extend:SUPERQI (mem:SUBX (match_operand 1
"absolute_symbolic_operand" ""]
"USE_LOAD_ADDRESS_MACRO (operands[1])"
"u\t%0,%1"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "load")
+ (set (attr "length") (const_int 8))])
;; We can support ANYLSF loads into X register if there is no double support
;; or if the target is 64-bit.
@@ -55,7 +58,8 @@ (define_insn "*local_pic_load"
"@
\t%0,%1,%2
\t%0,%1"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "fpload")
+ (set (attr "length") (const_int 8))])
;; ??? For a 32-bit target with double float, a DF load into a X reg isn't
;; supported. ld is not valid in that case. Punt for now. Maybe add a split
@@ -68,14 +72,16 @@ (define_insn "*local_pic_load_32d"
"TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
&& (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)"
"\t%0,%1,%2"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "fpload")
+ (set (attr "length") (const_int 8))])
(define_insn "*local_pic_load_sf"
[(set (match_operand:SOFTF 0 "register_operand" "=r")
(mem:SOFTF (match_operand 1 "absolute_symbolic_operand" "")))]
"!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])"
"\t%0,%1"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "fpload")
+ (set (attr "length") (const_int 8))])
;; Simplify PIC stores to static variables.
;; These should go away once we figure out how to emit auipc discretely.
@@ -86,7 +92,8 @@ (define_insn "*local_pic_store"
(clobber (match_scratch:P 2 "=&r"))]
"USE_LOAD_ADDRESS_MACRO (operands[0])"
"\t%z1,%0,%2"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "store")
+ (set (attr "length") (const_int 8))])
(define_insn "*local_pic_store"
[(set (mem:ANYLSF (match_operand 0 "absolute_symbolic_operand" ""))
@@ -97,7 +104,8 @@ (define_insn "*local_pic_store"
"@
\t%1,%0,%2
\t%1,%0,%2"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "fpstore")
+ (set (attr "length") (const_int 8))])
;; ??? For a 32-bit target with double float, a DF store from a X reg isn't
;; supported. sd is not valid in that case. Punt for now. Maybe add a split
@@ -110,7 +118,8 @@ (define_insn "*local_pic_store_32d"
"TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
&& (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)"
"\t%1,%0,%2"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "fpstore")
+ (set (attr "length") (const_int 8))])
(define_insn "*local_pic_store_sf"
[(set (mem:SOFTF (match_operand 0 "absolute_symbolic_operand" ""))
@@ -118,4 +127,5 @@ (define_insn "*local_pic_store_sf"
(clobber (match_scratch:P 2 "=&r"))]
"!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])"
"\t%1,%0,%2"
- [(set (attr "length") (const_int 8))])
+ [(set_attr "type" "fpstore")
+ (set (attr "length") (const_int 8))])
--
2.34.1
