Re: [PATCH] Microblaze: Fixes for RTL Checking

[Michael Eager]

On 03/09/2017 03:35 PM, Segher Boessenkool wrote:

Hi!

On Thu, Mar 09, 2017 at 10:18:43AM -0800, Michael Eager wrote:

--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -3323,10 +3323,10 @@ microblaze_expand_shift (rtx operands[])
   || (GET_CODE (operands[1]) == SUBREG));

/* Shift by zero -- copy regs if necessary.  */
-  if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 0))
+  if (CONST_INT_P (operands[2]) && (operands[2] == const0_rtx)


You don't need that first test since you have the second (and the parens
are superfluous as well).


Yes.  Fixed.

--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306  650-325-8077

Re: [PATCH] Microblaze: Fixes for RTL Checking

[Segher Boessenkool]

Hi!

On Thu, Mar 09, 2017 at 10:18:43AM -0800, Michael Eager wrote:
> --- a/gcc/config/microblaze/microblaze.c
> +++ b/gcc/config/microblaze/microblaze.c
> @@ -3323,10 +3323,10 @@ microblaze_expand_shift (rtx operands[])
>   || (GET_CODE (operands[1]) == SUBREG));
> 
>/* Shift by zero -- copy regs if necessary.  */
> -  if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 0))
> +  if (CONST_INT_P (operands[2]) && (operands[2] == const0_rtx)

You don't need that first test since you have the second (and the parens
are superfluous as well).


Segher

[PATCH] Microblaze: Fixes for RTL Checking

[Michael Eager]

2017-03-09  Michael Eager  

   Correct failures with --enable-checking=yes,rtl.

   * config/microblaze/microblaze.c (microblaze_expand_shift):
   Replace GET_CODE test with CONST_INT_P and INTVAL test with
   test for const0_rtx.
   * config/microblaze/microblaze.md (ashlsi3_byone, ashrsi3_byone,
   lshrsi3_byone): Replace INTVAL with test for const1_rtx.

diff --git a/gcc/config/microblaze/microblaze.c 
b/gcc/config/microblaze/microblaze.c
index 746bef1..fb115e6 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -3323,10 +3323,10 @@ microblaze_expand_shift (rtx operands[])
  || (GET_CODE (operands[1]) == SUBREG));

   /* Shift by zero -- copy regs if necessary.  */
-  if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 0))
+  if (CONST_INT_P (operands[2]) && (operands[2] == const0_rtx)
+  && !rtx_equal_p (operands[0], operands[1]))
 {
-  if (REGNO (operands[0]) != REGNO (operands[1]))
-   emit_insn (gen_movsi (operands[0], operands[1]));
+  emit_insn (gen_movsi (operands[0], operands[1]));
   return 1;
 }

diff --git a/gcc/config/microblaze/microblaze.md 
b/gcc/config/microblaze/microblaze.md
index 66ebc1e..b3a0011 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -1321,7 +1321,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand""I")))]
-  "(INTVAL (operands[2]) == 1)"
+  "(operands[2] == const1_rtx)"
   "addk\t%0,%1,%1"
   [(set_attr "type""arith")
(set_attr "mode""SI")
@@ -1482,7 +1482,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
  (match_operand:SI 2 "arith_operand""I")))]
-  "(INTVAL (operands[2]) == 1)"
+  "(operands[2] == const1_rtx)"
   "sra\t%0,%1"
   [(set_attr "type""arith")
(set_attr "mode""SI")
@@ -1571,7 +1571,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
  (match_operand:SI 2 "arith_operand""I")))]
-  "(INTVAL (operands[2]) == 1)"
+  "(operands[2] == const1_rtx)"
   "srl\t%0,%1"
   [(set_attr "type""arith")
(set_attr "mode""SI")

Committed revision 246012.

--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306  650-325-8077