Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the riscv instructions to ensure that no insn is left
without a type attribute. Added new types: "trap" (self explanatory) and "cbo"
(for cache related instructions)
Tested for regressions using rv32/64 multilib for linux/newlib. Also tested
rv32/64 gcv for linux.
gcc/Changelog:
* config/riscv/riscv.md: Update/Add types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.md | 112 --
1 file changed, 82 insertions(+), 30 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4041875e0e3..d80b6938f84 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -303,12 +303,14 @@ (define_attr "ext_enabled" "no,yes"
;; auipc integer addition to PC
;; sfb_alu SFB ALU instruction
;; nop no operation
+;; traptrap instruction
;; ghost an instruction that produces no real code
;; bitmanipbit manipulation instructions
;; clmulclmul, clmulh, clmulr
;; rotate rotation instructions
;; atomic atomic instructions
;; condmoveconditional moves
+;; cbocache block instructions
;; crypto cryptography instructions
;; Classification of RVV instructions which will be added to each RVV .md
pattern and used by scheduler.
;; rdvlenb vector byte length vlenb csrr read
@@ -417,9 +419,9 @@ (define_attr "ext_enabled" "no,yes"
(define_attr "type"
"unknown,branch,jump,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
- fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
- clmul,min,max,minu,maxu,clz,ctz,cpop,
- atomic,condmove,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
+ fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
+ rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
+ atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
@@ -1652,6 +1654,7 @@ (define_insn_and_split "*zero_extendsidi2_internal"
(lshiftrt:DI (match_dup 0) (const_int 32)))]
{ operands[1] = gen_lowpart (DImode, operands[1]); }
[(set_attr "move_type" "shift_shift,load")
+ (set_attr "type" "load")
(set_attr "mode" "DI")])
(define_expand "zero_extendhi2"
@@ -1680,6 +1683,7 @@ (define_insn_and_split "*zero_extendhi2"
operands[2] = GEN_INT(GET_MODE_BITSIZE(mode) - 16);
}
[(set_attr "move_type" "shift_shift,load")
+ (set_attr "type" "load")
(set_attr "mode" "")])
(define_insn "zero_extendqi2"
@@ -1691,6 +1695,7 @@ (define_insn "zero_extendqi2"
andi\t%0,%1,0xff
lbu\t%0,%1"
[(set_attr "move_type" "andi,load")
+ (set_attr "type" "multi")
(set_attr "mode" "")])
;;
@@ -1709,6 +1714,7 @@ (define_insn "extendsidi2"
sext.w\t%0,%1
lw\t%0,%1"
[(set_attr "move_type" "move,load")
+ (set_attr "type" "multi")
(set_attr "mode" "DI")])
(define_expand "extend2"
@@ -1736,6 +1742,7 @@ (define_insn_and_split
"*extend2"
- GET_MODE_BITSIZE (mode));
}
[(set_attr "move_type" "shift_shift,load")
+ (set_attr "type" "load")
(set_attr "mode" "SI")])
(define_insn "extendhfsf2"
@@ -1784,6 +1791,7 @@ (define_insn "*movhf_hardfloat"
|| reg_or_0_operand (operands[1], HFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type"
"fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+ (set_attr "type" "fmove")
(set_attr "mode" "HF")])
(define_insn "*movhf_softfloat"
@@ -1794,6 +1802,7 @@ (define_insn "*movhf_softfloat"
|| reg_or_0_operand (operands[1], HFmode))"
{ return riscv_output_move (operands[0], operands[1]); }
[(set_attr "move_type" "fmove,move,load,store,mtc,mfc")
+ (set_attr "type" "fmove")
(set_attr "mode" "HF")])
;;
@@ -1888,6 +1897,7 @@ (define_insn "got_load"
""
"la\t%0,%1"
[(set_attr "got" "load")
+(set_attr "type" "load")
(set_attr "mode" "")])
(define_insn "tls_add_tp_le"
@@ -1910,6 +1920,7 @@ (define_insn "got_load_tls_gd"
""
"la.tls.gd\t%0,%1"
[(set_attr "got" "load")
+ (set_attr "type" "load")
(set_attr "mode" "")])
(define_insn "got_load_tls_ie"
@@ -1920,6 +1931,7 @@ (define_insn "got_load_tls_ie"
""
"la.tls.ie\t%0,%1"
[(set_attr "got" "load")
+ (set_attr "type" "load")
(set_attr "mode" "")])
(define_insn "auipc"
@@ -1989,7 +2001,8 @@ (define_insn_and_split "*mvconst_internal"
riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
mode);
DONE;
-})
+}
+[(set_attr "type" "move")])
;; 64-bit integer moves
@@ -2011,6 +2024,7 @@ (define_insn "*movdi_32bit"
{ return riscv_output_move (operands[0],
