Re: [PATCH] RISC-V: Add crypto machine descriptions
On 12/26/23 19:47, Kito Cheng wrote: Thanks Feng, the patch is LGTM from my side, I am happy to accept vector crypto stuffs for GCC 14, it's mostly intrinsic stuff, and the only few non-intrinsic stuff also low risk enough (e.g. vrol, vctz) I won't object. I'm disappointed that we're in a similar situation as last year, but at least the scope is smaller. jeff
Re: [PATCH] RISC-V: Add crypto machine descriptions
Thanks Feng, the patch is LGTM from my side, I am happy to accept vector crypto stuffs for GCC 14, it's mostly intrinsic stuff, and the only few non-intrinsic stuff also low risk enough (e.g. vrol, vctz) On Fri, Dec 22, 2023 at 10:04 AM Feng Wang wrote: > > 2023-12-22 09:59 Feng Wang wrote: > > Sorry for forgetting to add the patch version number. It should be [PATCH v8 > 2/3] > > >Patch v8: Remove unused iterator and add newline at the end. > > > > >Patch v7: Remove mode of const_int_operand and typo. Add > > > > > newline at the end and comment at the beginning. > > > > >Patch v6: Swap the operator order of vandn.vv > > > > >Patch v5: Add vec_duplicate operator. > > > > >Patch v4: Add process of SEW=64 in RV32 system. > > > > >Patch v3: Moidfy constrains for crypto vector. > > > > >Patch v2: Add crypto vector ins into RATIO attr and use vr as > > > > >destination register. > > > > > > > > > >This patch add the crypto machine descriptions(vector-crypto.md) and > > > > >some new iterators which are used by crypto vector ext. > > > > > > > > > >Co-Authored by: Songhe Zhu > > > > >Co-Authored by: Ciyan Pan > > > > >gcc/ChangeLog: > > > > > > > > > > * config/riscv/iterators.md: Add rotate insn name. > > > > > * config/riscv/riscv.md: Add new insns name for crypto vector. > > > > > * config/riscv/vector-iterators.md: Add new iterators for crypto > > vector. > > > > > * config/riscv/vector.md: Add the corresponding attr for crypto > > vector. > > > > > * config/riscv/vector-crypto.md: New file.The machine descriptions > > for crypto vector. > > > > >--- > > > > > gcc/config/riscv/iterators.md| 4 +- > > > > > gcc/config/riscv/riscv.md| 33 +- > > > > > gcc/config/riscv/vector-crypto.md| 654 +++ > > > > > gcc/config/riscv/vector-iterators.md | 36 ++ > > > > > gcc/config/riscv/vector.md | 55 ++- > > > > > 5 files changed, 761 insertions(+), 21 deletions(-) > > > > > create mode 100755 gcc/config/riscv/vector-crypto.md > > > > > > > > > >diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md > > > > >index ecf033f2fa7..f332fba7031 100644 > > > > >--- a/gcc/config/riscv/iterators.md > > > > >+++ b/gcc/config/riscv/iterators.md > > > > >@@ -304,7 +304,9 @@ > > > > >(umax "maxu") > > > > >(clz "clz") > > > > >(ctz "ctz") > > > > >- (popcount "cpop")]) > > > > >+ (popcount "cpop") > > > > >+ (rotate "rol") > > > > >+ (rotatert "ror")]) > > > > > > > > > > ;; --- > > > > > ;; Int Iterators. > > > > >diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > > > >index ee8b71c22aa..88019a46a53 100644 > > > > >--- a/gcc/config/riscv/riscv.md > > > > >+++ b/gcc/config/riscv/riscv.md > > > > >@@ -427,6 +427,34 @@ > > > > > ;; vcompressvector compress instruction > > > > > ;; vmov whole vector register move > > > > > ;; vector unknown vector instruction > > > > >+;; 17. Crypto Vector instructions > > > > >+;; vandncrypto vector bitwise and-not instructions > > > > >+;; vbrevcrypto vector reverse bits in elements instructions > > > > >+;; vbrev8 crypto vector reverse bits in bytes instructions > > > > >+;; vrev8crypto vector reverse bytes instructions > > > > >+;; vclz crypto vector count leading Zeros instructions > > > > >+;; vctz crypto vector count lrailing Zeros instructions > > > > >+;; vrol crypto vector rotate left instructions > > > > >+;; vror crypto vector rotate right instructions > > > > >+;; vwsllcrypto vector widening shift left logical instructions > > > > >+;; vclmul crypto vector carry-less multiply - return low half > >instructions > > > > >+;; vclmulh crypto vector carry-less multiply - return high half > >instructions > > > > >+;; vghshcrypto vector add-multiply over GHASH Galois-Field > >instructions > > > > >+;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions > > > > >+;; vaesef crypto vector AES final-round encryption instructions > > > > >+;; vaesem crypto vector AES middle-round encryption instructions > > > > >+;; vaesdf crypto vector AES final-round decryption instructions > > > > >+;; vaesdm crypto vector AES middle-round decryption instructions > > > > >+;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation > >instructions > > > > >+;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation > >instructions > > > > >+;; vaeszcrypto vector AES round zero encryption/decryption > >instructions > > > > >+;; vsha2ms crypto vector SHA-2 message schedule instructions > > > > >+;; vsha2ch
Re: [PATCH] RISC-V: Add crypto machine descriptions
2023-12-22 09:59 Feng Wang wrote: Sorry for forgetting to add the patch version number. It should be [PATCH v8 2/3] >Patch v8: Remove unused iterator and add newline at the end. >Patch v7: Remove mode of const_int_operand and typo. Add > newline at the end and comment at the beginning. >Patch v6: Swap the operator order of vandn.vv >Patch v5: Add vec_duplicate operator. >Patch v4: Add process of SEW=64 in RV32 system. >Patch v3: Moidfy constrains for crypto vector. >Patch v2: Add crypto vector ins into RATIO attr and use vr as >destination register. > >This patch add the crypto machine descriptions(vector-crypto.md) and >some new iterators which are used by crypto vector ext. > >Co-Authored by: Songhe Zhu >Co-Authored by: Ciyan Pan >gcc/ChangeLog: > > * config/riscv/iterators.md: Add rotate insn name. > * config/riscv/riscv.md: Add new insns name for crypto vector. > * config/riscv/vector-iterators.md: Add new iterators for crypto vector. > * config/riscv/vector.md: Add the corresponding attr for crypto vector. > * config/riscv/vector-crypto.md: New file.The machine descriptions for > crypto vector. >--- > gcc/config/riscv/iterators.md | 4 +- > gcc/config/riscv/riscv.md | 33 +- > gcc/config/riscv/vector-crypto.md | 654 +++ > gcc/config/riscv/vector-iterators.md | 36 ++ > gcc/config/riscv/vector.md | 55 ++- > 5 files changed, 761 insertions(+), 21 deletions(-) > create mode 100755 gcc/config/riscv/vector-crypto.md > >diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md >index ecf033f2fa7..f332fba7031 100644 >--- a/gcc/config/riscv/iterators.md >+++ b/gcc/config/riscv/iterators.md >@@ -304,7 +304,9 @@ >(umax "maxu") >(clz "clz") >(ctz "ctz") >- (popcount "cpop")]) >+ (popcount "cpop") >+ (rotate "rol") >+ (rotatert "ror")]) > > ;; --- > ;; Int Iterators. >diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md >index ee8b71c22aa..88019a46a53 100644 >--- a/gcc/config/riscv/riscv.md >+++ b/gcc/config/riscv/riscv.md >@@ -427,6 +427,34 @@ > ;; vcompress vector compress instruction > ;; vmov whole vector register move > ;; vector unknown vector instruction >+;; 17. Crypto Vector instructions >+;; vandn crypto vector bitwise and-not instructions >+;; vbrev crypto vector reverse bits in elements instructions >+;; vbrev8 crypto vector reverse bits in bytes instructions >+;; vrev8 crypto vector reverse bytes instructions >+;; vclz crypto vector count leading Zeros instructions >+;; vctz crypto vector count lrailing Zeros instructions >+;; vrol crypto vector rotate left instructions >+;; vror crypto vector rotate right instructions >+;; vwsll crypto vector widening shift left logical instructions >+;; vclmul crypto vector carry-less multiply - return low half >instructions >+;; vclmulh crypto vector carry-less multiply - return high half >instructions >+;; vghsh crypto vector add-multiply over GHASH Galois-Field >instructions >+;; vgmul crypto vector multiply over GHASH Galois-Field instrumctions >+;; vaesef crypto vector AES final-round encryption instructions >+;; vaesem crypto vector AES middle-round encryption instructions >+;; vaesdf crypto vector AES final-round decryption instructions >+;; vaesdm crypto vector AES middle-round decryption instructions >+;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation >instructions >+;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation >instructions >+;; vaesz crypto vector AES round zero encryption/decryption >instructions >+;; vsha2ms crypto vector SHA-2 message schedule instructions >+;; vsha2ch crypto vector SHA-2 two rounds of compression instructions >+;; vsha2cl crypto vector SHA-2 two rounds of compression instructions >+;; vsm4k crypto vector SM4 KeyExpansion instructions >+;; vsm4r crypto vector SM4 Rounds instructions >+;; vsm3me crypto vector SM3 Message Expansion instructions >+;; vsm3c crypto vector SM3 Compression instructions > (define_attr "type" > "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, > mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, >@@ -446,7 +474,9 @@ > vired,viwred,vfredu,vfredo,vfwredu,vfwredo, > vmalu,vmpop,vmffs
Re: [PATCH] RISC-V: Add crypto machine descriptions
Machine description part is ok from my side. But I don't know the plan of vector crypto. I'd like to wait kito or Jeff to make sure we allow vector-crypto intrinsics as part of GCC-14 release. Thanks. juzhe.zh...@rivai.ai From: Feng Wang Date: 2023-12-22 09:59 To: gcc-patches CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang Subject: [PATCH] RISC-V: Add crypto machine descriptions Patch v8: Remove unused iterator and add newline at the end. Patch v7: Remove mode of const_int_operand and typo. Add newline at the end and comment at the beginning. Patch v6: Swap the operator order of vandn.vv Patch v5: Add vec_duplicate operator. Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 654 +++ gcc/config/riscv/vector-iterators.md | 36 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 761 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") - (popcount "cpop")]) + (popcount "cpop") + (rotate "rol") + (rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ee8b71c22aa..88019a46a53 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpo
[PATCH] RISC-V: Add crypto machine descriptions
Patch v8: Remove unused iterator and add newline at the end. Patch v7: Remove mode of const_int_operand and typo. Add newline at the end and comment at the beginning. Patch v6: Swap the operator order of vandn.vv Patch v5: Add vec_duplicate operator. Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 654 +++ gcc/config/riscv/vector-iterators.md | 36 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 761 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ee8b71c22aa..88019a46a53 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a do
