Hi,
There is a new failed RISC-V
testcase(testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c)
on the current trunk branch when use medany as default cmodel.
The reason is the load of half floating-point imm is convert from RTL 1 to RTL
2 as the cmodel be changed from medlow to medany. This change let insn 7 be
combineed with @pred_broadcast patterns (insn 8) at combine pass. However,
insn 6 and insn 7 are combined for SF and DF mode, but not for HF mode, and
the fail combined leads to insn 7 and insn 8 be combined. The reason of the
fail combined is the local_pic_loadhf pattern doesn't exist when only enable
zfhmin(implied by zvfh).
Therefore, when only zfhmin but not zfh is enabled, the define_insn of
*local_pic_load must also be able to produce the pattern for
*load_pic_loadhf pattern, since the zfhmin extension also includes a
half floating-point load/store instructions. So, I added an ANFLSF Iterator
and applied it to local_pic_load/store define_insns. I have checked other ANYF
usage scenarios and feel that this is the only place that needs to be corrected.
I may have missed something, please correct. Thanks.
RTL 1:
(insn 6 3 7 2 (set (reg:DI 137)
(high:DI (symbol_ref/u:DI ("*.LC0") [flags 0x82])))
"/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1
discrim 3 179 {*movdi_64bit}
(nil))
(insn 7 6 8 2 (set (reg:HF 136)
(mem/u/c:HF (lo_sum:DI (reg:DI 137)
(symbol_ref/u:DI ("*.LC0") [flags 0x82])) [0 S2 A16]))
"/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1
discrim 3 126 {*movhf_hardfloat}
(expr_list:REG_EQUAL (const_double:HF 8.8828125e+0 [0x0.8e2p+4])
(nil)))
RTL 2:
(insn 6 3 7 2 (set (reg/f:DI 137)
(symbol_ref/u:DI ("*.LC0") [flags 0x82]))
"/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1
discrim 3 179 {*movdi_64bit}
(nil))
(insn 7 6 8 2 (set (reg:HF 136)
(mem/u/c:HF (reg/f:DI 137) [0 S2 A16]))
"/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":7:1
discrim 3 126 {*movhf_hardfloat}
(expr_list:REG_EQUAL (const_double:HF 8.8828125e+0 [0x0.8e2p+4])
(nil)))
(insn 8 7 9 2 (set (reg:V2HF 135)
(if_then_else:V2HF (unspec:V2BI [
(const_vector:V2BI [
(const_int 1 [0x1]) repeated x2
])
(const_int 2 [0x2]) repeated x3
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(vec_duplicate:V2HF (reg:HF 136))
(unspec:V2HF [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)))
"/work/home/lding/open-source/riscv-gnu-toolchain-push/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c":6:1
discrim 3 1389 {*pred_broadcastv2hf}
(nil))
Best,
Lehua
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_HARD_FLOAT || TARGET_ZFINX): New.
* config/riscv/pic.md (*local_pic_load): Change ANYF.
(*local_pic_load): To ANYLSF.
(*local_pic_load_32d): Ditto.
(*local_pic_load_32d): Ditto.
(*local_pic_store): Ditto.
(*local_pic_store): Ditto.
(*local_pic_store_32d): Ditto.
(*local_pic_store_32d): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Float16-zfhmin-4.c: New test.
---
gcc/config/riscv/iterators.md | 5 +++
gcc/config/riscv/pic.md | 34 +--
.../gcc.target/riscv/_Float16-zfhmin-4.c | 11 ++
3 files changed, 33 insertions(+), 17 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-4.c
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index d374a10810c..39c2dd629a2 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -67,6 +67,11 @@
(DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
(HF "TARGET_ZFH || TARGET_ZHINX")])
+;; Iterator for hardware-supported load/store floating-point modes.
+(define_mode_iterator ANYLSF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+ (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
+ (HF "TARGET_ZFHMIN || TARGET_ZHINX")])
+
;; Iterator for floating-point modes that can be loaded into X registers.
(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md
index 9507850455a..da636e31619 100644
--- a/gcc/config/riscv/pic.md
+++ b/gcc/config/riscv/pic.md
@@ -43,17 +43,17 @@
"u\t%0,%1"
[(set (attr "length") (const_int 8))])
-;; We can support ANYF loads into X register if there
