Re: [PATCH] RISC-V: Add vle/vse C++ overloaded API intrinsic testcases
committed, thanks!
On Fri, Jan 20, 2023 at 10:26 AM wrote:
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/vle-1.C: New test.
> * g++.target/riscv/rvv/base/vle_tu-1.C: New test.
> * g++.target/riscv/rvv/base/vle_tum-1.C: New test.
> * g++.target/riscv/rvv/base/vle_tumu-1.C: New test.
> * g++.target/riscv/rvv/base/vse-1.C: New test.
>
> ---
> .../g++.target/riscv/rvv/base/vle-1.C | 345 +
> .../g++.target/riscv/rvv/base/vle_tu-1.C | 345 +
> .../g++.target/riscv/rvv/base/vle_tum-1.C | 345 +
> .../g++.target/riscv/rvv/base/vle_tumu-1.C| 345 +
> .../g++.target/riscv/rvv/base/vse-1.C | 685 ++
> 5 files changed, 2065 insertions(+)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tum-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tumu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vse-1.C
>
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
> b/gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
> new file mode 100644
> index 000..e06f62a8fb9
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
> @@ -0,0 +1,345 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t
> +test___riscv_vle8(vbool64_t mask,int8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vint8mf4_t
> +test___riscv_vle8(vbool32_t mask,int8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vint8mf2_t
> +test___riscv_vle8(vbool16_t mask,int8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vint8m1_t
> +test___riscv_vle8(vbool8_t mask,int8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vint8m2_t
> +test___riscv_vle8(vbool4_t mask,int8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vint8m4_t
> +test___riscv_vle8(vbool2_t mask,int8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vint8m8_t
> +test___riscv_vle8(vbool1_t mask,int8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vuint8mf8_t
> +test___riscv_vle8(vbool64_t mask,uint8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vuint8mf4_t
> +test___riscv_vle8(vbool32_t mask,uint8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vuint8mf2_t
> +test___riscv_vle8(vbool16_t mask,uint8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vuint8m1_t
> +test___riscv_vle8(vbool8_t mask,uint8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vuint8m2_t
> +test___riscv_vle8(vbool4_t mask,uint8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vuint8m4_t
> +test___riscv_vle8(vbool2_t mask,uint8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vuint8m8_t
> +test___riscv_vle8(vbool1_t mask,uint8_t* base,size_t vl)
> +{
> + return __riscv_vle8(mask,base,vl);
> +}
> +
> +vint16mf4_t
> +test___riscv_vle16(vbool64_t mask,int16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vint16mf2_t
> +test___riscv_vle16(vbool32_t mask,int16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vint16m1_t
> +test___riscv_vle16(vbool16_t mask,int16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vint16m2_t
> +test___riscv_vle16(vbool8_t mask,int16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vint16m4_t
> +test___riscv_vle16(vbool4_t mask,int16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vint16m8_t
> +test___riscv_vle16(vbool2_t mask,int16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vuint16mf4_t
> +test___riscv_vle16(vbool64_t mask,uint16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vuint16mf2_t
> +test___riscv_vle16(vbool32_t mask,uint16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vuint16m1_t
> +test___riscv_vle16(vbool16_t mask,uint16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vuint16m2_t
> +test___riscv_vle16(vbool8_t mask,uint16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vuint16m4_t
> +test___riscv_vle16(vbool4_t mask,uint16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vuint16m8_t
> +test___riscv_vle16(vbool2_t mask,uint16_t* base,size_t vl)
> +{
> + return __riscv_vle16(mask,base,vl);
> +}
> +
> +vint32mf2_t
>
[PATCH] RISC-V: Add vle/vse C++ overloaded API intrinsic testcases
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vle-1.C: New test.
* g++.target/riscv/rvv/base/vle_tu-1.C: New test.
* g++.target/riscv/rvv/base/vle_tum-1.C: New test.
* g++.target/riscv/rvv/base/vle_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vse-1.C: New test.
---
.../g++.target/riscv/rvv/base/vle-1.C | 345 +
.../g++.target/riscv/rvv/base/vle_tu-1.C | 345 +
.../g++.target/riscv/rvv/base/vle_tum-1.C | 345 +
.../g++.target/riscv/rvv/base/vle_tumu-1.C| 345 +
.../g++.target/riscv/rvv/base/vse-1.C | 685 ++
5 files changed, 2065 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tum-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tumu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vse-1.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
new file mode 100644
index 000..e06f62a8fb9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C
@@ -0,0 +1,345 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t
+test___riscv_vle8(vbool64_t mask,int8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vint8mf4_t
+test___riscv_vle8(vbool32_t mask,int8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vint8mf2_t
+test___riscv_vle8(vbool16_t mask,int8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vint8m1_t
+test___riscv_vle8(vbool8_t mask,int8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vint8m2_t
+test___riscv_vle8(vbool4_t mask,int8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vint8m4_t
+test___riscv_vle8(vbool2_t mask,int8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vint8m8_t
+test___riscv_vle8(vbool1_t mask,int8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vuint8mf8_t
+test___riscv_vle8(vbool64_t mask,uint8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vuint8mf4_t
+test___riscv_vle8(vbool32_t mask,uint8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vuint8mf2_t
+test___riscv_vle8(vbool16_t mask,uint8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vuint8m1_t
+test___riscv_vle8(vbool8_t mask,uint8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vuint8m2_t
+test___riscv_vle8(vbool4_t mask,uint8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vuint8m4_t
+test___riscv_vle8(vbool2_t mask,uint8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vuint8m8_t
+test___riscv_vle8(vbool1_t mask,uint8_t* base,size_t vl)
+{
+ return __riscv_vle8(mask,base,vl);
+}
+
+vint16mf4_t
+test___riscv_vle16(vbool64_t mask,int16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vint16mf2_t
+test___riscv_vle16(vbool32_t mask,int16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vint16m1_t
+test___riscv_vle16(vbool16_t mask,int16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vint16m2_t
+test___riscv_vle16(vbool8_t mask,int16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vint16m4_t
+test___riscv_vle16(vbool4_t mask,int16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vint16m8_t
+test___riscv_vle16(vbool2_t mask,int16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vuint16mf4_t
+test___riscv_vle16(vbool64_t mask,uint16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vuint16mf2_t
+test___riscv_vle16(vbool32_t mask,uint16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vuint16m1_t
+test___riscv_vle16(vbool16_t mask,uint16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vuint16m2_t
+test___riscv_vle16(vbool8_t mask,uint16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vuint16m4_t
+test___riscv_vle16(vbool4_t mask,uint16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vuint16m8_t
+test___riscv_vle16(vbool2_t mask,uint16_t* base,size_t vl)
+{
+ return __riscv_vle16(mask,base,vl);
+}
+
+vint32mf2_t
+test___riscv_vle32(vbool64_t mask,int32_t* base,size_t vl)
+{
+ return __riscv_vle32(mask,base,vl);
+}
+
+vint32m1_t
+test___riscv_vle32(vbool32_t mask,int32_t* base,size_t vl)
+{
+ return __riscv_vle32(mask,base,vl);
+}
+
+vint32m2_t
+test___riscv_vle32(vbool16_t mask,int32_t* base,size_t vl)
+{
+ return __riscv_vle32(mask,base,vl);
+}
+
+vint32m4_t
+test___riscv_vle32(vbool8_t mask,int32_t* base,size_t vl)
+{
+ return __riscv_vle32(mask,base,vl);
+}
+
