Re: [PATCH] RISC-V: Fix ICE in LRA for LMUL < 1 vector spillings
Committed as
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=cd0c433e5faba9a18f64881cd761a53a530aa798
with comment tweak.
On Wed, Mar 22, 2023 at 10:50 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global.
> (emit_vlmax_op): Ditto.
> * config/riscv/riscv-v.cc (get_sew): New function.
> (emit_vlmax_vsetvl): Adapt function.
> (emit_pred_op): Ditto.
> (emit_vlmax_op): Ditto.
> (emit_nonvlmax_op): Ditto.
> (legitimize_move): Fix LRA ICE.
> (gen_no_side_effects_vsetvl_rtx): Adapt function.
> * config/riscv/vector.md (@mov_lra): New
> pattern.
> (@mov_lra): Ditto.
> (*mov_lra): Ditto.
> (*mov_lra): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/binop_vv_constraint-4.c: Adapt testcase.
> * gcc.target/riscv/rvv/base/binop_vv_constraint-6.c: Ditto.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-127.c: Ditto.
> * gcc.target/riscv/rvv/base/spill-1.c: Ditto.
> * gcc.target/riscv/rvv/base/spill-2.c: Ditto.
> * gcc.target/riscv/rvv/base/spill-3.c: Ditto.
> * gcc.target/riscv/rvv/base/spill-5.c: Ditto.
> * gcc.target/riscv/rvv/base/spill-7.c: Ditto.
> * g++.target/riscv/rvv/base/bug-18.C: New test.
> * gcc.target/riscv/rvv/base/merge_constraint-3.c: New test.
> * gcc.target/riscv/rvv/base/merge_constraint-4.c: New test.
>
> ---
> gcc/config/riscv/riscv-protos.h | 2 +
> gcc/config/riscv/riscv-v.cc | 67 +--
> gcc/config/riscv/vector.md| 56 ++
> .../g++.target/riscv/rvv/base/bug-18.C| 140 +++
> .../riscv/rvv/base/binop_vv_constraint-4.c| 1 +
> .../riscv/rvv/base/binop_vv_constraint-6.c| 1 +
> .../riscv/rvv/base/binop_vx_constraint-127.c | 2 +-
> .../riscv/rvv/base/merge_constraint-3.c | 95 ++
> .../riscv/rvv/base/merge_constraint-4.c | 28 +++
> .../gcc.target/riscv/rvv/base/spill-1.c | 168 +-
> .../gcc.target/riscv/rvv/base/spill-2.c | 112 ++--
> .../gcc.target/riscv/rvv/base/spill-3.c | 56 +++---
> .../gcc.target/riscv/rvv/base/spill-5.c | 26 +--
> .../gcc.target/riscv/rvv/base/spill-7.c | 161 +
> 14 files changed, 636 insertions(+), 279 deletions(-)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-3.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-4.c
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index f35aaf35b48..060dddbdc22 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -157,7 +157,9 @@ bool check_builtin_call (location_t, vec,
> unsigned int,
>tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> bool legitimize_move (rtx, rtx, machine_mode);
> +void emit_vlmax_vsetvl (machine_mode, rtx);
> void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
> +void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
> void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
> enum vlmul_type get_vlmul (machine_mode);
> unsigned int get_ratio (machine_mode);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 9b83ef6ea5e..d7b77fd6123 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -98,6 +98,15 @@ private:
>expand_operand m_ops[MAX_OPERANDS];
> };
>
> +static unsigned
> +get_sew (machine_mode mode)
> +{
> + unsigned int sew = GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL
> + ? 8
> + : GET_MODE_BITSIZE (GET_MODE_INNER (mode));
> + return sew;
> +}
> +
> /* Return true if X is a const_vector with all duplicate elements, which is
> in
> the range between MINVAL and MAXVAL. */
> bool
> @@ -109,13 +118,10 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
> minval,
> && IN_RANGE (INTVAL (elt), minval, maxval));
> }
>
> -static rtx
> -emit_vlmax_vsetvl (machine_mode vmode)
> +void
> +emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
> {
> - rtx vl = gen_reg_rtx (Pmode);
> - unsigned int sew = GET_MODE_CLASS (vmode) == MODE_VECTOR_BOOL
> - ? 8
> - : GET_MODE_BITSIZE (GET_MODE_INNER (vmode));
> + unsigned int sew = get_sew (vmode);
>enum vlmul_type vlmul = get_vlmul (vmode);
>unsigned int ratio = calculate_ratio (sew, vlmul);
>
> @@ -125,8 +131,6 @@ emit_vlmax_vsetvl (machine_mode vmode)
>const0_rtx));
>else
> emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
> -
> - return vl;
> }
>
> /* Calculate
[PATCH] RISC-V: Fix ICE in LRA for LMUL < 1 vector spillings
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global.
(emit_vlmax_op): Ditto.
* config/riscv/riscv-v.cc (get_sew): New function.
(emit_vlmax_vsetvl): Adapt function.
(emit_pred_op): Ditto.
(emit_vlmax_op): Ditto.
(emit_nonvlmax_op): Ditto.
(legitimize_move): Fix LRA ICE.
(gen_no_side_effects_vsetvl_rtx): Adapt function.
* config/riscv/vector.md (@mov_lra): New pattern.
(@mov_lra): Ditto.
(*mov_lra): Ditto.
(*mov_lra): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vv_constraint-4.c: Adapt testcase.
* gcc.target/riscv/rvv/base/binop_vv_constraint-6.c: Ditto.
* gcc.target/riscv/rvv/base/binop_vx_constraint-127.c: Ditto.
* gcc.target/riscv/rvv/base/spill-1.c: Ditto.
* gcc.target/riscv/rvv/base/spill-2.c: Ditto.
* gcc.target/riscv/rvv/base/spill-3.c: Ditto.
* gcc.target/riscv/rvv/base/spill-5.c: Ditto.
* gcc.target/riscv/rvv/base/spill-7.c: Ditto.
* g++.target/riscv/rvv/base/bug-18.C: New test.
* gcc.target/riscv/rvv/base/merge_constraint-3.c: New test.
* gcc.target/riscv/rvv/base/merge_constraint-4.c: New test.
---
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/riscv/riscv-v.cc | 67 +--
gcc/config/riscv/vector.md| 56 ++
.../g++.target/riscv/rvv/base/bug-18.C| 140 +++
.../riscv/rvv/base/binop_vv_constraint-4.c| 1 +
.../riscv/rvv/base/binop_vv_constraint-6.c| 1 +
.../riscv/rvv/base/binop_vx_constraint-127.c | 2 +-
.../riscv/rvv/base/merge_constraint-3.c | 95 ++
.../riscv/rvv/base/merge_constraint-4.c | 28 +++
.../gcc.target/riscv/rvv/base/spill-1.c | 168 +-
.../gcc.target/riscv/rvv/base/spill-2.c | 112 ++--
.../gcc.target/riscv/rvv/base/spill-3.c | 56 +++---
.../gcc.target/riscv/rvv/base/spill-5.c | 26 +--
.../gcc.target/riscv/rvv/base/spill-7.c | 161 +
14 files changed, 636 insertions(+), 279 deletions(-)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/bug-18.C
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-4.c
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index f35aaf35b48..060dddbdc22 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -157,7 +157,9 @@ bool check_builtin_call (location_t, vec,
unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx, machine_mode);
+void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
+void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
enum vlmul_type get_vlmul (machine_mode);
unsigned int get_ratio (machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 9b83ef6ea5e..d7b77fd6123 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -98,6 +98,15 @@ private:
expand_operand m_ops[MAX_OPERANDS];
};
+static unsigned
+get_sew (machine_mode mode)
+{
+ unsigned int sew = GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL
+ ? 8
+ : GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+ return sew;
+}
+
/* Return true if X is a const_vector with all duplicate elements, which is in
the range between MINVAL and MAXVAL. */
bool
@@ -109,13 +118,10 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
minval,
&& IN_RANGE (INTVAL (elt), minval, maxval));
}
-static rtx
-emit_vlmax_vsetvl (machine_mode vmode)
+void
+emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
{
- rtx vl = gen_reg_rtx (Pmode);
- unsigned int sew = GET_MODE_CLASS (vmode) == MODE_VECTOR_BOOL
- ? 8
- : GET_MODE_BITSIZE (GET_MODE_INNER (vmode));
+ unsigned int sew = get_sew (vmode);
enum vlmul_type vlmul = get_vlmul (vmode);
unsigned int ratio = calculate_ratio (sew, vlmul);
@@ -125,8 +131,6 @@ emit_vlmax_vsetvl (machine_mode vmode)
const0_rtx));
else
emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
-
- return vl;
}
/* Calculate SEW/LMUL ratio. */
@@ -166,7 +170,7 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
/* Emit an RVV unmask && vl mov from SRC to DEST. */
static void
emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
- machine_mode mask_mode)
+ machine_mode mask_mode, bool vlmax_p)
{
insn_expander<8> e;
machine_mode mode = GET_MODE (dest);
@@
