Re: [PATCH] RISC-V: Fix pr109479 RVV ISA inconsistency bug
Thanks for the quick response! verified and pushed to trunk. On Wed, Apr 12, 2023 at 9:56 PM wrote: > > From: Ju-Zhe Zhong > > Fix supporting data type according to RVV ISA. > For vint64m*_t, we should only allow them in zve64* instead of zve32*_zvl64b > (>=64b). > Ideally, we should make error message more friendly like Clang. > https://godbolt.org/z/f9GMv4dMo to report the RVV type require extenstion > name. > However, I failed to find a way to do that. So current GCC can only report > "unknown" type. > And I added comments to remind us doing this in the future. > > PR 109479 > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-types.def (vint8mf8_t): Fix > predicate. > (vint16mf4_t): Ditto. > (vint32mf2_t): Ditto. > (vint64m1_t): Ditto. > (vint64m2_t): Ditto. > (vint64m4_t): Ditto. > (vint64m8_t): Ditto. > (vuint8mf8_t): Ditto. > (vuint16mf4_t): Ditto. > (vuint32mf2_t): Ditto. > (vuint64m1_t): Ditto. > (vuint64m2_t): Ditto. > (vuint64m4_t): Ditto. > (vuint64m8_t): Ditto. > (vfloat32mf2_t): Ditto. > (vbool64_t): Ditto. > * config/riscv/riscv-vector-builtins.cc (register_builtin_type): Add > comments. > (register_vector_type): Ditto. > (check_required_extensions): Fix condition. > * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ZVE64): Remove it. > (RVV_REQUIRE_ELEN_64): New define. > (RVV_REQUIRE_MIN_VLEN_64): Ditto. > * config/riscv/riscv-vector-switch.def (TARGET_VECTOR_FP32): Remove > it. > (TARGET_VECTOR_FP64): Ditto. > (ENTRY): Fix predicate. > * config/riscv/vector-iterators.md: Fix predicate. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr109479-1.c: New test. > * gcc.target/riscv/rvv/base/pr109479-2.c: New test. > * gcc.target/riscv/rvv/base/pr109479-3.c: New test. > * gcc.target/riscv/rvv/base/pr109479-4.c: New test. > * gcc.target/riscv/rvv/base/pr109479-5.c: New test. > * gcc.target/riscv/rvv/base/pr109479-6.c: New test. > > --- > .../riscv/riscv-vector-builtins-types.def | 348 +- > gcc/config/riscv/riscv-vector-builtins.cc | 14 +- > gcc/config/riscv/riscv-vector-builtins.h | 3 +- > gcc/config/riscv/riscv-vector-switch.def | 56 ++- > gcc/config/riscv/vector-iterators.md | 68 ++-- > .../gcc.target/riscv/rvv/base/pr109479-1.c| 13 + > .../gcc.target/riscv/rvv/base/pr109479-2.c| 13 + > .../gcc.target/riscv/rvv/base/pr109479-3.c| 20 + > .../gcc.target/riscv/rvv/base/pr109479-4.c| 20 + > .../gcc.target/riscv/rvv/base/pr109479-5.c| 20 + > .../gcc.target/riscv/rvv/base/pr109479-6.c| 20 + > 11 files changed, 349 insertions(+), 246 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-6.c > > diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def > b/gcc/config/riscv/riscv-vector-builtins-types.def > index a55d494f1d9..a74df066521 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-types.def > +++ b/gcc/config/riscv/riscv-vector-builtins-types.def > @@ -235,53 +235,53 @@ along with GCC; see the file COPYING3. If not see > #define DEF_RVV_LMUL4_OPS(TYPE, REQUIRE) > #endif > > -DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64) > +DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) > DEF_RVV_I_OPS (vint8mf4_t, 0) > DEF_RVV_I_OPS (vint8mf2_t, 0) > DEF_RVV_I_OPS (vint8m1_t, 0) > DEF_RVV_I_OPS (vint8m2_t, 0) > DEF_RVV_I_OPS (vint8m4_t, 0) > DEF_RVV_I_OPS (vint8m8_t, 0) > -DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64) > +DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) > DEF_RVV_I_OPS (vint16mf2_t, 0) > DEF_RVV_I_OPS (vint16m1_t, 0) > DEF_RVV_I_OPS (vint16m2_t, 0) > DEF_RVV_I_OPS (vint16m4_t, 0) > DEF_RVV_I_OPS (vint16m8_t, 0) > -DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64) > +DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) > DEF_RVV_I_OPS (vint32m1_t, 0) > DEF_RVV_I_OPS (vint32m2_t, 0) > DEF_RVV_I_OPS (vint32m4_t, 0) > DEF_RVV_I_OPS (vint32m8_t, 0) > -DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ZVE64) > -DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ZVE64) > -DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ZVE64) > -DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ZVE64) > +DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64) > +DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) > +DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) > +DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) > > -DEF_RVV_U_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64) >
[PATCH] RISC-V: Fix pr109479 RVV ISA inconsistency bug
From: Ju-Zhe Zhong Fix supporting data type according to RVV ISA. For vint64m*_t, we should only allow them in zve64* instead of zve32*_zvl64b (>=64b). Ideally, we should make error message more friendly like Clang. https://godbolt.org/z/f9GMv4dMo to report the RVV type require extenstion name. However, I failed to find a way to do that. So current GCC can only report "unknown" type. And I added comments to remind us doing this in the future. PR 109479 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-types.def (vint8mf8_t): Fix predicate. (vint16mf4_t): Ditto. (vint32mf2_t): Ditto. (vint64m1_t): Ditto. (vint64m2_t): Ditto. (vint64m4_t): Ditto. (vint64m8_t): Ditto. (vuint8mf8_t): Ditto. (vuint16mf4_t): Ditto. (vuint32mf2_t): Ditto. (vuint64m1_t): Ditto. (vuint64m2_t): Ditto. (vuint64m4_t): Ditto. (vuint64m8_t): Ditto. (vfloat32mf2_t): Ditto. (vbool64_t): Ditto. * config/riscv/riscv-vector-builtins.cc (register_builtin_type): Add comments. (register_vector_type): Ditto. (check_required_extensions): Fix condition. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ZVE64): Remove it. (RVV_REQUIRE_ELEN_64): New define. (RVV_REQUIRE_MIN_VLEN_64): Ditto. * config/riscv/riscv-vector-switch.def (TARGET_VECTOR_FP32): Remove it. (TARGET_VECTOR_FP64): Ditto. (ENTRY): Fix predicate. * config/riscv/vector-iterators.md: Fix predicate. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr109479-1.c: New test. * gcc.target/riscv/rvv/base/pr109479-2.c: New test. * gcc.target/riscv/rvv/base/pr109479-3.c: New test. * gcc.target/riscv/rvv/base/pr109479-4.c: New test. * gcc.target/riscv/rvv/base/pr109479-5.c: New test. * gcc.target/riscv/rvv/base/pr109479-6.c: New test. --- .../riscv/riscv-vector-builtins-types.def | 348 +- gcc/config/riscv/riscv-vector-builtins.cc | 14 +- gcc/config/riscv/riscv-vector-builtins.h | 3 +- gcc/config/riscv/riscv-vector-switch.def | 56 ++- gcc/config/riscv/vector-iterators.md | 68 ++-- .../gcc.target/riscv/rvv/base/pr109479-1.c| 13 + .../gcc.target/riscv/rvv/base/pr109479-2.c| 13 + .../gcc.target/riscv/rvv/base/pr109479-3.c| 20 + .../gcc.target/riscv/rvv/base/pr109479-4.c| 20 + .../gcc.target/riscv/rvv/base/pr109479-5.c| 20 + .../gcc.target/riscv/rvv/base/pr109479-6.c| 20 + 11 files changed, 349 insertions(+), 246 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-6.c diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index a55d494f1d9..a74df066521 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -235,53 +235,53 @@ along with GCC; see the file COPYING3. If not see #define DEF_RVV_LMUL4_OPS(TYPE, REQUIRE) #endif -DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_I_OPS (vint8mf4_t, 0) DEF_RVV_I_OPS (vint8mf2_t, 0) DEF_RVV_I_OPS (vint8m1_t, 0) DEF_RVV_I_OPS (vint8m2_t, 0) DEF_RVV_I_OPS (vint8m4_t, 0) DEF_RVV_I_OPS (vint8m8_t, 0) -DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_I_OPS (vint16mf2_t, 0) DEF_RVV_I_OPS (vint16m1_t, 0) DEF_RVV_I_OPS (vint16m2_t, 0) DEF_RVV_I_OPS (vint16m4_t, 0) DEF_RVV_I_OPS (vint16m8_t, 0) -DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_I_OPS (vint32m1_t, 0) DEF_RVV_I_OPS (vint32m2_t, 0) DEF_RVV_I_OPS (vint32m4_t, 0) DEF_RVV_I_OPS (vint32m8_t, 0) -DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ZVE64) -DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ZVE64) -DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ZVE64) -DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) -DEF_RVV_U_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64) +DEF_RVV_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_U_OPS (vuint8mf4_t, 0) DEF_RVV_U_OPS (vuint8mf2_t, 0) DEF_RVV_U_OPS (vuint8m1_t, 0) DEF_RVV_U_OPS (vuint8m2_t, 0) DEF_RVV_U_OPS (vuint8m4_t, 0) DEF_RVV_U_OPS (vuint8m8_t, 0) -DEF_RVV_U_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64) +DEF_RVV_U_OPS (vuint16mf4_t,
