RE: [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API

[Li, Pan2 via Gcc-patches]

Great! Thanks yanzhang.

Could you please help to add some text about the changes below? Or kito may 
meet some error by git hook when commit the PATCH.


gcc/ChangeLog:



* config/riscv/vector-iterators.md:   <- add text for change.



gcc/testsuite/ChangeLog:



* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

Pan

From: juzhe.zhong 
Sent: Wednesday, April 26, 2023 8:15 PM
To: Wang, Yanzhang 
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Li, Pan2 
; Wang, Yanzhang 
Subject: Re: [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API

LGTM. Thanks for fixing my silly mistake.
 Replied Message 
From
yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>
Date
04/26/2023 20:05
To
gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>
Cc
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>,
kito.ch...@sifive.com<mailto:kito.ch...@sifive.com>,
pan2...@intel.com<mailto:pan2...@intel.com>,
yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>
Subject
[PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API

[PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API

[yanzhang.wang--- via Gcc-patches]

From: Yanzhang Wang 

PR 109617

gcc/ChangeLog:

* config/riscv/vector-iterators.md:

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

Signed-off-by: Yanzhang Wang 
Co-authored-by: Pan Li 
---
 gcc/config/riscv/vector-iterators.md   |  3 ++-
 .../gcc.target/riscv/rvv/base/vlmul_ext-1.c| 14 ++
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index a8e856161d3..033659930d1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -189,6 +189,7 @@
   (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI 
"TARGET_MIN_VLEN >= 128")
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 
128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
+  (VNx4DI "TARGET_VECTOR_ELEN_64")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -220,7 +221,7 @@
 
 (define_mode_iterator VLMULEXT32 [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
-  (VNx1HI "TARGET_MIN_VLEN < 128")
+  (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
 ])
 
 (define_mode_iterator VLMULEXT64 [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
new file mode 100644
index 000..501d98c5897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include 
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
+  return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
+  return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
+}
+
+/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
-- 
2.39.2