Since cond_copysign has been support into match.pd (middle-end).
We don't need to support conditional copysign by RTL combine pass.
Instead, we can support it by direct explicit cond_copysign optab.
conditional copysign tests are already available in the testsuite.
No need to add tests.
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_copysign): Remove.
* config/riscv/autovec.md (cond_copysign): New pattern.
---
gcc/config/riscv/autovec-opt.md | 22 --
gcc/config/riscv/autovec.md | 22 ++
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 3c87e66ea49..986ac6e9181 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -486,28 +486,6 @@
}
[(set_attr "type" "vector")])
-;; Combine vfsgnj.vv + vcond_mask
-(define_insn_and_split "*cond_copysign"
- [(set (match_operand:V_VLSF 0 "register_operand")
-(if_then_else:V_VLSF
- (match_operand: 1 "register_operand")
- (unspec:V_VLSF
- [(match_operand:V_VLSF 2 "register_operand")
-(match_operand:V_VLSF 3 "register_operand")] UNSPEC_VCOPYSIGN)
- (match_operand:V_VLSF 4 "register_operand")))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, mode);
- rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4],
- gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
- riscv_vector::expand_cond_len_binop (icode, ops);
- DONE;
-}
-[(set_attr "type" "vector")])
-
;; Combine vnsra + vcond_mask
(define_insn_and_split
"*cond_vtrunc"
[(set (match_operand: 0 "register_operand")
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 973dc4ac235..33722ea1139 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1808,6 +1808,28 @@
DONE;
})
+;; -
+;; [FP] Conditional copysign operations
+;; -
+;; Includes:
+;; - vfsgnj
+;; -
+
+(define_expand "cond_copysign"
+ [(match_operand:V_VLSF 0 "register_operand")
+ (match_operand: 1 "register_operand")
+ (match_operand:V_VLSF 2 "register_operand")
+ (match_operand:V_VLSF 3 "register_operand")
+ (match_operand:V_VLSF 4 "register_operand")]
+ "TARGET_VECTOR"
+{
+ insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4],
+ gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
+ riscv_vector::expand_cond_len_binop (icode, ops);
+ DONE;
+})
+
;; -
;; [INT] Conditional ternary operations
;; -
--
2.36.3